BIOS booting method and apparatus, storage medium, and electronic device

Abstract

Embodiments of the present application provide a BIOS starting method and device, a storage medium and an electronic device, and relate to the field of computers. The BIOS starting method comprises: in the case that a CPLD is connected to a power supply and first indication information sent by a BMC is acquired, performing a first operation by the CPLD, wherein the first indication information is information sent by the BMC after the BMC verifies the Flash, and after the first operation is performed, the state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to the power supply, and the second state is a state in which the server is connected to the power supply and waits for a starting instruction; in the case that the CPLD acquires second indication information sent by the BMC, sending a reset signal to a CPU by the CPLD, wherein the second indication information is information sent by the BMC after the BMC verifies specified data stored in the CPU, the specified data is information acquired by the CPU from the Flash, and the reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and specifically, to a BIOS startup method and device, a storage medium, and an electronic device. Background Art

[0002] The Basic Input / Output System (BIOS) is a fixed software program that runs when a computer system boots up. It is responsible for initializing computer hardware, checking whether the system hardware is functioning properly, and loading the operating system. It is fundamental to the startup and operation of a computer system. Boot Guard (for example, Intel Boot Guard) is a CPU hardware-based root of trust designed to ensure that a known, good BIOS is used to boot the platform. Boot Guard uses an Authentication Code Module (ACM) to cryptographically verify the BIOS's Initial Boot Block (IBB) before the BIOS runs, handing control over to the BIOS. If IBB verification fails, Boot Guard prevents the platform from booting, preventing the execution of a potentially malicious BIOS. Boot Guard is implemented using Intel's Platform Controller Hub (PCH). However, Intel's newer BirchStream platforms lack a PCH, so functions that previously relied on the PCH must be implemented in other chips or CPUs. This means that the Boot Guard functionality previously performed by the PCH also relies on other components.

[0003] In related technologies, Boot Guard is implemented by Intel's Platform Firmware Resilience (PFR) chip. However, the PFR chip is not a mandatory feature of any product. For products without PFR configuration, implementing Boot Guard requires system design considerations.

[0004] With respect to the problem in related technologies that a server without PFR does not have the startup protection function, no effective solution has been proposed yet. Summary of the Invention

[0005] The embodiments of the present application provide a BIOS startup method and device, a storage medium, and an electronic device to at least solve the problem that a server without PFR does not have a startup protection function.

[0006] According to one embodiment of the present application, a BIOS startup method is provided, which is applied to a server. The server includes: a complex programmable logic device (CPLD), a baseboard management controller (BMC), a flash memory of a basic input / output system (BIOS), and a central processing unit (CPU). The method includes: when the CPLD is connected to a power supply and obtains first indication information sent by the BMC, performing a first operation through the CPLD, wherein the first indication information is information sent by the BMC after verifying the Flash memory, and after performing the first operation, the state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to a power supply, and the second state is a state in which the server is connected to a power supply and waiting for a power-on instruction; when the CPLD obtains second indication information sent by the BMC, sending a reset signal to the CPU through the CPLD, wherein the second indication information is information sent by the BMC after verifying specified data stored in the CPU, and the specified data is information obtained by the CPU from the Flash memory, and the reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS.

[0007] In an exemplary embodiment, the method further includes: when the CPLD is connected to a power supply and the first indication information sent by the BMC is not obtained, prohibiting the CPLD from performing the first operation; before sending a reset signal to the CPU through the CPLD, the method further includes: when the CPLD obtains a power-on instruction, sending a first signal to the CPU through the CPLD, wherein the power-on instruction is used to instruct to start the server, and the first signal is used to instruct the CPU to execute a power-on sequence; sending a second signal to the CPU through the CPLD, and prohibiting the CPLD from sending the power-on instruction to the CPU. A reset signal, wherein the second signal is used to indicate that the CPU power supply is in place; when the CPLD obtains a third signal sent by the CPU, third indication information is sent to the BMC through the CPLD, wherein the third signal is a signal sent by a designated module of the CPU after obtaining the second signal to request verification of the designated data stored in the CPU, and the third indication information is used to instruct the BMC to exchange data with the CPU based on the security protocol data model SPDM using the improved integrated circuit interconnect bus 13C of the management component transport protocol MCTP to verify the designated data stored in the CPU.

[0008] In an exemplary embodiment, the method further includes: when the BMC obtains the third indication information, sending a verification instruction to the CPU through the BMC based on SPDM and using 13C of MCTP; when the BMC obtains the target hash value of the specified data sent by the CPU in response to the verification instruction, determining through the BMC whether the target hash value is equal to a preset hash value, wherein the preset hash value is a hash value pre-stored by the BMC; when the BMC determines that the target hash value is equal to the preset hash value, determining that the verification of the specified data stored in the CPU is successful; when the BMC determines that the target hash value is not equal to the preset hash value, determining that the verification of the specified data stored in the CPU has failed.

[0009] In an exemplary embodiment, the method further includes: when the BMC is connected to a power supply for the first time within a preset time, obtaining first data and second data from the Flash based on a serial peripheral interface SPI by the BMC, wherein the second data is data obtained by operating the first data using a target algorithm; operating the first data using the target algorithm by the BMC to obtain third data; when it is determined that the second data is equal to the third data, determining that the verification of the Flash is passed; when it is determined that the second data is not equal to the third data, determining that the verification of the Flash is failed.

[0010] In an exemplary embodiment, the method further includes: when the BMC fails to verify the Flash, sending a first alarm message through the BMC, wherein the first alarm message is used to indicate that the data in the Flash has been tampered with; and / or when the BMC fails to verify the specified data stored in the CPU, sending a second alarm message through the BMC, wherein the second alarm message is used to indicate that the specified data stored in the CPU has been tampered with.

[0011] In an exemplary embodiment, the method further includes: when the BMC fails to verify the Flash or fails to verify the specified data stored in the CPU, refreshing the Flash using the obtained BIOS image through the BMC, or instructing the CPU to start the BIOS based on the target Flash, wherein the server also includes the target Flash, and the target Flash stores a BIOS program.

[0012] In an example embodiment, the method further comprises: after the BMC sends the second indication information to the CPLD, sending, by the BMC, a query instruction to the CPU based on SPDM using I3C of MCTP after a preset time; and in a case where the BMC acquires response information sent by the CPU in response to the query instruction and the response information is used to indicate that the BIOS fails to start, sending, by the BMC, third warning information, wherein the third warning information is used to indicate that the BIOS fails to start.

[0013] According to another embodiment of the present application, a BIOS starting device is also provided, which is applied to a server, and the server comprises a complex programmable logic device (CPLD), a baseboard management controller (BMC), a flash memory (Flash) of a basic input / output system (BIOS), and a central processing unit (CPU). The BIOS starting device comprises: an execution module, configured to execute a first operation by the CPLD in a case where the CPLD is connected to a power supply and first indication information sent by the BMC is acquired, wherein the first indication information is information sent by the BMC after the Flash is verified to pass, and after the first operation is executed, a state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to the power supply, and the second state is a state in which the server is connected to the power supply and waits for a starting instruction; and a first sending module, configured to send, by the CPLD, a reset signal to the CPU in a case where second indication information sent by the BMC is acquired by the CPLD, wherein the second indication information is information sent by the BMC after specified data stored in the CPU is verified to pass, the specified data is information acquired from the Flash by the CPU, and the reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS.

[0014] According to still another embodiment of the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program, wherein the computer program is set to execute steps in any of the above method embodiments when running.

[0015] According to still another embodiment of the present application, an electronic device is also provided, which comprises a memory and a processor, the memory stores a computer program, and the processor is set to run the computer program to execute steps in any of the above method embodiments.

[0016] According to still another embodiment of the present application, a computer program product is also provided, and the computer program product comprises a computer program, and the computer program is executed by a processor to implement steps in any of the above method embodiments.

[0017] Through this application, after the BMC passes the verification of the Flash, it sends a first indication message to the CPLD. After receiving the first indication message, the CPLD performs a first operation, and the server changes from a state where the power is not connected to a state where the power is connected and waiting to be powered on. After the BMC verifies the specified data stored in the CPU, it sends a second indication message to the CPLD. After receiving the second indication message, the CPLD sends a reset signal to the CPU. After receiving the reset signal, the CPU initializes according to a predetermined process and starts the BIOS. Since the verification of the specified data stored in the Flash and CPU is completed by using the BMC, and the CPLD sends a reset signal to the CPU after the verification is passed, the startup protection function is implemented, thereby solving the problem that servers without PFR do not have the startup protection function. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 This is a hardware structure block diagram of a server device according to a BIOS startup method of an embodiment of the present application;

[0020] Figure 2 1 is a schematic diagram of the interaction between a PFR chip and a BMC according to an embodiment of the present application;

[0021] Figure 3 This is a schematic diagram of an optional BIOS startup process according to an embodiment of the present application;

[0022] Figure 4 This is a schematic diagram of the interaction between a CPLD and a BMC according to an embodiment of the present application;

[0023] Figure 5 This is a flowchart of an optional BMC verification Flash according to an embodiment of the present application;

[0024] Figure 6 An optional flowchart of a BMC verifying CPU internal data according to an embodiment of the present application;

[0025] Figure 7 This is an optional flow chart of the factory notifying the BMC of the hash value according to an embodiment of the present application;

[0026] Figure 8 This is a flow chart of an optional BMC detecting that the startup protection function is normal according to an embodiment of the present application;

[0027] Figure 9This is a flow chart of an optional BIOS Flash notifying the BMC of a hash value according to an embodiment of the present application;

[0028] Figure 10 This is an optional flow chart of detecting the startup status of the BIOS system according to an embodiment of the present application;

[0029] Figure 11 This is a structural block diagram of a BIOS startup device according to an embodiment of the present application;

[0030] Figure 12 It is a schematic structural diagram of an optional electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0033] The BIOS startup method embodiment provided in the embodiment of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure diagram of a server device of a BIOS startup method according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown) processor 102 (processor 102 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 104 for storing data, wherein the above-mentioned server device may also include a transmission device 106 for communication functions and an input and output device 108. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0034] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the BIOS startup method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to a server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0035] Transmission device 106 is used to receive or transmit data via a network. A specific example of such a network may include a wireless network provided by a communication provider of a server device. In one embodiment, transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0036] To better understand the BIOS startup process, the following explanation is given of the BIOS startup process in related art:

[0037] One solution is to use the PFR chip to implement the Boot Guard function, thereby starting the BIOS. Figure 2 The diagram illustrates the interaction between the PFR chip and the baseboard management controller (BMC). The PFR is an independent field-programmable gate array (FPGA) chip that verifies the serial peripheral interface read-only memory (SPI ROM) before running the BMC / BIOS and performs Boot Guard verification on the central processing unit (CPU) after booting. However, not all servers are equipped with a PFR chip. The PFR firmware and hardware designs are relatively complex, and PFR resources are relatively abundant, resulting in high costs.

[0038] In order to solve the above problems existing in the related art, this embodiment provides a BIOS startup method, which is applied to a server, wherein the server includes: a complex programmable logic device CPLD, a baseboard management controller BMC, a flash memory of a basic input / output system BIOS, and a central processing unit CPU, such as Figure 3 As shown, the process includes the following steps S302-S304:

[0039] Step S302: When the CPLD is connected to a power source and first indication information sent by the BMC is obtained, a first operation is performed by the CPLD, wherein the first indication information is information sent by the BMC after the Flash memory is successfully verified. After the first operation is performed, the state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to a power source, and the second state is a state in which the server is connected to a power source and is waiting for a power-on instruction.

[0040] Optionally, when the server system is connected to an alternating current (AC), the BMC starts to execute Figure 4 In step 1, the BMC obtains data from the Flash using the Serial Peripheral Interface (SPI) and then verifies the Flash. Figure 5 The diagram illustrates the BMC Flash verification process. The server system is first in the first state, that is, the lowest power consumption state (G3 state). When the AC is inserted, the CPLD prohibits executing the first operation and waits for the first indication information from the BMC. When the BMC determines that it is the first time to be powered on and the server is not in the second state (S5 state), the BMC starts to switch and verify the Flash. After the verification is passed, it sends the first indication information to the CPLD. Then, after receiving the first indication information, the CPLD executes the first operation.

[0041] It should be noted that since the current BMC has a ready-made interface for accessing the BIOS SPI (because the BMC refreshes the BIOS Flash, there is also an interface for reading and writing the BIOS Flash), there is no need to make additional modifications to the BMC hardware design, avoiding the increase in CPLD resources caused by outsourcing the Flash verification work to the CPLD.

[0042] In an exemplary embodiment, the method further includes the following steps S11-S13:

[0043] Step S11: when the BMC is connected to a power source for the first time within a preset time, obtaining first data and second data from the Flash memory through the BMC based on a serial peripheral interface (SPI), wherein the second data is data obtained by operating the first data using a target algorithm;

[0044] Optionally, the target algorithm includes but is not limited to: a hash algorithm.

[0045] It should be noted that the hash algorithm is an algorithm used to convert input data of arbitrary length into output values ​​of fixed length. Its core idea is to generate a unique hash value, called a hash value, by performing a series of calculations and transformations on the input data.

[0046] Step S12: using the target algorithm to operate the first data by the BMC to obtain third data;

[0047] Step S13: If it is determined that the second data is equal to the third data, it is determined that the verification of the Flash is passed; if it is determined that the second data is not equal to the third data, it is determined that the verification of the Flash is failed.

[0048] Alternatively, as Figure 5 As shown in the figure, if the BMC fails to verify the Flash, the BMC will report an error.

[0049] It should be noted that the above steps enable the BMC to quickly and accurately verify the Flash memory. Furthermore, the Flash memory verification work, which is typically performed by the PFR chip in related technologies, is now completed by the BMC without requiring additional BMC reorganization. This significantly reduces system configuration requirements, especially the CPLD resource requirements, making the BIOS boot process more versatile and significantly reducing economic costs.

[0050] In an exemplary embodiment, the method further includes the following steps: when the CPLD is connected to a power source and the first indication information sent by the BMC is not obtained, prohibiting the CPLD from performing the first operation;

[0051] It should be noted that in order to ensure the secure booting of BIOS, the BIOS program in Flash must be successfully verified before the CPLD executes the first operation. When the CPLD does not receive the first indication information sent by the BMC, it means that the CPLD does not know whether the BIOS program in Flash has been tampered with, and thus does not execute the first operation.

[0052] It should be noted that, when the BMC fails to verify the Flash, the first indication information is not sent to the CPLD.

[0053] Step S304: When the CPLD obtains the second indication information sent by the BMC, a reset signal is sent to the CPU through the CPLD, wherein the second indication information is information sent by the BMC after verifying the specified data stored in the CPU, and the specified data is information obtained by the CPU from the Flash. The reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS.

[0054] In steps S302-S304, after the BMC verifies the Flash memory, it sends a first indication to the CPLD. Upon receiving the first indication, the CPLD performs a first operation, causing the server to transition from an unconnected state to a connected state awaiting power on. After the BMC verifies the specified data stored in the CPU, it sends a second indication to the CPLD. Upon receiving the second indication, the CPLD sends a reset signal to the CPU. Upon receiving the reset signal, the CPU initializes according to a predetermined process and boots the BIOS. Because the BMC verifies the specified data stored in the Flash memory and the CPU, and the CPLD sends a reset signal to the CPU after verification, the boot protection function is implemented, thereby resolving the issue of servers without PFR lacking boot protection.

[0055] In an exemplary embodiment, before sending a reset signal to the CPU via the CPLD, the method further includes the following steps S21-S23:

[0056] Step S21: When the CPLD obtains a power-on instruction, the CPLD sends a first signal to the CPU, wherein the power-on instruction is used to instruct to start the server, and the first signal is used to instruct the CPU to execute a power-on sequence;

[0057] Step S22: sending a second signal to the CPU via the CPLD, and prohibiting sending the reset signal to the CPU via the CPLD, wherein the second signal is used to indicate that the CPU power supply is in place;

[0058] Optionally, Figure 6 It shows the process of BMC verifying the internal data of CPU. The second signal is Figure 6 SYS_POWER_OK signal.

[0059] It should be noted that the CPLD sends the SYS_POWER_OK signal to the CPU to inform the server that the power supply is functioning properly and the system can begin operation. This signal serves as a system startup indicator, ensuring that the system only starts operating when the power supply is functioning properly. This prevents system failures or damage caused by power problems, thereby ensuring system stability and reliability.

[0060] Optionally, the reset signal is Figure 6 The Reset signal in.

[0061] Step S23: When the CPLD obtains the third signal sent by the CPU, third indication information is sent to the BMC through the CPLD, wherein the third signal is a signal sent by the designated module of the CPU after obtaining the second signal for requesting verification of the designated data stored in the CPU, and the third indication information is used to instruct the BMC to exchange data with the CPU based on the security protocol data model SPDM and the improved integrated circuit interconnect bus I3C of the management component transport protocol MCTP to verify the designated data stored in the CPU.

[0062] Alternatively, as Figure 4 As shown in step 3, the BMC has an Improved Inter-Integrated Circuit (I3C), a Security Protocol and Data Model IP (SPDM IP), and a Management Component Transport Protocol (MCTP) to communicate and verify with the CPU.

[0063] It should be noted that the current BMC manages the CPU through I3C, such as obtaining CPU temperature, status, registers and other information. Therefore, the BMC can use the I3C interface to complete the Boot Guard function. In other words, the BMC also has a ready-made interface for accessing the CPU through I3C, without the need for additional modifications to the hardware design.

[0064] Optionally, the designated module is an S3M module, and the third signal is Figure 6 PLTRST_SYNC signal in.

[0065] Optionally, after receiving the SYS_POWER_OK signal, the S3M module inside the CPU will send a PLTRST_SYNC signal to instruct to verify the internal data of the CPU.

[0066] It should be noted that through the above steps, the CPLD only completes the reception of the CPU ready signal and notifies the BMC to check the CPU internal data. Then the BMC completes the verification of the specified data stored in the Flash and the CPU, thereby completing the implementation of the startup protection function, avoiding the use of the PFR chip, and eliminating the need for the CPLD to check the CPU internal data, saving resources and significantly reducing costs.

[0067] In an exemplary embodiment, the method further includes the following steps S31-S33:

[0068] Step S31: When the BMC obtains the third indication information, the BMC sends a verification instruction to the CPU using I3C of MCTP based on SPDM;

[0069] Step S32: when the BMC obtains the target hash value of the designated data sent by the CPU in response to the verification instruction, determining, by the BMC, whether the target hash value is equal to a preset hash value, wherein the preset hash value is a hash value pre-stored by the BMC;

[0070] Alternatively, as Figure 7 As shown, when the BMC starts, the factory side will check the Boot Guard and the preset hash value of the BMC. The factory side will send the first command to the BMC to determine whether the BMC has saved the preset hash value. If there is no preset hash value in the BMC, the preset hash value will be written into the BMC.

[0071] Alternatively, as Figure 8 As shown, when the BMC starts, the BMC detects whether the startup protection function has been started and whether the preset hash value exists. If it is satisfied, the BMC will execute the process corresponding to the startup protection function. If it is not satisfied, the BMC will not execute the process corresponding to the startup protection function and work normally.

[0072] Alternatively, as Figure 9 As shown, after the BMC is started, the BIOS Flash update process begins, and the hash value is transmitted to the BMC through the refresh tool to ensure that the preset hash value stored in the BMC corresponds to the BIOS program in the Flash.

[0073] Step S33: If the BMC determines that the target hash value is equal to the preset hash value, it is determined that the verification of the specified data stored in the CPU is successful; if the BMC determines that the target hash value is not equal to the preset hash value, it is determined that the verification of the specified data stored in the CPU is failed.

[0074] It should be noted that through the above steps, the BMC verifies the CPU's internal data and determines that the data in the Flash has not been tampered with after the CPU obtains it. In addition, the BMC verifies the CPU's internal data, which can avoid the use of PFR chips or CPLDs to verify the CPU, thereby saving system resources and costs.

[0075] In an exemplary embodiment, the method further includes the following steps S41 and / or S42:

[0076] Step S41: When the BMC fails to verify the Flash, sending a first alarm message through the BMC, wherein the first alarm message is used to indicate that the data in the Flash has been tampered with;

[0077] Step S42: When the BMC fails to verify the designated data stored in the CPU, a second alarm message is sent through the BMC, wherein the second alarm message is used to indicate that the designated data stored in the CPU has been tampered with.

[0078] Optionally, the tampered data in the Flash and / or the tampered designated data stored in the CPU may be directly output or recorded via a serial port or a log, etc., to inform the user.

[0079] It should be noted that, by receiving the first warning information and / or the second warning information, the user promptly knows that the data in the Flash and / or the specified data stored in the CPU have been tampered with, so that the user can respond quickly.

[0080] In an exemplary embodiment, the method further includes the following steps: when the BMC fails to verify the Flash or fails to verify the specified data stored in the CPU, the BMC uses the obtained BIOS image to refresh the Flash, or instructs the CPU to start the BIOS based on the target Flash, wherein the server also includes the target Flash, and the target Flash stores the BIOS program.

[0081] Optionally, the BMC can restore the BIOS image through a Trans Flash (TF) card and / or an Embedded Multi Media Card (EMMC), or capture the BIOS image through the network, or switch to another BIOS Flash, greatly improving the flexibility of the BMC recovery mechanism.

[0082] In an exemplary embodiment, the method further includes the following steps S51-S52:

[0083] Step S51: After the BMC sends the second indication information to the CPLD, after a preset time, the BMC sends a query instruction to the CPU using the I3C of MCTP based on SPDM;

[0084] Step S52: When the BMC obtains the response information sent by the CPU in response to the query instruction, and the response information is used to indicate that the BIOS startup fails, the BMC sends a third warning message, wherein the third warning message is used to indicate that the BIOS startup fails.

[0085] Optionally, Figure 10 The diagram shows the detection process of the BIOS boot process. The BMC detects the BIOS boot through SPDM over MCTP over I3C to verify whether the CPU successfully boots the BIOS.

[0086] Obviously, the embodiments described above are only part of the embodiments of the present invention, rather than all the embodiments. In order to better understand the above method, the above process is described below in conjunction with the embodiments, but it is not intended to limit the technical solutions of the embodiments of the present invention. Specifically:

[0087] 1. As Figure 4 As shown in the figure, the BMC implements the PRoT function, which is divided into three parts:

[0088] Part 1: Figure 4 Step 1: Verify Flash;

[0089] Part II: Figure 4 Steps 3 and 4: Verify whether the information read from the Flash by the CPU (i.e. the above-mentioned CPU internal data) is correct;

[0090] Part III: Figure 4 Step 8: Detect BIOS system startup status.

[0091] 2. The description of the first part above is as follows:

[0092] 1. Reference Figure 5 In the middle process, when the server is in G3 state (the first state mentioned above) and an AC is inserted, the CPLD will stop the subsequent processes and wait for the BMC to power on and verify the SPI Flash. Then the CPLD will execute the subsequent processes.

[0093] 2. If the BMC is powered on for the first time and the server system is not in S5 state (the second state mentioned above), the BMC will switch and verify the BIOS SPI Flash;

[0094] 3. After the BMC passes the Flash verification, it notifies the CPLD that it can continue to power on normally. If the BMC fails the Flash verification, the BMC will report an error.

[0095] 3. The description of the above second part is as follows:

[0096] 1. Reference Figure 6 In the middle process, the system receives a power-on command or signal and initiates the power-on process;

[0097] 2. CPLD starts executing the power-on sequence and sends the SYS_POWER_OK signal after completion, indicating that the power is ready.

[0098] 3. After the power is ready, the CPLD needs to pull the CPU Reset signal (the reset signal mentioned above) to ensure that the CPU does not start (in order to wait for the BMC to complete the internal data verification of the CPU);

[0099] 4. After receiving the Power OK signal, the S3M module inside the CPU sends a PLTRST_SYNC signal, instructing the BMC to verify the data inside the CPU. The BMC obtains the hash value of the information stored inside the CPU through SPDM over MCTP over I3C. This hash value is compared with the hash value already known inside the BMC. If they are consistent, the verification passes; otherwise, it fails.

[0100] 5. If the BMC verification is successful, the result will be notified to the motherboard CPLD to execute the subsequent boot process. The motherboard CPLD releases the CPU Reset and starts the entire BIOS boot process.

[0101] 3. The description of the third part above is as follows: Figure 10 The middle process is the BMC detecting the BIOS startup process through SPDM over MCTP over I3C.

[0102] It should be noted that this application also has the following advantages: (1) High flexibility in configuration without extension: Whether the system supports Boot Guard and which functions of Boot Guard are supported can be switched on and off through configuration, allowing system administrators to customize the secure startup process as needed; (2) High compatibility: In existing systems, Boot Guard can be used as an additional function of BMC to enhance the secure startup function without the need for large-scale hardware replacement; (3) Reduced maintenance costs: Through remote management and automated security checks, BMC helps reduce the maintenance cost and complexity of the system.

[0103] In summary, the goal of the present invention is to design a method that can solve the problem of implementing the BootGuard function (BIOS secure boot) through BMC without a PCR chip by modifying the BMC code instead of adding a chip or upgrading the existing chip to a more expensive chip.

[0104] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0105] In this embodiment, a BIOS boot device is also provided, which is applied to a server, wherein the server includes: a complex programmable logic device (CPLD), a baseboard management controller (BMC), a flash memory of a basic input / output system (BIOS), and a central processing unit (CPU); and is used to implement the above-mentioned embodiments and preferred implementations. Details that have already been described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the modules described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0106] Figure 11 : is a structural block diagram of a BIOS boot device according to an embodiment of the present application, the device comprising:

[0107] An execution module 1102 is configured to, when the CPLD is connected to a power source and first indication information sent by the BMC is obtained, execute a first operation through the CPLD, wherein the first indication information is information sent by the BMC after the Flash memory is successfully verified. After executing the first operation, the state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to a power source, and the second state is a state in which the server is connected to a power source and is waiting for a power-on instruction.

[0108] The first sending module 1104 is used to send a reset signal to the CPU through the CPLD when the CPLD obtains the second indication information sent by the BMC, wherein the second indication information is information sent by the BMC after verifying the specified data stored in the CPU, the specified data is information obtained by the CPU from the Flash, and the reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS.

[0109] The above-mentioned device, after the BMC verifies the Flash memory, sends a first instruction to the CPLD. After receiving the first instruction, the CPLD performs a first operation, causing the server to change from a power-off state to a power-on state and waiting to be powered on. After the BMC verifies the specified data stored in the CPU, it sends a second instruction to the CPLD. After receiving the second instruction, the CPLD sends a reset signal to the CPU. After receiving the reset signal, the CPU initializes according to a predetermined process and starts the BIOS. Because the BMC verifies the specified data stored in the Flash memory and the CPU, and the CPLD sends a reset signal to the CPU after verification, the startup protection function is implemented, thereby resolving the problem of servers without PFR not having the startup protection function.

[0110] In an exemplary embodiment, the execution module 1102 is further configured to, when the CPLD is connected to a power supply and the first indication information sent by the BMC is not obtained, prohibit the CPLD from executing the first operation; the first sending module 1104 is further configured to, before the CPLD sends a reset signal to the CPU, when the CPLD obtains a power-on instruction, send a first signal to the CPU through the CPLD, wherein the power-on instruction is used to instruct to start the server, and the first signal is used to instruct the CPU to execute a power-on sequence; send a second signal to the CPU through the CPLD, and prohibit the CPLD from sending a reset signal to the CPU through the CPLD. The PU sends the reset signal, wherein the second signal is used to indicate that the CPU power is in place; when the CPLD obtains the third signal sent by the CPU, the CPLD sends third indication information to the BMC, wherein the third signal is a signal sent by the designated module of the CPU after obtaining the second signal to request verification of the designated data stored in the CPU, and the third indication information is used to instruct the BMC to interact with the CPU based on the security protocol data model SPDM and the improved integrated circuit interconnect bus I3C of the management component transport protocol MCTP to verify the designated data stored in the CPU.

[0111] In an exemplary embodiment, the above-mentioned device further includes: a second sending module, configured to send a verification instruction to the CPU through the BMC based on SPDM and using I3C of MCTP when the BMC obtains the third indication information; the above-mentioned device further includes: a determination module, configured to determine through the BMC whether the target hash value is equal to a preset hash value when the BMC obtains the target hash value of the specified data sent by the CPU in response to the verification instruction, wherein the preset hash value is a hash value pre-stored by the BMC; when the BMC determines that the target hash value is equal to the preset hash value, it is determined that the verification of the specified data stored in the CPU is successful; when the BMC determines that the target hash value is not equal to the preset hash value, it is determined that the verification of the specified data stored in the CPU has failed.

[0112] In an exemplary embodiment, the above-mentioned device also includes: a processing module, which is used to obtain first data and second data from the Flash based on a serial peripheral interface SPI through the BMC when the BMC is connected to a power supply for the first time within a preset time, wherein the second data is data obtained by using a target algorithm to operate on the first data; and obtain third data by using the target algorithm to operate on the first data through the BMC; and a determination module, which is further used to determine that the verification of the Flash is passed when it is determined that the second data is equal to the third data, and determine that the verification of the Flash is failed when it is determined that the second data is not equal to the third data.

[0113] In an exemplary embodiment, the second sending module is further used to send a first alarm message through the BMC when the BMC fails to verify the Flash, wherein the first alarm message is used to indicate that the data in the Flash has been tampered with; and / or send a second alarm message through the BMC when the BMC fails to verify the specified data stored in the CPU, wherein the second alarm message is used to indicate that the specified data stored in the CPU has been tampered with.

[0114] In an exemplary embodiment, the processing module is further configured to, when the BMC fails to verify the Flash or fails to verify the specified data stored in the CPU, refresh the Flash using the acquired BIOS image through the BMC, or instruct the CPU to start the BIOS based on the target Flash, wherein the server also includes the target Flash, and the target Flash stores a BIOS program.

[0115] In an exemplary embodiment, the second sending module is further configured to, after the BMC sends the second indication information to the CPLD, send a query instruction to the CPU through the BMC based on SPDM and using I3C of MCTP after a preset time; when the BMC obtains response information sent by the CPU in response to the query instruction, and the response information is used to indicate that the BIOS startup failed, send a third warning message through the BMC, wherein the third warning message is used to indicate that the BIOS startup failed.

[0116] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0117] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0118] Optionally, in this embodiment, the computer program may be configured to perform the following steps:

[0119] S1, when the CPLD is connected to a power source and first indication information sent by the BMC is obtained, performing a first operation through the CPLD, wherein the first indication information is information sent by the BMC after the Flash memory is successfully verified. After performing the first operation, the state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to a power source, and the second state is a state in which the server is connected to a power source and is waiting for a power-on instruction.

[0120] S2. When the CPLD obtains the second indication information sent by the BMC, a reset signal is sent to the CPU through the CPLD, wherein the second indication information is information sent by the BMC after verifying the specified data stored in the CPU, the specified data is information obtained by the CPU from the Flash, and the reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS.

[0121] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0122] The embodiment of the present application also provides an electronic device, such as Figure 12 As shown, the electronic device includes a memory 1202 and a processor 1204. The memory 1202 stores a computer program, and the processor 1204 is configured to execute the steps in any of the above method embodiments through the computer program.

[0123] Optionally, in this embodiment, the processor 1204 may be configured to execute the following steps through a computer program:

[0124] S1. When the CPLD is connected to a power source and first indication information sent by the BMC is obtained, a first operation is performed by the CPLD, wherein the first indication information is information sent by the BMC after the Flash memory is successfully verified. After the first operation is performed, the state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to a power source, and the second state is a state in which the server is connected to a power source and is waiting for a power-on instruction.

[0125] S2. When the CPLD obtains the second indication information sent by the BMC, a reset signal is sent to the CPU through the CPLD, wherein the second indication information is information sent by the BMC after verifying the specified data stored in the CPU, the specified data is information obtained by the CPU from the Flash, and the reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS.

[0126] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0127] Alternatively, those skilled in the art will appreciate that Figure 12 The structure shown is for illustration only. Figure 12 The structure of the electronic device is not limited. For example, the electronic device may also include Figure 1 2, or more or fewer components (such as network interfaces, etc.), or with Figure 12 Different configurations shown.

[0128] Among them, the memory 1202 can be used to store software programs and modules, such as the program instructions / modules corresponding to the BIOS startup method and BIOS startup device in the embodiment of the present application. The processor 1204 executes various functional applications and data processing by running the software programs and modules stored in the memory 1202, that is, realizing the above-mentioned BIOS startup method. The memory 1202 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1202 may further include a memory remotely located relative to the processor 1204, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof. Among them, the memory 1202 can be used specifically but not limited to store information such as system configuration files. As an example, Figure 12 As shown, the memory 1202 may include, but is not limited to, the execution module 1102 and the first sending module 1104 in the BIOS startup device. In addition, it may also include, but is not limited to, other module units in the BIOS startup device, which will not be described in detail in this example.

[0129] Optionally, the transmission device 1206 is configured to receive or send data via a network. Specific examples of the network may include a wired network and a wireless network. In one embodiment, the transmission device 1206 includes a network interface controller (NIC), which can be connected to other network devices and a router via a network cable to communicate with the Internet or a local area network. In one embodiment, the transmission device 1206 is a radio frequency (RF) module, which is configured to communicate with the Internet wirelessly.

[0130] In addition, the electronic device further includes: a display 1208; and a connection bus 1210 for connecting various module components in the electronic device.

[0131] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0132] An embodiment of the present application further provides another computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above method embodiments are implemented.

[0133] An embodiment of the present application also provides a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any of the above method embodiments.

[0134] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0135] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A BIOS startup method, characterized in that: Applicable to a server, the server including: CPLD, BMC, BIOS Flash and CPU; include: When the CPLD is connected to a power source and obtains first indication information sent by the BMC, a first operation is performed by the CPLD, wherein the first indication information is information sent by the BMC after the Flash memory is successfully verified. After the first operation is performed, the state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to a power source, and the second state is a state in which the server is connected to a power source and is waiting for a power-on instruction. When the CPLD obtains the second indication information sent by the BMC, a reset signal is sent to the CPU via the CPLD, wherein the second indication information is information sent by the BMC after verifying the specified data stored in the CPU, the specified data is information obtained by the CPU from the Flash, and the reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS; Before sending the reset signal to the CPU through the CPLD, the method further includes: When the CPLD obtains a power-on instruction, the CPLD sends a first signal to the CPU, wherein the power-on instruction is used to instruct to start the server, and the first signal is used to instruct the CPU to execute a power-on sequence; Sending a second signal to the CPU through the CPLD, and prohibiting sending the reset signal to the CPU through the CPLD, wherein the second signal is used to indicate that the CPU power supply is in place; When the CPLD obtains the third signal sent by the CPU, third indication information is sent to the BMC through the CPLD, wherein the third signal is a signal sent by the designated module of the CPU after obtaining the second signal and is used to request verification of the designated data stored in the CPU. The third indication information is used to instruct the BMC to exchange data with the CPU based on SPDM using I3C of MCTP to verify the designated data stored in the CPU.

2. The method according to claim 1, characterized in that The method further comprises: When the CPLD is connected to a power source and the first indication information sent by the BMC is not obtained, executing the first operation through the CPLD is prohibited.

3. The method according to claim 2, characterized in that The method further comprises: When the BMC obtains the third indication information, the BMC sends a verification instruction to the CPU using I3C of MCTP based on SPDM; When the BMC obtains a target hash value of the designated data sent by the CPU in response to the verification instruction, determining, by the BMC, whether the target hash value is equal to a preset hash value, wherein the preset hash value is a hash value pre-stored by the BMC; If the BMC determines that the target hash value is equal to the preset hash value, it is determined that the verification of the specified data stored in the CPU is successful. If the BMC determines that the target hash value is not equal to the preset hash value, it is determined that the verification of the specified data stored in the CPU has failed.

4. The method according to claim 1, wherein The method further comprises: When the BMC is connected to a power source for the first time within a preset time, obtaining first data and second data from the Flash through the BMC based on the SPI, wherein the second data is data obtained by operating the first data using a target algorithm; performing a calculation on the first data by the BMC using the target algorithm to obtain third data; If it is determined that the second data is equal to the third data, it is determined that the verification of the Flash is passed; if it is determined that the second data is not equal to the third data, it is determined that the verification of the Flash is failed.

5. The method according to claim 1, wherein The method further comprises: When the BMC fails to verify the Flash, sending a first alarm message through the BMC, wherein the first alarm message is used to indicate that data in the Flash has been tampered with; and / or When the BMC fails to verify the designated data stored in the CPU, second alarm information is sent through the BMC, wherein the second alarm information is used to indicate that the designated data stored in the CPU has been tampered with.

6. The method according to claim 1, characterized in that The method further comprises: When the BMC fails to verify the Flash or fails to verify the specified data stored in the CPU, the BMC uses the obtained BIOS image to refresh the Flash, or instructs the CPU to start the BIOS based on the target Flash, wherein the server also includes the target Flash, and the target Flash stores a BIOS program.

7. The method according to claim 1, characterized in that The method further comprises: After the BMC sends the second indication information to the CPLD, after a preset time, the BMC sends a query instruction to the CPU using the I3C of MCTP based on SPDM; When the BMC obtains the response information sent by the CPU in response to the query instruction, and the response information is used to indicate that the BIOS startup fails, the BMC sends a third warning message, wherein the third warning message is used to indicate that the BIOS startup fails.

8. A BIOS boot device, characterized in that: Applicable to a server, the server including: CPLD, BMC, BIOS Flash and CPU; include: an execution module, configured to, when the CPLD is connected to a power source and first indication information sent by the BMC is obtained, execute a first operation through the CPLD, wherein the first indication information is information sent by the BMC after the Flash memory is successfully verified. After executing the first operation, the state of the server changes from a first state to a second state, wherein the first state is a state in which the server is not connected to a power source, and the second state is a state in which the server is connected to a power source and is waiting for a power-on instruction; a first sending module, configured to send a reset signal to the CPU via the CPLD when the CPLD obtains second indication information sent by the BMC, wherein the second indication information is information sent by the BMC after validating specified data stored in the CPU, the specified data is information obtained by the CPU from the Flash, and the reset signal is used to instruct the CPU to initialize according to a predetermined process and start the BIOS; The first sending module is further configured to, before sending a reset signal to the CPU through the CPLD, send a first signal to the CPU through the CPLD when the CPLD obtains a power-on instruction, wherein the power-on instruction is used to instruct to start the server, and the first signal is used to instruct the CPU to execute a power-on sequence; send a second signal to the CPU through the CPLD, and prohibit sending the reset signal to the CPU through the CPLD, wherein the second signal is used to indicate that the CPU power supply is in place; and send third indication information to the BMC through the CPLD when the CPLD obtains a third signal sent by the CPU, wherein the third signal is a signal sent by a designated module of the CPU after obtaining the second signal, for requesting verification of the designated data stored in the CPU, and the third indication information is used to instruct the BMC to perform data exchange with the CPU using I3C of MCTP based on SPDM to verify the designated data stored in the CPU.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

Images