A method for identifying FPC areas and dividing wiring channels

Abstract

The present invention discloses a method for FPC area identification and wiring channel division, which includes: triangulating the FPC wiring area; constructing an ETP area division model, and dividing the FPC wiring area into an escape area E area, a triangle area T area, and a connection area P area based on the triangles obtained by triangulation, including: dividing the escape area and the channel area; dividing the channel area into a triangle area and a connection area; and performing global wiring of the channel area. In addition, the power integrity is considered to complete the subsequent wiring. The present invention proposes a global wiring technology for FPC board area identification and channel area, which solves the problems of insufficient area division and unreasonable global wiring of the channel area in traditional FPC wiring, and realizes the automation of the wiring process and a significant improvement in wiring quality through precise area division and optimized wiring strategy. The present invention can effectively optimize the wiring structure of the FPC board, reduce the intersection and overlap of wiring paths, and improve the performance and reliability of the FPC circuit board.

Description

Technical Field

[0001] The present invention belongs to the technical field of flexible circuit boards, and in particular relates to a method for identifying FPC areas and dividing wiring channels. Background Art

[0002] A flexible printed circuit (FPC) is a type of printed circuit board (PCB) made from a flexible substrate that can be bent and folded. Compared to traditional PCBs, FPCs offer greater flexibility and improved heat dissipation, enabling higher performance for densely interconnected circuits. They are widely used in small mobile communications devices and wearable electronics.

[0003] While research on routing issues in very large-scale integrated circuits (VLSIs) continues, research on FPC routing remains in its early stages. Industrial FPC routing, in particular, relies heavily on manual adjustments. FPC routing differs from IC routing in that punching holes in FPCs significantly impacts signal integrity. The horizontal or vertical routing patterns of ICs are not applicable to FPCs, necessitating the development of a routing algorithm specifically tailored for FPCs. Furthermore, the irregular boundaries of FPCs impose a mandatory constraint on routing paths. Furthermore, VLSI research rarely considers irregular routing area constraints.

[0004] Power integrity must be considered when routing. In multi-layer routing areas, VLSI typically employs power and ground layers. These layers are introduced to the power or ground layers using a minimal Steiner tree. However, FPCs, due to their flexible material and relatively compact routing resources, typically do not have dedicated power or ground layers.

[0005] In summary, compared to conventional PCBs, FPC pinouts tend to cluster together, forming areas with irregular polygonal shapes. Paths of different circuits often share common areas to ensure stable and reliable signal transmission. Furthermore, FPC routing requires consistent topology for local paths. Currently, research on FPC automated routing is still in its early stages of exploration. Further research is needed for FPC automated routing scenarios, including the following:

[0006] Zone Identification: To achieve automatic routing of FPCs, zone types must be identified first to divide the FPC board into different functional areas. Different algorithms can then be designed for each area to achieve optimal routing results. Automatic routing algorithms must accurately identify and assign pins to different zones based on their locations. Accurate zone identification is particularly challenging given the often irregular shapes of FPC routing zones. Currently, there is a lack of specialized methods for dividing routing zones.

[0007] Channel Division: Within the common channel area of ​​the FPC network, routing paths consistent with the bus topology must be constructed. This means that signal lines in the same location or function should utilize similar routing strategies and path planning. Therefore, a global routing operation must first be performed on the FPC to determine the approximate routing ranges for pins in different areas. Each distinct range is called a routing channel. Dividing signals into different channels and then performing detailed routing operations can simplify the complexity of detailed routing.

[0008] Ensuring power integrity: When completing circuit design, special consideration should be given to the layout of power lines. Proper power line layout can shorten their length, reduce resistance and inductance, lower local temperature concentration, and improve heat dissipation efficiency and power supply stability. However, due to limited wiring layer resources in FPCs, power layers are typically not defined. To ensure power integrity, it is necessary to maximize the power line routing area within the ordinary signal layer.

[0009] Algorithm efficiency and convergence: Automatic routing algorithms must demonstrate high efficiency and convergence, generating routing results that meet design requirements within a reasonable timeframe. For example, using the A* algorithm directly to complete all routing tasks would require unacceptable memory and time requirements. Furthermore, the algorithm's scalability and applicability must be considered to accommodate FPC routing design tasks of varying scale and complexity. Summary of the Invention

[0010] The purpose of the present invention is to provide a method for identifying FPC areas and dividing wiring channels to solve the problem of identifying FPC wiring areas.

[0011] The technical solution of the present invention is:

[0012] A method for identifying FPC areas and dividing wiring channels, the method comprising:

[0013] Triangulate the FPC wiring area;

[0014] Construct an ETP area division model, and divide the FPC wiring area into the escape area E area, the triangle area T area, and the connection area P area based on the triangles obtained by triangulation, including:

[0015] Divide the escape area and passage area, including:

[0016] Establish a mapping relationship between pins and triangles to identify whether there are pins distributed within each triangle, and then divide the triangles into two categories;

[0017] Initial clustering is performed by merging triangles: adjacent triangles of the same type are aggregated together to form a set of triangles of different types, thereby obtaining multiple sub-regions. Each sub-region is assigned a region type; the region type is divided into sub-regions with pins and sub-regions without pins;

[0018] Update sub-regions: Determine the representative points of the sub-region containing pins and the representative points of the sub-region without pins, and determine whether there are representative points of sub-regions without pins within a certain distance around the representative point of the sub-region containing pins. If there are, and the line connecting the representative points is within the routing area, update the latter area type to a sub-region containing pins.

[0019] Merge sub-regions to construct escape and channel regions: Merge adjacent sub-regions of the same type. The sub-region containing pins is the escape region, and the remaining sub-regions without pins are the channel region.

[0020] The channel area is divided into a triangular area and a connection area, wherein the triangular area is a triangle with wired network access on three sides, and the connection area is a triangle with wired network access on two sides;

[0021] Perform global routing in the channel area.

[0022] Furthermore, the FPC wiring area is triangulated, including:

[0023] Use the distance threshold T to encrypt the boundary point set of the FPC wiring area;

[0024] Based on the encrypted point set, create the Delaunay triangulation network;

[0025] Determine the center of gravity of each triangle and select the triangles whose center of gravity is within the FPC wiring area;

[0026] Construct triangulation graph G CDT (V, E), where V represents the triangle and E represents the adjacency relationship of the triangle.

[0027] Furthermore, determining representative points of the sub-region containing pins and representative points of the sub-region not containing pins includes:

[0028] For a sub-region containing pins, all its pins are set as candidate representative points. When determining whether there is a representative point of a sub-region without pins within a certain distance around the representative point of the sub-region containing pins, the candidate representative point closest to the sub-region without pins is used as the representative point.

[0029] For a sub-region without pins, its centroid is used as the representative point.

[0030] Furthermore, the channel area is divided into a triangular area and a connecting area, including:

[0031] According to the discontinuity of the channel zone edge chain on the original boundary, it is identified as multiple unconnected edge chains;

[0032] Find the triangle whose three vertices are on three different edge chains, which is the triangular area, and the remaining triangles in the channel area are the connection area.

[0033] Furthermore, global routing of the channel area is performed, including:

[0034] Get the initial passing point on the escape line; the escape line is the dividing line between the escape area and the channel area, and the initial passing point is the point where the wire net passes on the escape line. The wire net connects the pins in the two escape areas.

[0035] Using triangle as the basic unit, construct the initial wiring diagram G Route , add the initial nodes of the network into the wiring diagram G Route middle;

[0036] Based on the breadth-first algorithm BFS and the method of dynamically adding and deleting nodes, the wire network path is searched in the wiring diagram and the wiring diagram G is updated. Route And record the total capacity of the path passed by the node;

[0037] Check whether the bus fan-out result meets the channel area capacity requirement; if so, complete the routing.

[0038] Furthermore, the wiring diagram is G Route (V, E) means that V is composed of the points along the edge of the wired network. V stores the location coordinates of each point and the information of the edge it is on. E means that the nodes belong to the same Delaunay triangle.

[0039] Determine the line network of each sub-area in the channel area and the order of its passing points on the area boundary; since each set of line networks has only a unique path, the triangles passed through are certain, and thus the line network passing through each triangular area is obtained.

[0040] Furthermore, we can ensure that the network topology does not cross by dynamically adding and deleting nodes. The method of dynamically adding and deleting nodes is as follows:

[0041] For the triangle area T, the initial wiring diagram is divided into four areas by the lines connecting the nodes on the three sides of the triangle. When a new path is added, the two nodes of the line with the same direction as the new path are deleted, and a new node is added at the midpoint of the line segment on both sides of the deleted node. If the node connection line does not conflict with the existing route, it will be added to the overall wiring diagram. If the node connection line conflicts with the existing route, it will not be added to the overall wiring diagram. The area divided by the node connection line is the wire mesh path.

[0042] For the connection area P, the initial wiring diagram is the two areas divided by the lines connecting the nodes on the two sides of the triangle. The sides of the triangle located in the edge chain are boundary constraint edges and no nodes are set. When a new path is added, the two nodes of a line are deleted, and a new node is added at the midpoint of the line segments on both sides of the deleted node. If the node connection line does not conflict with the already laid path, it will be added to the overall wiring diagram. If the node connection line conflicts with the already laid path, it will not be added to the overall wiring diagram. The area divided by the node connection line is the wire network path.

[0043] Furthermore, the method further comprises:

[0044] Consider power integrity and improve routing results, including:

[0045] The power lines are divided into variable width power lines and constant width power lines.

[0046] First, the edge chains associated with the variable linewidth power lines are determined;

[0047] Route the constant width net along the other side chain according to the minimum width and spacing, and reserve the remaining routing resources for variable width power lines.

[0048] Furthermore, laying variable width power lines must meet the following two conditions:

[0049] (1) The area occupied is large, and the actual line width at each point on the line network path is greater than the preset minimum line width;

[0050] (2) Set it at the edge of the FPC to reduce interference with other wire networks.

[0051] A PCB / FPC, wherein the PCB / FPC adopts any one of the above-mentioned FPC area identification and wiring channel division methods to complete FPC wiring area division.

[0052] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0053] This invention proposes a technology for identifying FPC board regions and global routing of channel areas, addressing the issues of insufficient regional division and irrational global routing of channel areas in traditional FPC routing. Through precise regional division and optimized routing strategies, it automates the routing process and significantly improves routing quality. This invention can effectively optimize the routing structure of FPC boards, reduce the intersection and overlap of routing paths, and improve the performance and reliability of FPC circuit boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 The overall framework diagram of the FPC area identification and wiring channel division method;

[0055] Figure 2 This is the result of Delaunay triangulation;

[0056] Figure 3 This is a schematic diagram before and after the identification of the escape zone and the passage zone; Figure 3 (a) is a schematic diagram before recognition. Figure 3 (b) is a schematic diagram after identification;

[0057] Figure 4 The triangle area recognition result diagram of different FPCs;

[0058] Figure 5 Schematic diagram for dynamically adding and deleting nodes; Figure 5 (a) is the initial image of the T zone, Figure 5 (b) is the updated diagram after the network passes through the T zone. Figure 5 (c) is the initial map of the P region, Figure 5 (d) is the updated graph after the network passes through the P area;

[0059] Figure 6 This is the global routing result graph;

[0060] Figure 7 A wiring diagram for reserving power wiring resources;

[0061] Figure 8 A wiring result diagram of the present invention;

[0062] Figure 9 This is another wiring result diagram of the present invention. DETAILED DESCRIPTION

[0063] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0064] This paper proposes a method for identifying FPC regions and dividing routing channels for power integrity, a global routing planning technology for automated routing of flexible printed circuit boards (FPCs). This method effectively identifies various functional regions within the FPC and proposes a novel routing channel division strategy that considers the connection between signals and power while ensuring routing rationality and consistency. By introducing these region identification and routing channel division algorithms, a solid foundation can be laid for subsequent detailed routing work, improving routing efficiency and quality.

[0065] The overall framework of the present invention is as follows Figure 1 As shown, the process is divided into four parts: preprocessing FPC routing data, dividing routing areas, overall routing of the channel area, and completing routing with consideration of power integrity. Based on the given routing information, Delaunay triangulation of the routing area is completed. Then, combined with the pin distribution and graphical relationship, an ETP region partitioning model is constructed, namely the escape region (E region), triangle region (T region), and passage region (P region). Then, based on the overall routing algorithm for the channel area within a two-dimensional plane that satisfies channel capacity constraints, the topology of the line paths within the same layer is ensured to be non-intersecting. Finally, the subsequent routing is completed with consideration of power integrity.

[0066] 1. Preprocessing of FPC wiring data

[0067] Delaunay triangulation (DT) holds significant theoretical and practical value in environmental measurement, pattern recognition, and medial axis extraction. It offers numerous advantages in computer graphics and spatial data processing. Delaunay triangulation of a discrete set of points on a plane yields a triangulated network with numerous properties, including an empty circumcircle and a maximum minimum angle.

[0068] In FPC, the outer boundary of the wiring area is an irregular polygon. Dividing the area with a rectangular frame requires additional complex processing of the boundary, while triangles are flexible in expressing the area, so the present invention uses triangles to identify and divide the wiring area.

[0069] When the FPC wiring area is processed by the Delaunay triangulation algorithm, the input is the boundary point set P[1…n] of the wiring area and the distance threshold T of the encrypted boundary points. The output is G, which represents the convex hull of the Delaunay triangle inside the area. CDT (V, E) graph, where V represents triangles and E represents the adjacency relationship between triangles. The process is as follows:

[0070] (1) Use threshold T to encrypt the boundary point set of the wiring area;

[0071] (2) Create a Delaunay triangulation network;

[0072] (3) Check whether the centroid of the constructed Delaunay triangle is within the bounding box and filter out the triangles within the area;

[0073] (4) Using the triangles in the region as nodes, construct G CDT picture.

[0074] The distance threshold T is mainly used to segment the boundary line of the routing area to increase the number of boundary points. The pseudo code is shown in Table 1.

[0075] Table 1 Construction G CDT Algorithm pseudocode table

[0076]

[0077]

[0078] The Delaunay triangulation result is as follows Figure 2 shown.

[0079] 2. Construct ETP regional division model

[0080] 2.1 Identification of escape zone and passage zone

[0081] In an FPC, the channel area is usually only used for circuit routing, and no devices are placed. Circuits are also prohibited from changing layers in this area. The escape area is an area with dense pads, usually located at the end of the FPC, where the wire network is allowed to change layers. Therefore, the area can be divided into two adjacent parts by establishing a dividing line. In CDT, any edge of any triangle can be used as a candidate edge for the dividing line. By establishing a mapping relationship between pins and triangles in CDT, the channel area and escape area can be quickly identified, and the escape area can be formed by adjacent triangles. Different sub-areas are marked with area numbers and types.

[0082] Because pins in some escape zones may be scattered, Delaunay triangulation results in individual triangles containing no pins. Identifying these triangles as channel zones would affect routing performance, so this situation also needs to be addressed.

[0083] The specific process of identifying the passage area and escape area is as follows:

[0084] (1) Identify whether there is pin distribution in each triangle and classify the triangles;

[0085] (2) Initial clustering is performed by merging triangles. Adjacent triangles of the same type are grouped together to form a set of triangles of different types. Each sub-region is assigned a region number and region type.

[0086] (3) Update the subregions. For subregions containing pins, select the pin center coordinates as the representative point. For subregions without pins, use the center of gravity as the region representative point. Determine whether there is a center of gravity of a subregion without pins within a certain distance of the representative point of the subregion containing pins. If so, update the latter region type to a subregion containing pins.

[0087] In this embodiment, the center coordinates of pins in the subregion containing pins are set as candidate regional representative points. This regional representative point is dynamically selected based on the adjacent subregions identified. Generally, the center coordinates of the pin closest to the adjacent subregion are set as the regional representative point. The line connecting the representative points of the merged region cannot cross the boundary of the routing region (crossing the boundary indicates that the two subregions are physically disconnected and cannot be merged), and the distance between the representative points must be less than a set value.

[0088] (4) Merge sub-regions. Construct the channel region and escape region based on the above results.

[0089] The pseudo code is shown in Table 2.

[0090] Table 2 Pseudo code table of the algorithm for identifying the channel area and escape area

[0091]

[0092]

[0093] The identification results of escape area and channel area are as follows Figure 3 shown. Figure 3 The blue blocks in (a) are pins, indicating the soldering positions of the device in the FPC. Figure 3 (b) Clustering the triangles, the pins at the two ends are divided into two categories. The three dividing lines in the figure divide the routing area into the channel area and the escape area.

[0094] 3.2 Identification of triangular areas and connecting areas within the channel area

[0095] A triangle is a polygonal area enclosed by a portion of the area's boundaries. In a typical access area, a set of wire meshes enters from one straight edge of the triangle and exits from another straight edge. The number of wire meshes remains constant, representing a common access for the wire meshes. Generally, only two edges have wire meshes entering and exiting. A triangle is an area where the number of wire meshes changes, typically with wire meshes entering and exiting on all three edges. The steps for identifying triangles within a access area are as follows:

[0096] (1) According to the discontinuity of the channel region edge chain on the original boundary, it is identified as a disconnected edge chain.

[0097] (2) Find the triangle formed by three vertices on three different edge chains and mark it as a triangle area.

[0098] The identification results of the triangle area in the channel area are as follows: Figure 4 As shown, the red area in the middle of the figure is the triangle area. Figure 4 The two figures in the figure are the recognition results of different FPCs.

[0099] 3.FPC global wiring

[0100] The goal of overall wiring is to provide guidance for subsequent detailed wiring, ensuring that it has a good wiring path and efficient operating speed. The wiring boundary shape of the FPC channel area is irregular, so using a triangle as the overall wiring unit has a strong generalization ability. The overall wiring algorithm proposed in the present invention ensures that the wire network topology does not cross by dynamically adding and deleting nodes. Then, the wire networks of each sub-area in the channel area and the order of their passing points on the area boundary are determined according to the ETP area recognition model. Each group of wire networks has a unique path, and the Delaunay triangle it passes through is determined, from which the wire networks passing through each triangular area can be obtained.

[0101] 3.1 Dynamically add and delete node settings

[0102] (1) T zone

[0103] The initial wiring diagram of the T area is as follows Figure 5 (a) shows the green lines dividing the triangle into four regions. The three outer regions represent feasible paths for the wire mesh. A wire mesh can enter or exit any edge of the triangle. For example, a wire mesh enters from Ac and exits from Ab, while another wire mesh enters from Bc and exits from Ba.

[0104] When adding a new path, Figure 5 In (b), first delete the two nodes (b, c) on the line segment that runs in the same direction as the newly added path. Then, add four new nodes (d, e, f, g) at the midpoints of the line segments on either side of (b, c). The green solid edges (df, eg, ea, ga) do not conflict with existing paths and are added to the overall wiring diagram. The gray dashed edges (da, fa, fe, dg) conflict with existing paths and are not added to the overall wiring diagram.

[0105] (2) P zone

[0106] The area on both sides of the green line segment represents the initial feasible path of the network. Assume that the initial network enters from the AB edge and exits from the AC edge. The BC edge is the boundary constraint edge and no nodes are set. Figure 5After the new line segment in (d) passes through area P, the two nodes b and c that the original line segment passes through are deleted. Then, four new nodes d, e, f, and g are added at the midpoints of the line segments on either side of b and c. The green solid edges df and eg do not conflict with existing routes and are therefore added to the overall routing diagram. The gray dashed edges fe and dg conflict with existing routes and are therefore not added to the overall routing diagram. This allows routing to be performed in the area enclosed by Adf, bceg, and BCge.

[0107] 3.2 Algorithm Flow

[0108] The overall wiring diagram of the present invention is shown in G Route (V, E) represents V, which is the midpoint of the edges that the wire mesh passes through. V stores the coordinates of each point and the edge it is on. E represents the Delaunay triangle to which the node belongs. Each wire mesh has a unique path.

[0109] Using the triangle in the Delaunay triangular grid as the basic unit, construct the initial wiring diagram G Route . Add the initial nodes of the network into G Route In. Gradually move towards G Route Add nodes and edges to the graph, search for network paths in the graph based on the breadth-first algorithm (BFS), and update G Route And record the total capacity of the path that the node passes through. Check whether the bus fan-out result meets the channel area capacity requirements.

[0110] The steps are as follows:

[0111] (1) Input the initial passing point on the escape line;

[0112] (2) Using triangles as the basic unit, construct the initial wiring diagram G Route , record the total capacity of the edge where the node is located;

[0113] (3) Based on the breadth-first search algorithm (BFS) and the steps of dynamically adding and deleting nodes, search for the network path in the graph; (4) Check whether the bus fan-out result meets the channel area capacity requirements.

[0114] The pseudo code is shown in Table 3.

[0115] Table 3 Pseudo code table of overall wiring algorithm

[0116]

[0117]

[0118] The overall routing results based on this algorithm are as follows Figure 6 shown.

[0119] 4. Consider power integrity to complete subsequent wiring

[0120] There are two types of power lines in FPC. One is a metal line laid over a certain area with an irregular shape and variable line width, which is called a variable line width power line (PS) in this invention. The other is a wire mesh with a constant line width. The latter can be regarded as an ordinary signal line, while the former requires special treatment. In practical applications, laying a variable line width wire mesh must meet two conditions:

[0121] (1) It occupies a large area, and the actual line width at each point on the network path is greater than the minimum line width.

[0122] (2) Usually set at the edge of FPC to reduce interference with other wire networks.

[0123] If you want to reserve routing resources for power lines, you first need to determine the boundary edge chains between the power supply and the adjacent P area. Then, in the direction guidance algorithm, you need to exclude the influence of the related edge chains on the routing path direction. For example, Figure 7 In the example, assuming the power line is associated with edge chain ABC, N1 and N2 will be routed in the direction indicated by the dotted line, following the minimum line width and line spacing requirements. The remaining routing resources are reserved for the power line.

[0124] This part mainly sets up a wire network with constant line width first to reserve wiring resources for variable line width power lines.

[0125] Figure 8 and Figure 9 These are two results obtained by the algorithm. It can be seen that the present invention realizes FPC area identification and channel division for power integrity.

[0126] The present invention also provides a PCB / FPC, which is manufactured using any one of the above-mentioned FPC area identification and wiring channel division methods.

[0127] In summary, this invention proposes a technology for identifying FPC board regions and global routing of channel areas, addressing the issues of insufficient region division and irrational global routing of channel areas in traditional FPC routing. Through precise region division and optimized routing strategies, the routing process is automated and routing quality is significantly improved. This technology effectively optimizes the FPC board's routing structure, reduces crossing and overlapping routing paths, and improves the performance and reliability of the FPC circuit board.

[0128] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0129] It will be easily understood by those skilled in the art that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for identifying FPC areas and dividing wiring channels, characterized in that: The method includes: Triangulate the FPC wiring area; Construct an ETP area division model, and divide the FPC wiring area into the escape area E area, the triangle area T area, and the connection area P area based on the triangles obtained by triangulation, including: Divide the escape area and passage area, including: Establish a mapping relationship between pins and triangles to identify whether there are pins distributed within each triangle, and then divide the triangles into two categories; Initial clustering is performed by merging triangles: adjacent triangles of the same type are aggregated together to form a set of triangles of different types, thereby obtaining multiple sub-regions. Each sub-region is assigned a region type; the region type is divided into sub-regions with pins and sub-regions without pins; Update sub-regions: Determine the representative points of the sub-region containing pins and the representative points of the sub-region without pins, and determine whether there are representative points of sub-regions without pins within a certain distance around the representative point of the sub-region containing pins. If there are, and the line connecting the representative points is within the routing area, update the latter area type to a sub-region containing pins. Merge sub-regions to construct escape and channel regions: Merge adjacent sub-regions of the same type. The sub-region containing pins is the escape region, and the remaining sub-regions without pins are the channel region. The channel area is divided into a triangular area and a connection area, wherein the triangular area is a triangle with wired network access on three sides, and the connection area is a triangle with wired network access on two sides; Perform global routing in the channel area.

2. The FPC area identification and wiring channel division method according to claim 1, characterized in that: Triangulate the FPC routing area, including: Use the distance threshold T to encrypt the boundary point set of the FPC wiring area; Based on the encrypted point set, create the Delaunay triangulation network; Determine the center of gravity of each triangle and select the triangles whose center of gravity is within the FPC wiring area; Construct triangulation graph G CDT (V, E), where V represents the triangle and E represents the adjacency relationship of the triangle.

3. The FPC area identification and wiring channel division method according to claim 1, characterized in that: Determining representative points of the sub-region containing pins and representative points of the sub-region not containing pins includes: For a sub-region containing pins, all its pins are set as candidate representative points. When determining whether there is a representative point of a sub-region without pins within a certain distance around the representative point of the sub-region containing pins, the candidate representative point closest to the sub-region without pins is used as the representative point. For a sub-region without pins, its centroid is used as the representative point.

4. The FPC area identification and wiring channel division method according to claim 1, characterized in that: The channel area is divided into triangular area and connecting area, including: According to the discontinuity of the channel zone edge chain on the original boundary, it is identified as multiple unconnected edge chains; Find the triangle whose three vertices are on three different edge chains, which is the triangular area, and the remaining triangles in the channel area are the connection area.

5. The FPC area identification and wiring channel division method according to claim 1, characterized in that: Perform global routing of the channel area, including: Get the initial passing point on the escape line; the escape line is the dividing line between the escape area and the channel area, and the initial passing point is the point where the wire net passes on the escape line. The wire net connects the pins in the two escape areas. Using triangle as the basic unit, construct the initial wiring diagram G Route , add the initial nodes of the network into the wiring diagram G Route middle; Based on the breadth-first algorithm BFS and the method of dynamically adding and deleting nodes, the wire network path is searched in the wiring diagram and the wiring diagram G is updated. Route And record the total capacity of the path passed by the node; Check whether the bus fan-out result meets the channel area capacity requirement; if so, complete the routing.

6. The FPC area identification and wiring channel division method according to claim 5, characterized in that: Wiring diagram with G Route (V, E) means that V is composed of the points along the edge of the wired network. V stores the location coordinates of each point and the information of the edge it is on. E means that the nodes belong to the same Delaunay triangle. Determine the line network of each sub-area in the channel area and the order of its passing points on the area boundary; since each set of line networks has only a unique path, the triangles passed through are certain, and thus the line network passing through each triangular area is obtained.

7. The FPC area identification and wiring channel division method according to claim 5, characterized in that: The method of dynamically adding and deleting nodes is used to ensure that the network topology does not cross. The method of dynamically adding and deleting nodes is as follows: For the triangle area T, the initial wiring diagram is divided into four areas by the lines connecting the nodes on the three sides of the triangle. When a new path is added, the two nodes of the line with the same direction as the new path are deleted, and a new node is added at the midpoint of the line segment on both sides of the deleted node. If the node connection line does not conflict with the existing route, it will be added to the overall wiring diagram. If the node connection line conflicts with the existing route, it will not be added to the overall wiring diagram. The area divided by the node connection line is the wire mesh path. For the connection area P, the initial wiring diagram is the two areas divided by the lines connecting the nodes on the two sides of the triangle. The sides of the triangle located in the edge chain are boundary constraint edges and no nodes are set. When a new path is added, the two nodes of a line are deleted, and a new node is added at the midpoint of the line segments on both sides of the deleted node. If the node connection line does not conflict with the already laid path, it will be added to the overall wiring diagram. If the node connection line conflicts with the already laid path, it will not be added to the overall wiring diagram. The area divided by the node connection line is the wire network path.

8. The FPC area identification and wiring channel division method according to claim 1, characterized in that: The method further includes: Consider power integrity and improve routing results, including: The power lines are divided into variable width power lines and constant width power lines. First, the edge chains associated with the variable linewidth power lines are determined; Route the constant width net along the other side chain according to the minimum width and spacing, and reserve the remaining routing resources for variable width power lines.

9. The FPC area identification and wiring channel division method according to claim 8, characterized in that: The following two conditions must be met when laying variable width power lines: (1) The area occupied is large, and the actual line width at each point on the line network path is greater than the preset minimum line width; (2) Set it at the edge of the FPC to reduce interference with other wire networks.

10. A PCB / FPC, characterized in that: The PCB / FPC is manufactured by using the FPC area identification and wiring channel division method according to any one of claims 1 to 9.

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