Gate driving circuit and driving method thereof, display panel and display device

Abstract

The present application discloses a gate drive circuit and its driving method, a display panel and a display device, and relates to the field of display technology. The present application accesses a gate drive signal through a gate drive module, and enables the current pixel row to display the current frame picture under the drive of the gate drive signal; when the current frame picture is in the blank stage of display, the gate drive module is de-noised by accessing a de-noising signal through a dual de-noising tube module; when the dual de-noising tube module de-noises the gate drive module, the de-noising management module charges the first capacitor by accessing a capacitor charging signal through a first signal terminal, and after the first capacitor is charged, in response to a high level signal outputted from a second signal terminal accessed by a second capacitor terminal, the terminal voltage of the first capacitor terminal is subjected to charge conservation adjustment according to the level voltage of the level signal. The present application aims to suppress the right shift of the IV characteristic of the dual de-noising tube to improve the display performance of LCD products.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit and a driving method thereof, a display panel and a display device. Background Art

[0002] With the continuous development of display technology, LCD (Liquid Crystal Display) products are widely used in many fields such as mobile phones, cars, central control, smart home, smart office, watches, bracelets, etc. However, during the screen display process, the dual noise reduction tubes set in the existing LCD design are in a forward bias working state of 20V most of the time (about 88%). Especially in high temperature and high humidity environments, long-term operation will accelerate the speed of the IV (Current-Voltage) characteristics of the dual noise reduction tubes shifting to the right, resulting in a decrease in the ability to turn on and control noise, which in turn increases the risk of the GDL (Gate Driver less) circuit being interfered by the signal source to generate noise, which may cause the GDL circuit to generate unstable or abnormal output signals, and ultimately have a serious impact on the overall display performance.

[0003] Therefore, how to suppress the right shift of the IV characteristics of the dual noise reduction tubes to improve the display performance of LCD products is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The main purpose of the present application is to provide a gate drive circuit and a driving method thereof, a display panel and a display device, aiming to suppress the right shift of the IV characteristics of the dual noise reduction tubes to improve the display performance of LCD products.

[0005] To achieve the above object, the present application provides a gate driving circuit, the gate driving circuit comprising:

[0006] A gate driving module, used for receiving a gate driving signal and enabling a current pixel row to display a current frame image under the drive of the gate driving signal;

[0007] A dual noise reduction tube module, the dual noise reduction tube module is electrically connected to the gate driving module, and the dual noise reduction tube module is used to access the noise reduction signal to perform noise reduction processing on the gate driving module when the current frame is in a blank stage of display;

[0008] A noise reduction management module, wherein the noise reduction management module comprises a first capacitor, wherein the first end of the first capacitor is electrically connected to the dual noise reduction tube module and the first signal end respectively, and the second end of the first capacitor is electrically connected to the second signal end. The noise reduction management module is used to charge the first capacitor by connecting a capacitor charging signal to the first signal end when the dual noise reduction tube module performs noise reduction processing on the gate driving module, and after the first capacitor is charged, in response to a high-level signal output from the second signal end connected to the second capacitor end, charge conservation adjustment is performed on the terminal voltage of the first capacitor end according to the level voltage of the high-level signal.

[0009] In one embodiment, the noise cancellation management module further includes a first thin film transistor, a second thin film transistor and a third signal terminal;

[0010] The first channel end of the first thin film transistor constitutes the first end of the noise reduction management module, and is connected between the pre-charge position end of the gate driving module and the first capacitive coupling end of the gate driving module;

[0011] The first channel end of the second thin film transistor constitutes the second end of the noise reduction management module, and is connected between the first channel end of the dual noise reduction tube module and the second capacitive coupling end of the gate driving module;

[0012] The gate terminal of the first thin film transistor and the gate terminal of the second thin film transistor are both electrically connected to the first signal terminal, and the second channel terminal of the first thin film transistor and the second channel terminal of the second thin film transistor are both electrically connected to the third signal terminal.

[0013] In one embodiment, the gate driving module includes a signal input unit, a noise removal control unit and a pull-up unit;

[0014] The signal output end of the signal input unit constitutes the pre-charge end of the gate driving module, and is electrically connected to the control end of the noise reduction control unit, the first end of the pull-up unit and the first end of the noise reduction management module respectively;

[0015] The second end of the noise reduction management module is connected between the second end of the pull-up unit and the first passage end of the dual noise reduction tube module, the first end of the noise reduction control unit is connected between the output end of the dual noise reduction tube module and the first container end, and the second end of the noise reduction control unit is electrically connected to the control end of the dual noise reduction tube module; wherein,

[0016] The first end of the pull-up unit constitutes a first capacitive coupling end of the gate driving module, and the second end of the pull-up unit constitutes a second capacitive coupling end of the gate driving module.

[0017] In one embodiment, the signal input unit includes a third thin film transistor and a first pixel signal terminal;

[0018] The gate terminal of the third thin film transistor is electrically connected to the first pixel signal terminal, and the first channel terminal of the third thin film transistor is connected to the power supply terminal;

[0019] The second channel end of the third thin film transistor constitutes the signal output end of the signal input unit, and is electrically connected to the control end of the noise reduction control unit, the first end of the pull-up unit and the first end of the noise reduction management module respectively.

[0020] In one embodiment, the denoising control unit includes a fourth thin film transistor and a fourth signal terminal;

[0021] The gate end of the fourth thin film transistor constitutes the control end of the noise reduction control unit and is electrically connected to the signal output end of the signal input unit and the second passage end of the dual noise reduction tube module respectively. The first passage end of the fourth thin film transistor is connected between the output end of the dual noise reduction tube module and the first capacitance end. The control end of the dual noise reduction tube module is connected between the second passage end of the fourth thin film transistor and the fourth signal end.

[0022] The first channel end of the fourth thin film transistor constitutes a first end of the denoising control unit, and the second channel end of the fourth thin film transistor is electrically connected to a connection node of the fourth signal end to constitute a second end of the denoising control unit.

[0023] In one embodiment, the pull-up unit includes a fifth thin film transistor, a second capacitor, a clock signal terminal and a second pixel signal terminal;

[0024] The gate terminal of the fifth thin film transistor is electrically connected to the signal output terminal of the signal input unit and the first terminal of the second capacitor respectively, the connection node where the gate terminal of the fifth thin film transistor is electrically connected to the first terminal of the second capacitor constitutes the first terminal of the pull-up unit, and the first terminal of the noise elimination management module is connected between the signal output terminal of the signal input unit and the first terminal of the pull-up unit;

[0025] The second end of the noise reduction management module is connected between the first channel end of the dual noise reduction tube module and the second end of the second capacitor, the first channel end of the fifth thin film transistor is connected between the second end of the second capacitor and the second pixel signal end, and the second channel end of the fifth thin film transistor is connected to the clock signal end, wherein the second end of the second capacitor constitutes the second end of the pull-up unit.

[0026] In one embodiment, the dual noise reduction tube module includes a sixth thin film transistor and a seventh thin film transistor;

[0027] The gate of the sixth thin film transistor is electrically connected to the gate of the seventh thin film transistor;

[0028] The gate of the sixth thin film transistor is electrically connected to the connection node of the gate of the sixth thin film transistor, forming the control end of the dual noise elimination tube module, and is electrically connected to the second end of the noise elimination control unit;

[0029] The second end of the noise elimination management module is connected between the second end of the pull-up unit and the first channel end of the sixth thin film transistor, the second channel end of the sixth thin film transistor is electrically connected to the first channel end of the seventh thin film transistor, and the control end of the noise elimination control unit is connected between the first end of the pull-up unit and the second channel end of the seventh thin film transistor; wherein,

[0030] The first channel end of the sixth thin film transistor constitutes the first channel end of the dual noise reduction tube module, the second channel end of the seventh thin film transistor constitutes the second channel end of the dual noise reduction tube module, and the connection node of the second channel end of the sixth thin film transistor electrically connected to the first channel end of the seventh thin film transistor constitutes the output end of the dual noise reduction tube module.

[0031] In addition, to achieve the above-mentioned purpose, the present application also provides a driving method of a gate driving circuit, the driving method of the gate driving circuit is applied to the gate driving circuit described in any one of the above items, and the driving method of the gate driving circuit includes:

[0032] Accessing a gate drive signal through a gate drive module, and enabling the current pixel row to display a current frame image under the drive of the gate drive signal;

[0033] When the current frame is in a blank stage of display, the gate driving module is subjected to denoising processing by accessing the denoising signal through the dual denoising tube module;

[0034] When the dual noise reduction tube module performs noise reduction processing on the gate driving module, the noise reduction management module charges the first capacitor by connecting the capacitor charging signal to the first signal terminal, and after the first capacitor is charged, in response to the high-level signal output by the second signal terminal connected to the second capacitor terminal, the terminal voltage of the first capacitor terminal is charge-conserved according to the level voltage of the high-level signal.

[0035] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes the gate drive circuit described in any one of the above items.

[0036] In addition, to achieve the above-mentioned purpose, the present application also provides a display device, which includes the above-mentioned display panel, a memory, a processor, and a driver program for a gate drive circuit stored in the memory and runable on the processor, and when the processor executes the driver program for the gate drive circuit, the steps of the driving method of the gate drive circuit as described in any one of the above items are implemented.

[0037] The present application provides a gate drive circuit and a driving method thereof, a display panel and a display device. When the dual noise reduction tube module performs noise reduction processing on the gate drive module, the noise reduction management module provided in the present application effectively suppresses the right shift of the IV characteristics of the dual noise reduction tube module, thereby significantly improving the display performance of the LCD product. Specifically, the gate driving module enables the current pixel row to display the current frame image under the drive of the gate driving signal, thereby ensuring the clear presentation of the current frame image; next, in the blank stage of the current frame image display, the dual noise reduction tube module automatically accesses the noise reduction signal to perform efficient noise reduction processing on the gate driving module, and when the dual noise reduction tube module performs noise reduction processing on the gate driving module, the noise reduction management module receives the capacitor charging signal through the first signal terminal to charge the first capacitor, so that the first capacitor can be fully charged to maximize the charge coupling effect, and after the first capacitor is charged, in response to the high-level signal output by the second signal terminal connected to the second capacitor terminal, the terminal voltage of the first capacitor terminal is adjusted according to the level voltage of the high-level signal to maintain the charge balance of the first capacitor, so that the IV characteristic of the dual noise reduction tube module electrically connected to the first capacitor terminal in the blank stage of the current frame image display drifts to the left, effectively counteracting the natural rightward shift phenomenon of the IV characteristic of the dual noise reduction tube module due to long-term use or environmental factors, preventing the decline or failure of the noise reduction efficiency of the dual noise reduction tube module, and thus significantly improving the display performance of the LCD product applied to the gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0040] Figure 1 It is a schematic diagram of the circuit involved in LCD display technology;

[0041] Figure 2 It is a schematic diagram of the signal waveform involved in LCD display technology;

[0042] Figure 3 is a structural block diagram of the first embodiment of the gate driving circuit of the present application;

[0043] Figure 4 It is a schematic diagram of multi-stage capacitive coupling involved in the first embodiment of the gate driving circuit of the present application;

[0044] Figure 5 is a circuit diagram of an embodiment of a gate driving circuit of the present application;

[0045] Figure 6 It is a waveform diagram involved in an embodiment of the gate driving circuit of the present application;

[0046] Figure 7 This is a schematic flow chart of a second embodiment of a driving method for a gate driving circuit of the present application;

[0047] Figure 8 It is a schematic diagram of the structure of the display device involved in the embodiment of the present application.

[0048] Description of Figure Numbers:

[0049] 10. Gate drive module; 20. Dual noise reduction tube module; 30. Noise reduction management module; C1. First capacitor; C2. Second capacitor; T1. First thin film transistor; T2. Second thin film transistor; T3. Third thin film transistor; T4. Fourth thin film transistor; T5. Fifth thin film transistor; T6. Sixth thin film transistor; T7. Seventh thin film transistor; 101. Signal input unit; 102. Noise reduction control unit; 103. Pull-up unit; Power supply terminal VDD.

[0050] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0053] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0054] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0055] With the rapid development of LCD display technology, LCD products have been widely used in many fields such as mobile phones, cars, central control, smart home, smart office, watches, bracelets, etc. With the emergence of many application requirements such as technology, wisdom, intelligence, and integration, the market has strengthened its demand for product quality and trust, and specification requirements have become increasingly stringent. However, the design effects of existing LCD products still have shortcomings.

[0056] When the screen is on, each row of pixels will be turned on in turn for individual charging. Figure 1 As shown, the third thin film transistor T3 gives a pre-charge position to the Q point. When the CLK of this stage is at a high level, the Q point will be coupled to a higher voltage by the second capacitor C2 to fully open the fifth thin film transistor T5, and the pixels of this row begin to charge. After the charging is completed, the Q point and the Gn point are pulled to the VGL voltage, so that the pixels of this row are completely closed. When the Q point of this row is at a high level, the fourth thin film transistor T4 is turned on to pull the d signal low, so that the dual noise elimination tubes (the sixth thin film transistor T6 and the seventh thin film transistor T7) are turned off. When the charging of this row is completed, the Q point is at a low potential, the fourth thin film transistor T4 is turned off, and the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned on to pull down the Q point and the Gn voltage respectively. The role of the fourth thin film transistor T4 is to control the pull-down unit to be closed when the row is charged.

[0057] like Figure 2As shown, the waveform relationship between signal a and signal d of each frame is that in the Display (i.e. display stage) of each frame, except for being turned off when the row is charged, the rest of the time is in the open state. Assuming that the resolution of the display area is 1000 levels, the working time of the sixth thin film transistor T6 and the seventh thin film transistor T7 in the Display (i.e. display stage) is 999 / 1000=99.9%. As the resolution increases, the working time of the sixth thin film transistor T6 and the seventh thin film transistor T7 will also increase. In Blank (i.e. the blank stage of display), signal d gives a low level, and the sixth thin film transistor T6 and the seventh thin film transistor T7 are turned off. The Blank (i.e. the blank stage of display) time of each frame is about 2ms. Assuming that the refresh rate of the screen is 60HZ, the working time of the sixth thin film transistor T6 and the seventh thin film transistor T7 in one frame is about 14.67ms / 16.67ms≈88%.

[0058] When the sixth thin film transistor T6 and the seventh thin film transistor T7 are working, the gate voltage is a high level VGH (10V) signal, and the drain voltage is a low level VGL (-10V), so the sixth thin film transistor T6 and the seventh thin film transistor T7 are in a forward bias working state of Vgs=20V for a long time.

[0059] In summary, it can be concluded that when LCD products are subjected to reliability verification, that is, they are operated under extreme conditions of high temperature and high humidity (also known as the double 85 test), the dual noise cancelling tubes T6 and T7 are in a 20V forward bias state for 88% of the time. High temperature and high humidity will accelerate the speed at which the IV characteristics of the dual noise cancelling tubes T6 and T7 shift to the right, resulting in a decrease in the ability to turn on the dual noise cancelling tubes T6 and T7, and a decrease in the ability to control noise. The GDL circuit is interfered by the source signal during high-temperature operation and is prone to generate noise. If this part of the noise cannot be effectively controlled, abnormal GDL output will occur.

[0060] In order to solve the display defects existing in the above-mentioned existing LCD display technology, the present application provides a gate driving circuit and a driving method thereof, a display panel and a display device.

[0061] The present application embodiment provides a gate drive circuit, referring to Figure 3 As shown, Figure 3 1 is a structural block diagram of the first embodiment of the gate drive circuit of the present application. The gate drive circuit comprises:

[0062] The gate driving module 10 is used to receive the gate driving signal and enable the current pixel row to display the current frame image under the drive of the gate driving signal;

[0063] The dual noise reduction tube module 20 is electrically connected to the gate driving module 10 and is used to access the noise reduction signal to perform noise reduction processing on the gate driving module 10 when the current frame is in a blank stage of display.

[0064] In this example, after determining that the gate drive module 10 provided in the present application is connected to the gate drive signal, and driven by the gate drive signal, the current pixel row is enabled to display the current frame image; next, when the current frame image is in the blank stage of display, that is, in the blank gap of the current frame image display, the dual noise reduction tube module 20 provided in the present application automatically intervenes, and uses the noise reduction signal to perform fine noise reduction processing on the gate drive module 10, so as to eliminate potential electrical noise interference, thereby ensuring the display quality of the LCD product.

[0065] The noise reduction management module 30 includes a first capacitor C1, wherein the first capacitor end of the first capacitor C1 is electrically connected to the dual noise reduction tube module 20 and the first signal end respectively, and the second capacitor end of the first capacitor C1 is electrically connected to the second signal end. The noise reduction management module 30 is used to charge the first capacitor C1 by connecting the capacitor charging signal to the first signal end when the dual noise reduction tube module 20 performs noise reduction processing on the gate driving module 10, and after the first capacitor C1 is charged, in response to the high-level signal output from the second signal end connected to the second capacitor end, the terminal voltage of the first capacitor end is charge-conserved according to the level voltage of the high-level signal.

[0066] In this example, since the dual noise reduction tube module 20 will be in a 20V forward bias state during the denoising process, that is, the IV characteristics of the dual noise reduction tube module 20 during the denoising process are shifted to the right. Therefore, the present application is provided with a noise reduction management module 30 to counteract the natural rightward shift of the IV characteristics of the dual noise reduction tube module 20 due to long-term use or environmental factors. Specifically, the present application connects the first capacitor end of the first capacitor C1 between the dual noise reduction tube module 20 and the first signal end. When the dual noise reduction tube module 20 performs denoising on the gate drive module 10, that is, when the dual noise reduction tube module 20 is in the denoising process, the first capacitor C1 is fully charged by connecting the capacitor charging signal output by the first signal end through the first capacitor end of the first capacitor C1 to maximize the charge coupling effect of the first capacitor C1, and after charging is completed, the second signal end is automatically triggered to output a high-level signal representing 10V to the second capacitor end of the first capacitor C1. Before the second signal terminal outputs a high-level signal representing 10V to the second capacitor terminal of the first capacitor C1, the voltages across the first capacitor C1 are respectively a voltage VGH (10V) and a voltage VGL (-10V), wherein the voltage VGH represents the terminal voltage of the first capacitor terminal, and the voltage VGL represents the terminal voltage of the second capacitor terminal. When the second capacitor terminal of the first capacitor C1 is connected to the high-level signal representing 10V outputted from the second signal terminal, it is determined that the terminal voltage of the second capacitor terminal jumps from -10V to the level voltage of the high-level signal, and the level voltage of the high-level signal is 10V. That is to say, when it is determined that the terminal voltage of the second capacitor terminal has a voltage jump of 20V, according to the first capacitor C 1, the first end of the first capacitor C1 will also experience a 20V voltage jump, that is, the voltage of the first end will also jump from 10V to 30V instantly, that is, the voltage Vgs=10-30=-20V connected to the connection node of the dual noise reduction tube module 20 electrically connected to the first end of the capacitor, so that the IV characteristic of the dual noise reduction tube module 20 drifts to the left during the blank stage of the current frame display, effectively counteracting the natural rightward shift of the IV characteristic of the dual noise reduction tube module 20 due to long-term use or environmental factors, preventing the dual noise reduction tube module 20 from declining or failing in noise reduction performance, thereby significantly improving the display performance of the LCD product applied to the gate drive circuit.

[0067] It should be noted that Figure 3 The signal a shown represents the capacitor charging signal output by the first signal terminal, Figure 3The signal b shown represents a high-level signal representing 10V outputted from the second signal terminal. In addition, the voltage level of the high-level signal set in the present application is 10V, and the voltages at both ends of the first capacitor C1 are respectively voltage VGH (10V) and voltage VGL (-10V), which is only a feasible implementation of the present application. Since the Blank period is longer than the Display period (i.e., the blank stage of the display is longer than the display stage), the voltage difference between the voltage VGH and the voltage VGL is as small as possible without affecting the normal display, and can be customized according to application requirements. The present application does not impose any restrictions here.

[0068] In addition, it should be noted that the present application sets signal a and signal b to successively give high-level signals representing the voltage VGH, that is, the capacitor charging signal is a high-level signal representing the voltage VGH. Exemplarily, signal a needs to give a high-level signal representing the voltage VGH in advance by time T. The purpose of preferentially turning on signal a is to first fully charge the first capacitor C1, that is, time T can be understood as the charging completion time of the first capacitor C1, and the size of time T is adjusted according to the size of the first capacitor C1. The larger the first capacitor C1, the better the coupling effect will be and the longer the required time T will be.

[0069] In a specific embodiment, the first capacitor circuit provided in the present application can be changed to 2-stage coupling or more stages. The more stages there are, the higher the coupling voltage will be, which can enhance the speed of the left shift of the IV characteristic. Figure 4 , Figure 4 The circuit diagram of the first capacitor C1-1 and the first capacitor C1-2 shown in the figure involves a 2-level coupling. First, the signal a representing a high level is turned on to fully charge the first capacitor C1-1 and the first capacitor C1-2, and then the signal b representing 10V is connected through the second end of the first capacitor C1-1. At this time, the terminal voltage of the second end of the first capacitor C1 jumps from -10V to 10V. According to the law of conservation of charge, the terminal voltage of the first end of the first capacitor C1 also jumps from 10V to 30V. Since the first end of the first capacitor C1-1 is electrically connected to the first end of the first capacitor C1-2, the terminal voltage of the first end of the first capacitor C1-2 is 30V, and when the second end of the first capacitor C1-1 is connected to the high level provided by the signal e, the first end of the first capacitor C1-2 will also undergo a voltage jump of 20V, that is, the first end of the first capacitor C1-2 becomes 50V, thereby further enhancing the speed of the left shift of the IV characteristic of the dual noise reduction tube module 20.

[0070] In summary, the present application provides a gate drive circuit and its driving method, a display panel and a display device. When the dual noise reduction tube module 20 performs noise reduction processing on the gate drive module 10, the noise reduction management module 30 provided by the present application effectively suppresses the right shift of the IV characteristic of the dual noise reduction tube module 20, thereby significantly improving the display performance of the LCD product. Specifically, the gate drive module 10 enables the current pixel row to display the current frame image under the drive of the gate drive signal, thereby ensuring the clear presentation of the current frame image; next, in the blank stage of the current frame image display, the dual noise reduction tube module 20 automatically accesses the noise reduction signal to perform efficient noise reduction processing on the gate drive module 10, and when the dual noise reduction tube module 20 performs noise reduction processing on the gate drive module 10, the noise reduction management module 30 receives the capacitor charging signal through the first signal terminal to charge the first capacitor C1, so that the first capacitor C1 can be fully charged to maximize the charge coupling effect, and after the first capacitor C1 is fully charged Afterwards, in response to the high-level signal output from the second signal terminal connected to the second capacitor terminal, the terminal voltage of the first capacitor terminal is charge-conservation adjusted according to the level voltage of the high-level signal to maintain the charge balance of the first capacitor C1, so that the IV characteristic of the dual noise reduction tube module 20 electrically connected to the first capacitor terminal during the blank stage of the current frame image display is drifted to the left, effectively counteracting the natural rightward shift of the IV characteristic of the dual noise reduction tube module 20 due to long-term use or environmental factors, preventing the noise reduction performance of the dual noise reduction tube module 20 from declining or failing, thereby significantly improving the display performance of the LCD product applied to the gate drive circuit.

[0071] Further, in some feasible embodiments, referring to Figure 5 , Figure 5 It is a circuit diagram involved in an embodiment of the gate drive circuit of the present application. The noise reduction management module 30 also includes a first thin film transistor T1, a second thin film transistor T2 and a third signal terminal; the first channel end of the first thin film transistor T1 constitutes the first end of the noise reduction management module 30, connected between the pre-charge position end of the gate drive module 10 and the first capacitor C1 coupling end of the gate drive module 10; the first channel end of the second thin film transistor T2 constitutes the second end of the noise reduction management module 30, connected between the first channel end of the dual noise reduction tube module 20 and the second capacitor C2 coupling end of the gate drive module 10; the gate end of the first thin film transistor T1 and the gate end of the second thin film transistor T2 are both electrically connected to the first signal terminal, and the second channel end of the first thin film transistor T1 and the second channel end of the second thin film transistor T2 are both electrically connected to the third signal terminal.

[0072] In this embodiment, if the current frame is in the display stage (i.e. Figure 6The dual noise reduction tube module 20 provided in the present application causes the gate drive module 10 to enter the pull-down stage, such as Figure 6 The waveform relationship corresponding to each frame is shown. The waveform shows the process of pull-down. Figure 5 The signal d outputted from the fourth signal terminal is high level to keep the dual noise reduction tube module 20 in the on state (i.e. Figure 5 T6 and T7 are turned on as shown), at this time, the signal a output by the first signal terminal is low level, thereby pulling down the Q point voltage of the pre-charge terminal and the voltage Gn of the second pixel signal terminal; in addition, according to the electrical connection between the gate terminal of the first thin film transistor T1 and the gate terminal of the second thin film transistor T2 and the first signal terminal, it can be determined that the signal a representing the low level of the first signal terminal is also input to the gate terminal of the first thin film transistor T1 and the gate terminal of the second thin film transistor T2, that is, the first thin film transistor T1 and the second thin film transistor T2 set in the present application are always in the cut-off state and will not affect the original circuit; in addition, since the signal c output by the third signal terminal and the signal b output by the second signal terminal are both low level, both ends of the first capacitor C1 are also low level, that is, the potential difference between the two ends of the first capacitor C1 is 0v, so the first capacitor C1 is not charged and belongs to the open circuit state, and will not affect the normal operation of the original circuit.

[0073] If the current frame is in the blank stage (i.e. Figure 6 When the blank phase is shown, Figure 6The waveform relationship corresponding to each frame of the picture shown in the figure shows that the signal d of the fourth signal output is continuously output at a high level, so that the dual noise reduction tube module 20 is continuously in a conducting state. In addition, the signal a and the signal b set in the present application are successively given a high level in the Blank period (i.e., the blank stage of the display). Specifically, the signal a needs to be given a high level in advance by time T, and the purpose of signal a being turned on first is to first charge the first capacitor C1, and the size of the time T is adjusted according to the size of the first capacitor C1. The larger the first capacitor C1, the better the coupling effect will be and the longer the time T required will be. At this time, after the gate terminal of the first thin-film transistor T1 and the gate terminal of the second thin-film transistor T2 are connected to the signal a representing a high level, the first thin-film transistor T1 and the second thin-film transistor T2 are switched from a cut-off state to a conducting state. At this time, due to the third signal terminal output connected to the second channel terminal of the first thin-film transistor T1 and the second channel terminal of the second thin-film transistor T2 The signal c is low level, so that the Q point voltage of the pre-charge position terminal electrically connected to the first channel end of the first thin film transistor T1 can be pulled down, and the voltage Gn of the second pixel voltage terminal electrically connected to the first channel end of the second thin film transistor T2 through the coupling end of the second capacitor C2 can be pulled down. In other words, the present application outputs a signal a representing a high level during the blank stage of the current frame image display to ensure that the first thin film transistor T1 and the second thin film transistor T2 are switched from the off state to the on state, and the second channel end of the first thin film transistor T1 and the second channel end of the second thin film transistor T2 are connected to the third signal terminal. Since the signal c output from the third signal terminal is low level, the first thin film transistor T1 and the second thin film transistor T2 set in the present application can effectively prevent the signal a representing a high level from being reversely charged to the pre-charge position terminal and the second pixel voltage terminal through the dual noise elimination tube module 20 after being turned on, thereby causing the Q point voltage and voltage Gn to be abnormally output.

[0074] Further, in some other feasible embodiments, referring to Figure 5 The signal output end of the signal input unit 101 constitutes the pre-charge position end of the gate driving module 10, and is respectively electrically connected to the control end of the denoising control unit 102, the first end of the pull-up unit 103 and the first end of the denoising management module 30; the second end of the denoising management module 30 is connected between the second end of the pull-up unit 103 and the first passage end of the dual noise cancellation tube module 20, the first end of the denoising control unit 102 is connected between the output end of the dual noise cancellation tube module 20 and the first capacitance end, and the second end of the denoising control unit 102 is electrically connected to the control end of the dual noise cancellation tube module 20; wherein, the first end of the pull-up unit 103 constitutes the first capacitor C1 coupling end of the gate driving module 10, and the second end of the pull-up unit 103 constitutes the second capacitor C2 coupling end of the gate driving module 10.

[0075] In this embodiment, refer to Figure 5 After the signal input unit 101 provided in the present application is turned on, a Q-point voltage is provided to the signal output end of the signal input unit 101 (i.e., the pre-charge end of the gate driving module 10). When the signal CLK connected to the pull-up unit 103 is at a high level, according to the electrical connection between the pre-charge end of the gate driving module 10 and the first end of the pull-up unit 103 (i.e., the coupling end of the first capacitor C1 of the gate driving module 10), the capacitor voltage of the second capacitor C2 in the pull-up unit 103 is superimposed on the Q-point voltage, that is, the Q-point voltage is coupled into a higher voltage through the second capacitor C2, so that the fifth thin film transistor T5 in the pull-up unit 103 is fully turned on (i.e., the fifth thin film transistor T5 is turned on), so as to pull up the voltage Gn outputted by the second pixel signal end in the pull-up unit 103 to the voltage CLK corresponding to the signal CLK, so that the current pixel row electrically connected to the second pixel signal end starts to be charged, thereby ensuring that the current pixel row can normally display the current frame picture. In addition, after the current pixel row is charged, the voltage at the Q point and the voltage Gn are pulled down to a low level so that all pixels in the current pixel row are completely turned off.

[0076] It should be noted that when the voltage at the Q point is at a high level, the fourth thin film transistor T4 in the denoising control unit 102 provided in the present application will be turned on, thereby pulling down the signal d outputted from the fourth signal terminal in the denoising control unit 102, so that the dual denoising tube module 20 (i.e. Figure 5 When the current pixel row is fully charged and the voltage at the Q point is at a low level, the fourth thin film transistor T4 in the denoising control unit 102 switches from the on state to the off state. At this time, the signal d outputted from the fourth signal terminal in the denoising control unit 102 remains at a high level, automatically triggering the dual noise elimination tube module 20 (i.e. Figure 5 T6 and T7 shown in the figure are turned on, pulling down the voltage Gn and the Q point voltage respectively.

[0077] The gate drive signal provided in the present application can be understood as the Q-point voltage signal obtained by superimposing the capacitance voltage of the second capacitor C2 in the pull-up unit 103 on the Q-point voltage. In addition, the denoising control unit 102 provided in the present application is used to control the dual denoising tube module 20 (i.e. Figure 5 T6 and T7 shown in the figure are always kept in the off state.

[0078] Further, in some other feasible embodiments, referring to Figure 5The signal input unit 101 includes a third thin film transistor T3 and a first pixel signal terminal; the gate terminal of the third thin film transistor T3 is electrically connected to the first pixel signal terminal, and the first channel terminal of the third thin film transistor T3 is connected to the power supply terminal VDD; the second channel terminal of the third thin film transistor T3 constitutes the signal output terminal of the signal input unit 101, which is electrically connected to the control terminal of the denoising control unit 102, the first terminal of the pull-up unit 103 and the first terminal of the denoising management module 30 respectively.

[0079] In this embodiment, refer to Figure 5 When the gate terminal of the third thin film transistor T3 is connected to the voltage Gn-4 output by the first pixel signal terminal, the third thin film transistor T3 automatically connects the link from the first channel terminal of the third thin film transistor T3 to the second channel terminal of the third thin film transistor T3 in response to the voltage Gn-4, that is, after the third thin film transistor T3 is turned on to pull up the second channel terminal of the third thin film transistor T3 to the power supply terminal VDD electrically connected to the second channel terminal of the third thin film transistor T3, a Q point voltage is provided through the second channel terminal of the third thin film transistor T3 to be input to the control terminal and the upper terminal of the denoising control unit 102. The first end of the pull-up unit 103, since the Q-point voltage at this time is in a high-level state, after determining that the first end of the pull-up unit 103 is connected to the Q-point voltage, the Q-point voltage is coupled into a gate drive signal through the second capacitor C2 in the pull-up unit 103 to provide a charging power supply for the current pixel row, and the control end of the denoising control unit 102 set in the present application will also be synchronously connected to the Q-point voltage representing the high-level state to turn on the fourth thin-film transistor T4 in the denoising control unit 102, thereby pulling down the signal d output by the fourth signal end of the denoising control unit 102, so that the dual noise elimination tube module 20 (i.e. Figure 5 T6 and T7 are shown in the cut-off state.

[0080] It should be noted that the present application sets the first end of the noise reduction management module 30 and the second path end of the third thin-film transistor T3 to form an electrical connection between the signal output end of the signal input unit 101 in order to prevent the signal a representing a high level from being reversely charged to the signal output end of the signal input unit 101 (i.e., the pre-charge end of the gate driving module 10) through the dual noise reduction tube module 20, thereby causing abnormal Q-point voltage output.

[0081] Further, in some feasible embodiments, referring to Figure 5The denoising control unit 102 includes a fourth thin film transistor T4 and a fourth signal terminal; the gate terminal of the fourth thin film transistor T4 constitutes the control terminal of the denoising control unit 102 and is respectively electrically connected to the signal output terminal of the signal input unit 101 and the second passage terminal of the dual noise reduction tube module 20, the first passage terminal of the fourth thin film transistor T4 is connected between the output terminal of the dual noise reduction tube module 20 and the first capacitance terminal, and the control terminal of the dual noise reduction tube module 20 is connected between the second passage terminal of the fourth thin film transistor T4 and the fourth signal terminal; wherein the first passage terminal of the fourth thin film transistor T4 constitutes the first terminal of the denoising control unit 102, and the second passage terminal of the fourth thin film transistor T4 is electrically connected to the connection node of the fourth signal terminal to constitute the second terminal of the denoising control unit 102.

[0082] In this embodiment, refer to Figure 5 If the gate terminal of the fourth thin-film transistor T4 is connected to the Q-point voltage representing a high-level state, the fourth thin-film transistor T4 responds to the Q-point voltage representing a high-level state to turn on the connection link from the first path terminal of the fourth thin-film transistor T4 to the second path terminal of the fourth thin-film transistor T4, so as to pull the signal d output by the fourth signal terminal down to a low level represented by the signal a, thereby ensuring that the dual noise reduction tube module 20 set in the present application is in a cut-off state when the current pixel row is charged.

[0083] Further, in some other feasible embodiments, referring to Figure 5 The pull-up unit 103 includes a fifth thin film transistor T5, a second capacitor C2, a clock signal terminal and a second pixel signal terminal; the gate terminal of the fifth thin film transistor T5 is electrically connected to the signal output terminal of the signal input unit 101 and the first end of the second capacitor C2 respectively, and the connection node where the gate terminal of the fifth thin film transistor T5 is electrically connected to the first end of the second capacitor C2 constitutes the first end of the pull-up unit 103, the first end of the noise reduction management module 30 is connected between the signal output terminal of the signal input unit 101 and the first end of the pull-up unit 103; the second end of the noise reduction management module 30 is connected between the first channel end of the dual noise reduction tube module 20 and the second end of the second capacitor C2, the first channel end of the fifth thin film transistor T5 is connected between the second end of the second capacitor C2 and the second pixel signal terminal, and the second channel end of the fifth thin film transistor T5 is connected to the clock signal terminal, wherein the second end of the second capacitor C2 constitutes the second end of the pull-up unit 103.

[0084] In this embodiment, refer to Figure 5After the signal input unit 101 provided in the present application is turned on, a Q-point voltage is provided to the signal output terminal of the signal input unit 101 (i.e., the pre-charge terminal of the gate driving module 10). When the second channel terminal of the fifth thin film transistor T5 is connected to the signal CLK representing a high level output by the clock signal terminal, the gate terminal of the fifth thin film transistor T5 is electrically connected to the first end of the second capacitor C2 to superimpose the capacitor voltage of the second capacitor C2 on the Q-point voltage connected to the gate terminal of the fifth thin film transistor T5, that is, the Q-point voltage is coupled into a higher voltage through the second capacitor C2 so that the fifth thin film transistor T5 is fully turned on (i.e., the fifth thin film transistor T5 is turned on), so that the voltage Gn output by the second pixel signal terminal is pulled up to the voltage CLK corresponding to the signal CLK, so that the current pixel row electrically connected to the second pixel signal terminal starts to charge, thereby ensuring that the current pixel row can normally display the current frame image.

[0085] Further, in some feasible embodiments, referring to Figure 5 The dual noise elimination tube module includes a sixth thin film transistor T6 and a seventh thin film transistor T7; the gate of the sixth thin film transistor T6 is electrically connected to the gate of the seventh thin film transistor T7; the connection node where the gate of the sixth thin film transistor T6 is electrically connected to the gate of the sixth thin film transistor T6 constitutes the control end of the dual noise elimination tube module, and is electrically connected to the second end of the noise elimination control unit 102; the second end of the noise elimination management module is connected between the second end of the pull-up unit 103 and the first channel end of the sixth thin film transistor T6, the second channel end of the sixth thin film transistor T6 is electrically connected to the first channel end of the seventh thin film transistor T7, and the control end of the noise elimination control unit 102 is connected between the first end of the pull-up unit 103 and the second channel end of the seventh thin film transistor T7; wherein the first channel end of the sixth thin film transistor T6 constitutes the first channel end of the dual noise elimination tube module, the second channel end of the seventh thin film transistor T7 constitutes the second channel end of the dual noise elimination tube module, and the connection node where the second channel end of the sixth thin film transistor T6 is electrically connected to the first channel end of the seventh thin film transistor T7 constitutes the output end of the dual noise elimination tube module.

[0086] In this embodiment, refer to Figure 5The output end of the dual noise reduction tube module 20 provided in the present application is electrically connected to the first end of the first capacitor C1. After the second end of the first capacitor C1 is connected to the high-level signal representing 10V output by the second signal end, it is determined that the terminal voltage of the second end of the capacitor jumps from -10V to the level voltage of the high-level signal, and the level voltage of the high-level signal is 10V. That is to say, when it is determined that the terminal voltage of the second end of the capacitor has a voltage jump of 20V, according to the charge conservation law of the first capacitor C1, the first end of the first capacitor C1 will also have a voltage jump of 20V, that is, the first end of the capacitor The voltage will also jump from 10V to 30V instantly, that is to say, the voltage Vgs=10-30=-20V connected to the connection node of the control end of the dual noise reduction tube module 20 electrically connected to the first capacitor end, so that the IV characteristic of the dual noise reduction tube module 20 drifts to the left during the blank stage of the current frame display, effectively counteracting the natural rightward shift of the IV characteristic of the dual noise reduction tube module 20 caused by long-term use or environmental factors, preventing the decline or failure of the noise reduction performance of the dual noise reduction tube module 20, and thus significantly improving the display performance of the LCD product applied to the gate drive circuit.

[0087] Further, based on the first embodiment of the gate driving circuit of the present application, a second embodiment of the driving method of the gate driving circuit of the present application is proposed, referring to Figure 7 , Figure 7 It is a flow chart of a second embodiment of a driving method of a gate driving circuit of the present application.

[0088] The driving method of the gate driving circuit of the present application is applied to any of the above-mentioned gate driving circuits. The driving method of the gate driving circuit of the present application is executed by a display device applied to the gate driving circuit. The driving method of the gate driving circuit of the present application includes the following implementation steps S10 to S30.

[0089] Step S10: accessing a gate driving signal through the gate driving module 10, and enabling the current pixel row to display the current frame image under the drive of the gate driving signal;

[0090] Step S20: When the current frame is in a blank display stage, the gate driving module 10 is subjected to denoising processing by accessing the denoising signal through the dual denoising tube module 20 .

[0091] In this example, after determining that the gate drive module 10 provided in the present application is connected to the gate drive signal, and driven by the gate drive signal, the current pixel row is enabled to display the current frame image; next, when the current frame image is in the blank stage of display, that is, in the blank gap of the current frame image display, the dual noise reduction tube module 20 provided in the present application automatically intervenes, and uses the noise reduction signal to perform fine noise reduction processing on the gate drive module 10, so as to eliminate potential electrical noise interference, thereby ensuring the display quality of the LCD product.

[0092] Step S30: When the dual noise reduction tube module 20 performs noise reduction processing on the gate driving module 10, the noise reduction management module 30 charges the first capacitor C1 by connecting the capacitor charging signal to the first signal terminal, and after the first capacitor C1 is charged, in response to the high-level signal output by the second signal terminal connected to the second capacitor terminal, the terminal voltage of the first capacitor terminal is charge-conserved according to the level voltage of the high-level signal.

[0093] In this example, since the dual noise reduction tube module 20 will be in a 20V forward bias state during the denoising process, that is, the IV characteristics of the dual noise reduction tube module 20 during the denoising process are shifted to the right. Therefore, the present application is provided with a noise reduction management module 30 to counteract the natural rightward shift of the IV characteristics of the dual noise reduction tube module 20 due to long-term use or environmental factors. Specifically, the present application connects the first capacitor end of the first capacitor C1 between the dual noise reduction tube module 20 and the first signal end. When the dual noise reduction tube module 20 performs denoising on the gate drive module 10, that is, when the dual noise reduction tube module 20 is in the denoising process, the first capacitor C1 is fully charged by connecting the capacitor charging signal output by the first signal end through the first capacitor end of the first capacitor C1 to maximize the charge coupling effect of the first capacitor C1, and after charging is completed, the second signal end is automatically triggered to output a high-level signal representing 10V to the second capacitor end of the first capacitor C1. Before the second signal terminal outputs a high-level signal representing 10V to the second capacitor terminal of the first capacitor C1, the voltages across the first capacitor C1 are respectively a voltage VGH (10V) and a voltage VGL (-10V), wherein the voltage VGH represents the terminal voltage of the first capacitor terminal, and the voltage VGL represents the terminal voltage of the second capacitor terminal. When the second capacitor terminal of the first capacitor C1 is connected to the high-level signal representing 10V outputted from the second signal terminal, it is determined that the terminal voltage of the second capacitor terminal jumps from -10V to the level voltage of the high-level signal, and the level voltage of the high-level signal is 10V. That is to say, when it is determined that the terminal voltage of the second capacitor terminal has a voltage jump of 20V, according to the first capacitor C 1, the first end of the first capacitor C1 will also experience a 20V voltage jump, that is, the voltage of the first end will also jump from 10V to 30V instantly, that is, the voltage Vgs=10-30=-20V connected to the connection node of the dual noise reduction tube module 20 electrically connected to the first end of the capacitor, so that the IV characteristic of the dual noise reduction tube module 20 drifts to the left during the blank stage of the current frame display, effectively counteracting the natural rightward shift of the IV characteristic of the dual noise reduction tube module 20 due to long-term use or environmental factors, preventing the dual noise reduction tube module 20 from declining or failing in noise reduction performance, thereby significantly improving the display performance of the LCD product applied to the gate drive circuit.

[0094] In summary, the present application can effectively avoid the double noise reduction tube module 20 (i.e. Figure 5 In the process of reliability testing (i.e., double 85 testing) of T6 and T7 shown in the figure, the IV characteristic shifts to the right, resulting in a decrease or failure of the noise reduction function, thereby causing display abnormality. The IV characteristic of the dual noise reduction tube module 20 can be maintained to maintain the noise reduction capability, thereby improving the display performance of the LCD product applied to the gate drive circuit.

[0095] In addition, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes any of the above-mentioned gate driving circuits.

[0096] In addition, the present application also provides a display device. Figure 8 , Figure 8 1 is a schematic diagram of the structure of a display device according to an embodiment of the present application. The display device according to the embodiment of the present application may be a device for locally running a driving method of a gate driving circuit.

[0097] like Figure 8 As shown, the display device of the embodiment of the present application may include: a display panel, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen, an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0098] The memory 1005 is arranged on the display device body, and a program is stored in the memory 1005, and the program implements the corresponding operation when it is executed by the processor 1001. The memory 1005 is also used to store parameters for use by the display device. The memory 1005 can be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0099] Those skilled in the art will understand that Figure 8 The display device structure shown in the figure does not constitute a limitation on the display device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0100] like Figure 8 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a driver program of a gate driving circuit.

[0101] exist Figure 8 In the display device shown, the processor 1001 can be used to call the driver program of the gate driving circuit stored in the memory 1005 and execute the steps of the driving method of the gate driving circuit as described above.

[0102] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0103] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0104] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium such as ROM / RAM, a magnetic disk, or an optical disk as described above, and includes a number of instructions for enabling a display device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0105] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate drive circuit comprises: A gate driving module, used for receiving a gate driving signal and enabling a current pixel row to display a current frame image under the drive of the gate driving signal; A dual noise reduction tube module, the dual noise reduction tube module is electrically connected to the gate driving module, and the dual noise reduction tube module is used to access the noise reduction signal to perform noise reduction processing on the gate driving module when the current frame is in a blank stage of display; A noise reduction management module, wherein the noise reduction management module comprises a first capacitor, wherein the first capacitor end is electrically connected to the dual noise reduction tube module and the first signal end respectively, and the second capacitor end is electrically connected to the second signal end. The noise reduction management module is used to charge the first capacitor by connecting the capacitor charging signal to the first signal end when the dual noise reduction tube module performs noise reduction processing on the gate driving module, and after the first capacitor is charged, in response to the high level signal output by the second signal end connected to the second capacitor end, the terminal voltage of the first capacitor end is subjected to charge conservation adjustment according to the level voltage of the high level signal; wherein, The noise reduction management module also includes a first thin film transistor, a second thin film transistor and a third signal terminal, and the gate driving module includes a pull-up unit; the first channel end of the first thin film transistor constitutes the first end of the noise reduction management module, and is connected between the pre-charge position end of the gate driving module and the first capacitor coupling end of the pull-up unit; the first channel end of the second thin film transistor constitutes the second end of the noise reduction management module, and is connected between the first channel end of the dual noise reduction tube module and the second capacitor coupling end of the pull-up unit; the gate end of the first thin film transistor and the gate end of the second thin film transistor are both electrically connected to the first signal terminal, and the second channel end of the first thin film transistor and the second channel end of the second thin film transistor are both electrically connected to the third signal terminal.

2. The gate driving circuit according to claim 1, characterized in that: The gate driving module also includes a signal input unit and a noise removal control unit; The signal output end of the signal input unit constitutes the pre-charge position end of the gate driving module, and is electrically connected to the control end of the noise reduction control unit, the first capacitor coupling end of the pull-up unit and the first end of the noise reduction management module respectively; The second end of the noise reduction management module is connected between the second capacitor coupling end of the pull-up unit and the first path end of the dual noise reduction tube module, the first end of the noise reduction control unit is connected between the output end of the dual noise reduction tube module and the first capacitor end, and the second end of the noise reduction control unit is electrically connected to the control end of the dual noise reduction tube module.

3. The gate driving circuit according to claim 2, characterized in that: The signal input unit includes a third thin film transistor and a first pixel signal terminal; The gate terminal of the third thin film transistor is electrically connected to the first pixel signal terminal, and the first channel terminal of the third thin film transistor is connected to the power supply terminal; The second channel end of the third thin film transistor constitutes the signal output end of the signal input unit, and is electrically connected to the control end of the noise reduction control unit, the first capacitor coupling end of the pull-up unit and the first end of the noise reduction management module respectively.

4. The gate driving circuit according to claim 2, wherein: The denoising control unit includes a fourth thin film transistor and a fourth signal terminal; The gate end of the fourth thin film transistor constitutes the control end of the noise reduction control unit and is electrically connected to the signal output end of the signal input unit and the second passage end of the dual noise reduction tube module respectively. The first passage end of the fourth thin film transistor is connected between the output end of the dual noise reduction tube module and the first capacitance end. The control end of the dual noise reduction tube module is connected between the second passage end of the fourth thin film transistor and the fourth signal end. The first channel end of the fourth thin film transistor constitutes a first end of the denoising control unit, and the second channel end of the fourth thin film transistor is electrically connected to a connection node of the fourth signal end to constitute a second end of the denoising control unit.

5. The gate driving circuit according to claim 2, wherein: The pull-up unit includes a fifth thin film transistor, a second capacitor, a clock signal terminal and a second pixel signal terminal; The gate terminal of the fifth thin film transistor is electrically connected to the signal output terminal of the signal input unit and the first terminal of the second capacitor respectively, the connection node where the gate terminal of the fifth thin film transistor is electrically connected to the first terminal of the second capacitor constitutes the first capacitor coupling terminal of the pull-up unit, and the first terminal of the noise elimination management module is connected between the signal output terminal of the signal input unit and the first capacitor coupling terminal of the pull-up unit; The second end of the noise reduction management module is connected between the first channel end of the dual noise reduction tube module and the second end of the second capacitor, the first channel end of the fifth thin film transistor is connected between the second end of the second capacitor and the second pixel signal end, and the second channel end of the fifth thin film transistor is connected to the clock signal end, wherein the second end of the second capacitor constitutes the second capacitive coupling end of the pull-up unit.

6. The gate driving circuit according to claim 2, wherein: The dual noise reduction tube module includes a sixth thin film transistor and a seventh thin film transistor; The gate of the sixth thin film transistor is electrically connected to the gate of the seventh thin film transistor; The gate of the sixth thin film transistor is electrically connected to the connection node of the gate of the sixth thin film transistor, forming the control end of the dual noise elimination tube module, and is electrically connected to the second end of the noise elimination control unit; The second end of the noise elimination management module is connected between the second capacitive coupling end of the pull-up unit and the first channel end of the sixth thin film transistor, the second channel end of the sixth thin film transistor is electrically connected to the first channel end of the seventh thin film transistor, and the control end of the noise elimination control unit is connected between the first capacitive coupling end of the pull-up unit and the second channel end of the seventh thin film transistor; wherein, The first channel end of the sixth thin film transistor constitutes the first channel end of the dual noise reduction tube module, the second channel end of the seventh thin film transistor constitutes the second channel end of the dual noise reduction tube module, and the connection node of the second channel end of the sixth thin film transistor electrically connected to the first channel end of the seventh thin film transistor constitutes the output end of the dual noise reduction tube module.

7. A driving method for a gate driving circuit, characterized in that: The driving method of the gate driving circuit is applied to the gate driving circuit according to any one of claims 1 to 6, and the driving method of the gate driving circuit comprises: Accessing a gate drive signal through a gate drive module, and enabling the current pixel row to display a current frame image under the drive of the gate drive signal; When the current frame is in a blank stage of display, the gate driving module is subjected to denoising processing by accessing the denoising signal through the dual denoising tube module; When the dual noise elimination tube module performs noise elimination processing on the gate driving module, the noise elimination management module charges the first capacitor by connecting the capacitor charging signal to the first signal terminal, and after the first capacitor is charged, in response to the high level signal output by the second signal terminal connected to the second capacitor terminal, the terminal voltage of the first capacitor terminal is subjected to charge conservation adjustment according to the level voltage of the high level signal; wherein, The noise reduction management module also includes a first thin film transistor, a second thin film transistor and a third signal terminal, and the gate driving module includes a pull-up unit; the first channel end of the first thin film transistor constitutes the first end of the noise reduction management module, and is connected between the pre-charge position end of the gate driving module and the first capacitor coupling end of the pull-up unit; the first channel end of the second thin film transistor constitutes the second end of the noise reduction management module, and is connected between the first channel end of the dual noise reduction tube module and the second capacitor coupling end of the pull-up unit; the gate end of the first thin film transistor and the gate end of the second thin film transistor are both electrically connected to the first signal terminal, and the second channel end of the first thin film transistor and the second channel end of the second thin film transistor are both electrically connected to the third signal terminal.

8. A display panel, characterized in that: The display panel comprises a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate comprises the gate driving circuit according to any one of claims 1 to 6.

9. A display device, characterized in that: The display device includes the display panel described in claim 8, a memory, a processor, and a driver program for a gate drive circuit stored in the memory and executable on the processor, and the processor implements the steps of the driving method for the gate drive circuit described in claim 7 when executing the driver program for the gate drive circuit.

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