Signal optimization method, computer program product, device and medium for memory chip

Abstract

The present application provides a signal optimization method, computer program product, device and medium for a memory chip, including: obtaining the topological structure of the memory chip to confirm the partition chip contained in the memory chip and the partition chip select signal corresponding to the partition chip; generating a termination resistor combination value list corresponding to each partition chip according to the partition chip select signal and the preset selection configuration rule; selecting an idle partition chip and configuring the termination resistor in the memory chip according to the termination resistor combination value list to optimize the memory chip signal. The configurable number of ODT parameter values ​​is increased, the ODT step accuracy is improved, and the signal quality is further optimized by adding independent configuration of read and write parameters.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a signal optimization method, system and device for a memory chip. Background Art

[0002] With the continuous development of information technology, people have more and more stringent requirements for the storage and reading of information, and therefore the capacity requirements and access rate requirements for SSD storage media are also getting higher and higher. To meet this requirement, SSD products increase the capacity by increasing the number of memory chip loads when designing the memory chip (NAND, Electrically Erasable Programmable Read Only Memory, EEPROM) bus, and simultaneously improve the operating rate of the memory chip signal.

[0003] Existing technical solutions still rely on topological optimization of memory chips, but relying solely on topological optimization can no longer meet the requirements. Therefore, a signal optimization method based on termination resistor configuration is urgently needed to solve the above technical problems. Summary of the invention

[0004] Based on this, it is necessary to provide a signal optimization method, computer program product, device and medium for a memory chip to address the above technical problems.

[0005] In a first aspect, the present application provides a signal optimization method for a memory chip, the method comprising:

[0006] Acquire the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip select signal corresponding to the partition chip;

[0007] Generate a list of termination resistance combination values ​​corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0008] An idle partition chip is selected and, according to the termination resistor combination value list, the termination resistors in the memory chip are configured to optimize the memory chip signal.

[0009] In some embodiments, the generating a termination resistor combination value list corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule includes:

[0010] Obtain the number of partition chip select signals contained in each partition chip, and determine the number of selectable partition chip select signals;

[0011] Selecting a first partition chip select signal that matches the number of selectable chip select signals;

[0012] The termination resistance value on the signal line corresponding to the first partition chip selection signal is configured to generate a termination resistance combination value list corresponding to each partition chip.

[0013] In some embodiments, the step of obtaining the number of partition chip select signals contained in each partition chip and determining the number of selectable partition chip select signals includes:

[0014] If the number of partition chip select signals contained in the partition chip is greater than 2, determining the number of the optional partition chip select signals matched by the partition chip according to the difference between the number of partition chip select signals and 1;

[0015] If the number of partition chip select signals included in the partition chip is equal to 2, determining that the number of optional partition chip select signals matches the partition chip select signals included in the partition chip;

[0016] If the number of partition chip selection signals contained in the partition chip is equal to 1, then the generation of the termination resistance combination value list corresponding to the partition chip is stopped.

[0017] In some embodiments, selecting the first partition chip select signal that matches the number of selectable chip select signals includes:

[0018] If the number of partition chip select signals contained in the partition chip is greater than 2, for each number of partition chip select signals, a partition chip select signal matching the number of optional partition chip select signals in the partition chip is randomly selected as the first partition chip select signal;

[0019] If the number of partition chip select signals included in the partition chip is equal to 2, all the partition chip select signals in the partition chip are selected as first partition chip select signals.

[0020] In some embodiments, configuring the termination resistance value on the signal line corresponding to the first partition chip select signal to generate a termination resistance combination value list corresponding to each partition chip includes:

[0021] Acquire multiple termination resistor initial values ​​included in the termination resistor default value list to construct a termination resistor value set corresponding to each first partition chip select signal;

[0022] A set of termination resistance values ​​corresponding to the first partition chip select signal is input into a nested loop script and the nested loop script is run to generate a list of termination resistance combination values ​​corresponding to the partition chip.

[0023] In some embodiments, configuring the termination resistance value on the signal line corresponding to the first partition chip select signal to generate a termination resistance combination value list corresponding to each partition chip includes:

[0024] Acquire multiple termination resistor initial values ​​included in the termination resistor default value list to construct a termination resistor value set corresponding to each first partition chip select signal;

[0025] A set of termination resistance values ​​corresponding to the first partition chip select signal is input into a recursive loop script and the recursive loop script is run to generate a list of termination resistance combination values ​​corresponding to the partition chip.

[0026] In some embodiments, the method further comprises:

[0027] Obtaining the generated termination resistance combination value list;

[0028] Merging the same termination resistor combination values ​​in the termination resistor combination value list;

[0029] The termination resistor combination value list is sorted according to the magnitude of the termination resistor combination value.

[0030] In some embodiments, the merging of the same termination resistor combination values ​​in the termination resistor combination value list comprises:

[0031] Comparing the first partition chip select signal configurations matched with the same termination resistance combination value, the first partition chip select configurations including the number of first partition chip select signals and the termination resistance values ​​corresponding to the first partition chip select signals;

[0032] If there are duplicate first partition chip select signal configurations that match the same termination resistor combination value, merging the duplicate first partition chip select signal configurations;

[0033] If there is no duplication of the first partition chip select signal configuration matching the same termination resistor combination value, a plurality of different partition chip select signals matching the same termination resistor combination value are retained.

[0034] In some embodiments, selecting an idle partition chip and configuring the termination resistor in the memory chip according to the termination resistor combination value list to optimize the memory chip signal includes:

[0035] In response to detecting the read-write optimization configuration, selecting an idle partition chip remote from the target partition chip corresponding to the read-write operation received by the memory chip;

[0036] According to a first preset rule, determining a target termination resistor combination value in the termination resistor combination value list that matches the idle partition chip;

[0037] The termination resistance value on the signal line corresponding to the partition chip select signal contained in the idle partition chip is configured according to the target termination resistance combination value to optimize the memory chip signal.

[0038] In some embodiments, selecting an idle partition chip and configuring the termination resistor in the memory chip according to the termination resistor combination value list to optimize the memory chip signal includes:

[0039] In response to detecting a multi-load optimization configuration, selecting a first partition chip at a far end of a target partition chip and a second partition chip at a near end of the target partition chip corresponding to a read operation received by the memory chip;

[0040] Determine the idle partition chip according to the first partition chip and the second partition chip;

[0041] According to a second preset rule, determining a target termination resistor combination value in the termination resistor combination value list that matches the idle partition chip;

[0042] The termination resistance value on the signal line corresponding to the partition chip select signal contained in the idle partition chip is configured according to the target termination resistance combination value to optimize the memory chip signal.

[0043] In some embodiments, searching the termination resistor combination value list for a target termination resistor combination value that matches the idle partition chip according to the second preset rule includes:

[0044] Generate the combination configuration list according to all the termination resistance combination values ​​included in the termination resistance combination value list, wherein the combination configuration list includes all combination configurations of the termination resistance combination values ​​configurable by the first partition chip and the termination resistance combination values ​​configurable by the second partition chip;

[0045] According to the combination configuration list, the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the first partition chip and the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the second partition chip are configured one by one, and the configured signal lines are simulated to generate simulation results to be selected, wherein the simulation results to be selected represent the quality of the signals to be selected transmitted on the signal lines;

[0046] Determine that the termination resistance combination value of the first partition chip included in the combination configuration matching the candidate simulation result that represents the best candidate signal quality is a target termination resistance combination value matching the first partition chip;

[0047] The termination resistance combination value of the second partition chip included in the combination configuration matching the candidate simulation result that represents the best candidate signal quality is determined to be the target termination resistance combination value matching the second partition chip.

[0048] In some embodiments, searching the termination resistor combination value list for a target termination resistor combination value that matches the idle partition chip according to the first preset rule includes:

[0049] Sequentially read the termination resistor combination value list to obtain a first termination resistor combination value;

[0050] According to the read first termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured;

[0051] Simulating the signal line to obtain a first simulation result when the idle partition chip is configured as a first terminal resistance combination value, wherein the first simulation result represents a quality of a first signal transmitted on the signal line;

[0052] comparing the first signal quality with a preset signal quality represented by a preset simulation result;

[0053] If the first signal quality is better than the preset signal quality, the first termination resistance combination value is determined to be a target termination resistance combination value.

[0054] In some embodiments, searching the termination resistor combination value list for a target termination resistor combination value that matches the idle partition chip according to the first preset rule includes:

[0055] Sequentially read the termination resistor combination value list to obtain a first termination resistor combination value;

[0056] According to the read first termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured, and the first termination resistance combination value is defined as a target termination resistance combination value;

[0057] Simulating the signal line to obtain a first simulation result when the idle partition chip is configured as a target termination resistance combination value;

[0058] Perform the first operation until the quality of the first signal transmitted on the signal line represented by the first simulation result is better than the quality of the second signal transmitted on the signal line represented by the generated second simulation result;

[0059] The first operation includes:

[0060] Sequentially read the second termination resistor combination value adjacent to the target termination resistor combination value in the termination resistor combination value list;

[0061] According to the read second termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured;

[0062] Simulating the signal line to obtain a second simulation result when the idle partition chip is configured with a second terminal resistance combination value;

[0063] If the second signal quality transmitted on the signal line represented by the second simulation result is better than the first signal quality transmitted on the signal line represented by the first simulation result, the second termination resistance combination value is updated to the target termination resistance combination value.

[0064] In some embodiments, searching the termination resistor combination value list for a target termination resistor combination value that matches the idle partition chip according to the first preset rule includes:

[0065] Read all the termination resistor combination values ​​included in the termination resistor combination value list;

[0066] For all the read termination resistance combination values, configure the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the idle partition chips one by one and simulate the configured signal lines;

[0067] Acquire a candidate simulation result corresponding to a termination resistance value on a signal line corresponding to a partition chip select signal of the idle partition chip configured according to each termination resistance combination value, wherein the candidate simulation result represents a quality of the candidate signal transmitted on the signal line;

[0068] The termination resistance combination value corresponding to the candidate simulation result that represents the best quality of the candidate signal is determined as the target termination resistance combination value.

[0069] In some embodiments, comparing the first signal quality with a preset signal quality includes:

[0070] Obtaining an eye height and an eye width of a first eye diagram corresponding to the first simulation result;

[0071] Obtaining an eye height and an eye width of a preset eye diagram corresponding to the preset simulation result;

[0072] Comparing an eye height of a first eye diagram corresponding to the first simulation result with an eye height of a preset eye diagram corresponding to a preset simulation result to obtain a first comparison result;

[0073] Comparing an eye width of a first eye diagram corresponding to the first simulation result with an eye width of a preset eye diagram corresponding to a preset simulation result to obtain a second comparison result;

[0074] Whether the first signal quality is better than the preset signal quality is determined according to the first comparison result and the second comparison result.

[0075] In some embodiments, judging whether the first signal quality is better than the preset signal quality according to the first comparison result and the second comparison result includes:

[0076] If the first comparison result is that the eye height of the first eye diagram is higher than the eye height of the preset eye diagram, and the second comparison result is that the eye width of the first eye diagram is wider than the eye width of the preset eye diagram, then it is determined that the first signal quality is better than the preset signal quality;

[0077] If the first comparison result is that the eye height of the first eye diagram is lower than the eye height of the preset eye diagram, and the second comparison result is that the eye width of the first eye diagram is narrower than the eye width of the preset eye diagram, it is determined that the preset signal quality is better than the first signal quality.

[0078] In some embodiments, the method comprises:

[0079] Establishing a signal line model according to the transmission line module, characteristic impedance and interconnection line length of the memory chip;

[0080] According to the signal line model, the signal line in the memory chip is simulated to obtain an eye diagram representing the quality of the signal transmitted on the signal line.

[0081] In a second aspect, the present application provides a signal optimization system for a memory chip, the system comprising:

[0082] A processing module, used for acquiring the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip selection signal corresponding to the partition chip;

[0083] The processing module is further used to generate a termination resistance combination value list corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0084] The configuration module is used to select an idle partition chip and configure the termination resistor in the memory chip according to the termination resistor combination value list to optimize the memory chip signal.

[0085] In a third aspect, the present application provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, the following steps are implemented:

[0086] Acquire the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip select signal corresponding to the partition chip;

[0087] Generate a list of termination resistance combination values ​​corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0088] An idle partition chip is selected and, according to the termination resistor combination value list, the termination resistors in the memory chip are configured to optimize the memory chip signal.

[0089] In a fourth aspect, the present application provides an electronic device, the electronic device comprising:

[0090] one or more processors;

[0091] and a memory associated with one or more processors, the memory being used to store program instructions, which, when read and executed by the one or more processors, perform the following operations:

[0092] Acquire the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip select signal corresponding to the partition chip;

[0093] Generate a list of termination resistance combination values ​​corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0094] An idle partition chip is selected and, according to the termination resistor combination value list, the termination resistors in the memory chip are configured to optimize the memory chip signal.

[0095] In a fifth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program enables a computer to perform the following operations:

[0096] Acquire the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip select signal corresponding to the partition chip;

[0097] Generate a list of termination resistance combination values ​​corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0098] An idle partition chip is selected and, according to the termination resistor combination value list, the termination resistors in the memory chip are configured to optimize the memory chip signal.

[0099] The beneficial effects achieved by this application are:

[0100] The present application provides a signal optimization method for a memory chip, comprising: obtaining the topological structure of the memory chip to confirm the partition chip contained in the memory chip and the partition chip select signal corresponding to the partition chip; generating a termination resistor combination value list corresponding to each partition chip according to the partition chip select signal and a preset selection configuration rule; selecting an idle partition chip and configuring the termination resistor in the memory chip according to the termination resistor combination value list to optimize the memory chip signal. The configurable number of ODT parameter values ​​is increased, the ODT step accuracy is improved, and the signal quality is further optimized by adding independent configuration of read and write parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0101] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0102] Figure 1 It is a schematic diagram of an existing memory chip structure provided by an embodiment of the present application;

[0103] Figure 2 This is a schematic diagram of an existing termination resistor configuration provided in an embodiment of the present application;

[0104] Figure 3 It is a combination schematic diagram provided in an embodiment of the present application;

[0105] Figure 4 It is a schematic diagram of the data flow of read and write operations provided in an embodiment of the present application;

[0106] Figure 5 It is a configuration correspondence diagram of the conventional solution provided in the embodiment of the present application and the solution disclosed in the present application;

[0107] Figure 6 This is a simulation effect eye diagram provided by an embodiment of the present application;

[0108] Figure 7 is a schematic diagram of a multi-load ODT configuration provided in an embodiment of the present application;

[0109] Figure 8 is a schematic diagram of a signal optimization method provided in an embodiment of the present application;

[0110] Fig. 9 This is a system architecture diagram of a signal optimization method provided in an embodiment of the present application;

[0111] Fig.10 This is a diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0112] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0113] It should be understood that in the description of the present application, unless the context clearly requires otherwise, words such as "include", "comprises", and the like in the entire specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, the meaning of "including but not limited to".

[0114] It should also be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0115] It should be noted that the terms "S1", "S2", etc. are only used for the purpose of describing the steps, and do not specifically refer to the order or sequence, nor are they used to limit the present application. They are only for the convenience of describing the method of the present application, and cannot be understood as indicating the order of the steps. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0116] According to the background technology, memory chips are usually defined by Target (partition chip) / CE (partition chip select signal) / LUN (logical unit) according to their internal structure. Figure 1 As shown, taking ODP NAND as an example, a single NAND particle contains two Targets, and each Target contains two CEs. The existing technology usually performs No-Target ODT configuration in units of Target. Since the No-Target ODT parameter value is only configured during the initialization of the main control chip (PHY), and all memory chips in the same channel can only use the same value for configuration in the read and write states, it cannot be dynamically modified during the read and write process.

[0117] The existing technology also has the following problems: it only supports a few existing fixed value configurations, with a small number of values ​​and a large stepping precision; since the read and write operation signals flow in opposite directions, the same configuration parameters cannot guarantee the simultaneous optimization of read and write operations; in multiple No-Target ODT configuration scenarios, multiple No-Target ODTs can only be configured to the same value, and it is impossible to flexibly configure a combination of high and low values. Figure 2 As shown in the existing On-Die Termination (ODT) configuration diagram, when Target3 is in working state, the No-Target ODT of Target1 and Target4 can only be configured to the same 50 ohm.

[0118] In response to the problems existing in the prior art, the present application implements a more flexible NAND ODT strategy solution by adding an ODT logic strategy form based on CE + a multi-CE combination method + a new read-write independent parameter configuration; the read-write independent configuration is implemented to realize the bidirectional signal optimization ODT strategy and improve the NAND rate limit; the ODT logic strategy form based on CE + the logic method of multiple CE combinations can realize high and low combination logic strategies and finer ODT layout accuracy, which can significantly improve the NAND signal rate in large-capacity and high-speed scenarios.

[0119] Embodiment 1

[0120] The embodiment of the present application provides a method for optimizing the signal of a memory chip. Specifically, the method disclosed in the embodiment of the present application is used to optimize the signal transmitted by the memory chip, including the following contents:

[0121] S1. Obtain the topological structure of the memory chip to confirm the partition chips included in the memory chip and the partition chip select signals corresponding to the partition chips.

[0122] Specifically, by acquiring the topological structure of the memory chip and confirming the number of partition chips and the number of partition chip select signals contained in the memory chip, it is convenient to confirm whether the memory chip can generate a termination resistance combination value and the specific termination resistance combination value.

[0123] S2. Generate a list of termination resistance combination values ​​corresponding to each partition chip according to the partition chip selection signal and the preset selection configuration rule.

[0124] Specifically, according to the partition chip select signal and the preset selection configuration rule, a termination resistor combination value list corresponding to each partition chip is generated, including: obtaining the number of partition chip select signals contained in each partition chip, determining the number of optional partition chip select signals; selecting the first partition chip select signal that matches the number of optional chip select signals; configuring the termination resistor value on the signal line corresponding to the first partition chip select signal to generate a termination resistor combination value list corresponding to each partition chip. It can be understood that, as shown in Table 1, the termination resistor combination value list includes the selected partition chip select signal and the corresponding configured termination resistor initial value and the termination resistor combination value generated by the final combination.

[0125] Among them, the number of partition chip select signals contained in each partition chip is obtained, and the number of optional partition chip select signals is determined, including: if the number of partition chip select signals contained in the partition chip is greater than 2, then the number of optional partition chip select signals matching the partition chip is determined according to the difference between the number of partition chip select signals and 1, wherein the number of optional partition chip select signals represents the number of partition chip select signals that can be selected at one time, for example, when there are four partition chip select signals, the number of optional partition chip select signals is 3, and the specific numbers of optional partition chip select signals are 2, 3, and 4 respectively; if the number of partition chip select signals contained in the partition chip is equal to 2, then it is determined that the number of optional partition chip select signals matches the partition chip contained in the partition chip, that is, the number of optional partition chip select signals is 2; if the number of partition chip select signals contained in the partition chip is equal to 1, then the generation of the list of termination resistance combination values ​​corresponding to the partition chip is stopped, that is, the termination resistance combination cannot be performed to generate a new termination resistance combination value at this time. The number of optional partition chip select signals is determined according to the partition chip select signal, and the combinable partition chip select signal is further selected according to the number of optional partition chip select signals. The initial value of the termination resistance included in the original termination resistance default value list is combined to generate a new termination resistance value, thereby expanding the configurable number of ODT parameters and improving the stepping accuracy.

[0126] Among them, selecting the first partition chip select signal that matches the number of optional chip select signals includes: if the number of partition chip select signals contained in the partition chip is greater than 2, for each number of partition chip select signals, randomly selecting the partition chip select signal that matches the number of optional partition chip select signals in the partition chip as the first partition chip select signal, for example, including three partition chip select signals CE0, CE1 and CE2, when the number of optional partition chip select signals is 2, CE0 and CE1, CE1 and CE2, CE0 and CE2 can be combined; if the number of partition chip select signals contained in the partition chip is equal to 2, selecting all partition chip select signals in the partition chip as the first partition chip select signal.

[0127] Among them, in one of the implementation scenarios, the termination resistance value on the signal line corresponding to the first partition chip select signal is configured to generate a list of termination resistance combination values ​​corresponding to each partition chip, including: obtaining multiple termination resistance initial values ​​contained in the termination resistance default value list to construct a set of termination resistance values ​​corresponding to each first partition chip select signal; inputting the set of termination resistance values ​​corresponding to the first partition chip select signal into a nested loop script and running the nested loop script to generate a list of termination resistance combination values ​​corresponding to the partition chip.

[0128] Among them, in one of the implementation scenarios, the termination resistance value on the signal line corresponding to the first partition chip select signal is configured to generate a termination resistance combination value list corresponding to each partition chip, including: obtaining multiple termination resistance initial values ​​contained in the termination resistance default value list to construct a termination resistance value set corresponding to each first partition chip select signal; inputting the termination resistance value set corresponding to the first partition chip select signal into a recursive loop script and running the recursive loop script to generate a termination resistance combination value list corresponding to the partition chip. It can be understood that the specific nested loop script and the programming logic of the recursive loop script are common knowledge in the art, and this application will not be expanded here. Based on the nested loop and recursive method, all combinations of numerical values ​​in the set are generated, and the automatic combination of different termination resistance combination values ​​is realized by writing scripts, which saves labor costs and greatly improves the speed of generating the termination resistance combination value list.

[0129] exist Figure 2 In the specific implementation scenario of the NAND topology shown in the figure, the conventional No-Target ODT value only includes seven fixed configurations of 37.5ohom / 50ohom / 75ohom / 100ohom / 150ohom / 300ohom / OFF. This practical application adopts a combination of multiple CEs to generate the No-Target ODT value. A single DQ link load includes two CEs, that is, one partition chip (Target) includes two partition chip select signals CE0 and CE1. At this time, Figure 3 As shown, by combining two CE ODT values, a new ODT value can be generated. For the specific combination method, reference can be made to the nested loop method and recursive loop method disclosed above. The termination resistance value set corresponding to CE0 is {37.5, 50, 75, 100, 150, 300, OFF}, and the termination resistance value set corresponding to CE1 is also expressed as {37.5 / 50 / 75 / 100 / 150 / 300 / OFF}. By combining the two sets, a combination of all the values ​​in the two sets is generated. The specific combined values ​​are shown in Table 1. In this implementation scenario, eight new ODTs can be added.

[0130] Table 1

[0131]

[0132] In some implementation scenarios, in order to facilitate the subsequent use of the termination resistor combination value list, after the termination resistor combination value list is generated as described above, it is also proposed to optimize the termination resistor combination value list: obtain the generated termination resistor combination value list; merge the same termination resistor combination values ​​in the termination resistor combination value list; sort the termination resistor combination value list according to the size of the termination resistor combination value.

[0133] Among them, merging the same termination resistor combination value in the termination resistor combination value list includes: comparing the first partition chip select signal configuration matching the same termination resistor combination value, the first partition chip select configuration including the number of first partition chip select signals and the termination resistor value corresponding to the first partition chip select signal configuration; if there is a duplicate first partition chip select signal configuration matching the same termination resistor combination value, then merging the duplicate first partition chip select signal configuration; if there is no duplicate first partition chip select signal configuration matching the same termination resistor combination value, then retaining multiple different partition chip select signals matching the same termination resistor combination value. By merging the same termination resistor combination values ​​generated based on the same partition chip select configuration, the waste of resources when the termination resistor combination value list is used for subsequent configuration and simulation is avoided; and by sorting the combination value list, the efficiency of determining the target termination resistor combination value in the subsequent determination is improved.

[0134] S3. Select an idle partition chip and configure the termination resistors in the memory chip according to the termination resistor combination value list to optimize the memory chip signal.

[0135] Specifically, in one embodiment, in response to detecting the read / write optimization configuration, select the idle partition chip at the far end of the target partition chip corresponding to the read / write operation received by the memory chip; determine the target termination resistance combination value in the termination resistance combination value list that matches the idle partition chip according to the first preset rule; configure the termination resistance value on the signal line corresponding to the partition chip select signal contained in the idle partition chip according to the target termination resistance combination value to optimize the memory chip signal. It can be understood that the optimization configuration during the read operation is the same as the optimization configuration process during the write operation.

[0136] It is understandable that when designing the signal of a multi-load topology memory chip, multiple branches will produce negative reflections that degrade the signal quality and limit the NAND signal rate. It is usually necessary to perform internal termination of the ODT chip to optimize the configuration to reduce the negative reflection impact of the topology routing branches and thus improve the signal margin. Figure 4 As shown, during write operations, the signal flows from the main control chip to all NAND Targets, and during read operations, the signal flows from Target3 to PHY and other NAND Targets. Since the topological signal flows corresponding to NAND read and write operations are opposite, the required ODT logic strategies are also different. Therefore, the current strategy of sharing No-Target ODT for read and write operations cannot achieve signal quality optimization. Therefore, this embodiment discloses an independent configuration process for read and write operations, adds a parameter configuration during initialization, and independently configures the ODT value in the read and write state to avoid the problem that the ODT strategy for read and write operations cannot be shared, and at the same time achieves simultaneous optimization of read and write operations.

[0137] Specifically, in some implementation scenarios, according to the first preset rule, searching for the target termination resistance combination value that matches the idle partition chip in the termination resistance combination value list includes: sequentially reading the termination resistance combination value list to obtain the first termination resistance combination value; configuring the termination resistance value on the signal line corresponding to the partition chip select signal in the idle partition chip according to the read first termination resistance combination value; simulating the signal line to obtain the first simulation result when the idle partition chip is configured as the first termination resistance combination value, the first simulation result represents the first signal quality transmitted on the signal line; comparing the first signal quality with the preset signal quality represented by the preset simulation result; if the first signal quality is better than the preset signal quality, determining that the first termination resistance combination value is the target termination resistance combination value. Wherein, the preset simulation result is the optimal simulation result in the read operation scenario and the optimal simulation result in the write operation scenario obtained after configuration based on the default termination resistance value, that is, the preset simulation result includes two, namely the first preset simulation result and the second preset simulation result, which correspond to the read operation and the write operation respectively. When comparing the first simulation result, the current optimization scenario needs to be clarified. If it is a read operation optimization configuration, the first simulation result is compared with the first preset simulation result. If it is a write operation optimization configuration, the first simulation result is compared with the second preset simulation result. In the above manner, the termination resistance combination value corresponding to the first simulation result that is better than the existing optimal simulation result is screened out, and the current NAND signal can be optimized. Among them, comparing the first signal quality with the preset preset signal quality includes: obtaining the eye height and eye width of the first eye diagram corresponding to the first simulation result; obtaining the eye height and eye width of the preset eye diagram corresponding to the preset simulation result; comparing the eye height of the first eye diagram corresponding to the first simulation result with the eye height of the preset eye diagram corresponding to the preset simulation result to obtain the first comparison result; comparing the eye width of the first eye diagram corresponding to the first simulation result with the eye width of the preset eye diagram corresponding to the preset simulation result to obtain the second comparison result; judging whether the first signal quality is better than the preset signal quality according to the first comparison result and the second comparison result. If the first comparison result is that the eye height of the first eye diagram is higher than the eye height of the preset eye diagram, and the second comparison result is that the eye width of the first eye diagram is wider than the eye width of the preset eye diagram, then it is determined that the first signal quality is better than the preset signal quality; if the first comparison result is that the eye height of the first eye diagram is lower than the eye height of the preset eye diagram, and the second comparison result is that the eye width of the first eye diagram is narrower than the eye width of the preset eye diagram, then it is determined that the preset signal quality is better than the first signal quality.

[0138] The simulation method includes: establishing a signal line model according to the transmission line module, characteristic impedance and interconnection line length of the memory chip; simulating the signal line in the memory chip according to the signal line model to obtain an eye diagram representing the signal quality transmitted on the signal line. The establishment of the signal line model is a conventional technical means in this field, and this application will not be expanded here. It is understandable that the signal quality can also be detected by other simulation methods, which is not restricted by this application.

[0139] like Figure 5 Taking the topology scenario shown in the figure as an example, the signal eye diagram simulation is performed. Assuming that CE0 is in working state, Write ODT=50ohm is configured for write operation. To reduce the influence of branch reflection, CE4 at the far end of CE0 needs to be enabled. During the read operation, since the master end has turned on ODT, simulation analysis shows that if the same ODT value as the write operation is used, the voltage will be low. Analysis shows that the signal quality is better when a large value No-target ODT is turned on at the NAND end. To reduce the influence of branch reflection, CE4 at the far end of CE0 needs to be enabled, so Read ODT=150ohm is selected. The simulation results are as follows: Figure 6 , where the eye diagram on the left is a signal eye diagram under a conventional solution, and the eye diagram on the right is a signal eye diagram under the solution disclosed in this embodiment. Table 2 specifically shows the read and write ODT configuration logic in this topology scenario.

[0140] Table 2

[0141]

[0142] Specifically, in some implementation scenarios, according to a first preset rule, searching for a target termination resistance combination value that matches the idle partition chip in a termination resistance combination value list includes: sequentially reading the termination resistance combination value list to obtain a first termination resistance combination value; configuring the termination resistance value on the signal line corresponding to the partition chip select signal in the idle partition chip according to the read first termination resistance combination value, and defining the first termination resistance combination value as the target termination resistance combination value; simulating the signal line to obtain a first simulation result when the idle partition chip is configured as the target termination resistance combination value; performing a first operation until the quality of a first signal transmitted on the signal line represented by the first simulation result is better than that of the signal line generated by the production process. The second simulation result represents the second signal quality transmitted on the signal line; wherein the first operation includes: sequentially reading the second termination resistance combination value adjacent to the target termination resistance combination value in the termination resistance combination value list; configuring the termination resistance value on the signal line corresponding to the partition chip select signal in the idle partition chip according to the read second termination resistance combination value; simulating the signal line to obtain the second simulation result when the idle partition chip is configured as the second termination resistance combination value; if the second signal quality transmitted on the signal line represented by the second simulation result is better than the first signal quality transmitted on the signal line represented by the first simulation result, then the second termination resistance combination value is updated to the target termination resistance combination value. Among them, the comparison method of the first signal quality and the second signal quality is the same as the comparison of the first signal quality and the preset signal quality mentioned above, and this application will not be expanded here. In this implementation scenario, by reading the termination resistance combination value in sequence, when the peak value is detected, it is determined that the current termination resistance combination value is the optimal value, that is, the target termination resistance combination value, so as to speed up the determination efficiency of the target termination resistance combination value and reduce the simulation workload.

[0143] Specifically, in some implementation scenarios, according to the first preset rule, the target termination resistance combination value that matches the idle partition chip in the termination resistance combination value list is searched, including: reading all the termination resistance combination values ​​contained in the termination resistance combination value list; for all the termination resistance combination values ​​read out, configuring the termination resistance value on the signal line corresponding to the partition chip select signal in the idle partition chip one by one and simulating the configured signal line; obtaining the simulation result corresponding to the termination resistance value on the signal line corresponding to the partition chip select signal of the idle partition chip configured according to each termination resistance combination value, the simulation result to be selected represents the quality of the selected signal transmitted on the signal line; determining the termination resistance combination value corresponding to the selected simulation result that represents the best quality of the selected signal as the target termination resistance combination value. Among them, the comparison method between the qualities of the selected signals is similar to the comparison between the first signal quality and the preset signal quality, that is, determining the simulation result to be selected corresponding to the eye diagram with the highest eye height and the widest eye width as the optimal simulation result, and the termination resistance combination value corresponding to the optimal simulation result is the target termination resistance combination value, and the specific steps are not expanded in this application. It can be understood that in this implementation scenario, by simulating configurations of all possible terminal resistance combination values, all ODT configurations are covered to find the optimal simulation result with high accuracy.

[0144] Specifically, in one of the embodiments, in response to detecting a multi-load optimization configuration, a first partition chip at the far end of the target partition chip and a second partition chip at the near end of the target partition chip corresponding to the read operation received by the memory chip are selected; the idle partition chip is determined based on the first partition chip and the second partition chip; according to a second preset rule, a target termination resistance combination value in the termination resistance combination value list that matches the idle partition chip is determined; and according to the target termination resistance combination value, the termination resistance value on the signal line corresponding to the partition chip select signal contained in the idle partition chip is configured to optimize the memory chip signal.

[0145] Among them, according to the second preset rule, searching for the target termination resistance combination value that matches the idle partition chip in the termination resistance combination value list includes: generating a combination configuration list according to all the termination resistance combination values ​​contained in the termination resistance combination value list, the combination configuration list including all combination configurations of the termination resistance combination values ​​configurable by the first partition chip and the termination resistance combination values ​​configurable by the second partition chip; according to the combination configuration list, configuring the termination resistance value on the signal line corresponding to the partition chip select signal in the first partition chip and the termination resistance value on the signal line corresponding to the partition chip select signal in the second partition chip one by one, and simulating the configured signal line to generate a candidate simulation result, the candidate simulation result representing the quality of the candidate signal transmitted on the signal line; determining that the termination resistance combination value of the first partition chip contained in the combination configuration matching the candidate simulation result representing the best quality of the candidate signal is the target termination resistance combination value matching the first partition chip; determining that the termination resistance combination value of the second partition chip contained in the combination configuration matching the candidate simulation result representing the best quality of the candidate signal is the target termination resistance combination value matching the second partition chip. Through the termination resistance combination value list and the customized ODT logic strategy, multiple value configurations in multiple ODT scenarios are achieved, which improves the flexibility of ODT parameter configuration.

[0146] In a multi-load topology scenario, a large and a small ODT configuration is usually required to balance the mutual influence between voltage and reflection caused by multiple ODTs. The method disclosed in this embodiment can be used to configure different termination resistors. Figure 7 The NAND topology shown takes the operation of partition chip 3 (target3) as an example. Through the above steps and simulation, the logical combination of ODT with the target termination resistance value of 50ohm at the far end (target4) and 100ohm at the near end (target2) can be determined. Since the reading and writing principles are the same, this example takes the read operation as an example. Through simulation analysis, the corresponding target termination resistance combination values ​​and the corresponding partition chips and partition chip select signals when different channels are working are determined. The read operation form first defines the information of the CE in the working state, including channel / CE / Reversal information. The first column defines the name of the working state channel. The conventional master contains 8 or 16 channels; the second column defines all CEs contained in the channel. The CE name is defined according to the master chip definition. This example refers to Figure 6 A single channel of a one-to-four ODP particle contains eight CEs (CE0-CE7); the third column records whether the corresponding CE has performed a Lane Reversal operation; the subsequent unit columns continue to define the channel _CE in the idle state in the same format. Figure 7Topology, this example assumes that channel 0_CE0 is in working state. According to the simulation results, it can be determined that the near-end branch CE2 50ohm No-Target ODT + far-end branch CE4 50ohm is the optimal configuration in the read operation scenario, and three non-idle CEs need to be enabled at the same time. In order to reduce the impact of branch reflection, it is necessary to enable Active CE0 corresponding to the far-end CE4&CE5 (CE4 / CE5 two 100ohm ODTs are connected in parallel to form a 50ohm termination) and the corresponding near-end CE2 (100ohm). Other channels and CE logic are similar, as shown in Table 3.

[0147] Table 3

[0148]

[0149] This application increases the number of configurable ODT parameter values, achieving an improvement in ODT step accuracy. At the same time, based on simulation analysis, new read and write parameters are independently configured, and signal quality is further optimized to improve the read and write bidirectional signal rate limit; and through the above-mentioned termination resistor combination value list and customized ODT logic strategy, multiple value configurations in multiple ODT scenarios are achieved, which improves the flexibility of ODT parameter configuration. In addition, the extreme speed increase of the back-end NAND signal rate improves the read / write bandwidth performance of SSD products and enhances product competitiveness. At the same time, since the long-stable state signal voltage is only related to the ODT resistance value, the voltage amplitude of the long-stable state waveform of the signal measured by an oscilloscope can be used to distinguish and determine whether the disclosure of this application is adopted.

[0150] Embodiment 2

[0151] Corresponding to the above-mentioned embodiment 1, the present application also provides a signal optimization method in an embodiment, such as Figure 8 As shown, specifically including:

[0152] 810. Acquire a topological structure of a memory chip to confirm partition chips included in the memory chip and partition chip select signals corresponding to the partition chips;

[0153] 820. Generate a termination resistor combination value list corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0154] 830. Select a free partition chip and configure the termination resistors in the memory chip according to the termination resistor combination value list to optimize the memory chip signal.

[0155] Embodiment 3

[0156] Corresponding to the above-mentioned embodiment 1 and embodiment 2, as Fig. 9 As shown, the embodiment of the present application also provides a signal optimization system, including:

[0157] The processing module 910 is used to obtain the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip selection signal corresponding to the partition chip;

[0158] The processing module 910 is further used to generate a termination resistance combination value list corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0159] The configuration module 920 is used to select an idle partition chip and configure the termination resistors in the memory chip according to the termination resistor combination value list to optimize the memory chip signal.

[0160] Embodiment 4

[0161] The present application also provides a computer program, which, when executed by a processor, implements the following method steps:

[0162] Acquire the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip select signal corresponding to the partition chip;

[0163] Generate a list of termination resistance combination values ​​corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0164] An idle partition chip is selected and, according to the termination resistor combination value list, the termination resistors in the memory chip are configured to optimize the memory chip signal.

[0165] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0166] Obtain the number of partition chip select signals contained in each partition chip, and determine the number of selectable partition chip select signals;

[0167] Selecting a first partition chip select signal that matches the number of selectable chip select signals;

[0168] The termination resistance value on the signal line corresponding to the first partition chip selection signal is configured to generate a termination resistance combination value list corresponding to each partition chip.

[0169] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0170] If the number of partition chip select signals contained in the partition chip is greater than 2, determining the number of the optional partition chip select signals matched by the partition chip according to the difference between the number of partition chip select signals and 1;

[0171] If the number of partition chip select signals included in the partition chip is equal to 2, determining that the number of optional partition chip select signals matches the partition chip select signals included in the partition chip;

[0172] If the number of partition chip selection signals contained in the partition chip is equal to 1, then the generation of the termination resistance combination value list corresponding to the partition chip is stopped.

[0173] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0174] If the number of partition chip select signals contained in the partition chip is greater than 2, for each number of partition chip select signals, a partition chip select signal matching the number of optional partition chip select signals in the partition chip is randomly selected as the first partition chip select signal;

[0175] If the number of partition chip select signals included in the partition chip is equal to 2, all the partition chip select signals in the partition chip are selected as first partition chip select signals.

[0176] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0177] Acquire multiple termination resistor initial values ​​included in the termination resistor default value list to construct a termination resistor value set corresponding to each first partition chip select signal;

[0178] A set of termination resistance values ​​corresponding to the first partition chip select signal is input into a nested loop script and the nested loop script is run to generate a list of termination resistance combination values ​​corresponding to the partition chip.

[0179] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0180] Acquire multiple termination resistor initial values ​​included in the termination resistor default value list to construct a termination resistor value set corresponding to each first partition chip select signal;

[0181] A set of termination resistance values ​​corresponding to the first partition chip select signal is input into a recursive loop script and the recursive loop script is run to generate a list of termination resistance combination values ​​corresponding to the partition chip.

[0182] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0183] Obtaining the generated termination resistance combination value list;

[0184] Merging the same termination resistor combination values ​​in the termination resistor combination value list;

[0185] The termination resistor combination value list is sorted according to the magnitude of the termination resistor combination value.

[0186] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0187] Comparing the first partition chip select signal configurations matched with the same termination resistance combination value, the first partition chip select configurations including the number of first partition chip select signals and the termination resistance values ​​corresponding to the first partition chip select signals;

[0188] If there are duplicate first partition chip select signal configurations that match the same termination resistor combination value, merging the duplicate first partition chip select signal configurations;

[0189] If there is no duplication of the first partition chip select signal configuration matching the same termination resistor combination value, a plurality of different partition chip select signals matching the same termination resistor combination value are retained.

[0190] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0191] In response to detecting the read-write optimization configuration, selecting an idle partition chip remote from the target partition chip corresponding to the read-write operation received by the memory chip;

[0192] According to a first preset rule, determining a target termination resistor combination value in the termination resistor combination value list that matches the idle partition chip;

[0193] The termination resistance value on the signal line corresponding to the partition chip select signal contained in the idle partition chip is configured according to the target termination resistance combination value to optimize the memory chip signal.

[0194] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0195] In response to detecting a multi-load optimization configuration, selecting a first partition chip at a far end of a target partition chip and a second partition chip at a near end of the target partition chip corresponding to a read operation received by the memory chip;

[0196] Determine the idle partition chip according to the first partition chip and the second partition chip;

[0197] According to a second preset rule, determining a target termination resistor combination value in the termination resistor combination value list that matches the idle partition chip;

[0198] The termination resistance value on the signal line corresponding to the partition chip select signal contained in the idle partition chip is configured according to the target termination resistance combination value to optimize the memory chip signal.

[0199] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0200] Generate the combination configuration list according to all the termination resistance combination values ​​included in the termination resistance combination value list, wherein the combination configuration list includes all combination configurations of the termination resistance combination values ​​configurable by the first partition chip and the termination resistance combination values ​​configurable by the second partition chip;

[0201] According to the combination configuration list, the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the first partition chip and the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the second partition chip are configured one by one, and the configured signal lines are simulated to generate simulation results to be selected, wherein the simulation results to be selected represent the quality of the signals to be selected transmitted on the signal lines;

[0202] Determine that the termination resistance combination value of the first partition chip included in the combination configuration matching the candidate simulation result that represents the best candidate signal quality is a target termination resistance combination value matching the first partition chip;

[0203] The termination resistance combination value of the second partition chip included in the combination configuration matching the candidate simulation result that represents the best candidate signal quality is determined to be the target termination resistance combination value matching the second partition chip.

[0204] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0205] Sequentially read the termination resistor combination value list to obtain a first termination resistor combination value;

[0206] According to the read first termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured;

[0207] Simulating the signal line to obtain a first simulation result when the idle partition chip is configured as a first terminal resistance combination value, wherein the first simulation result represents a quality of a first signal transmitted on the signal line;

[0208] comparing the first signal quality with a preset signal quality represented by a preset simulation result;

[0209] If the first signal quality is better than the preset signal quality, the first termination resistance combination value is determined to be a target termination resistance combination value.

[0210] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0211] Sequentially read the termination resistor combination value list to obtain a first termination resistor combination value;

[0212] According to the read first termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured, and the first termination resistance combination value is defined as a target termination resistance combination value;

[0213] Simulating the signal line to obtain a first simulation result when the idle partition chip is configured as a target termination resistance combination value;

[0214] Perform the first operation until the quality of the first signal transmitted on the signal line represented by the first simulation result is better than the quality of the second signal transmitted on the signal line represented by the generated second simulation result;

[0215] The first operation includes:

[0216] Sequentially read the second termination resistor combination value adjacent to the target termination resistor combination value in the termination resistor combination value list;

[0217] According to the read second termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured;

[0218] Simulating the signal line to obtain a second simulation result when the idle partition chip is configured with a second terminal resistance combination value;

[0219] If the second signal quality transmitted on the signal line represented by the second simulation result is better than the first signal quality transmitted on the signal line represented by the first simulation result, the second termination resistance combination value is updated to the target termination resistance combination value.

[0220] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0221] Read all the termination resistor combination values ​​included in the termination resistor combination value list;

[0222] For all the read termination resistance combination values, configure the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the idle partition chips one by one and simulate the configured signal lines;

[0223] Acquire a candidate simulation result corresponding to a termination resistance value on a signal line corresponding to a partition chip select signal of the idle partition chip configured according to each termination resistance combination value, wherein the candidate simulation result represents a quality of the candidate signal transmitted on the signal line;

[0224] The termination resistance combination value corresponding to the candidate simulation result that represents the best quality of the candidate signal is determined as the target termination resistance combination value.

[0225] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0226] Obtaining an eye height and an eye width of a first eye diagram corresponding to the first simulation result;

[0227] Obtaining an eye height and an eye width of a preset eye diagram corresponding to the preset simulation result;

[0228] Comparing an eye height of a first eye diagram corresponding to the first simulation result with an eye height of a preset eye diagram corresponding to a preset simulation result to obtain a first comparison result;

[0229] Comparing an eye width of a first eye diagram corresponding to the first simulation result with an eye width of a preset eye diagram corresponding to a preset simulation result to obtain a second comparison result;

[0230] Whether the first signal quality is better than the preset signal quality is determined according to the first comparison result and the second comparison result.

[0231] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0232] If the first comparison result is that the eye height of the first eye diagram is higher than the eye height of the preset eye diagram, and the second comparison result is that the eye width of the first eye diagram is wider than the eye width of the preset eye diagram, then it is determined that the first signal quality is better than the preset signal quality;

[0233] If the first comparison result is that the eye height of the first eye diagram is lower than the eye height of the preset eye diagram, and the second comparison result is that the eye width of the first eye diagram is narrower than the eye width of the preset eye diagram, it is determined that the preset signal quality is better than the first signal quality.

[0234] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0235] Establishing a signal line model according to the transmission line module, characteristic impedance and interconnection line length of the memory chip;

[0236] According to the signal line model, the signal line in the memory chip is simulated to obtain an eye diagram representing the quality of the signal transmitted on the signal line.

[0237] Embodiment 5

[0238] Corresponding to all the above embodiments, an embodiment of the present application provides an electronic device, including: one or more processors; and a memory associated with the one or more processors, the memory is used to store program instructions, and when the program instructions are read and executed by the one or more processors, the following operations are performed:

[0239] in, Fig.10 The electronic device architecture is shown as an example, which may include a processor 1010, a video display adapter 1011, a disk drive 1012, an input / output interface 1013, a network interface 1014, and a memory 1020. The processor 1010, the video display adapter 1011, the disk drive 1012, the input / output interface 1013, the network interface 1014, and the memory 1020 may be communicatively connected via a bus 1030.

[0240] Among them, the processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc., to execute relevant programs to implement the technical solution provided in this application.

[0241] The memory 1020 can be implemented in the form of ROM (Read Only Memory, writable memory), RAM (Random Access Memory, random access memory), static storage device, dynamic storage device, etc. The memory 1020 can store an operating system 1021 for controlling the execution of the electronic device 1000, and a basic input and output system (BIOS) 1022 for controlling the low-level operations of the electronic device 1000. In addition, a web browser 1023, a data storage management system 1024, and an icon font processing system 1025, etc. can also be stored. The above-mentioned icon font processing system 1025 can be an application program that specifically implements the operations of the aforementioned steps in the embodiment of the present application. In short, when the technical solution provided in the present application is implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0242] The input / output interface 1013 is used to connect the input / output module to realize information input and output. The input / output module can be configured as a component in the device (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0243] The network interface 1014 is used to connect to a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired method (such as USB, network cable, etc.) or a wireless method (such as mobile network, WIFI, Bluetooth, etc.).

[0244] The bus 1030 comprises a pathway for transmitting information between the various components of the device (eg, the processor 1010 , the video display adapter 1011 , the disk drive 1012 , the input / output interface 1013 , the network interface 1014 , and the memory 1020 ).

[0245] In addition, the electronic device 1000 can also obtain information on specific collection conditions from the virtual resource object collection condition information database for use in condition judgment, etc.

[0246] It should be noted that, although the above device only shows a processor 1010, a video display adapter 1011, a disk drive 1012, an input / output interface 1013, a network interface 1014, a memory 1020, a bus 1030, etc., in the specific implementation process, the device may also include other components necessary for normal execution. In addition, it can be understood by those skilled in the art that the above device may also only include components necessary for implementing the solution of the present application, and does not necessarily include all the components shown in the figure.

[0247] It can be seen from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a disk, an optical disk, etc., including several instructions for enabling a computer device (which can be a personal computer, a cloud service end, or a network device, etc.) to execute the methods of various embodiments of the present application or certain parts of the embodiments.

[0248] Embodiment 6

[0249] Corresponding to all the above embodiments, the embodiments of the present application further provide a computer-readable storage medium, characterized in that it stores a computer program, and the computer program enables a computer to perform the following operations:

[0250] Acquire the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip select signal corresponding to the partition chip;

[0251] Generate a list of termination resistance combination values ​​corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule;

[0252] An idle partition chip is selected and, according to the termination resistor combination value list, the termination resistors in the memory chip are configured to optimize the memory chip signal.

[0253] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, in which the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0254] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A signal optimization method for a memory chip, characterized in that: The method comprises: Acquire the topological structure of the memory chip to confirm the partition chip included in the memory chip and the partition chip select signal corresponding to the partition chip; Generate a list of termination resistance combination values ​​corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule; Selecting an idle partition chip and configuring the termination resistors in the memory chip according to the termination resistor combination value list to optimize the memory chip signal; The step of generating a termination resistor combination value list corresponding to each partition chip according to the partition chip selection signal and a preset selection configuration rule includes: Obtain the number of partition chip select signals contained in each partition chip, and determine the number of selectable partition chip select signals; Selecting a first partition chip select signal that matches the number of optional partition chip select signals; The termination resistance value on the signal line corresponding to the first partition chip selection signal is configured to generate a termination resistance combination value list corresponding to each partition chip.

2. The method according to claim 1, characterized in that The obtaining the number of partition chip select signals contained in each partition chip and determining the number of selectable partition chip select signals includes: If the number of partition chip select signals contained in the partition chip is greater than 2, determining the number of the optional partition chip select signals matched by the partition chip according to the difference between the number of partition chip select signals and 1; If the number of partition chip select signals included in the partition chip is equal to 2, determining that the number of optional partition chip select signals matches the partition chip select signals included in the partition chip; If the number of partition chip selection signals contained in the partition chip is equal to 1, then the generation of the termination resistance combination value list corresponding to the partition chip is stopped.

3. The method according to claim 2, characterized in that The selecting a first partition chip select signal matching the number of selectable chip select signals comprises: If the number of partition chip select signals contained in the partition chip is greater than 2, for each number of partition chip select signals, a partition chip select signal matching the number of optional partition chip select signals in the partition chip is randomly selected as the first partition chip select signal; If the number of partition chip select signals included in the partition chip is equal to 2, all the partition chip select signals in the partition chip are selected as first partition chip select signals.

4. The method according to claim 1, characterized in that The configuring the termination resistance value on the signal line corresponding to the first partition chip select signal to generate a termination resistance combination value list corresponding to each partition chip includes: Acquire multiple termination resistor initial values ​​included in the termination resistor default value list to construct a termination resistor value set corresponding to each first partition chip select signal; A set of termination resistance values ​​corresponding to the first partition chip select signal is input into a nested loop script and the nested loop script is run to generate a list of termination resistance combination values ​​corresponding to the partition chip.

5. The method according to claim 1, characterized in that: The configuring the termination resistance value on the signal line corresponding to the first partition chip select signal to generate a termination resistance combination value list corresponding to each partition chip includes: Acquire multiple termination resistor initial values ​​included in the termination resistor default value list to construct a termination resistor value set corresponding to each first partition chip select signal; A set of termination resistance values ​​corresponding to the first partition chip select signal is input into a recursive loop script and the recursive loop script is run to generate a list of termination resistance combination values ​​corresponding to the partition chip.

6. The method according to claim 4 or 5, characterized in that: The method further comprises: Obtaining the generated termination resistance combination value list; Merging the same termination resistor combination values ​​in the termination resistor combination value list; The termination resistor combination value list is sorted according to the magnitude of the termination resistor combination value.

7. The method according to claim 6, characterized in that The same termination resistor combination values ​​in the merging termination resistor combination value list include: Comparing the first partition chip select signal configurations matched with the same termination resistance combination value, the first partition chip select configurations including the number of first partition chip select signals and the termination resistance values ​​corresponding to the first partition chip select signals; If there are duplicate first partition chip select signal configurations that match the same termination resistor combination value, merging the duplicate first partition chip select signal configurations; If there is no duplication of the first partition chip select signal configuration matching the same termination resistor combination value, a plurality of different partition chip select signals matching the same termination resistor combination value are retained.

8. The method according to claim 6, characterized in that The selecting of idle partition chips and configuring the termination resistors in the memory chip according to the termination resistor combination value list to optimize the memory chip signal includes: In response to detecting the read-write optimization configuration, selecting an idle partition chip remote from the target partition chip corresponding to the read-write operation received by the memory chip; According to a first preset rule, determining a target termination resistor combination value in the termination resistor combination value list that matches the idle partition chip; The termination resistance value on the signal line corresponding to the partition chip select signal contained in the idle partition chip is configured according to the target termination resistance combination value to optimize the memory chip signal.

9. The method according to claim 6, characterized in that The selecting of idle partition chips and configuring the termination resistors in the memory chip according to the termination resistor combination value list to optimize the memory chip signal includes: In response to detecting a multi-load optimization configuration, selecting a first partition chip at a far end of a target partition chip and a second partition chip at a near end of the target partition chip corresponding to a read operation received by the memory chip; Determine the idle partition chip according to the first partition chip and the second partition chip; According to a second preset rule, determining a target termination resistor combination value in the termination resistor combination value list that matches the idle partition chip; The termination resistance value on the signal line corresponding to the partition chip select signal contained in the idle partition chip is configured according to the target termination resistance combination value to optimize the memory chip signal.

10. The method according to claim 9, characterized in that The step of searching, according to the second preset rule, the target termination resistor combination value matching the idle partition chip in the termination resistor combination value list comprises: Generate a combination configuration list according to all the termination resistance combination values ​​included in the termination resistance combination value list, wherein the combination configuration list includes all combination configurations of the termination resistance combination values ​​configurable by the first partition chip and the termination resistance combination values ​​configurable by the second partition chip; According to the combination configuration list, the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the first partition chip and the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the second partition chip are configured one by one, and the configured signal lines are simulated to generate simulation results to be selected, wherein the simulation results to be selected represent the quality of the signals to be selected transmitted on the signal lines; Determine that the termination resistance combination value of the first partition chip included in the combination configuration matching the candidate simulation result that represents the best candidate signal quality is a target termination resistance combination value matching the first partition chip; The termination resistance combination value of the second partition chip included in the combination configuration matching the candidate simulation result that represents the best candidate signal quality is determined to be the target termination resistance combination value matching the second partition chip.

11. The method according to claim 8, characterized in that The step of searching, according to the first preset rule, the target termination resistor combination value matching the idle partition chip in the termination resistor combination value list comprises: Sequentially read the termination resistor combination value list to obtain a first termination resistor combination value; According to the read first termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured; Simulating the signal line to obtain a first simulation result when the idle partition chip is configured as a first terminal resistance combination value, wherein the first simulation result represents a quality of a first signal transmitted on the signal line; comparing the first signal quality with a preset signal quality represented by a preset simulation result; If the first signal quality is better than the preset signal quality, the first termination resistance combination value is determined to be a target termination resistance combination value.

12. The method according to claim 8, characterized in that The step of searching, according to the first preset rule, the target termination resistor combination value matching the idle partition chip in the termination resistor combination value list comprises: Sequentially read the termination resistor combination value list to obtain a first termination resistor combination value; According to the read first termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured, and the first termination resistance combination value is defined as a target termination resistance combination value; Simulating the signal line to obtain a first simulation result when the idle partition chip is configured as a target termination resistance combination value; Perform the first operation until the quality of the first signal transmitted on the signal line represented by the first simulation result is better than the quality of the second signal transmitted on the signal line represented by the generated second simulation result; The first operation includes: Sequentially read the second termination resistor combination value adjacent to the target termination resistor combination value in the termination resistor combination value list; According to the read second termination resistance combination value, a termination resistance value on a signal line corresponding to a partition chip select signal in the idle partition chip is configured; Simulating the signal line to obtain a second simulation result when the idle partition chip is configured with a second terminal resistance combination value; If the second signal quality transmitted on the signal line represented by the second simulation result is better than the first signal quality transmitted on the signal line represented by the first simulation result, the second termination resistance combination value is updated to the target termination resistance combination value.

13. The method according to claim 8, characterized in that The step of searching, according to the first preset rule, the target termination resistor combination value matching the idle partition chip in the termination resistor combination value list comprises: Read all the termination resistor combination values ​​included in the termination resistor combination value list; For all the read termination resistance combination values, configure the termination resistance values ​​on the signal lines corresponding to the partition chip select signals in the idle partition chips one by one and simulate the configured signal lines; Acquire a candidate simulation result corresponding to a termination resistance value on a signal line corresponding to a partition chip select signal of the idle partition chip configured according to each termination resistance combination value, wherein the candidate simulation result represents a quality of the candidate signal transmitted on the signal line; The termination resistance combination value corresponding to the candidate simulation result that represents the best quality of the candidate signal is determined as the target termination resistance combination value.

14. The method according to claim 11, characterized in that The comparing the first signal quality with a preset signal quality includes: Obtaining an eye height and an eye width of a first eye diagram corresponding to the first simulation result; Obtaining an eye height and an eye width of a preset eye diagram corresponding to the preset simulation result; Comparing an eye height of a first eye diagram corresponding to the first simulation result with an eye height of a preset eye diagram corresponding to a preset simulation result to obtain a first comparison result; Comparing an eye width of a first eye diagram corresponding to the first simulation result with an eye width of a preset eye diagram corresponding to a preset simulation result to obtain a second comparison result; Whether the first signal quality is better than the preset signal quality is determined according to the first comparison result and the second comparison result.

15. The method according to claim 14, characterized in that The determining whether the first signal quality is better than the preset signal quality according to the first comparison result and the second comparison result includes: If the first comparison result is that the eye height of the first eye diagram is higher than the eye height of the preset eye diagram, and the second comparison result is that the eye width of the first eye diagram is wider than the eye width of the preset eye diagram, then it is determined that the first signal quality is better than the preset signal quality; If the first comparison result is that the eye height of the first eye diagram is lower than the eye height of the preset eye diagram, and the second comparison result is that the eye width of the first eye diagram is narrower than the eye width of the preset eye diagram, it is determined that the preset signal quality is better than the first signal quality.

16. The method according to claim 15, characterized in that The method comprises: Establishing a signal line model according to the transmission line module, characteristic impedance and interconnection line length of the memory chip; According to the signal line model, the signal line in the memory chip is simulated to obtain an eye diagram representing the quality of the signal transmitted on the signal line.

17. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 16 are implemented.

18. An electronic device, characterized in that: The electronic device comprises: one or more processors; And a memory associated with the one or more processors, the memory is used to store program instructions, and when the program instructions are read and executed by the one or more processors, the method of any one of claims 1-16 is executed.

19. A computer-readable storage medium, characterized in that: The computer program stores a computer program, wherein the computer program enables a computer to execute the method according to any one of claims 1 to 16.

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