Semiconductor structure and method of manufacturing the same

Abstract

Disclosed are a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate with a groove; forming a first thin film on the bottom surface of the groove; performing a first ion implantation process on the first thin film to make the first thin film contain first doping ions; forming a second thin film on the surface of the first thin film, the inner wall surface of the groove and a second surface; forming a gate conductive layer in the groove; performing a second ion implantation process on the second thin film on the second surface to make the second thin film on the second surface contain second doping ions; and performing an annealing treatment process on the second thin film and the first thin film to make part of the second thin film contain the first doping ions; the first thin film and the second thin film containing the first doping ions serve as a first source-drain region, the second thin film containing the second doping ions serves as a second source-drain region, and the remaining second thin film serves as a channel region; and the first source-drain region, the second source-drain region and the channel region constitute an active layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used by a general computer system can be divided into dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, which is composed of many repeated memory cells.

[0003] A memory cell generally includes a storage element and a transistor. The drain of the transistor is connected to a bit line structure, and the source is connected to the storage element. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the storage element through the bit line structure or writing the data information into the storage element through the bit line structure for storage.

[0004] Then, the current active layer of the transistor has poor electrical performance, thereby affecting the speed of the memory. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, which at least facilitate to improve the electrical performance of the active layer of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, the present disclosure provides a method for manufacturing a semiconductor structure. The method comprises: providing a substrate having a recess, the substrate having a first surface and a second surface opposite to the first surface, the recess extending from the first surface to the second surface; forming a first thin film on a bottom surface of the recess; performing a first ion implantation process on the first thin film to form first dopant ions in the first thin film; forming a second thin film on a surface of the first thin film, an inner wall surface of the recess, and the second surface; forming a gate dielectric layer and a gate conductive layer, the gate conductive layer being located in the recess, and the gate dielectric layer being located between the second thin film and the gate conductive layer; performing a second ion implantation process on the second thin film on the second surface to form second dopant ions in the second thin film on the second surface, the second dopant ions having a same conductivity type as the first dopant ions; and performing an annealing process on the second thin film and the first thin film to form the first dopant ions in a portion of the second thin film between the first thin film and the gate dielectric layer. The first thin film having the first dopant ions and the second thin film having the first dopant ions serve as a first source / drain region, the second thin film having the second dopant ions serves as a second source / drain region, and a remaining portion of the second thin film serves as a channel region. The first source / drain region, the second source / drain region, and the channel region form an active layer.

[0007] In some embodiments, the first implantation dose is an implantation dose of a first implantation source in the first ion implantation process, and the second implantation dose is an implantation dose of a second implantation source in the second ion implantation process. The first implantation dose is greater than or equal to the second implantation dose.

[0008] In some embodiments, before performing the second ion implantation process on the second thin film, the method further comprises: forming a mask layer on a surface of the second thin film on the second surface; and removing the mask layer after performing the annealing process.

[0009] In some embodiments, a material of the mask layer comprises silicon oxide, silicon nitride, aluminum oxide, or aluminum. A thickness of the mask layer ranges from 3 nm to 50 nm.

[0010] In some embodiments, a material of at least one of the first thin film or the second thin film comprises a silicon material or an amorphous material. The silicon material comprises silicon or germanium-silicon. The amorphous material comprises indium-gallium-zinc oxide.

[0011] In some embodiments, the first doping concentration is a doping concentration of the first dopant ions in the second thin film after the annealing process, and the second doping concentration is a doping concentration of the first dopant ions in the first thin film after the annealing process; the first doping concentration is less than or equal to the second doping concentration.

[0012] In some embodiments, the method for providing a substrate comprises: providing a substrate, the substrate having a first side and a third side; forming a first conductive layer on a portion of the third side of the substrate; forming an isolation layer, the isolation layer covering the third side and a surface of the first conductive layer; forming a second conductive layer on a surface of the isolation layer; patterning the second conductive layer and the isolation layer to form a recess, a bottom of the recess exposing a surface of the first conductive layer, a side of the second conductive layer away from the substrate serving as a second side, and the substrate, the first conductive layer, the remaining isolation layer, and the remaining second conductive layer serving as the substrate.

[0013] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a semiconductor structure, comprising: a substrate, the substrate having a gate conductive layer therein, the gate conductive layer comprising a first side and a second side; an active layer, the active layer being located between the gate conductive layer and the substrate and a surface of the substrate; the active layer comprising: a first source-drain region, the first source-drain region being located between the first side of the gate conductive layer and the substrate; a channel region, the channel region surrounding the gate conductive layer; a second source-drain region, the second source-drain region being located on the surface of the substrate; the first source-drain region, the channel region, and the second source-drain region being arranged in sequence and in electrical contact with each other in a direction from the first side to the second side; the first source-drain region having first dopant ions therein, the first source-drain region comprising a first part and a second part stacked, the first part being located between the second part and the first side of the gate conductive layer; the first doping concentration of the first part being less than or equal to the second doping concentration of the second part; a gate dielectric layer, the gate dielectric layer being located between the active layer and the gate conductive layer.

[0014] In some embodiments, the substrate comprises: a substrate; an isolation layer, the isolation layer being located on a surface of the substrate, the gate conductive layer being located in the isolation layer; a first conductive layer, the first conductive layer being located in the isolation layer, the first conductive layer being located between the substrate and the first source-drain region; a second conductive layer, the second conductive layer being located between the second source-drain region and the isolation layer.

[0015] In some embodiments, the material of the first part and the second part is the same, and the material of the first part comprises indium-gallium-zinc oxide.

[0016] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0017] The semiconductor structure preparation method provided by the embodiment of the present disclosure includes: forming the first source-drain region and the second source-drain region by the first ion implantation process, the second ion implantation process and the annealing process. Compared with the first ion implantation process, the two ion implantation processes can better control the distribution of the doping elements in the source-drain region and the doping concentration, and improve the electrical performance of the transistor. The annealing process is performed on the second film and the first film to make the second film on the surface of the first film have the first doping ions, and the second film on the surface of the first film also serves as the first source-drain region. The contact performance between the first source-drain region and the channel region is better, and the electrical performance of the whole active layer is better. BRIEF DESCRIPTION OF DRAWINGS

[0018] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the present embodiments, unless otherwise specified; in order to clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, a brief introduction will be given to the drawings needed in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0019] Figure 1 The flowchart of the semiconductor structure preparation method provided by an embodiment of the present disclosure is shown in the figure.

[0020] Figures 2 to 18 The structure diagram of the semiconductor structure corresponding to each step of the semiconductor structure preparation method provided by an embodiment of the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0021] As known from the background, the electrical performance of the active layer of the semiconductor structure is poor.

[0022] The semiconductor structure provided by the embodiment of the present disclosure is formed by a first ion implantation process to have first doping ions in a first thin film, a second ion implantation process to have second doping ions in a part of a second thin film, and an annealing process to form a first source-drain region and a second source-drain region. Compared with the first source-drain region and the second source-drain region formed by only one ion implantation process, the two ion implantation processes can better control the distribution of the doping elements and the doping concentration in the source-drain region, and improve the electrical performance of the source-drain region of the transistor. The annealing process is performed on the second thin film and the first thin film to have the first doping ions in the second thin film on the surface of the first thin film, and the second thin film on the surface of the first thin film also serves as the first source-drain region. Therefore, the contact performance between the first source-drain region and the channel region is good, and the electrical performance of the whole active layer is good.

[0023] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to enable the readers to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0024] Figure 1 The flowchart of the preparation method of the semiconductor structure provided by an embodiment of the present disclosure is shown in the figure. Figures 2 to 16 The structure diagram of the semiconductor structure corresponding to each step in the preparation method of the semiconductor structure provided by an embodiment of the present disclosure is shown in the figure. Among them, Figures 2 to 12 and Figures 14 to 17 The cross-sectional structure diagram of the semiconductor structure corresponding to each step along the A1-A2 cross section (reference Figure 18 A1-A2 cross section) of the figure, Figure 13 is Figure 12 the cross-sectional structure diagram along the B1-B2 cross section.

[0025] According to some embodiments of the present disclosure, the embodiment of the present disclosure provides a preparation method of a semiconductor structure. In the preparation method, the electrical performance of the source-drain region of the transistor is similar by changing the preparation method of the active layer. In this way, the deviation and delay caused by the different electrical performance of the source-drain region of the transistor can be removed, so as to improve the response speed and yield of the transistor.

[0026] Referring to Figures 1 to 4 , the preparation method comprises: providing a substrate 10 with a groove 104, the substrate 10 having opposite first and second surfaces 11 and 12, and the groove 104 extending from the first surface 11 to the second surface 12.

[0027] Referring to Figure 2, a substrate 100 is provided, the substrate 100 has a first surface 11 and a third surface 13. The first surface of the substrate 100 is also the first surface 11 of the base 10, so the same feature and label are used to represent.

[0028] In some embodiments, the material of the substrate 100 can be a semiconductor material, which can include any one of silicon, germanium, silicon carbide, or silicon germanium. The substrate 100 has a doping element, which can be an N-type doping element or a P-type doping element. The N-type doping element can be a group V element such as phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element. The P-type doping element can be a group III element such as boron (B) element, aluminum (Al) element, gallium (Ga) element, or indium (In) element.

[0029] Referring to Figure 3 The first conductive layer 101 is formed on a portion of the third surface 13 of the substrate 100.

[0030] In some embodiments, the first conductive layer 101 serves as a first electrode of a semiconductor structure, and the first conductive layer 101 can be one of a bit line or a storage structure. The material of the first conductive layer 101 can be a metal material, which has a small resistance value, thereby reducing electrical loss and facilitating an increase in the operating speed and response speed of the semiconductor structure. The metal material can include silver, aluminum, tungsten, molybdenum, or copper.

[0031] In some embodiments, the first conductive layer 101 can be formed by any one of a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process. When the first conductive layer 101 is a bit line, the material of the first conductive layer 101 can be a semiconductor material, and the first conductive layer 101 can be formed by selective epitaxial growth using the substrate as a base material or the first conductive layer and the substrate can be formed from a raw substrate by doping treatment.

[0032] Referring to Figure 3 The isolation layer 102 is formed to cover the third surface 13 and the surface of the first conductive layer 101, and the second conductive layer 103 is formed on the surface of the isolation layer 102.

[0033] In some embodiments, the isolation layer 102 serves as a support layer of a subsequently formed active layer and a spacing structure for isolating adjacent active layers. The material of the isolation layer 102 can include silicon oxide, silicon nitride, or silicon oxynitride.

[0034] In some embodiments, the second conductive layer 103 can be used as a second electrode of the semiconductor structure, and the second conductive layer 103 can be used as a bit line or another structure of the semiconductor structure. The material of the second conductive layer 103 can be a metal material, and the metal material has a small resistance value, thereby reducing electrical loss and improving the operation speed and response speed of the semiconductor structure. The metal material can include silver, aluminum, tungsten, molybdenum, or copper.

[0035] In some embodiments, any one of the isolation layer 102 and the second conductive layer 103 can be formed by any one of a PVD, a CVD, and an atomic layer deposition process.

[0036] Referring to Figure 4 , the second conductive layer 103 and the isolation layer 102 are patterned to form a recess 104, the bottom of the recess 104 exposes the surface of the first conductive layer 101, the side of the second conductive layer 103 away from the substrate 100 is used as the second surface 12, and the substrate 100, the first conductive layer 101, the remaining isolation layer 102, and the remaining second conductive layer 103 are used as the base 10.

[0037] In some embodiments, a portion of the thickness of the first conductive layer 101 is etched during the process of forming the recess 104, so that the contact area between the first thin film and the first conductive layer is large, the contact resistance between the first thin film and the first conductive layer is reduced, and the Schottky contact area between the first thin film and the first conductive layer is large.

[0038] In some embodiments, referring to Figure 18 , the first conductive layer and the second conductive layer can not be formed, that is, the step of forming the first conductive layer is directly skipped, the isolation layer is directly formed, and the isolation layer covers the third surface of the substrate; after the isolation layer is formed, the second conductive layer is not formed, and the isolation layer is patterned to form a recess, the bottom of the recess exposes the third surface of the substrate, the side of the isolation layer away from the substrate is used as the second surface, and the base includes the substrate and the isolation layer.

[0039] Referring to Figure 5 , the first thin film 111 is formed on the bottom surface of the recess 104.

[0040] In some embodiments, the material of the first thin film 111 can be a semiconductor material, and the semiconductor material can include a silicon material or a germanium material. The silicon material includes monocrystalline silicon, amorphous silicon, microcrystalline silicon, germanium silicon, or polycrystalline silicon, and the germanium material includes germanium.

[0041] In some embodiments, the material of the first thin film 111 includes an amorphous material, which has a high mobility itself, so that the thickness of the active layer can be reduced under the requirement of the semiconductor device, i.e. the line width of the semiconductor structure can be reduced in a limited cell area, and the storage density of the semiconductor structure can be further improved. The amorphous material can include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide) or ITO (Indium Tin Oxide). For example, when the material of the first thin film 111 is IGZO, the carrier mobility of IGZO is 20-50 times of that of polysilicon, which is beneficial to improve the carrier mobility in the active layer, so as to reduce the leakage current of the semiconductor structure in operation, and reduce the power consumption and improve the operation efficiency of the semiconductor structure.

[0042] In some embodiments, when the material of the first conductive layer 101 is aluminum or molybdenum, and the material of the first thin film 111 is IGZO, a Schottky contact can be formed between the first conductive layer 101 and the first thin film 111 due to the work function of aluminum or molybdenum being greater than that of IGZO, and the IGZO / Mo or IGZO / Al Schottky barrier height is regulated by the gate electric field. When the gate voltage is negative, the Fermi level of IGZO moves to the valence band under the action of the gate electric field, and thus the barrier height for the movement of electrons from molybdenum / aluminum to IGZO is increased, and the source-drain current is reduced. When the gate voltage is positive, the Fermi level of IGZO moves to the conduction band under the action of the gate electric field, and thus the barrier height for the movement of electrons from molybdenum / aluminum to IGZO is reduced, and the source-drain current is increased. Therefore, the source-drain current can be changed in a large range under the action of the gate electric field, and an SB-TFT with high field-effect mobility, large on-off ratio and small leakage current is formed.

[0043] In some embodiments, the top surface of the first thin film 111 away from the substrate 100 is flush with the top surface of the first conductive layer 101 away from the substrate 100, the top surface of the first thin film 111 away from the substrate 100 is higher than the top surface of the first conductive layer 101 away from the substrate 100, or the top surface of the first thin film 111 away from the substrate 100 is lower than the top surface of the first conductive layer 101 away from the substrate 100.

[0044] Reference Figure 6 The first ion implantation process is performed on the first thin film 111 to make the first thin film 111 have first doping ions. The first doping ions are N-type doping ions or P-type doping ions. The N-type doping ions include phosphorus ions, bismuth ions, antimony ions or arsenic ions, and the P-type doping ions can include boron ions, aluminum ions, gallium ions or indium ions.

[0045] In some embodiments, the first thin film 111 is doped by a first ion implantation process. The ion implantation process can precisely control the concentration distribution and implantation concentration of the impurities doped into the first thin film 111 by controlling the ion energy and the amount of charge, thereby more precisely controlling the impurity concentration and distribution of the source and drain regions.

[0046] In some embodiments, a protective layer can be formed on the sidewall of the recess 104 before the first ion implantation process is performed on the first thin film 111, so as to avoid damaging the isolation layer 102 during the first ion implantation process. The material of the protective layer can include silicon oxide, silicon nitride or silicon oxynitride.

[0047] In some embodiments, a masking layer can be formed on the surface of the first thin film 111 before the first ion implantation process is performed on the first thin film 111, so as to reduce the lattice defects and surface defects caused by the first ion implantation process. The material of the masking layer can include silicon oxide, silicon nitride, aluminum oxide or aluminum. The first thickness of the masking layer increases with the increase of the electric field intensity and the impurity dose.

[0048] The above describes that the recess is formed first and then the first thin film is formed. The embodiments of the present disclosure also provide that the first thin film is formed between the second isolation layers. In this way, the material of the isolation layer and the plasma loss during the ion implantation process do not need to be considered, thereby facilitating the precise control of the doping concentration of the first doping ions in the first thin film.

[0049] Reference Figure 7 A substrate 100 is provided; a first isolation layer 141 is formed on the third surface 13 of the substrate 100; and the first isolation layer 141 is patterned to form a first trench.

[0050] In some embodiments, a first conductive layer 101 is formed, and the first conductive layer 101 fills the first trench; the first conductive layer 101 is patterned to form a second trench 108, and the second trench 108 does not penetrate through the first conductive layer 101.

[0051] In some embodiments, a first conductive layer 101 is formed, and the first conductive layer 101 is located on the sidewall of the first trench, the bottom of the first trench and the surface of the first isolation layer 141; the first conductive layer 101 located on the top of the first isolation layer 141 is removed, and the first conductive layer 101 located in the first trench constitutes the second trench 108.

[0052] Reference Figure 8 A first thin film 111 is formed, and the first thin film 111 is located in the second trench; and a first ion implantation process is performed on the first thin film 111 to make the first thin film 111 have first doping ions.

[0053] Reference Figure 9The second isolation layer 142 and the second conductive layer 103 are formed in a stack, the second isolation layer 142 covers the first isolation layer 141, the first conductive layer 101 and the surface of the first thin film 111, and the second isolation layer 142 and the first isolation layer 141 form the isolation layer 102.

[0054] Referring to Figure 10 The second conductive layer 103 and the second isolation layer 142 are patterned, and the third groove 109 is formed, wherein the second groove 108 and the third groove 109 serve as the recess.

[0055] It can be understood that the first conductive layer 101 surrounds the first thin film 111 in the semiconductor structure described in the above embodiments, so as to increase the contact area between the first conductive layer 101 and the first thin film 111 and reduce the contact resistance between the first conductive layer 101 and the first thin film 111. In some embodiments, the first conductive layer 101 and the first thin film 111 are in a stacked position relationship, that is, the side of the first conductive layer 101 away from the substrate 100 is in electrical contact with the bottom surface of the first thin film 111 or the first conductive layer 101 is partially in contact with the first thin film 111.

[0056] Referring to Figure 11 The second thin film 112 is formed on the surface of the first thin film 111, the inner wall surface of the recess 104 and the second surface 12.

[0057] In some embodiments, the material of the second thin film 112 can be a semiconductor material or an amorphous material, the semiconductor material can include silicon material or germanium material, and the amorphous material can include at least one of IGZO, IWO or ITO. When the second thin film 112 is an amorphous material and the material of the first thin film 111 is an amorphous material, the same effect is achieved, which will not be described here.

[0058] In some embodiments, the material of the first thin film 111 is the same as the material of the second thin film 112. When the carriers subsequently jump or migrate in the first thin film 111 and the second thin film 112, there is no interface state or threshold difference, so as to facilitate the improvement of the electrical performance of the semiconductor structure.

[0059] In some embodiments, the first thin film 111 and the second thin film 112 are made of different materials. For example, the first thin film 111 is made of silicon, and the second thin film 112 is made of germanium-silicon, and the lattice constant of the germanium-silicon is larger than that of the silicon. Due to the difference in the lattice constant, the first thin film 111 will generate a compressive stress in the direction of the second thin film 112, thereby increasing the mobility of the carriers (electrons or holes) in the channel region, improving the driving current and the speed of the transistor formed by the active layer. The increase in the mobility can offset the decrease in the mobility caused by the vertical electric field generated by the formation of multiple transistors on the surface of the vertical substrate 10, i.e., the semiconductor structure can be converted from 2D dimension to 3D dimension, which is beneficial to improve the storage density of the semiconductor structure.

[0060] In some embodiments, after the formation of the second thin film 112, the method further comprises a doping treatment on the second thin film 112, the doping treatment is used to make the second thin film 112 have third doping ions, and the third doping ions are of N-type or P-type.

[0061] In some embodiments, the third doping ions are of the same type as the first doping ions, for example, the third doping ions are of N-type, and the first doping ions are of N-type. In this way, the transistor formed by the active layer is a junctionless transistor. In some embodiments, the third doping ions are of a different type from the first doping ions, for example, the third doping ions are of P-type, and the first doping ions are of N-type. In this way, the transistor formed by the active layer is a junction transistor. In the “junction” in the “junctionless transistor” and the “junction transistor”, the “junction” refers to the PN junction.

[0062] In some embodiments, the doping treatment includes an ion implantation process or a thermal diffusion. When the doping treatment is an ion implantation process, an annealing process can be performed on the first thin film 111 and the second thin film 112 after the second ion implantation process to remove impurities in the first thin film 111 and the second thin film 112, which can reduce the thermal damage to the substrate 10, the first thin film 111 and the second thin film 112 compared with a high-temperature diffusion process.

[0063] Reference Figure 12 And Figure 13 The gate dielectric layer 121 and the gate conductive layer 122 are formed, the gate conductive layer 122 is located in the recess, and the gate dielectric layer 121 is located between the second thin film 112 and the gate conductive layer 122.

[0064] In some embodiments, the material of the gate dielectric layer 121 includes silicon dioxide or high dielectric constant material. The high dielectric constant material can include hafnium dioxide, which can provide high unit capacitance, enhance the control of the channel electrons by the gate capacitance, and increase the current of the tunneling breakdown gate node and the operating voltage of the device. In addition, the introduction of hafnium dioxide blocks the diffusion of ambient oxygen to the IGZO / Mo or IGZO / Al interface, avoiding the degradation of the IGZO / Mo or IGZO / Al Schottky junction into ohmic contact due to the diffusion of ambient oxygen. The presence of a large number of oxygen vacancies at the IGZO / HfO2 interface can significantly increase the carrier concentration, and thus the conductivity of IGZO / HfO2 is significantly improved compared to pure IGZO, further improving the overall field effect mobility and on / off ratio of the device.

[0065] In some embodiments, the gate conductive layer 122 can be a single layer film structure. The material of the gate conductive layer 122 is a metal conductive material, such as silver, tungsten, or copper. The metal conductive material has a small resistance value, which can reduce the electrical loss of the gate conductive layer 122 itself.

[0066] In some embodiments, the gate conductive layer 122 can be a multi-layer film structure, such as a work function layer and a conductive layer, a metal diffusion layer and a metal layer. When the gate conductive layer 122 includes a work function layer and a conductive layer, the threshold voltage of the channel region can be adjusted by regulating the work function of the gate, and the sensitivity of the on / off of the channel region can be improved. When the gate conductive layer 122 includes a metal diffusion layer and a metal layer, it can prevent the metal material from diffusing into the gate dielectric layer 121, and even into the active layer, which is beneficial to improve the yield of the semiconductor structure.

[0067] Reference is made to Figure 14 A mask layer 123 is formed on the surface of the second thin film 112 of the second surface. The mask layer 123 is used to reduce the lattice defects and surface defects caused to the second thin film 112 in the second ion implantation process.

[0068] In some embodiments, the material of the mask layer 123 includes silicon oxide, silicon nitride, aluminum oxide, or aluminum. The second thickness of the mask layer 123 increases with the increase of the electric field intensity and the impurity dose.

[0069] In some embodiments, the second thickness of the mask layer 123 ranges from 3 nm to 50 nm. The thickness range of the mask layer 123 can accommodate part of the second implantation source in the second ion implantation process, so that the doping concentration of the second doped ions after the second ion implantation is less than the doping concentration of the first doped ions, and the degree of lattice defects and surface defects caused to the second thin film 112 is weaker.

[0070] Reference is made to Figure 15A second ion implantation process is performed on the second film 112 located on the second surface 12 to have second dopant ions in the second film 112 located on the second surface 12, the second dopant ions have the same conductivity type as the first dopant ions.

[0071] In some embodiments, the first implantation dose is an implantation dose of the first implantation source in the first ion implantation process, and the second implantation dose is an implantation dose of the second implantation source in the second ion implantation process. The first implantation dose is greater than the second implantation dose, so that the first dopant ions in the first film 111 have a greater doping concentration before the annealing process is performed. In this way, the first dopant ions in the first film 111 can diffuse into part of the second film 112 before the annealing process is performed, so that part of the second film 112 also serves as the first source / drain region. Based on the similar doping concentration of the dopant ions in the diffused first source / drain region and the second source / drain region, the electrical properties of the source and the drain of the transistor are similar.

[0072] In some embodiments, when the first implantation dose is greater than the second implantation dose, the mask layer 123 and the shielding layer can not be formed, or the second thickness of the mask layer 123 is similar to the first thickness of the shielding layer.

[0073] In some embodiments, the first implantation dose is equal to the second implantation dose, and the mask layer 123 is formed as a shielding layer for reducing the doping concentration of the second dopant ions. In this way, the first dopant ions in the first film 111 have a greater doping concentration before the annealing process is performed. In this way, the first dopant ions in the first film 111 can diffuse into part of the second film 112 before the annealing process is performed, so that part of the second film 112 also serves as the first source / drain region. Based on the similar doping concentration of the dopant ions in the diffused first source / drain region and the second source / drain region, the electrical properties of the source and the drain of the transistor are similar.

[0074] In some embodiments, if the shielding layer is formed, the first thickness of the shielding layer is less than the second thickness of the mask layer 123, so that the mask layer 123 can shield more second implantation sources in the second ion implantation process from entering the second film 112, to ensure that the doping concentration of the second dopant ions is less than the doping concentration of the first dopant ions.

[0075] It can be understood that the difference between the doping concentration of the first dopant ions and the doping concentration of the second dopant ions is positively correlated with the thickness of the second film 112 formed on the first film 111, and the difference between the second thickness of the mask layer 123 and the first thickness of the shielding layer is positively correlated with the thickness of the second film 112 formed on the first film 111.

[0076] Reference Figure 16 or Figure 18The second thin film 112 and the first thin film 111 are subjected to an annealing process to have first doped ions in a part of the second thin film 112 between the first thin film 111 and the gate dielectric layer 123; the first thin film 111 with the first doped ions and the second thin film 112 with the first doped ions are the first source-drain region 131, the second thin film with the second doped ions is the second source-drain region 133, and the remaining second thin film is the channel region 132; and the first source-drain region 131, the second source-drain region 133, and the channel region 132 form the active layer 130.

[0077] In some embodiments, the first doping concentration is a doping concentration of the first doped ions in the second thin film after the annealing process, and the second doping concentration is a doping concentration of the first doped ions in the first thin film after the annealing process; the first doping concentration is less than or equal to the second doping concentration.

[0078] In some embodiments, the channel region 132 surrounds the gate conductive layer 122, and the transistor forms a Channel-All-Around (CAA) structure, which effectively reduces the device area and supports multi-layer stacking; by directly connecting two CAA devices, the size of each memory cell can be reduced to 4F2, and the IGZO-DRAM has a density advantage.

[0079] In some embodiments, the second thin film with the first doped ions is the first part 106 of the first source-drain region 131, and the first thin film with the first doped ions is the second part 105 of the first source-drain region 131.

[0080] In some embodiments, the side of the gate conductive layer 121 facing the first source-drain region 131 is the first side 21, and the side of the gate conductive layer 121 away from the first source-drain region 131 is the second side 22.

[0081] The semiconductor structure preparation method provided by the embodiments of the present disclosure includes: forming the first source-drain region 131 and the second source-drain region 133 by the first ion implantation process, the second ion implantation process and the annealing process, compared with the first source-drain region and the second source-drain region formed by only one ion implantation process, the two ion implantation processes better control the distribution of the doping elements and the doping concentration in the source-drain region, and improve the electrical performance of the source-drain of the transistor; the annealing process is performed on the second thin film 112 and the first thin film 111 to make the second thin film 112 on the surface of the first thin film 111 have the first doping ions, and make the second thin film 112 on the surface of the first thin film 111 also serve as the first source-drain region, so that the contact performance between the first source-drain region 131 and the channel region 132 is better, and the electrical performance of the whole active layer is better.

[0082] Accordingly, according to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a semiconductor structure prepared by the semiconductor structure preparation method of any one of the above embodiments, and the same elements as the above embodiments are not described here.

[0083] Reference Figures 16 to 18 The semiconductor structure includes: a substrate 10, the substrate 10 has a gate conductive layer 122 therein, the gate conductive layer 122 includes a first side 21 and a second side 22 opposite to each other; an active layer 130, the active layer 130 is located between the gate conductive layer 122 and the substrate 10 and on the surface of the substrate 10; the active layer 130 includes: a first source-drain region 131, the first source-drain region 131 is located between the first side 21 of the gate conductive layer 122 and the substrate 10; a channel region 132, the channel region 132 surrounds the gate conductive layer 122; a second source-drain region 133, the second source-drain region 133 is located on the surface of the substrate 10; in the direction from the first side 21 to the second side 22, the first source-drain region 131, the channel region 132 and the second source-drain region 133 are arranged in sequence and electrically connected to each other; a gate dielectric layer 121, the gate dielectric layer 121 is located between the active layer 130 and the gate conductive layer 122.

[0084] In some embodiments, reference Figure 16, the base 10 comprises: a substrate 100; an isolation layer 102 on the surface of the substrate 100, and a gate conductive layer 122 in the isolation layer 102; a first conductive layer 101 in the isolation layer 102, the first conductive layer 101 being between the substrate 100 and the first source-drain region 131; and a second conductive layer 103 between the second source-drain region 133 and the isolation layer 102. The bottom surface of the substrate 100 away from the isolation layer 102 serves as a first surface 11 of the base 10. The top surface of the second conductive layer 103 away from the isolation layer 102 serves as a second surface 12 of the base 10.

[0085] In some embodiments, the first conductive layer 101 serves as a first electrode of the semiconductor structure, and can be one of a bit line or a storage structure. The material of the first conductive layer 101 can be a metal material, which can include silver, aluminum, tungsten, molybdenum, or copper.

[0086] In some embodiments, the second conductive layer 103 serves as a second electrode of the semiconductor structure, and can be the other of a bit line or a storage structure. The material of the second conductive layer 103 can be a metal material, which can include silver, aluminum, tungsten, molybdenum, or copper.

[0087] In some embodiments, referring to Figure 17 , the base 10 comprises: a substrate 100; an isolation layer 102 on the surface of the substrate 100, and a gate conductive layer 122 in the isolation layer 102, a first source-drain region 131 between the isolation layer 102 and a first side 21 of the gate conductive layer 122, a channel region 132 between the sidewall of the gate conductive layer 122 and the isolation layer 102, and a second source-drain region 133 on the surface of the isolation layer 102. The bottom surface of the substrate 100 away from the isolation layer 102 serves as a first surface 11 of the base 10. The top surface of the isolation layer 102 away from the substrate 100 serves as a second surface 12 of the base 10.

[0088] In some embodiments, the material of the substrate 100 can be a semiconductor material, which can include any one of silicon, germanium, silicon carbide, or silicon germanium. The substrate 100 has a doping element therein, which can be an N-type doping element or a P-type doping element.

[0089] In some embodiments, the isolation layer 102 serves as a support layer of the active layer 130 and a spacing structure for isolating adjacent active layers 130. The material of the isolation layer 102 can include silicon oxide, silicon nitride, or silicon oxynitride.

[0090] In some embodiments, the first source / drain region 131 has first doping ions therein, and the first source / drain region 131 includes a first portion 106 and a second portion 105, the first portion 106 is located between the second portion 105 and the first side 21 of the gate conductive layer 122; the first doping concentration of the first portion 106 is less than or equal to the second doping concentration of the second portion 105.

[0091] In some embodiments, the material of the first portion 106 includes a semiconductor material, and the semiconductor material can include a silicon material or a germanium material, the silicon material includes monocrystalline silicon, amorphous silicon, microcrystalline silicon, germanium silicon or polycrystalline silicon, and the germanium material includes germanium.

[0092] In some embodiments, the material of the first portion 106 includes an amorphous material, and the amorphous material includes indium-gallium-zinc oxide.

[0093] In some embodiments, the material of the first portion 106 is the same as that of the second portion 105. When the carriers jump or migrate in the first portion 106 and the second portion 105, there is no interface state or threshold difference, thereby facilitating the improvement of the electrical performance of the semiconductor structure.

[0094] In some embodiments, the material of the first portion 106 is different from that of the second portion 105, and the lattice constant of the material of the first portion 106 is greater than that of the material of the second portion 105. Due to the difference in the lattice constant, the second portion 105 will generate a compressive stress in the direction of the first portion 106, thereby increasing the mobility of the carriers (electrons or holes) in the channel region and improving the driving current and the speed of the transistor composed of the active layer.

[0095] In some embodiments, the material of the gate dielectric layer 121 includes silicon dioxide or high dielectric constant material.

[0096] In some embodiments, the gate conductive layer 122 can be a single-layer film structure. The material of the gate conductive layer 122 is a metal conductive material, such as silver, tungsten or copper. The metal conductive material has a small resistance value, which can reduce the electrical loss of the gate conductive layer 122 itself.

[0097] In some embodiments, the gate conductive layer 122 can be a multi-layer film structure, such as a work function layer and a conductive layer, a metal diffusion layer and a metal layer. When the gate conductive layer 122 includes a work function layer and a conductive layer, the threshold voltage of the channel region can be adjusted by regulating the work function of the gate, thereby improving the sensitivity of the on / off of the channel region. When the gate conductive layer 122 includes a metal diffusion layer and a metal layer, it can prevent the metal material from diffusing into the gate dielectric layer 121, and even into the active layer 130, thereby improving the yield of the semiconductor structure.

[0098] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate having a groove, the substrate having a first surface and a second surface opposite to each other, the groove extending from the first surface to the second surface; forming a first film, wherein the first film is located on the bottom surface of the groove; performing a first ion implantation process on the first film so that first dopant ions are present in the first film; forming a second film, wherein the second film is located on the surface of the first film, the inner wall surface of the groove, and the second surface; forming a gate dielectric layer and a gate conductive layer, wherein the gate conductive layer is located in the groove and the gate dielectric layer is located between the second film and the gate conductive layer; performing a second ion implantation process on the second film located on the second surface, so that the second film located on the second surface has second dopant ions, and the conductivity type of the second dopant ions is the same as the conductivity type of the first dopant ions; The second film and the first film are subjected to an annealing process so that a portion of the second film located between the first film and the gate dielectric layer contains the first dopant ions; wherein the first film containing the first dopant ions and the second film containing the first dopant ions serve as a first source / drain region, the second film containing the second dopant ions serves as a second source / drain region, and the remaining second film serves as a channel region; the first source / drain region, the second source / drain region, and the channel region constitute an active layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The first implantation dose is the implantation dose of the first implantation source in the first ion implantation process, and the second implantation dose is the implantation dose of the second implantation source in the second ion implantation process; The first implantation dose is greater than or equal to the second implantation dose.

3. The method for preparing a semiconductor structure according to claim 1 or 2, wherein: Before performing the second ion implantation process on the second thin film, the method further includes: forming a mask layer, the mask layer being located on the surface of the second thin film on the second side; and removing the mask layer after performing the annealing process.

4. The method for preparing a semiconductor structure according to claim 3, wherein: The material of the mask layer includes silicon oxide, silicon nitride, aluminum oxide or aluminum; the thickness of the mask layer ranges from 3 nm to 50 nm.

5. The method for preparing a semiconductor structure according to claim 1, wherein: A material of at least one of the first thin film or the second thin film includes a silicon material or an amorphous material. The silicon material includes silicon or silicon germanium. The amorphous material includes indium-gallium-zinc oxide.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The first doping concentration is the doping concentration of the first doping ions in the second film after the annealing process, and the second doping concentration is the doping concentration of the first doping ions in the first film after the annealing process; the first doping concentration is less than or equal to the second doping concentration.

7. The method for preparing a semiconductor structure according to claim 1, wherein: Providing a base includes: providing a substrate having a first surface and a third surface opposite to each other; forming a first conductive layer on a portion of the third surface of the substrate; forming an isolation layer, wherein the isolation layer covers the third surface and a surface of the first conductive layer; forming a second conductive layer on the surface of the isolation layer; The second conductive layer and the isolation layer are patterned to form a groove, the bottom of the groove exposes the surface of the first conductive layer, the side of the second conductive layer away from the substrate serves as the second surface, and the substrate, the first conductive layer, the remaining isolation layer and the remaining second conductive layer serve as the base.

8. A semiconductor structure, characterized in that include: A substrate having a gate conductive layer therein, wherein the gate conductive layer includes a first side and a second side opposite to each other; an active layer, the active layer being located between the gate conductive layer and the substrate and on the surface of the substrate; the active layer comprising: a first source / drain region, the first source / drain region being located between a first side of the gate conductive layer and the substrate; a channel region, the channel region surrounding the gate conductive layer; and a second source / drain region, the second source / drain region being located on the surface of the substrate; the first source / drain region, the channel region, and the second source / drain region being arranged in sequence and electrically contacting each other along a direction from the first side to the second side; the first source / drain region having first dopant ions therein, the first source / drain region comprising a first portion and a second portion stacked together, the first portion being located between the second portion and the first side of the gate conductive layer; a first doping concentration of the first portion being less than or equal to a second doping concentration of the second portion; A gate dielectric layer is located between the active layer and the gate conductive layer.

9. The semiconductor structure according to claim 8, wherein: The base includes: a substrate; an isolation layer, the isolation layer is located on the surface of the substrate, and the gate conductive layer is located in the isolation layer; a first conductive layer, the first conductive layer is located in the isolation layer, and the first conductive layer is located between the substrate and the first source and drain region; a second conductive layer, the second conductive layer is located between the second source and drain region and the isolation layer.

10. The semiconductor structure according to claim 8, wherein: The first portion and the second portion are made of the same material, and the first portion is made of indium-gallium-zinc oxide.

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