Back contact battery with specific P-type emitter and its manufacture and application

Abstract

The present invention belongs to the technical field of back contact batteries, and specifically relates to a back contact battery with a specific P-type emitter, and its preparation and application, including a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon wafer, the first semiconductor layer comprising a passivation layer and an N-type doped silicon layer, the second semiconductor layer comprising an intrinsic silicon layer, and the second semiconductor layer further comprising a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer sequentially arranged on the surface of the side of the intrinsic silicon layer away from the silicon wafer, forming a P-type emitter, along the direction away from the back of the silicon wafer, the effective boron doping concentration of the P-type microcrystalline silicon carbide layer and / or the P-type microcrystalline silicon layer gradually increases according to the layered structure, the layered structure is not less than 5 layers, and the thickness of the P-type microcrystalline silicon carbide layer is 3-6nm. The present invention adopts a P-type emitter with a specific structure, which is conducive to improving the open circuit voltage of the battery, improving the conductivity of the thin film, and improving the fill factor and conversion efficiency of the battery.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery with a specific P-type emitter and its manufacture and application. Background Art

[0002] The existing back contact cell includes an N-type single crystal silicon wafer, an intrinsic amorphous silicon layer and an anti-reflection layer (anti-reflection layer) arranged on the pyramid velvet surface on the front of the silicon wafer, an intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal gate line layer arranged on the surface of the P region on the back of the silicon wafer, and an intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal gate line layer arranged on the surface of the N region on the back of the silicon wafer. In the prior art, the deposition process conditions of P-type amorphous silicon are: the PECVD film forming temperature is preset to 180-200°C, and then a mixed gas of silane, diborane, and hydrogen is introduced, the reaction gas pressure is 40-90Pa, and the diborane flow rate is 5%-10% of the silane flow rate; the thickness of the P-type amorphous silicon film is 8-15nm.

[0003] However, the P-type amorphous silicon layer has low carrier mobility, more impurities and defects, and poor conductivity, which affects battery efficiency.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] The purpose of the present invention is to overcome the defect of the prior art that the P-type amorphous silicon layer affects the efficiency of the battery, and to provide a back-contact battery with a specific P-type emitter and its preparation and application. The battery adopts a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer with a specific structure, which is beneficial to improving the open circuit voltage of the battery, improving the conductivity of the thin film, and improving the fill factor and conversion efficiency of the battery.

[0006] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a back-contact battery with a specific P-type emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, the first semiconductor layer comprising a passivation layer and an N-type doped silicon layer, the second semiconductor layer comprising an intrinsic silicon layer, and the second semiconductor layer further comprising a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer sequentially arranged on the surface of the intrinsic silicon layer away from the silicon wafer to form a P-type emitter, along the direction away from the back side of the silicon wafer, the effective boron doping concentration of the P-type microcrystalline silicon carbide layer and / or the P-type microcrystalline silicon layer gradually increases according to the layered structure, and the layered structure is not less than 5 layers; and the crystallization rate of the P-type microcrystalline silicon carbide layer is 20%-40%, and the crystallization rate of the P-type microcrystalline silicon layer is 40%-80%; wherein, the thickness of the P-type microcrystalline silicon carbide layer is 3-6nm, and the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer and the intrinsic silicon layer is 1:5-10:1.5-4.

[0007] In some preferred embodiments of the present invention, the crystallization rate of the P-type microcrystalline silicon layer is greater than the crystallization rate of the P-type microcrystalline silicon carbide layer.

[0008] In some preferred embodiments of the present invention, the ratio of the crystallization rate of the P-type microcrystalline silicon layer to the P-type microcrystalline silicon carbide layer is 1.5-4:1.

[0009] In some preferred embodiments of the present invention, the effective boron doping concentration of the first layer of the P-type microcrystalline silicon carbide layer is 1e18 cm -3 -3e19cm -3 、The effective boron doping concentration of the last layer is 1e19cm -3 -8e20cm -3 The effective boron doping concentration of the first layer of the P-type microcrystalline silicon layer is 5e18cm -3 -5e19cm -3 、The effective boron doping concentration of the last layer is 5e19cm -3 -5e21cm -3 .

[0010] In some preferred embodiments of the present invention, the corresponding layered structures of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer are independently 8-15 layers.

[0011] In some preferred embodiments of the present invention, the effective boron doping concentrations of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer independently satisfy: the absolute value of the difference in effective boron doping concentrations between two adjacent layers in the layered structure of the P-type microcrystalline silicon carbide layer is within 5e18cm -3 -5e20cm -3 The absolute value of the difference in effective boron doping concentration between two adjacent layers in the layer structure of P-type microcrystalline silicon layer is 1e19cm -3 -1e21cm -3 .

[0012] Preferably, in the present invention, the thickness of the P-type microcrystalline silicon layer is 15-40 nm.

[0013] In some preferred embodiments of the present invention, the back-contact battery with a specific P-type emitter also includes a P-type amorphous silicon film, which is arranged on the outer surface of the P-type microcrystalline silicon layer on the side away from the P-type microcrystalline silicon carbide layer, and the P-type amorphous silicon film, the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer together form a P-type emitter.

[0014] Further preferably, the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the total thickness formed by the P-type microcrystalline silicon layer and the P-type amorphous silicon film is 1:5-10, and the ratio of the thickness of the P-type microcrystalline silicon layer to the P-type amorphous silicon film is 6-12:1.

[0015] More preferably, the thickness of the P-type amorphous silicon film is 2-5 nm, and the thickness of the P-type microcrystalline silicon layer is 15-35 nm.

[0016] In the embodiment of the present invention further including a P-type amorphous silicon film, preferably, the corresponding layered structures of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer are independently 6-12 layers.

[0017] Further preferably, the effective boron doping concentration of the P-type amorphous silicon film is 3e19cm -3 -5e20cm -3 , and / or, the crystallization rate of the P-type microcrystalline silicon layer is 50%-80%.

[0018] In some preferred embodiments of the present invention, the back contact cell with a specific P-type emitter further has the following structure:

[0019] Structure 1: The intrinsic silicon layer is a first intrinsic amorphous silicon layer;

[0020] Structure 2: The passivation layer is an intrinsic amorphous silicon or a tunneling oxide layer, the thickness of the tunneling oxide layer is 1-2 nm, the thickness ratio of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer, the intrinsic silicon layer, and the tunneling oxide layer is 1-3:10-20:2-7:1; the thickness of the intrinsic amorphous silicon and the intrinsic silicon layer is independently 5-12 nm, and the N-type doped silicon layer is an N-type doped polycrystalline silicon layer;

[0021] Structure 3: The passivation layer is a tunneling oxide layer, the thickness of the N-type doped silicon layer is 100-200nm, and the effective phosphorus doping concentration is 5e19cm -3 -5e20cm -3 .

[0022] In some preferred embodiments of the present invention, the back-contact cell with a specific P-type emitter further comprises a third semiconductor layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer.

[0023] In some preferred embodiments of the present invention, the third semiconductor layer comprises a second intrinsic amorphous silicon layer and a microcrystalline silicon oxygen layer sequentially arranged in a direction away from the front side of the silicon wafer, the thickness of the second intrinsic amorphous silicon layer is 4-8nm, and the thickness of the microcrystalline silicon oxygen layer is 6-20nm.

[0024] In some preferred embodiments of the present invention, two ends of the second semiconductor layer respectively extend outward to cover the back side of part of the adjacent first semiconductor layer, and a first semiconductor opening area not covering the second semiconductor layer is opened on the back side of the first semiconductor layer, a second semiconductor opening area is formed between adjacent first semiconductor layers, the second semiconductor opening area is arranged at intervals from the first semiconductor opening area and the area between them is a spacing area, in which a mask layer or no mask layer is arranged between the first semiconductor layer and the second semiconductor layer; the back contact battery with a specific P-type emitter also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, an insulating groove is opened on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area; wherein the front side of the silicon wafer and the back side of the silicon wafer corresponding to the second semiconductor opening area are velvet surfaces, and the back side of the silicon wafer located outside the second semiconductor opening area is a polished surface.

[0025] In a second aspect, the present invention provides a method for manufacturing a back contact battery, comprising the following steps:

[0026] S01. Provide double-sided polished silicon wafers;

[0027] S02, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer comprises a passivation layer and an N-type doped silicon layer;

[0028] S03, performing a first etching opening on the back surface obtained in S02 to form a second semiconductor opening region;

[0029] S04, removing the remaining mask layer and the first semiconductor layer in the second semiconductor opening region by texturing and cleaning, and forming a texturing surface on the front side of the silicon wafer and the second semiconductor opening region, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer by cleaning as needed;

[0030] S05, depositing an intrinsic silicon layer of a second semiconductor layer on the back surface obtained in S04;

[0031] S06, forming a third semiconductor layer on the front side of the silicon wafer obtained in S05;

[0032] S07. Using PECVD technology, a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer of a second semiconductor layer are sequentially deposited on the back side obtained in S06. During the deposition of the P-type microcrystalline silicon carbide layer and / or the P-type microcrystalline silicon layer, the volume flow ratio of diborane to silane gradually increases according to the corresponding required layered structure, and the number of layers of the layered structure is not less than 5. The crystallization rate of the P-type microcrystalline silicon carbide layer is controlled to be 20%-40%, the crystallization rate of the P-type microcrystalline silicon layer is controlled to be 40%-80%, the thickness of the P-type microcrystalline silicon carbide layer is controlled to be 3-6nm, and the thickness ratio of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer and the intrinsic silicon layer is controlled to be 1:5-10:1.5-4.

[0033] In some preferred embodiments of the present invention, the deposition rate of the P-type microcrystalline silicon carbide layer is controlled at 0.3-1 A / s, and the deposition rate of the P-type microcrystalline silicon layer is controlled at 0.5-2 A / s.

[0034] In some preferred embodiments of the present invention, in the first layer of deposited P-type microcrystalline silicon carbide layer, the volume flow rate of diborane is 0.1%-0.8% of the volume flow rate of silane, and in the last layer of deposited P-type microcrystalline silicon carbide layer, the volume flow rate of diborane is 1%-3% of the volume flow rate of silane; in the first layer of deposited P-type microcrystalline silicon layer, the volume flow rate of diborane is 0.1%-0.8% of the volume flow rate of silane, and in the last layer of deposited P-type microcrystalline silicon layer, the volume flow rate of diborane is 1.0%-4.0% of the volume flow rate of silane.

[0035] In some preferred embodiments of the present invention, the conditions for depositing a P-type microcrystalline silicon carbide layer include: a preset film forming temperature of 50-150°C, and under the condition of introducing a mixed gas of silane, diborane, hydrogen and methane, the methane introduced is controlled to be 3%-30% of the volume flow rate of silane, the silane flow rate is 10-200sccm, the hydrogen flow rate is 20000-200000sccm, and the reaction gas pressure is 100-1000Pa; the conditions for depositing a P-type microcrystalline silicon layer include: a preset film forming temperature of 140-200°C, and under the condition of introducing a mixed gas of silane, diborane and hydrogen, the volume flow ratio of hydrogen and silane is controlled to be 100-500:1, the silane flow rate is 100-1000sccm, and the reaction gas pressure is 100-1000Pa.

[0036] In some preferred embodiments of the present invention, the method for manufacturing the back-contact battery also includes: in S07, after depositing the P-type microcrystalline silicon layer, then depositing a P-type amorphous silicon film on the outer surface of the P-type microcrystalline silicon layer, controlling the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the total thickness formed by the P-type microcrystalline silicon layer and the P-type amorphous silicon film to be 1:5-10, preferably 1:5-8.3, and the ratio of the thickness of the P-type microcrystalline silicon layer to the P-type amorphous silicon film to be 6-12:1, preferably 8.2-12:1.

[0037] In some preferred embodiments of the present invention, the deposition conditions of the P-type amorphous silicon film include: the preset PECVD film forming temperature is 160-220°C, silane, diborane and hydrogen are introduced, the reaction gas pressure is 100-300Pa, the volume flow ratio of diborane to silane is 5%-10%, and the deposition rate is 0.5-1.5A / s.

[0038] In some preferred embodiments of depositing a P-type amorphous silicon film of the present invention, diborane in the first layer of deposited P-type microcrystalline silicon layer is 0.1%-0.5% of the volume flow of silane, and diborane in the last layer of deposited P-type microcrystalline silicon layer is 1.0%-3.0% of the volume flow of silane.

[0039] In some preferred embodiments of the present invention, the method for manufacturing the back contact battery also includes: performing a methane pretreatment step before depositing the P-type microcrystalline silicon carbide layer in S07, and the conditions for the methane pretreatment include: introducing methane and hydrogen, with a methane flow rate of 100-1000sccm, a hydrogen flow rate of 1000-20000sccm, and a pretreatment time of 20-60s.

[0040] In some preferred embodiments of the present invention, the third semiconductor layer is deposited by plate PECVD, which comprises a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer deposited sequentially, the second intrinsic amorphous silicon layer has a thickness of 4-8 nm, and the microcrystalline silicon oxide layer has a thickness of 6-20 nm.

[0041] In some preferred embodiments of the present invention, the method for manufacturing the back contact battery further comprises:

[0042] S08, depositing an anti-reflection layer on the outer surface of the third semiconductor layer on the front side obtained in S07;

[0043] S09, performing a second etching opening on a portion of the second semiconductor layer on the back side obtained in S08 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then performing cleaning;

[0044] S10, depositing a conductive film layer on the back surface obtained in S09;

[0045] S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove;

[0046] S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0047] In a third aspect, the present invention provides a back-contact battery, which is manufactured by the method for manufacturing a back-contact battery described in the second aspect.

[0048] In a fourth aspect, the present invention provides a photovoltaic module, comprising the back-contact cell with a specific P-type emitter as described in the first aspect, or comprising the back-contact cell as described in the third aspect.

[0049] Beneficial effects:

[0050] The present invention adopts the above-mentioned technical scheme, especially utilizes P-type microcrystalline silicon carbide layer and P-type microcrystalline silicon layer to form P-type emitter to replace the existing P-type amorphous silicon technology. P-type microcrystalline silicon carbide has a larger optical band gap than P-type amorphous silicon and P-type microcrystalline silicon, which is conducive to forming a larger energy band bending at the PN junction interface, generating a more effective built-in electric field, promoting the rapid separation of photogenerated carriers, reducing recombination, and thus facilitating the improvement of the open circuit voltage of the battery; and, the P-type microcrystalline silicon carbide layer and P-type microcrystalline silicon layer used in the present invention are both microcrystalline silicon, which has a more ordered lattice structure than amorphous silicon, and the crystal structure of the microcrystalline silicon after crystallization is more regular and ordered, which is conducive to the positioning and diffusion of doped atoms, and improves the doping efficiency, thereby helping to improve the carrier mobility, improve the conductivity of the thin film, and improve the fill factor and conversion efficiency of the battery. Moreover, the P-type microcrystalline silicon carbide layer has good acid corrosion resistance and is applicable to a wide range of manufacturing processes. In each manufacturing step (such as etching openings on the back and cleaning thereof), it can ensure that the film performance will not be affected, which is conducive to retaining the film performance well.

[0051] At the same time, the P-type microcrystalline silicon carbide layer affects the mobility of carriers in microcrystalline silicon carbide due to the incorporation of carbon, and the conductivity is affected. To this end, the present invention adopts a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer with a suitable high crystallization rate and a suitable thickness ratio, and controls the film thickness of the P-type microcrystalline silicon carbide layer within a suitable range. Under the effect of increasing the built-in electric field, a P-type microcrystalline silicon layer with good conductivity can be superimposed. The conductivity of the P-type microcrystalline silicon layer is about 4 orders of magnitude higher than that of conventional P-type amorphous silicon. The carrier transmission capacity in the battery is significantly improved, which is beneficial to improving the carrier collection efficiency, and is beneficial to improving the battery fill factor, thereby improving the battery efficiency. Among them, the present invention adopts a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer and an intrinsic silicon layer with a suitable thickness ratio, which can maximize the improvement of the open circuit voltage and fill factor of the battery, thereby improving the battery conversion efficiency.

[0052] Moreover, it has been found through research that the presence of boron may change the surface energy and structure of the film, affect the formation and growth mode of the crystal nucleus, and cause the crystallization process to be disturbed. Therefore, too high boron doping will cause the film to be difficult to crystallize and form a microcrystalline film. In this regard, the present invention sets the P-type microcrystalline silicon carbide layer and / or the P-type microcrystalline silicon layer to have an increasing boron doping concentration and a layered structure of not less than 5 layers. By starting from a small amount of boron doping and then gradually increasing the boron doping, on the one hand, the film in the initial stage of film formation is easy to crystallize and guide the subsequent crystallization growth of the film, so that the film achieves the desired microcrystallization effect; on the other hand, through gradient doping, with a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer with a suitable high crystallization rate and a suitable thickness ratio, an energy band gradient is formed at the PN junction interface, which can further promote the transmission of carriers and improve the fill factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 It is a schematic structural diagram of a specific embodiment of the back contact battery of the present invention.

[0055] Figure 2 It is a schematic structural diagram of another specific embodiment of the back contact battery of the present invention.

[0056] Description of Reference Numerals

[0057] 101-N-type silicon wafer; 201-tunneling oxide layer; 202-N-type doped polysilicon layer; 401-first intrinsic amorphous silicon layer; 501-second intrinsic amorphous silicon layer; 502-microcrystalline silicon oxide layer; 601-P-type microcrystalline silicon carbide layer; 602-P-type microcrystalline silicon layer; 603-P-type amorphous silicon film; 701-anti-reflection layer; 801-transparent conductive film; 901-metal electrode. DETAILED DESCRIPTION

[0058] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0059] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0060] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0061] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0062] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0063] In the first aspect, the present invention provides a back-contact battery with a specific P-type emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, the first semiconductor layer comprising a passivation layer and an N-type doped silicon layer, the second semiconductor layer comprising an intrinsic silicon layer, and the second semiconductor layer further comprising a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer sequentially arranged on the surface of the intrinsic silicon layer away from the silicon wafer to form a P-type emitter, along the direction away from the back side of the silicon wafer, the effective boron doping concentration of the P-type microcrystalline silicon carbide layer and / or the P-type microcrystalline silicon layer gradually increases according to the layered structure, and the layered structure is not less than 5 layers; and the crystallization rate of the P-type microcrystalline silicon carbide layer is 20%-40%, and the crystallization rate of the P-type microcrystalline silicon layer is 40%-80%; wherein, the thickness of the P-type microcrystalline silicon carbide layer is 3-6nm, and the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer and the intrinsic silicon layer is 1:5-10:1.5-4, preferably 1:5-10:2.0-4.

[0064] The crystallization rate of the P-type microcrystalline silicon carbide layer is 20%-40%, and specifically can be 20%, 23%, 25%, 28%, 30%, 35%, 40%, etc., and the range between any two point values.

[0065] The crystallization rate of the P-type microcrystalline silicon layer is 40%-80%, and specifically can be 40%, 43%, 45%, 50%, 55%, 60%, 65%, 70%, 80%, etc., and the range between any two point values.

[0066] In some preferred embodiments of the present invention, the crystallization rate of the P-type microcrystalline silicon layer is greater than the crystallization rate of the P-type microcrystalline silicon carbide layer.

[0067] In some preferred embodiments of the present invention, the ratio of the crystallization rate of the P-type microcrystalline silicon layer to the P-type microcrystalline silicon carbide layer is 1.5-4:1, for example, it can be 1.5:1, 1.9:1, 2.0:1, 2.5:1, 2.8:1, 3.0:1, 3.5:1, 3.8:1, 4:1, etc., and the range between any two point values.

[0068] The scheme of using a P-type microcrystalline silicon layer and a P-type microcrystalline silicon carbide layer with an optimal crystallization ratio of the present invention can improve the conductivity of the film layer, is more conducive to the band bending of the PN junction interface, and improves the separation and transport capabilities of carriers.

[0069] Preferably, the effective boron doping concentration of the first layer of the P-type microcrystalline silicon carbide layer is 1e18cm -3 -3e19cm -3 、The effective boron doping concentration of the last layer is 1e19cm -3 -8e20cm -3 The effective boron doping concentration of the first layer of the P-type microcrystalline silicon layer is 5e18cm -3 -5e19cm -3 、The effective boron doping concentration of the last layer is 5e19cm -3 -5e21cm -3 This preferred solution uses a P-type microcrystalline silicon layer and a P-type microcrystalline silicon carbide layer with suitable effective boron doping concentration variation trends, which is more conducive to improving the crystallization rates of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer to a suitably high and matching level.

[0070] In the present invention, the effective boron doping concentration of the P-type microcrystalline silicon layer and the P-type microcrystalline silicon carbide layer may be increased uniformly or non-uniformly, and may be adjusted according to actual needs and effects.

[0071] In some preferred embodiments of the present invention, the corresponding layered structures of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer are independently 8-15 layers.

[0072] In some preferred embodiments of the present invention, the effective boron doping concentrations of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer independently satisfy: the absolute value of the difference in effective boron doping concentrations between two adjacent layers in the layered structure of the P-type microcrystalline silicon carbide layer is within 5e18cm -3 -5e20cm -3 The absolute value of the difference in effective boron doping concentration between two adjacent layers in the layer structure of P-type microcrystalline silicon layer is 1e19cm -3 -1e21cm -3 This preferred solution uses a P-type microcrystalline silicon layer and a P-type microcrystalline silicon carbide layer with a suitable effective boron doping concentration gradient, which is more conducive to improving the doping efficiency of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer.

[0073] In some preferred embodiments of the present invention, the thickness of the P-type microcrystalline silicon layer is 15-40 nm.

[0074] In the solution where the P-type emitter is composed of a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer, the thickness of the P-type microcrystalline silicon layer is 20-40nm, which is more conducive to improving the battery conversion efficiency.

[0075] In some preferred embodiments of the present invention, the back contact cell with a specific P-type emitter further includes a P-type amorphous silicon film, which is disposed on the outer surface of the P-type microcrystalline silicon layer away from the P-type microcrystalline silicon carbide layer, and the P-type amorphous silicon film, the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer together form a P-type emitter. The P-type emitter is formed by stacking a P-type amorphous silicon film, a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer, the P-type amorphous silicon film has relatively few grain boundaries and crystal defects, and the top layer of the P-type microcrystalline silicon layer uses a high-density P-type amorphous silicon film, which is beneficial to improving the corrosion resistance of the P-type emitter, and is also beneficial to reducing the diffusion of In in transparent conductive film layers such as ITO films, reducing recombination, and further improving the conversion efficiency and stability of the battery.

[0076] Further preferably, the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the total thickness formed by the P-type microcrystalline silicon layer and the P-type amorphous silicon film is 1:5-10, and the ratio of the thickness of the P-type microcrystalline silicon layer to the P-type amorphous silicon film is 6-12: 1. The use of a P-type amorphous silicon film with a suitable specific thickness ratio, a P-type microcrystalline silicon carbide layer, and a P-type microcrystalline silicon layer can improve the conductivity of the film and is more conducive to improving the conversion efficiency of the battery.

[0077] More preferably, the thickness of the P-type amorphous silicon film is 2-5 nm, and the thickness of the P-type microcrystalline silicon layer is 15-35 nm. Using appropriately thin P-type amorphous silicon film and P-type microcrystalline silicon layer is more conducive to improving the fill factor of the battery.

[0078] In the solution of the present invention further including a P-type amorphous silicon film, preferably, the corresponding layered structures of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer are independently 6-12 layers. In the solution of providing a P-type amorphous silicon film, using a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer with a suitable layered structure is more conducive to improving the crystallization rate of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer.

[0079] Further preferably, the effective boron doping concentration of the P-type amorphous silicon film is 3e19cm -3 -5e20cm -3 , and / or, the crystallization rate of the P-type microcrystalline silicon layer is 50%-80%. In the scheme of setting the P-type amorphous silicon film, the P-type amorphous silicon film with a suitable doping concentration is used, which is more conducive to forming a good interface contact with the transparent conductive film layer; the P-type amorphous silicon film is combined with the P-type microcrystalline silicon layer with a suitable crystallization rate, which is more conducive to improving the conductivity and corrosion resistance of the film layer.

[0080] Preferably, in the present invention, the passivation layer is an intrinsic amorphous silicon or a tunneling oxide layer, the thickness of the intrinsic amorphous silicon is 5-12 nm, and the thickness of the tunneling oxide layer is 1-2 nm.

[0081] Preferably, the N-type doped silicon layer is an N-type doped polysilicon layer or an N-type doped amorphous silicon layer.

[0082] More preferably, the passivation layer is a tunneling oxide layer, and the N-type doped silicon layer is an N-type doped polysilicon layer. The combined passivation structure is more conducive to improving the passivation effect.

[0083] Further preferably, the thickness ratio of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer, the intrinsic silicon layer, and the tunneling oxide layer is 1-3:10-20:2-7:1, preferably 1-3:10-20:2-5:1.

[0084] In some preferred embodiments of the present invention, the passivation layer is a tunneling oxide layer, the thickness of the N-type doped silicon layer is 100-200 nm, and the effective phosphorus doping concentration is 5e19 cm -3 -5e20cm -3 .

[0085] In some other preferred embodiments of the present invention, the passivation layer is intrinsic amorphous silicon, the thickness of the N-type doped silicon layer is 7-45nm, and the effective phosphorus doping concentration is 5e18cm -3 -3e20cm -3 .

[0086] In some preferred embodiments of the present invention, the thickness of the intrinsic silicon layer is 5-12 nm.

[0087] In some preferred embodiments of the present invention, the intrinsic silicon layer is a first intrinsic amorphous silicon layer, which is more conducive to reducing surface defects, lowering surface state density, and further improving the passivation effect.

[0088] In some preferred embodiments of the present invention, the back-contact cell with a specific P-type emitter further comprises a third semiconductor layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer.

[0089] In some preferred embodiments of the present invention, the third semiconductor layer comprises a second intrinsic amorphous silicon layer and a microcrystalline silicon oxygen layer sequentially arranged in a direction away from the front side of the silicon wafer, the thickness of the second intrinsic amorphous silicon layer is 4-8nm, and the thickness of the microcrystalline silicon oxygen layer is 6-20nm. The third semiconductor layer with this preferred stacked combination is more conducive to forming a good surface field passivation effect and improving light transmittance.

[0090] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outward to cover part of the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, and a second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening region is spaced apart from the first semiconductor opening region, and the area between them is a spacing region.

[0091] Preferably, in the spacing region, a mask layer is disposed between the first semiconductor layer and the second semiconductor layer, or no mask layer is disposed, preferably no mask layer is disposed.

[0092] The type and thickness of the mask layer can refer to the prior art, for example, the type can be at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, preferably silicon nitride. The thickness of the mask layer can be, for example, 40-90nm, preferably 60-80nm.

[0093] In some preferred embodiments of the present invention, the back-contact battery with a specific P-type emitter also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an insulating groove is opened on the portion of the conductive film layer located in the spacing area; the metal electrode is arranged on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area.

[0094] The formation of the conductive film layer and its thickness and type can refer to the methods of the prior art, for example, physical vapor deposition technology (PVD) or reactive plasma deposition technology (RPD) can be used. Exemplarily, the thickness of the conductive film layer is 40-80nm, and the material of the conductive film layer can be an indium oxide-based film doped with at least one of tin, tungsten, titanium, zinc, and gallium, or a zinc oxide-based film doped with at least one of aluminum, gallium, and boron.

[0095] Preferably, the front side of the silicon wafer and the back side of the silicon wafer corresponding to the second semiconductor opening area are textured surfaces, and the back side of the silicon wafer part outside the second semiconductor opening area is a polished surface.

[0096] In a second aspect, the present invention provides a method for manufacturing a back contact battery, comprising the following steps:

[0097] S01. Provide double-sided polished silicon wafers;

[0098] S02, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer comprises a passivation layer and an N-type doped silicon layer;

[0099] S03, performing a first etching opening on the back surface obtained in S02 to form a second semiconductor opening region;

[0100] S04, removing the remaining mask layer and the first semiconductor layer in the second semiconductor opening region by texturing and cleaning, and forming a texturing surface on the front side of the silicon wafer and the second semiconductor opening region, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer by cleaning as needed;

[0101] S05, depositing an intrinsic silicon layer of a second semiconductor layer on the back surface obtained in S04;

[0102] S06, forming a third semiconductor layer on the front side of the silicon wafer obtained in S05;

[0103] S07. Using PECVD technology, a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer of a second semiconductor layer are sequentially deposited on the back side obtained in S06. During the deposition of the P-type microcrystalline silicon carbide layer and / or the P-type microcrystalline silicon layer, the volume flow ratio of diborane to silane gradually increases according to the corresponding required layered structure, and the number of layers of the layered structure is not less than 5. The crystallization rate of the P-type microcrystalline silicon carbide layer is controlled to be 20%-40%, the crystallization rate of the P-type microcrystalline silicon layer is controlled to be 40%-80%, the thickness of the P-type microcrystalline silicon carbide layer is controlled to be 3-6nm, and the thickness ratio of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer and the intrinsic silicon layer is controlled to be 1:5-10:1.5-4.

[0104] The silicon wafer in S01 is preferably an N-type single crystal silicon wafer. The silicon wafer can be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer. After double-sided polishing, the silicon wafer can also be subjected to conventional steps such as cleaning treatment, and the damaged layer on the surface of the silicon wafer can be removed by polishing and cleaning, and kept clean; the specific selection can be based on actual needs.

[0105] The structures of the first semiconductor layer, the intrinsic silicon layer, the mask layer, and the third semiconductor layer are respectively the same as the corresponding layers in the first aspect, and their formation can refer to the methods of the prior art, as long as the corresponding film layer with the required thickness and the required doping concentration can be obtained. For example, the tunneling oxide layer can be formed by a dry method or a wet method, for example, the N-type doped polysilicon layer, the mask layer, the intrinsic silicon layer, and the third semiconductor layer can be formed by tubular PECVD, LPCVD or PVD in-situ doping deposition annealing, preferably using a tubular polysilicon deposition furnace for sequential deposition and high temperature annealing.

[0106] In some preferred embodiments of the present invention, the deposition rate of the P-type microcrystalline silicon carbide layer is controlled at 0.3-1A / s, preferably 0.3-0.5A / s, and the deposition rate of the P-type microcrystalline silicon layer is controlled at 0.5-2A / s, preferably 0.5-1A / s. The present invention controls the low deposition rate, which is beneficial to improving the crystallization of the corresponding film on the one hand, and on the other hand, can promote the dense growth of the corresponding film, reduce the formation of pores and defects, and is beneficial to improving the corrosion resistance of the film, thereby further reducing the impact of the film in the subsequent cleaning process.

[0107] Further preferably, in the first layer of deposited P-type microcrystalline silicon carbide layer, the volume flow rate of diborane is 0.1%-0.8% of the volume flow rate of silane, and in the last layer of deposited P-type microcrystalline silicon carbide layer, the volume flow rate of diborane is 1%-3% of the volume flow rate of silane, which is conducive to obtaining the aforementioned preferred boron-doped concentration layered structure of the P-type microcrystalline silicon carbide layer.

[0108] Further preferably, in the first layer of deposited P-type microcrystalline silicon layer, the volume flow rate of diborane is 0.1%-0.8% of the volume flow rate of silane, and in the last layer of deposited P-type microcrystalline silicon layer, the volume flow rate of diborane is 1.0%-4.0%, preferably 1.5%-4.0%, of the volume flow rate of silane, which is beneficial to obtain the aforementioned preferred boron-doped concentration layered structure of the P-type microcrystalline silicon layer.

[0109] In some preferred embodiments of the present invention, the conditions for depositing a P-type microcrystalline silicon carbide layer include: a preset film forming temperature of 50-150°C, under the conditions of introducing a mixed gas of silane, diborane, hydrogen and methane, the methane introduced is controlled to be 3%-30% of the volume flow rate of silane, the silane flow rate is 10-200sccm, the hydrogen flow rate is 20000-200000sccm, and the reaction gas pressure is 100-1000Pa.

[0110] Preferably, the conditions for depositing a P-type microcrystalline silicon layer include: a preset film forming temperature of 140-200°C, a mixed gas of silane, diborane and hydrogen, the volume flow ratio of hydrogen and silane is controlled to be 100-500:1, a silane flow rate is 100-1000sccm, and a reaction gas pressure is 100-1000Pa.

[0111] In the present invention, the time for depositing the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer can be adjusted according to the desired target film thickness, etc. Preferably, the time for depositing the P-type microcrystalline silicon carbide layer is 20-100s, and the time for depositing the P-type microcrystalline silicon layer is 50-500s.

[0112] In some preferred embodiments of the present invention, the method for manufacturing the back contact cell further includes: in S07, after depositing the P-type microcrystalline silicon layer, depositing a P-type amorphous silicon film on the outer surface of the P-type microcrystalline silicon layer.

[0113] Further preferably, the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the total thickness formed by the P-type microcrystalline silicon layer and the P-type amorphous silicon film is controlled to be 1:5-10, and the ratio of the thickness of the P-type microcrystalline silicon layer to the P-type amorphous silicon film is controlled to be 6-12:1.

[0114] In some preferred embodiments of the present invention, the deposition conditions of the P-type amorphous silicon film include: introducing silane, diborane, and hydrogen, the reaction gas pressure is 100-300 Pa, and the deposition rate is 0.5-1.5 A / s. By depositing the P-type amorphous silicon film in a manner of adopting a higher gas pressure and a lower deposition rate, the holes can be reduced, thereby improving the compactness of amorphous silicon, which is beneficial to improving the corrosion resistance of the P-type emitter, thereby reducing the impact of the P-type emitter in the subsequent cleaning process, and is also beneficial to preventing the diffusion of In in the subsequent production of transparent conductive film layers such as ITO, reducing recombination, and further improving the battery conversion efficiency and stability.

[0115] In some preferred embodiments of the present invention, the deposition conditions of the P-type amorphous silicon film also include: a preset PECVD film forming temperature of 160-220°C, a volume flow ratio of diborane to silane of 5%-10%; and / or; a hydrogen flow rate of 1000-15000sccm, and a silane flow rate of 100-1000sccm; which is conducive to obtaining a P-type amorphous silicon film with a target doping concentration.

[0116] In some preferred embodiments of the present invention for depositing a P-type amorphous silicon film, the diborane in the first layer of the deposited P-type microcrystalline silicon layer is 0.1%-0.5% of the volume flow of silane, and the diborane in the last layer of the deposited P-type microcrystalline silicon layer is 1.0%-3.0% of the volume flow of silane. The use of a suitable flow ratio of diborane to prepare a P-type microcrystalline silicon layer can make the P-type microcrystalline silicon layer easier to crystallize, and in combination with a P-type amorphous silicon film, it is more conducive to reducing the diffusion of In in a transparent conductive film layer such as an ITO film.

[0117] In some preferred embodiments of the present invention, the method for manufacturing the back contact cell further comprises: performing a methane pretreatment step before depositing the P-type microcrystalline silicon carbide layer in S07,

[0118] Preferably, the conditions for methane pretreatment include: introducing methane and hydrogen, with a methane flow rate of 100-1000 sccm, a hydrogen flow rate of 1000-20000 sccm, and a pretreatment time of 20-60 s.

[0119] The present invention adopts a scheme of preferably performing a methane pretreatment step, which can affect the size and orientation of microcrystalline silicon film grains. The methane pretreatment is beneficial to promoting crystal growth and orderly structure formation, and is beneficial to further improving the crystallinity and electrical properties of the film.

[0120] In some preferred embodiments of the present invention, the third semiconductor layer is deposited by plate PECVD, which comprises a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer deposited sequentially, the second intrinsic amorphous silicon layer has a thickness of 4-8 nm, and the microcrystalline silicon oxide layer has a thickness of 6-20 nm.

[0121] In some preferred embodiments of the present invention, the method for manufacturing the back contact battery further comprises:

[0122] S08, depositing an anti-reflection layer on the outer surface of the third semiconductor layer on the front side obtained in S07;

[0123] S09, performing a second etching opening on a portion of the second semiconductor layer on the back side obtained in S08 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then performing cleaning;

[0124] S10, depositing a conductive film layer on the back surface obtained in S09;

[0125] S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove;

[0126] S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0127] In a third aspect, the present invention provides a back contact battery, which is made by the method for making a back contact battery according to the second aspect. The structure and performance of the back contact battery in the third aspect are the same as those of the back contact battery in the first aspect, and will not be described in detail here.

[0128] In a fourth aspect, the present invention provides a photovoltaic module, comprising the back-contact cell with a specific P-type emitter as described in the first aspect, or comprising the back-contact cell as described in the third aspect.

[0129] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0130] Example 1

[0131] A back contact battery, such as Figure 1 As shown, it is prepared by the following method:

[0132] S01, providing a polished and cleaned N-type silicon wafer 101; the N-type silicon wafer 101 is polished and cleaned to remove the damaged layer on the surface of the silicon wafer and keep it clean; the N-type silicon wafer 101 is a single crystal silicon wafer.

[0133] S02, forming a first semiconductor layer and a mask layer on the back of the silicon wafer; the first semiconductor layer comprises a tunneling oxide layer 201 and an N-type doped polysilicon layer 202; the tunneling oxide layer 201 is formed by a dry process and has a thickness of 1.5 nm; the N-type doped polysilicon layer 202 has a thickness of 150 nm and an effective phosphorus doping concentration of 8e19 cm -3 ; The mask layer is silicon nitride, formed by PECVD deposition, with a thickness of 70nm;

[0134] S03, opening the back side of the silicon wafer obtained in S02 by laser etching to remove the mask layer, the N-type doped polysilicon layer 202 and the tunnel oxide layer 201 in the second semiconductor opening region;

[0135] S04, performing texturing and cleaning on the silicon wafer obtained in S03, removing the residual mask layer 301, the N-type doped polysilicon layer 202 and the tunneling oxide layer 201 in the second semiconductor opening region; and forming a texturing surface on the surface of the silicon wafer;

[0136] S05, depositing a first intrinsic amorphous silicon layer 401 of the second semiconductor layer on the back side of the silicon wafer obtained in S04; the first intrinsic amorphous silicon layer 401 is formed by plate-type PECVD deposition and has a thickness of 10 nm;

[0137] S06, forming a third semiconductor layer on the front side of the silicon wafer obtained in S05; the third semiconductor layer is formed by depositing a second intrinsic amorphous silicon layer 501 with a thickness of 6 nm and a microcrystalline silicon oxide layer 502 with a thickness of 10 nm by plate-type PECVD;

[0138] S07, first introduce a mixed gas of methane and hydrogen for methane pretreatment, the methane flow rate is 300 sccm, the hydrogen flow rate is 10000 sccm, and the pretreatment time is 40 s;

[0139] Then, a P-type microcrystalline silicon carbide layer 601 and a P-type microcrystalline silicon layer 602 of the second semiconductor layer are deposited on the back of the silicon wafer obtained in S06. The thickness of the P-type microcrystalline silicon carbide layer 601 is 4 nm, and the thickness of the P-type microcrystalline silicon layer 602 is 30 nm;

[0140] The specific method for depositing the P-type microcrystalline silicon carbide layer 601 is as follows: firstly, the PECVD film forming temperature is preset to 80°C, and then a mixed gas of silane, diborane, hydrogen and methane is introduced, the reaction gas pressure is 500Pa, the silane flow rate is 50sccm, the hydrogen flow rate is 30000sccm, and the methane is 10% of the silane flow rate; the diborane to silane flow rate ratio gradually increases according to the layering, and the number of layering layers is 10; in the first layer, the diborane is 0.3% of the silane flow rate, and in the last layer, the diborane is 1.1% of the silane flow rate, and the diborane flow rate ratio increases uniformly from the first layer to the last layer; the deposition rate is controlled at 0.6A / s, and the total deposition time is 67s. The crystallization rate of the P-type microcrystalline silicon carbide layer 601 is 30%, and the effective boron doping concentration gradually and uniformly increases according to the layered structure in the direction away from the back of the silicon wafer. The effective boron doping concentration of the first layer of the P-type microcrystalline silicon carbide layer 601 is 5e18cm -3 、The effective boron doping concentration of the last layer is 2e20cm -3 The absolute value of the difference in effective boron doping concentration between two adjacent layers in the layered structure is 2e19cm -3 .

[0141] The specific method for depositing the P-type microcrystalline silicon layer 602 is as follows: firstly, the PECVD film forming temperature is preset to 140°C, and then a mixed gas of silane, diborane and hydrogen is introduced, the silane flow rate is 200sccm, the reaction gas pressure is 500Pa, the hydrogen and silane flow ratio is 200:1, and the diborane and silane flow ratio gradually and evenly increases according to the layering, and the number of layering layers is 8; the diborane and silane flow ratio in the first layer is 0.3%, and the diborane and silane flow ratio in the last layer is 1.5%, and the diborane flow ratio increases evenly from the first layer to the last layer; the deposition rate is controlled at 1A / s, and the total deposition time is 300s. The crystallization rate of the P-type microcrystalline silicon layer 602 is 60%, and the effective boron doping concentration gradually and evenly increases according to the layered structure in the direction away from the back of the silicon wafer. The effective boron doping concentration of the first layer of the P-type microcrystalline silicon layer 602 is 2e19cm -3 、The effective boron doping concentration of the last layer is 9e20cm -3 The absolute value of the difference in effective boron doping concentration between two adjacent layers in the layered structure is 1e20cm -3 .

[0142] S08, depositing an anti-reflection layer 701 on the front side of the silicon wafer obtained in S07;

[0143] S09, opening the back side of the silicon wafer obtained in S08 by laser etching to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning;

[0144] S10, depositing a transparent conductive film 801 on the back of the silicon wafer obtained in S09; the transparent conductive film 801 is a doped indium oxide system, deposited by PVD, and has a thickness of 100 nm;

[0145] S11, etching an opening on the surface of the spacer region between the second semiconductor opening region and the first semiconductor opening region on the back side of the silicon wafer obtained in S10 to form an insulating groove between the second semiconductor opening region and the first semiconductor opening region to isolate the first semiconductor and the second semiconductor to avoid short circuit;

[0146] S12, forming metal electrodes 901 on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S11.

[0147] Example 2

[0148] The method of Example 1 is referred to, except that the thickness of the P-type microcrystalline silicon carbide layer is changed to 3nm, and the thickness ratio of the P-type microcrystalline silicon carbide layer to the tunneling oxide layer is calculated to be 2:1, and the thickness ratio of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer and the first intrinsic amorphous silicon layer is 1:10:3.3, and the crystallization rate and layered structure of the P-type microcrystalline silicon carbide layer remain unchanged (that is, the number of layers remains unchanged, and the doping concentrations of the first and last layers remain unchanged). The process parameters that need to be changed to obtain a P-type microcrystalline silicon carbide layer of this thickness are: the deposition rate is controlled at 0.5A / s, and the total deposition time is 60s.

[0149] Example 3

[0150] The method of Example 1 is referred to, except that the thickness of the first intrinsic amorphous silicon layer is changed to 7.5 nm. After calculation, the thickness ratio of the first intrinsic amorphous silicon layer and the tunneling oxide layer is 5:1, and the thickness ratio of the P-type microcrystalline silicon carbide layer and the first intrinsic amorphous silicon layer is 1:1.88.

[0151] Example 4

[0152] The method of Example 1 is followed, except that the crystallization rate of the P-type microcrystalline silicon layer is adjusted so that its ratio to the crystallization rate of the P-type microcrystalline silicon carbide layer is 1.5:1, and the process parameters that need to be changed to achieve this goal are: adjusting the hydrogen flow rate so that the ratio of hydrogen to silane flow rates is 150:1.

[0153] Example 5

[0154] The method of Example 1 is followed, except that the P-type microcrystalline silicon carbide layer has a layered structure of 5 layers, the effective boron doping concentration of the first layer and the last layer remains unchanged, but the absolute value of the difference in effective boron doping concentration between two adjacent layers in the layered structure is 4e19cm -3,The process parameters that need to be changed to achieve this goal are: the diborane flow rate of each layer is evenly increased in a 5-layer structure according to the diborane to silane flow ratio, and the deposition time of each layer is 12 s.

[0155] Example 6

[0156] The method of Example 1 is referred to, except that no methane pretreatment step is performed before depositing the P-type microcrystalline silicon carbide layer in S07, and the structural change of the obtained P-type microcrystalline silicon carbide layer is as follows: the crystallization rate of the P-type microcrystalline silicon carbide layer is 20%.

[0157] Example 7

[0158] The method of Example 1 is referred to, except that the passivation structure is not a joint passivation, but a conventional heterojunction passivation. Specifically, the first semiconductor layer comprises an intrinsic amorphous silicon layer with a thickness of 5 nm and an N-type doped amorphous silicon layer (with a thickness of 10 nm and a doping concentration of 2e19 cm -3 ).

[0159] Example 8

[0160] The method according to Example 1 is carried out, except that Figure 2 As shown, in S07, after depositing the P-type microcrystalline silicon layer 602, a P-type amorphous silicon film 603 is then deposited on the outer surface of the P-type microcrystalline silicon layer 602. The deposition process of the P-type amorphous silicon film 603 includes: the PECVD film forming temperature is preset to 180°C, and then silane, diborane and hydrogen are introduced. The silane flow rate is 100sccm, the hydrogen flow rate is 5000sccm, the volume flow ratio of diborane to silane is 8%, the reaction gas pressure is 200Pa, and the deposition rate is 1.0A / s; the film thickness of the P-type amorphous silicon film 603 is 3nm. After calculation, the ratio of the thickness of the P-type microcrystalline silicon carbide layer 601 to the total thickness formed by the P-type microcrystalline silicon layer 602 and the P-type amorphous silicon film 603 is 1:8.25, and the ratio of the thickness of the P-type microcrystalline silicon layer 602 to the P-type amorphous silicon film 603 is 10:1.

[0161] Example 9

[0162] The method of Example 8 is referred to, except that the thickness of the P-type amorphous silicon film is adjusted to 4 nm, so that the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the total thickness formed by the P-type microcrystalline silicon layer and the P-type amorphous silicon film is 1:8.5, and the ratio of the thickness of the P-type microcrystalline silicon layer to the P-type amorphous silicon film is 7.5:1. The process parameters that need to be adjusted accordingly to meet the film thickness of the P-type amorphous silicon film are: the silane flow rate is 150 sccm, and the reaction gas pressure is 150 Pa.

[0163] Comparative Example 1

[0164] The method of Example 1 is referred to, except that, instead of depositing a P-type microcrystalline silicon carbide layer in the second semiconductor layer, a P-type microcrystalline silicon layer is directly deposited on the outer surface of the first intrinsic amorphous silicon layer.

[0165] Comparative Example 2

[0166] The method of Example 1 is followed, except that the P-type microcrystalline silicon layer is replaced by a conventional P-type amorphous silicon layer, and the deposition method of the corresponding P-type amorphous silicon layer is as follows: the PECVD film forming temperature is preset to 200°C, and then a mixed gas of silane, diborane and hydrogen is introduced, the reaction gas pressure is 80Pa, the silane flow rate is 1000sccm, the hydrogen flow rate is 1000sccm, and the diborane flow rate is 6% of the silane flow rate; the film thickness of the P-type amorphous silicon layer is 12nm.

[0167] Comparative Example 3

[0168] The method of Example 1 is referred to, except that the boron doping concentrations of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer are adjusted to remain unchanged, and their boron doping concentrations in the thickness direction are respectively the effective boron doping concentrations of the last layer of the corresponding silicon layer in Example 1, and the process parameters that need to be changed to achieve this goal are: during the deposition of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer, the volume flow ratio of diborane to silane remains unchanged, and are respectively based on the volume flow ratio of diborane to silane of the last layer of the corresponding silicon layer in Example 1.

[0169] Test Case

[0170] The back contact cells obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The performance indicators of each embodiment and comparative example were converted using comparative example 2 as a reference benchmark, and the data of comparative example 2 was normalized to 1.000. Other examples were converted based on comparative example 2, such as the short-circuit current of embodiment 1 / short-circuit current of comparative example 2 was 1.003. Among them, when converting, the unit of short-circuit current is A, the unit of open-circuit voltage is V, the unit of fill factor is %, the unit of battery conversion efficiency is %, and the unit of conductivity is S / cm.

[0171] Table 1

[0172]

[0173] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention is beneficial to improving the open circuit voltage of the battery, improving the conductivity of the film, and improving the fill factor and conversion efficiency of the battery.

[0174] Furthermore, according to Examples 1 and 2-9, it can be seen that the use of the preferred battery structure of the present invention is more conducive to obtaining the comprehensive effect of further improving the open circuit voltage and short circuit current of the battery, improving the conductivity of the film, and improving the fill factor and conversion efficiency of the battery.

[0175] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A back-contact cell with a specific P-type emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon wafer, the first semiconductor layer comprising a passivation layer and an N-type doped silicon layer, and the second semiconductor layer comprising an intrinsic silicon layer, characterized in that: The second semiconductor layer also includes a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer sequentially arranged on the surface of the side of the intrinsic silicon layer away from the silicon wafer to form a P-type emitter, and along the direction away from the back of the silicon wafer, the effective boron doping concentration of the P-type microcrystalline silicon carbide layer and / or the P-type microcrystalline silicon layer gradually increases according to the layered structure, and the layered structure is not less than 5 layers; and the crystallization rate of the P-type microcrystalline silicon carbide layer is 20%-40%, and the crystallization rate of the P-type microcrystalline silicon layer is 40%-80%; wherein, the thickness of the P-type microcrystalline silicon carbide layer is 3-6nm, and the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer and the intrinsic silicon layer is 1:5-10:1.5-4.

2. The back contact cell with a specific P-type emitter according to claim 1, characterized in that: The crystallization rate of the P-type microcrystalline silicon layer is greater than the crystallization rate of the P-type microcrystalline silicon carbide layer.

3. The back contact cell with a specific P-type emitter according to claim 2, characterized in that: The ratio of the crystallization rate of the P-type microcrystalline silicon layer to the P-type microcrystalline silicon carbide layer is 1.5-4:

1.

4. The back contact cell with a specific P-type emitter according to claim 1, characterized in that: The effective boron doping concentration of the first layer of the P-type microcrystalline silicon carbide layer is 1e18cm -3 -3e19cm -3 、The effective boron doping concentration of the last layer is 1e19cm -3 -8e20cm -3 The effective boron doping concentration of the first layer of the P-type microcrystalline silicon layer is 5e18cm -3 -5e19cm -3 、The effective boron doping concentration of the last layer is 5e19cm -3 -5e21cm -3 .

5. The back contact cell with a specific P-type emitter according to claim 1, characterized in that: The corresponding layered structures of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer are independently 8-15 layers, and / or the thickness of the P-type microcrystalline silicon layer is 15-40 nm.

6. The back contact cell with a specific P-type emitter according to claim 1, characterized in that: The effective boron doping concentrations of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer independently satisfy: the absolute value of the difference in effective boron doping concentrations of two adjacent layers in the layered structure of the P-type microcrystalline silicon carbide layer is within 5e18cm -3 -5e20cm -3 The absolute value of the difference in effective boron doping concentration between two adjacent layers in the layer structure of P-type microcrystalline silicon layer is 1e19cm -3 -1e21cm -3 .

7. The back contact cell with a specific P-type emitter according to claim 1, characterized in that: The back-contact battery with a specific P-type emitter also includes a P-type amorphous silicon film, which is arranged on the outer surface of the P-type microcrystalline silicon layer on the side away from the P-type microcrystalline silicon carbide layer. The P-type amorphous silicon film, the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer together form a P-type emitter, the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the total thickness formed by the P-type microcrystalline silicon layer and the P-type amorphous silicon film is 1:5-10, and the ratio of the thickness of the P-type microcrystalline silicon layer to the P-type amorphous silicon film is 6-12:

1.

8. The back contact cell with a specific P-type emitter according to claim 7, characterized in that: The thickness of the P-type amorphous silicon film is 2-5 nm, and the thickness of the P-type microcrystalline silicon layer is 15-35 nm; and / or, The corresponding layered structures of the P-type microcrystalline silicon carbide layer and the P-type microcrystalline silicon layer are independently 6-12 layers.

9. The back contact cell with a specific P-type emitter according to claim 7 or 8, characterized in that: The effective boron doping concentration of P-type amorphous silicon film is 3e19cm -3 -5e20cm -3 , and / or, the crystallization rate of the P-type microcrystalline silicon layer is 50%-80%.

10. The back contact cell with a specific P-type emitter according to claim 1, characterized in that: The back contact cell with a specific P-type emitter also has the following structure: Structure 1: The intrinsic silicon layer is a first intrinsic amorphous silicon layer; Structure 2: The passivation layer is an intrinsic amorphous silicon or a tunneling oxide layer, the thickness of the tunneling oxide layer is 1-2 nm, the thickness ratio of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer, the intrinsic silicon layer, and the tunneling oxide layer is 1-3:10-20:2-7:1; the thickness of the intrinsic amorphous silicon and the intrinsic silicon layer is independently 5-12 nm, and the N-type doped silicon layer is an N-type doped polycrystalline silicon layer; Structure 3: The passivation layer is a tunneling oxide layer, the thickness of the N-type doped silicon layer is 100-200nm, and the effective phosphorus doping concentration is 5e19cm -3 -5e20cm -3 .

11. The back contact cell with a specific P-type emitter according to claim 1, characterized in that: The back-contact cell with a specific P-type emitter further comprises a third semiconductor layer and an anti-reflection layer which are sequentially arranged on the front side of the silicon wafer.

12. The back contact cell with a specific P-type emitter according to claim 11, characterized in that: The third semiconductor layer includes a second intrinsic amorphous silicon layer and a microcrystalline silicon oxygen layer arranged in sequence in a direction away from the front side of the silicon wafer. The thickness of the second intrinsic amorphous silicon layer is 4-8 nm, and the thickness of the microcrystalline silicon oxygen layer is 6-20 nm.

13. The back contact cell with a specific P-type emitter according to claim 1, characterized in that: The two ends of the second semiconductor layer extend outward to cover the part of the back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, and a second semiconductor opening area is formed between the adjacent first semiconductor layers. The second semiconductor opening area is arranged at intervals from the first semiconductor opening area, and the area between them is a spacing area. In the spacing area, a mask layer is set between the first semiconductor layer and the second semiconductor layer, or no mask layer is set. The back-contact battery with a specific P-type emitter also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an insulating groove is opened on the part of the conductive film layer located in the spacing area. The metal electrode is arranged on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area. The front side of the silicon wafer and the back side of the silicon wafer corresponding to the second semiconductor opening area are velvet surfaces, and the back side of the silicon wafer located outside the second semiconductor opening area is a polished surface.

14. A method for manufacturing a back contact battery, characterized in that: The steps include: S01. Provide double-sided polished silicon wafers; S02, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer comprises a passivation layer and an N-type doped silicon layer; S03, performing a first etching opening on the back surface obtained in S02 to form a second semiconductor opening region; S04, removing the remaining mask layer and the first semiconductor layer in the second semiconductor opening region by texturing and cleaning, and forming a texturing surface on the front side of the silicon wafer and the second semiconductor opening region, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer by cleaning as needed; S05, depositing an intrinsic silicon layer of a second semiconductor layer on the back surface obtained in S04; S06, forming a third semiconductor layer on the front side of the silicon wafer obtained in S05; S07. Using PECVD technology, a P-type microcrystalline silicon carbide layer and a P-type microcrystalline silicon layer of a second semiconductor layer are sequentially deposited on the back side obtained in S06. During the deposition of the P-type microcrystalline silicon carbide layer and / or the P-type microcrystalline silicon layer, the volume flow ratio of diborane to silane gradually increases according to the corresponding required layered structure, and the number of layers of the layered structure is not less than 5. The crystallization rate of the P-type microcrystalline silicon carbide layer is controlled to be 20%-40%, the crystallization rate of the P-type microcrystalline silicon layer is controlled to be 40%-80%, the thickness of the P-type microcrystalline silicon carbide layer is controlled to be 3-6nm, and the thickness ratio of the P-type microcrystalline silicon carbide layer to the P-type microcrystalline silicon layer and the intrinsic silicon layer is controlled to be 1:5-10:1.5-4.

15. The method for manufacturing a back contact battery according to claim 14, characterized in that: The deposition rate of the P-type microcrystalline silicon carbide layer is controlled at 0.3-1 A / s, and the deposition rate of the P-type microcrystalline silicon layer is controlled at 0.5-2 A / s.

16. The method for manufacturing a back contact battery according to claim 14, characterized in that: In the first layer of deposited P-type microcrystalline silicon carbide layer, the diborane is 0.1%-0.8% of the volume flow rate of silane, and in the last layer of deposited P-type microcrystalline silicon carbide layer, the diborane is 1%-3% of the volume flow rate of silane; in the first layer of deposited P-type microcrystalline silicon layer, the diborane is 0.1%-0.8% of the volume flow rate of silane, and in the last layer of deposited P-type microcrystalline silicon layer, the diborane is 1.0%-4.0% of the volume flow rate of silane; and / or, The conditions for depositing a P-type microcrystalline silicon carbide layer include: a preset film forming temperature of 50-150°C, under the condition of introducing a mixed gas of silane, diborane, hydrogen and methane, the methane introduced is controlled to be 3%-30% of the volume flow rate of silane, the silane flow rate is 10-200sccm, the hydrogen flow rate is 20000-200000sccm, and the reaction gas pressure is 100-1000Pa; the conditions for depositing a P-type microcrystalline silicon layer include: a preset film forming temperature of 140-200°C, under the condition of introducing a mixed gas of silane, diborane and hydrogen, the volume flow ratio of hydrogen and silane is controlled to be 100-500:1, the silane flow rate is 100-1000sccm, and the reaction gas pressure is 100-1000Pa.

17. The method for manufacturing a back contact battery according to claim 14, characterized in that: The method for manufacturing the back contact battery also includes: in S07, after depositing the P-type microcrystalline silicon layer, depositing a P-type amorphous silicon film on the outer surface of the P-type microcrystalline silicon layer, controlling the ratio of the thickness of the P-type microcrystalline silicon carbide layer to the total thickness formed by the P-type microcrystalline silicon layer and the P-type amorphous silicon film to be 1:5-10, and the ratio of the thickness of the P-type microcrystalline silicon layer to the P-type amorphous silicon film to be 6-12:

1.

18. The method for manufacturing a back contact battery according to claim 17, characterized in that: The deposition conditions of the P-type amorphous silicon film include: the PECVD film forming temperature is preset to be 160-220°C, silane, diborane and hydrogen are introduced, the reaction gas pressure is 100-300 Pa, the volume flow ratio of diborane to silane is 5%-10%, and the deposition rate is 0.5-1.5 A / s; and / or, In the first layer of deposited P-type microcrystalline silicon layer, the volume flow rate of diborane is 0.1%-0.5% of the volume flow rate of silane, and in the last layer of deposited P-type microcrystalline silicon layer, the volume flow rate of diborane is 1.0%-3.0% of the volume flow rate of silane.

19. The method for manufacturing a back contact battery according to any one of claims 14 to 18, characterized in that: The method for manufacturing the back contact battery also includes: performing a methane pretreatment step before depositing the P-type microcrystalline silicon carbide layer in S07, and the conditions for the methane pretreatment include: introducing methane and hydrogen, the methane flow rate is 100-1000sccm, the hydrogen flow rate is 1000-20000sccm, and the pretreatment time is 20-60s.

20. The method for manufacturing a back contact battery according to any one of claims 14 to 18, characterized in that: The third semiconductor layer is deposited by plate-type PECVD, which includes a second intrinsic amorphous silicon layer and a microcrystalline silicon oxygen layer deposited in sequence, the second intrinsic amorphous silicon layer has a thickness of 4-8 nm, and the microcrystalline silicon oxygen layer has a thickness of 6-20 nm; and / or, The method for manufacturing the back contact battery further includes: S08, depositing an anti-reflection layer on the outer surface of the third semiconductor layer on the front side obtained in S07; S09, performing a second etching opening on a portion of the second semiconductor layer on the back side obtained in S08 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then performing cleaning; S10, depositing a conductive film layer on the back surface obtained in S09; S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove; S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

21. A back contact battery, characterized in that: It is manufactured by the method for manufacturing a back contact battery as described in any one of claims 14 to 20.

22. A photovoltaic module, characterized in that: A back-contact cell comprising a specific P-type emitter as claimed in any one of claims 1 to 13, or a back-contact cell as claimed in claim 21.

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