Joint passivated back contact cell with specific P-type emitter and its preparation and application

Abstract

The present invention belongs to the technical field of back contact batteries, and specifically relates to a combined passivation back contact battery with a specific P-type emitter, and its preparation and application. The second semiconductor layer also includes hydrogenated microcrystalline silicon carbide and a P-type microcrystalline silicon film sequentially arranged on the outer surface of the first intrinsic amorphous silicon layer to form a P-type emitter, and in the direction away from the back of the silicon wafer, the effective boron doping concentration of the P-type microcrystalline silicon film gradually increases according to the layered structure, and the layered structure is greater than 3 layers; wherein the crystallization rate of hydrogenated microcrystalline silicon carbide is 40%-80%, the hydrogen content in hydrogenated microcrystalline silicon carbide in terms of atomic percentage is 10%-30%, and the ratio of the crystallization rate of hydrogenated microcrystalline silicon carbide to that of the P-type microcrystalline silicon film is 1:0.5-1.2. The present invention can be beneficial to promoting the rapid separation of photogenerated carriers, reducing recombination, improving the open circuit voltage of the battery, improving the collection efficiency of carriers, and improving the fill factor of the battery, thereby improving the battery conversion efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a combined passivation back contact battery with a specific P-type emitter and its manufacture and application. Background Art

[0002] The existing back-contact heterojunction battery includes an N-type single-crystal silicon wafer, an intrinsic amorphous silicon layer and an anti-transmittance layer (anti-reflection layer) arranged in sequence on the pyramid velvet surface on the front side of the silicon wafer, an intrinsic amorphous silicon layer, a P-type amorphous silicon layer, a transparent conductive film layer, and a metal gate line layer arranged in sequence on the surface of the P region on the back side of the silicon wafer, and an intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a transparent conductive film layer, and a metal gate line layer arranged in sequence on the surface of the N region on the back side of the silicon wafer.

[0003] There is also a combined passivation back contact cell in the prior art, in which the first semiconductor layer is passivated by a tunneling oxide layer and the second semiconductor layer is passivated by an intrinsic silicon layer, and the cell conversion efficiency is higher than that of a conventional heterojunction. However, the P-type amorphous silicon layer in the second semiconductor layer has low carrier mobility, more impurities and defects, and poor conductivity, which affects the cell conversion efficiency.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the prior art in that the P-type amorphous silicon layer in the second semiconductor layer of a combined passivated back contact battery has low carrier mobility, more impurities and defects, and poor conductivity, thereby affecting the battery conversion efficiency, and to provide a combined passivated back contact battery with a specific P-type emitter and its preparation and application, which can help promote the rapid separation of photogenerated carriers, reduce recombination, increase the open circuit voltage of the battery, improve the carrier collection efficiency, and improve the fill factor of the battery, thereby improving the battery conversion efficiency.

[0006] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a combined passivation back contact cell with a specific P-type emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, the first semiconductor layer comprising a tunneling oxide layer and an N-type doped polycrystalline silicon layer, the second semiconductor layer comprising a first intrinsic amorphous silicon layer, the second semiconductor layer further comprising hydrogenated microcrystalline silicon carbide and a P-type microcrystalline silicon film sequentially arranged on the outer surface of the first intrinsic amorphous silicon layer, forming a P-type emitter, and in a direction away from the back side of the silicon wafer, The effective boron doping concentration of the P-type microcrystalline silicon film gradually increases according to the layered structure, and the layered structure is greater than 3 layers; wherein the crystallization rate of hydrogenated microcrystalline silicon carbide is 40%-80%, the hydrogen content in the hydrogenated microcrystalline silicon carbide in terms of atomic percentage is 10%-30%, the ratio of the crystallization rate of hydrogenated microcrystalline silicon carbide to that of the P-type microcrystalline silicon film is 1:0.5-1.2, and the ratio of the thickness of the hydrogenated microcrystalline silicon carbide to the P-type microcrystalline silicon film, the first intrinsic amorphous silicon layer, and the N-type doped polycrystalline silicon layer is 1:4-10:1.5-3:20-100.

[0007] In some preferred embodiments of the present invention, the thickness of the hydrogenated microcrystalline silicon carbide is 2-4 nm, and / or the carbon doping concentration of the hydrogenated microcrystalline silicon carbide is 1e19 cm -3 -1e21cm -3 .

[0008] In some preferred embodiments of the present invention, the crystallization rate of the P-type microcrystalline silicon film is 40%-70%, and / or the thickness of the P-type microcrystalline silicon film is 15-30 nm.

[0009] In some preferred embodiments of the present invention, the effective boron doping concentration of the first layer of the P-type microcrystalline silicon film is 1e18 cm -3 -2e19cm -3 、The effective boron doping concentration of the last layer is 2e19cm -3 -3e21cm -3 ;

[0010] and / or,

[0011] The absolute value of the difference in effective boron doping concentration between two adjacent layers in the layered structure of P-type microcrystalline silicon film is 1e19cm -3 -8e20cm -3 .

[0012] In some preferred embodiments of the present invention, the layered structure of the P-type microcrystalline silicon film is 5-15 layers, and / or the thickness ratio of the hydrogenated microcrystalline silicon carbide to the first intrinsic amorphous silicon layer and the tunneling oxide layer is 1:1.5-3:0.5-0.8.

[0013] In some preferred embodiments of the present invention, the second semiconductor layer further comprises a P-type amorphous silicon film disposed on the outer surface of the P-type microcrystalline silicon film, the P-type amorphous silicon film, the hydrogenated microcrystalline silicon carbide, and the P-type microcrystalline silicon film together form a P-type emitter, and the thickness of the P-type amorphous silicon film is 2-5 nm, and the effective boron doping concentration is 1e18 cm -3 -1e20cm -3 .

[0014] In some preferred embodiments of the present invention, the combined passivation back contact cell with a specific P-type emitter further has at least one of the following structures:

[0015] Structure 1: The combined passivation back contact cell with a specific P-type emitter further comprises a third semiconductor layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, wherein the third semiconductor layer comprises a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer sequentially arranged;

[0016] Structure 2: The thickness of the tunnel oxide layer is 1-2nm, the thickness of the N-type doped polysilicon layer is 100-200nm, and the effective phosphorus doping concentration is 5e19cm -3 -5e20cm -3 ;

[0017] Structure 3: The thickness of the first intrinsic amorphous silicon layer is 5-12 nm;

[0018] Structure 4: The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, and a second semiconductor opening area is formed between the adjacent first semiconductor layers. The second semiconductor opening area is arranged at intervals from the first semiconductor opening area, and the area between them is an overlapping area. In the overlapping area, a mask layer is set between the first semiconductor layer and the second semiconductor layer, or no mask layer is set; the combined passivated back contact battery with a specific P-type emitter also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an insulating groove is opened on the portion of the conductive film layer located in the overlapping area; the metal electrode is set on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area.

[0019] In a second aspect, the present invention provides a method for manufacturing a combined passivation back contact cell having a specific P-type emitter, comprising the following steps:

[0020] S1, provide silicon wafers;

[0021] S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling oxide layer and an N-type doped polysilicon layer;

[0022] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0023] S4, performing texturing cleaning to simultaneously form a texturing surface on the front side of the silicon wafer and the second semiconductor opening region, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer through cleaning according to needs;

[0024] S5, depositing a first intrinsic amorphous silicon layer of a second semiconductor layer on the back surface obtained in S4;

[0025] S6, forming a third semiconductor layer on the front side of the silicon wafer obtained in S5;

[0026] S7, sequentially depositing a hydrogenated microcrystalline silicon carbide film and a P-type microcrystalline silicon film as a second semiconductor layer on the back surface obtained in S6;

[0027] The deposition conditions of hydrogenated microcrystalline silicon carbide include: setting the PECVD film forming temperature to 100-200°C, introducing silane, hydrogen and methane, controlling the volume flow ratio of hydrogen to silane to 190-500:1, the volume flow ratio of methane to silane to 1:5-50, and the power density to 80-200mW / cm 2 , the deposition rate is 0.2-0.8A / s; the crystallization rate of hydrogenated microcrystalline silicon carbide is controlled to be 40%-80%, and the hydrogen content in hydrogenated microcrystalline silicon carbide is 10%-30% in terms of atomic percentage;

[0028] The deposition conditions of the P-type microcrystalline silicon film include: introducing silane, diborane and hydrogen, the volume flow ratio of diborane to silane gradually increases according to the corresponding required layered structure, the number of layers of the layered structure is greater than 3, and the deposition rate is 1-3A / s; and the crystallization rate ratio of hydrogenated microcrystalline silicon carbide to the P-type microcrystalline silicon film is controlled to be 1:0.5-1.2, and the thickness ratio of hydrogenated microcrystalline silicon carbide to the P-type microcrystalline silicon film, the first intrinsic amorphous silicon layer, and the N-type doped polycrystalline silicon layer is 1:4-10:1.5-3:20-100.

[0029] In some preferred embodiments of the present invention, the volume flow rate of diborane in the first layer of the deposited P-type microcrystalline silicon film layered structure is 0.2%-1.0% of the volume flow rate of silane, and the volume flow rate of diborane in the last layer of the deposited P-type microcrystalline silicon film is 2.0%-5.0% of the volume flow rate of silane.

[0030] In some preferred embodiments of the present invention, the deposition conditions of the hydrogenated microcrystalline silicon carbide further include: a silane flow rate of 40-200 sccm, a reaction gas pressure of 100-1000 Pa;

[0031] and / or,

[0032] The deposition conditions of the P-type microcrystalline silicon film also include: a preset PECVD film forming temperature of 140-200° C., a reaction gas pressure of 100-1000 Pa, a volume flow ratio of hydrogen to silane of 100-500:1, a power density of 300-500 mW / cm 2 .

[0033] In some preferred embodiments of the present invention, the method for manufacturing the combined passivation back contact cell with a specific P-type emitter further comprises:

[0034] In S7, a layer of P-type amorphous silicon film is deposited on the outer surface of the P-type microcrystalline silicon film. The deposition conditions of the P-type amorphous silicon film include: a preset PECVD film forming temperature of 140-200° C., introduction of silane, diborane, and hydrogen, a reaction gas pressure of 40-100 Pa, a volume flow ratio of diborane to silane of 5%-10%, and a power density of 10-50 mW / cm 2 , the deposition rate of the P-type amorphous silicon film is 0.5-1.5A / s; the film thickness of the P-type amorphous silicon film is 2-5nm;

[0035] S8, depositing an anti-reflection layer on the outer surface of the third semiconductor layer on the front side obtained in S7;

[0036] S9, performing a second etching opening on a portion of the second semiconductor layer on the back side obtained in S8 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then performing cleaning;

[0037] S10, depositing a transparent conductive film layer on the back surface obtained in S9;

[0038] S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove;

[0039] S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0040] In a third aspect, the present invention provides a combined passivated back contact cell with a specific P-type emitter, which is manufactured by the method for manufacturing a combined passivated back contact cell with a specific P-type emitter described in the second aspect.

[0041] In a fourth aspect, the present invention provides a battery assembly, which includes the combined passivated back contact battery with a specific P-type emitter described in the first aspect, or includes the combined passivated back contact battery with a specific P-type emitter described in the third aspect.

[0042] Beneficial effects:

[0043] The present invention adopts the above-mentioned technical scheme, especially in the combined passivation structure, to replace the conventional P-type amorphous silicon emitter with hydrogenated microcrystalline silicon carbide and P-type microcrystalline silicon film. The hydrogenated microcrystalline silicon carbide adopts a higher crystallization rate to provide an ordered structure, which provides a starting point for the subsequent crystallization growth of the P-type microcrystalline silicon film, and is beneficial to the orderly growth of crystals to form a uniform, continuous and dense P-type microcrystalline silicon film. The introduction of carbon elements in hydrogenated microcrystalline silicon carbide and hydrogen with an appropriate content can adjust the lattice structure and grain orientation, which is beneficial to optimize the crystallization quality and stability of the film, and improve the film quality of hydrogenated microcrystalline silicon carbide and P-type microcrystalline silicon film. In addition, hydrogenated microcrystalline silicon carbide has a higher optical band gap. When combined with a P-type microcrystalline silicon film, a first intrinsic amorphous silicon layer, and an N-type doped polycrystalline silicon layer with a suitable thickness ratio, it is beneficial to promote the band bending at the PN junction interface, thereby forming a larger built-in electric field, which is beneficial to promote the rapid separation of photogenerated carriers at the interface of the joint passivation structure, reduce the recombination loss of carriers on the surface, and improve the open circuit voltage and conversion efficiency of the battery; the P-type microcrystalline silicon film with a suitable crystallization rate ratio has higher conductivity, and the carrier transmission capacity in the battery is significantly improved, which is beneficial to improve the carrier collection efficiency, improve the battery fill factor, and thus improve the battery conversion efficiency.

[0044] Among them, the present invention also combines a P-type microcrystalline silicon film with a specific effective boron doping concentration greater than a 3-layer layered structure with hydrogenated microcrystalline silicon carbide without boron doping, which can improve the crystallization rate of the overall microcrystalline silicon stack, and is more conducive to improving the conductivity of the film layer and improving battery efficiency.

[0045] In the manufacturing method of the present invention, hydrogenated microcrystalline silicon carbide is deposited at a relatively low deposition rate without the influence of doped boron atoms, and microcrystallization can be formed under conditions of a relatively low power density. Therefore, the influence on the first intrinsic amorphous silicon layer thereunder is relatively small, so that the battery can maintain a good passivation effect; and it is beneficial to reduce the difficulty of preparing the P-type microcrystalline silicon film, and the deposition rate of the P-type microcrystalline silicon film can be increased, which is beneficial to shortening the production cycle and improving production capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 It is a structural schematic diagram of a specific implementation mode of the combined passivation back contact battery of the present invention.

[0048] Description of Reference Numerals

[0049] 101-N-type silicon wafer; 201-tunneling silicon oxide layer; 202-N-type doped polysilicon layer; 401-first intrinsic amorphous silicon layer; 501-second intrinsic amorphous silicon layer; 502-microcrystalline silicon oxide layer; 601-hydrogenated microcrystalline silicon carbide; 602-P-type microcrystalline silicon film, 603-P-type amorphous silicon film; 701-anti-reflection layer; 801-transparent conductive film layer; 901-metal electrode. DETAILED DESCRIPTION

[0050] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0052] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0053] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0054] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0055] In the first aspect, the present invention provides a combined passivation back contact cell with a specific P-type emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon wafer, the first semiconductor layer comprising a tunneling oxide layer and an N-type doped polysilicon layer, the second semiconductor layer comprising a first intrinsic amorphous silicon layer, the second semiconductor layer further comprising hydrogenated microcrystalline silicon carbide and a P-type microcrystalline silicon film sequentially arranged on the outer surface of the first intrinsic amorphous silicon layer, forming a P-type emitter, and in the direction away from the back of the silicon wafer, the effective boron doping concentration of the P-type microcrystalline silicon film gradually increases according to the layered structure, and the layered structure is greater than 3 layers. It can be understood that the hydrogenated microcrystalline silicon carbide is not doped with boron.

[0056] The crystallization rate of hydrogenated microcrystalline silicon carbide is 40%-80%, preferably 50%-80%, and more preferably 55%-80%, and the ratio of the crystallization rate of hydrogenated microcrystalline silicon carbide to that of P-type microcrystalline silicon film is 1:0.5-1.2, preferably 1:0.5-0.9. The use of hydrogenated microcrystalline silicon carbide with a suitable high crystallization rate and hydrogenated microcrystalline silicon carbide and P-type microcrystalline silicon film with a suitable crystallization rate ratio is conducive to reducing the interface defect density.

[0057] The hydrogen content in hydrogenated microcrystalline silicon carbide is 10%-30% by atomic percentage, and specifically can be 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, etc. and the range between any two point values. Using hydrogenated microcrystalline silicon carbide with an appropriate hydrogen concentration is more conducive to improving the quality of the film.

[0058] The thickness ratio of hydrogenated microcrystalline silicon carbide to the P-type microcrystalline silicon film, the first intrinsic amorphous silicon layer, and the N-type doped polycrystalline silicon layer is 1:4-10:1.5-3:20-100, preferably 1:7-10:2.5-3:60-100. The use of hydrogenated microcrystalline silicon carbide to the P-type microcrystalline silicon film, the first intrinsic amorphous silicon layer, and the N-type doped polycrystalline silicon layer with a suitable thickness ratio is beneficial to the separation and transportation of carriers.

[0059] In some preferred embodiments of the present invention, the thickness of hydrogenated microcrystalline silicon carbide is 2-4 nm. Using hydrogenated microcrystalline silicon carbide of appropriate thickness can improve the quality of microcrystalline silicon growth in hydrogenated microcrystalline silicon carbide and is more conducive to improving the crystallization rate of microcrystalline silicon.

[0060] In some preferred embodiments of the present invention, the carbon doping concentration of hydrogenated microcrystalline silicon carbide is 1e19 cm -3 -1e21cm -3 , preferably 4e20cm -3 -1e21cm -3The use of hydrogenated microcrystalline silicon carbide with a suitable carbon doping concentration can promote the crystallization process of microcrystalline silicon and is more conducive to improving the built-in electric field.

[0061] In some preferred embodiments of the present invention, the crystallization rate of the P-type microcrystalline silicon film is 40%-70%, and / or the thickness of the P-type microcrystalline silicon film is 15-30nm. Using a P-type microcrystalline silicon film with a suitable crystallization rate and / or thickness, combined with hydrogenated microcrystalline silicon carbide, can be beneficial to forming an energy band bending of the interface, which is more conducive to the separation of carriers.

[0062] In some preferred embodiments of the present invention, the effective boron doping concentration of the first layer of the P-type microcrystalline silicon film is 1e18 cm -3 -2e19cm -3 、The effective boron doping concentration of the last layer is 2e19cm -3 -3e21cm -3 The use of a P-type microcrystalline silicon film with an effective boron doping concentration suitable for the first and last layers, combined with hydrogenated microcrystalline silicon carbide, can form an effective gradient concentration distribution, which is more conducive to the transmission of holes.

[0063] In some preferred embodiments of the present invention, the absolute value of the difference in effective boron doping concentration between two adjacent layers in the layered structure of the P-type microcrystalline silicon film is within 1e19 cm -3 -8e20cm -3 , preferably 1e19cm -3 -5e19cm -3 , which is more conducive to the improvement of the valence band energy level.

[0064] In some preferred embodiments of the present invention, the layered structure of the P-type microcrystalline silicon film is 5-15 layers, preferably 7-15 layers, which is more conducive to forming a suitable gradient energy level distribution and process control.

[0065] In some preferred embodiments of the present invention, the thickness ratio of hydrogenated microcrystalline silicon carbide to the first intrinsic amorphous silicon layer and the tunneling oxide layer is 1:1.5-3:0.5-0.8. Using hydrogenated microcrystalline silicon carbide to the first intrinsic amorphous silicon layer and the tunneling oxide layer with a suitable thickness ratio is more conducive to reducing recombination.

[0066] In some preferred embodiments of the present invention, the thickness of the first intrinsic amorphous silicon layer is 5-12 nm, which is more conducive to forming a good surface passivation effect.

[0067] In some preferred embodiments of the present invention, the second semiconductor layer further comprises a P-type amorphous silicon film disposed on the outer surface of the P-type microcrystalline silicon film, and the P-type amorphous silicon film, hydrogenated microcrystalline silicon carbide, and the P-type microcrystalline silicon film together form a P-type emitter. The P-type amorphous silicon film of the present invention has relatively few grain boundaries and crystal defects, and has a high density, which is beneficial to improving the corrosion resistance of the overall thin film of the P-type emitter, thereby reducing the impact of the overall thin film of the P-type emitter in the subsequent cleaning process, and is also beneficial to preventing the diffusion of In in the metal oxide transparent conductive film layer such as ITO, reducing recombination, and further improving the conversion efficiency and stability of the battery.

[0068] Further preferably, the thickness of the P-type amorphous silicon film is 2-5 nm, and / or the effective boron doping concentration of the P-type amorphous silicon film is 1e18 cm -3 -1e20cm -3 .

[0069] In some preferred embodiments of the present invention, the combined passivation back contact cell with a specific P-type emitter also includes a third semiconductor layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, and the third semiconductor layer includes a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer sequentially arranged, which is more conducive to improving the front passivation effect.

[0070] Further preferably, the thickness of the second intrinsic amorphous silicon layer is 4-8 nm, and the thickness of the microcrystalline silicon oxide layer is 6-20 nm.

[0071] In some preferred embodiments of the present invention, the thickness of the tunnel oxide layer is 1-2 nm, the thickness of the N-type doped polysilicon layer is 100-200 nm, and the effective phosphorus doping concentration is 5e19 cm -3 -5e20cm -3 .

[0072] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outward to cover part of the back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, and a second semiconductor opening area is formed between adjacent first semiconductor layers. The second semiconductor opening area is arranged at intervals from the first semiconductor opening area, and the area between them is an overlapping area.

[0073] Further preferably, in the overlapping region, a mask layer is disposed between the first semiconductor layer and the second semiconductor layer or no mask layer is disposed. The type and thickness of the mask layer can refer to the range in the prior art, for example, the thickness of the mask layer can be 60-80 nm.

[0074] In some preferred embodiments of the present invention, the combined passivation back contact cell with a specific P-type emitter also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an insulating groove is opened on the portion of the conductive film layer located in the overlapping area; the metal electrode is arranged on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area.

[0075] Preferably, the second semiconductor opening region and the corresponding area of ​​the front surface are textured surfaces, and the back surface area outside the second semiconductor opening region is a polished surface.

[0076] In a second aspect, the present invention provides a method for manufacturing a combined passivation back contact cell having a specific P-type emitter, comprising the following steps:

[0077] S1, provide silicon wafers;

[0078] S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling oxide layer and an N-type doped polysilicon layer;

[0079] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0080] S4, performing texturing cleaning to simultaneously form a texturing surface on the front side of the silicon wafer and the second semiconductor opening region, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer through cleaning according to needs;

[0081] S5, depositing a first intrinsic amorphous silicon layer of a second semiconductor layer on the back surface obtained in S4;

[0082] S6, forming a third semiconductor layer on the front side of the silicon wafer obtained in S5;

[0083] S7, sequentially depositing hydrogenated microcrystalline silicon carbide and P-type microcrystalline silicon film as the second semiconductor layer on the back surface obtained in S6.

[0084] The deposition conditions of hydrogenated microcrystalline silicon carbide include: setting the PECVD film forming temperature to 100-200°C, introducing silane, hydrogen and methane, controlling the volume flow ratio of hydrogen to silane to be 190-500:1, the volume flow ratio of methane to silane to be 1:5-50, preferably 1:9-50, and the power density to be 80-200 mW / cm 2 , the deposition rate is 0.2-0.8A / s; the crystallization rate of hydrogenated microcrystalline silicon carbide is controlled to be 40%-80%, and the hydrogen content in hydrogenated microcrystalline silicon carbide is 10%-30% in terms of atomic percentage. In the present invention, the volume flow ratio of hydrogen and silane and the volume flow ratio of methane and silane are adopted to facilitate the crystallization of the film; and the appropriate low power density and the appropriate low deposition rate are also combined to reduce the impact on the intrinsic amorphous silicon layer.

[0085] In some preferred embodiments of the present invention, the deposition conditions of the hydrogenated microcrystalline silicon carbide further include: a silane flow rate of 40-200 sccm, and a reaction gas pressure of 100-1000 Pa.

[0086] The deposition conditions of the P-type microcrystalline silicon film of the present invention include: introducing silane, diborane and hydrogen, the volume flow ratio of diborane to silane gradually increases according to the corresponding required layered structure, the number of layers of the layered structure is greater than 3, and the deposition rate is 1-3A / s. The present invention uses a suitable low deposition rate to deposit hydrogenated microcrystalline silicon carbide, which can have a small impact on the first intrinsic amorphous silicon layer thereunder, so that the battery can maintain a good passivation effect, and is conducive to reducing the difficulty of preparing the P-type microcrystalline silicon film; with a suitable high deposition rate to deposit the layered structure of the P-type microcrystalline silicon film, it is conducive to shortening the production cycle and improving production capacity.

[0087] The crystallization rate ratio of hydrogenated microcrystalline silicon carbide to P-type microcrystalline silicon film is controlled to be 1:0.5-1.2, and the thickness ratio of hydrogenated microcrystalline silicon carbide to P-type microcrystalline silicon film, first intrinsic amorphous silicon layer, and N-type doped polycrystalline silicon layer is controlled to be 1:4-10:1.5-3:20-100.

[0088] In some preferred embodiments of the present invention, in the first layer of the deposited P-type microcrystalline silicon film layered structure, the volume flow rate of diborane is 0.2%-1.0% of the volume flow rate of silane, and in the last layer of the deposited P-type microcrystalline silicon film, the volume flow rate of diborane is 2.0%-5.0% of the volume flow rate of silane; this is conducive to obtaining a P-type microcrystalline silicon film layered structure with a suitable change in boron doping concentration.

[0089] In some preferred embodiments of the present invention, the deposition conditions of the P-type microcrystalline silicon film also include: a preset PECVD film forming temperature of 140-200°C, a reaction gas pressure of 100-1000 Pa, a volume flow ratio of hydrogen to silane of 100-500:1, a power density of 300-500 mW / cm 2 .

[0090] Further preferably, the deposition conditions of the P-type microcrystalline silicon film also include: a flow rate of silane is 100-1000 sccm.

[0091] In some preferred embodiments of the present invention, the method for manufacturing a combined passivated back contact cell with a specific P-type emitter further comprises: depositing a layer of P-type amorphous silicon film on the outer surface of the P-type microcrystalline silicon film in S7.

[0092] Preferably, the deposition rate of the P-type amorphous silicon film is 0.5-1.5 A / s, for example, 0.5 A / s, 0.8 A / s, 1.0 A / s, 1.2 A / s, 1.5 A / s, etc. The P-type amorphous silicon film has relatively few grain boundaries and crystal defects. By adopting a low deposition rate method, it is beneficial to reduce holes, thereby improving the compactness of amorphous silicon, and is beneficial to improving the corrosion resistance of the overall P-type emitter film, thereby reducing the impact of the overall P-type emitter film in the subsequent cleaning process, and is also beneficial to preventing the diffusion of In in the metal oxide transparent conductive film layer such as ITO, reducing recombination, and further improving the battery conversion efficiency and stability.

[0093] Further preferably, the deposition conditions of the P-type amorphous silicon film include: the preset PECVD film forming temperature is 140-200°C, silane, diborane and hydrogen are introduced, the reaction gas pressure is 40-100 Pa, the volume flow ratio of diborane to silane is 5%-10%, and the power density is 10-50 mW / cm 2 .

[0094] Further preferably, the deposition conditions of the P-type amorphous silicon film also include: a silane flow rate of 100-1000 sccm, a hydrogen flow rate of 1000-20000 sccm, preferably 2000-20000 sccm.

[0095] More preferably, the thickness of the P-type amorphous silicon film is 2-5 nm.

[0096] The deposition time of each film layer in the present invention is sufficient as long as the corresponding film layer with the required thickness can be obtained.

[0097] The method for forming the first semiconductor layer and the mask layer of the present invention, as well as the first intrinsic amorphous silicon layer, the third semiconductor layer, and the anti-reflection layer can refer to the existing technology, as long as the corresponding film layer with the target thickness and doping concentration is obtained.

[0098] In some preferred embodiments of the present invention, the method for manufacturing the combined passivation back contact cell with a specific P-type emitter further comprises:

[0099] S8, depositing an anti-reflection layer on the outer surface of the third semiconductor layer on the front side obtained in S7;

[0100] S9, performing a second etching opening on a portion of the second semiconductor layer on the back side obtained in S8 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then performing cleaning;

[0101] S10, depositing a transparent conductive film layer on the back surface obtained in S9;

[0102] S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove;

[0103] S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0104] In a third aspect, the present invention provides a combined passivated back contact cell with a specific P-type emitter, which is manufactured by the method for manufacturing a combined passivated back contact cell with a specific P-type emitter described in the second aspect.

[0105] In a fourth aspect, the present invention provides a battery assembly, which includes the combined passivated back contact battery with a specific P-type emitter described in the first aspect, or includes the combined passivated back contact battery with a specific P-type emitter described in the third aspect.

[0106] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0107] Example 1

[0108] A combined passivated back contact cell, such as Figure 1 As shown, it is prepared by the following method:

[0109] S1, providing a polished and cleaned N-type silicon wafer 101; the N-type silicon wafer 101 is polished and cleaned to remove the damaged layer on the surface of the silicon wafer and keep it clean; the N-type silicon wafer is a single crystal silicon wafer.

[0110] S2, forming a first semiconductor layer and a mask layer on the back of the silicon wafer; the first semiconductor layer comprises a tunneling silicon oxide layer 201 and an N-type doped polysilicon layer 202; the tunneling silicon oxide layer 201 is formed by a dry process and has a thickness of 1.5 nm; the N-type doped polysilicon layer 202 is formed by LPCVD deposition of an intrinsic polysilicon layer followed by diffusion and has a thickness of 150 nm and an effective doping concentration of 2e20 cm -3 ; The mask layer is silicon nitride, formed by PECVD deposition, with a thickness of 80nm;

[0111] S3, opening the back side of the silicon wafer obtained in S2 by laser etching to remove the mask layer, the N-type doped polysilicon layer 202 and the tunneling silicon oxide layer 201 in the second semiconductor opening region;

[0112] S4, performing texturing and cleaning on the silicon wafer obtained in S3, removing the residual mask layer, the N-type doped polysilicon layer 202 and the tunneling silicon oxide layer 201 in the second semiconductor opening region; and forming a texturing surface on the front side of the silicon wafer and the surface of the second semiconductor opening region;

[0113] S5, depositing a first intrinsic amorphous silicon layer 401 of the second semiconductor layer on the back side of the silicon wafer obtained in S4; the first intrinsic amorphous silicon layer 401 is formed by plate-type PECVD deposition and has a thickness of 6 nm;

[0114] S6, forming a third semiconductor layer on the front side of the silicon wafer obtained in S5; the third semiconductor layer is formed by depositing a second intrinsic amorphous silicon layer 501 with a thickness of 5 nm and a microcrystalline silicon oxide layer 502 with a thickness of 10 nm by plate-type PECVD;

[0115] S7, on the back of the silicon wafer obtained in S6, hydrogenated microcrystalline silicon carbide 601, P-type microcrystalline silicon film 602, and P-type amorphous silicon film 603 of the second semiconductor layer are sequentially deposited. The thickness of hydrogenated microcrystalline silicon carbide 601 is 2nm, the crystallization rate is 60%, and the carbon doping concentration is 5e20cm -3 , the hydrogen content in terms of atomic percentage is 20%, the film thickness of the P-type microcrystalline silicon film 602 is 20 nm, and the crystallization rate is 50%;

[0116] The specific method for depositing hydrogenated microcrystalline silicon carbide 601 is as follows: first, the PECVD film forming temperature is preset to 100°C, and then a mixed gas of silane, hydrogen and methane is introduced, the reaction gas pressure is 600Pa, the flow rate of silane is 60sccm, the flow rate ratio of hydrogen to silane is 400:1, the flow rate ratio of methane to silane is 10:100, and the power density is 100mW / cm 2 , the deposition rate is 0.5A / s, and the deposition is carried out to the target thickness. Hydrogenated microcrystalline silicon carbide 601 adopts an undoped, low deposition rate method, which can form a film with a high crystallization rate, providing a starting point for the subsequent crystal growth of microcrystalline silicon, which is conducive to the orderly growth of crystals. The introduction of carbon elements can adjust the lattice structure and grain orientation, which is conducive to optimizing the crystal quality and stability of the film and improving the film quality.

[0117] The specific method for depositing the P-type microcrystalline silicon film 602 is as follows: firstly, the PECVD film forming temperature is preset to 160°C, and then a mixed gas of silane, diborane and hydrogen is introduced, the reaction gas pressure is 600Pa, the flow rate of silane is 200sccm, the flow rate ratio of hydrogen and silane is 200:1, and the flow rate ratio of diborane to silane is gradually and evenly increased according to the stratification, and the number of stratification layers is 10; the flow rate ratio of diborane to silane in the first layer is 0.3%, and the flow rate ratio of diborane to silane in the last layer is 3%; the power density is 400mW / cm 2 , deposition rate 1.0A / s; the effective boron doping concentration of the first layer of the P-type microcrystalline silicon film 602 is 5e18cm -3 、The effective boron doping concentration of the last layer is 3e20cm -3 The absolute value of the difference in effective boron doping concentration between two adjacent layers in the layered structure of P-type microcrystalline silicon film is 5e19cm -3 .

[0118] Then, a layer of P-type amorphous silicon film 603 is deposited on the P-type microcrystalline silicon film 602. The specific method is as follows: the PECVD film forming temperature is preset to 180°C, and then a mixed gas of silane, diborane and hydrogen is introduced. The reaction gas pressure is 100Pa, the flow rate of silane is 1000sccm, the flow rate of hydrogen is 1000sccm, the flow rate ratio of diborane to silane is 6%, and the power density is 15mW / cm 2 The deposition rate is 0.6A / s. The thickness of the P-type amorphous silicon film 603 is 3nm and the effective boron doping concentration is 8e19cm -3 .

[0119] S8, depositing an anti-reflection layer 701 on the front side of the silicon wafer obtained in S7;

[0120] S9, opening the back side of the silicon wafer obtained in S8 by laser etching to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then cleaning;

[0121] S10, depositing a transparent conductive film layer 801 on the back side of the silicon wafer obtained in S9;

[0122] S11, etching an opening on the surface of the transparent conductive film layer 801 in the overlapping area between the second semiconductor opening area and the first semiconductor opening area on the back side of the silicon wafer obtained in S10 to form an insulating groove between the second semiconductor opening area and the first semiconductor opening area to isolate the first semiconductor and the second semiconductor to avoid short circuit;

[0123] S12, forming metal electrodes 901 on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S11.

[0124] Example 2

[0125] The method of Example 1 is followed, except that the crystallization rate of hydrogenated microcrystalline silicon carbide is 50%, the hydrogen content in atomic percentage is 23%, and the ratio of the crystallization rate of hydrogenated microcrystalline silicon carbide to that of P-type microcrystalline silicon film is calculated to be 1:1. The deposition process parameters that need to be adjusted accordingly to meet this condition are: adjusting the hydrogen flow rate so that the flow ratio of hydrogen to silane is 300:1.

[0126] Example 3

[0127] The method of Example 1 is followed, except that the carbon doping concentration of hydrogenated microcrystalline silicon carbide is 3e20cm -3 , the hydrogen content in atomic percentage is 25%. The deposition process parameters that need to be adjusted to meet this condition are: adjusting the methane flow rate so that the flow ratio of methane to silane is 20:100.

[0128] Example 4

[0129] The method of Example 1 is referred to, except that the deposition time of hydrogenated microcrystalline silicon carbide is increased until the thickness of hydrogenated microcrystalline silicon carbide is 3 nm. The thickness ratio of hydrogenated microcrystalline silicon carbide to the P-type microcrystalline silicon film, the first intrinsic amorphous silicon layer, and the N-type doped polycrystalline silicon layer is calculated to be 1:6.7:2:50.

[0130] Example 5

[0131] The method of Example 1 is followed, except that the layered structure of the P-type microcrystalline silicon film is 6 layers, the effective boron doping concentration of the first layer and the last layer remains unchanged, but the absolute value of the difference in effective boron doping concentration between two adjacent layers in the layered structure is 6e19cm -3 ,The process parameters that need to be changed to achieve this goal are: the diborane flow rate of each layer is uniformly increased according to the diborane to silane flow ratio and the target layer structure, and the deposition time of each layer is 25 s.

[0132] Example 6

[0133] The method of Example 1 is referred to, except that the P-type amorphous silicon film is not provided.

[0134] Comparative Example 1

[0135] The method of Example 1 is followed, except that the structure of the second semiconductor layer is different. Specifically, a conventional P-type amorphous silicon layer (with a thickness of 8 nm and an effective doping concentration of 3e19 cm-1) is directly deposited on the outer surface of the first intrinsic amorphous silicon layer. -3 ), that is, hydrogenated microcrystalline silicon carbide and P-type microcrystalline silicon film are not set.

[0136] Comparative Example 2

[0137] The method of Example 1 is referred to, except that the structure of the second semiconductor layer is different, and specifically, a P-type microcrystalline silicon film (which is the same as Example 1) is directly deposited on the outer surface of the first intrinsic amorphous silicon layer, that is, hydrogenated microcrystalline silicon carbide and P-type amorphous silicon film are not set.

[0138] Comparative Example 3

[0139] The method of Example 1 is followed, except that the effective boron doping concentration of the P-type microcrystalline silicon film is not layered, but is uniformly 5e19cm -3 The deposition process parameters that need to be adjusted to meet this condition are: adjusting the diborane flow rate so that the diborane flow rate is always 1% of the silane flow rate.

[0140] Comparative Example 4

[0141] The method of Example 1 is referred to, except that the deposition rate of hydrogenated microcrystalline silicon carbide is 1.0 A / s, the crystallization rate of hydrogenated microcrystalline silicon carbide is 30%, and the hydrogen content in atomic percentage is 17%. The deposition process parameters that need to be adjusted accordingly to meet this condition are: adjusting the hydrogen flow rate so that the flow ratio of hydrogen to silane is 180:1.

[0142] Comparative Example 5

[0143] The method of Example 1 is followed, except that the first semiconductor layer is replaced by a conventional intrinsic amorphous silicon layer (5 nm thick) and an N-type doped amorphous silicon layer (7 nm thick, with an effective doping concentration of 2e19 cm -3 ) of the laminated structure.

[0144] Test Case

[0145] The combined passivated back contact cells obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The performance indicators of each embodiment and comparative example were converted using comparative example 1 as a reference benchmark, and the data of comparative example 1 was normalized to 1.000. Other examples were converted based on comparative example 1, such as the short-circuit current of embodiment 1 / short-circuit current of comparative example 1 was 1.002. In the conversion, the unit of short-circuit current is A, the unit of open-circuit voltage is V, the unit of fill factor is %, the unit of battery conversion efficiency is %, and the unit of conductivity is S / cm.

[0146] Table 1

[0147]

[0148] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can be used to improve the open circuit voltage of the battery, to improve the carrier collection efficiency, to improve the fill factor of the battery, and thus to improve the battery conversion efficiency.

[0149] Furthermore, according to Example 1 and Examples 2-6, it can be seen that the use of the preferred battery structure of the present invention is more conducive to improving the open circuit voltage of the battery, improving the carrier collection efficiency, improving the fill factor of the battery, and further improving the battery conversion efficiency.

[0150] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A combined passivated back contact cell with a specific P-type emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon wafer, the first semiconductor layer comprising a tunneling oxide layer and an N-type doped polysilicon layer, the second semiconductor layer comprising a first intrinsic amorphous silicon layer, characterized in that: The second semiconductor layer also includes hydrogenated microcrystalline silicon carbide and a P-type microcrystalline silicon film which are sequentially arranged on the outer surface of the first intrinsic amorphous silicon layer to form a P-type emitter, and in the direction away from the back side of the silicon wafer, the effective boron doping concentration of the P-type microcrystalline silicon film gradually increases according to the layered structure, and the layered structure is greater than 3 layers; wherein, the crystallization rate of hydrogenated microcrystalline silicon carbide is 40%-80%, the hydrogen content in hydrogenated microcrystalline silicon carbide in terms of atomic percentage is 10%-30%, the ratio of the crystallization rate of hydrogenated microcrystalline silicon carbide to that of the P-type microcrystalline silicon film is 1:0.5-1.2, and the ratio of the thickness of hydrogenated microcrystalline silicon carbide to that of the P-type microcrystalline silicon film, the first intrinsic amorphous silicon layer, and the N-type doped polycrystalline silicon layer is 1:4-10:1.5-3:20-100.

2. The combined passivated back contact cell with a specific P-type emitter according to claim 1, characterized in that: The thickness of the hydrogenated microcrystalline silicon carbide is 2-4 nm, and / or the carbon doping concentration of the hydrogenated microcrystalline silicon carbide is 1e19 cm -3 -1e21cm -3 .

3. The combined passivated back contact cell with a specific P-type emitter according to claim 1, characterized in that: The crystallization rate of the P-type microcrystalline silicon film is 40%-70%, and / or the thickness of the P-type microcrystalline silicon film is 15-30 nm.

4. The combined passivated back contact cell with a specific P-type emitter according to claim 1 or 3, characterized in that: The effective boron doping concentration of the first layer of P-type microcrystalline silicon film is 1e18cm -3 -2e19cm -3 、The effective boron doping concentration of the last layer is 2e19cm -3 -3e21cm -3 ; and / or, The absolute value of the difference in effective boron doping concentration between two adjacent layers in the layered structure of P-type microcrystalline silicon film is 1e19cm -3 -8e20cm -3 .

5. The combined passivated back contact cell with a specific P-type emitter according to claim 1, characterized in that: The layered structure of the P-type microcrystalline silicon film is 5-15 layers, and / or the thickness ratio of the hydrogenated microcrystalline silicon carbide to the first intrinsic amorphous silicon layer and the tunneling oxide layer is 1:1.5-3:0.5-0.

8.

6. The combined passivated back contact cell with a specific P-type emitter according to claim 1, characterized in that: The second semiconductor layer further includes a P-type amorphous silicon film disposed on the outer surface of the P-type microcrystalline silicon film, the P-type amorphous silicon film, hydrogenated microcrystalline silicon carbide, and the P-type microcrystalline silicon film together form a P-type emitter, the P-type amorphous silicon film has a thickness of 2-5 nm, and an effective boron doping concentration of 1e18 cm -3 -1e20cm -3 .

7. The combined passivated back contact cell with a specific P-type emitter according to claim 1, characterized in that: The combined passivation back contact cell with a specific P-type emitter further has at least one of the following structures: Structure 1: The combined passivation back contact cell with a specific P-type emitter further comprises a third semiconductor layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, wherein the third semiconductor layer comprises a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer sequentially arranged; Structure 2: The thickness of the tunnel oxide layer is 1-2nm, the thickness of the N-type doped polysilicon layer is 100-200nm, and the effective phosphorus doping concentration is 5e19cm -3 -5e20cm -3 ; Structure 3: The thickness of the first intrinsic amorphous silicon layer is 5-12 nm; Structure 4: The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, and a second semiconductor opening area is formed between the adjacent first semiconductor layers. The second semiconductor opening area is arranged at intervals from the first semiconductor opening area, and the area between them is an overlapping area. In the overlapping area, a mask layer is set between the first semiconductor layer and the second semiconductor layer, or no mask layer is set; the combined passivated back contact battery with a specific P-type emitter also includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an insulating groove is opened on the portion of the conductive film layer located in the overlapping area; the metal electrode is set on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening area and the first semiconductor opening area.

8. A method for manufacturing a joint passivation back contact cell with a specific P-type emitter, characterized in that: The steps include: S1, provide silicon wafers; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; the first semiconductor layer comprises a tunneling oxide layer and an N-type doped polysilicon layer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, performing texturing cleaning to simultaneously form a texturing surface on the front side of the silicon wafer and the second semiconductor opening region, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer through cleaning according to needs; S5, depositing a first intrinsic amorphous silicon layer of a second semiconductor layer on the back surface obtained in S4; S6, forming a third semiconductor layer on the front side of the silicon wafer obtained in S5; S7, sequentially depositing a hydrogenated microcrystalline silicon carbide film and a P-type microcrystalline silicon film as a second semiconductor layer on the back surface obtained in S6; The deposition conditions of hydrogenated microcrystalline silicon carbide include: setting the PECVD film forming temperature to 100-200°C, introducing silane, hydrogen and methane without introducing boron-containing gas, controlling the volume flow ratio of hydrogen to silane to 190-500:1, the volume flow ratio of methane to silane to 1:5-50, and the power density to 80-200mW / cm 2 , the deposition rate is 0.2-0.8A / s; the crystallization rate of hydrogenated microcrystalline silicon carbide is controlled to be 40%-80%, and the hydrogen content in hydrogenated microcrystalline silicon carbide is 10%-30% in terms of atomic percentage; The deposition conditions of the P-type microcrystalline silicon film include: introducing silane, diborane and hydrogen, the volume flow ratio of diborane to silane gradually increases according to the corresponding required layered structure, the number of layers of the layered structure is greater than 3, and the deposition rate is 1-3A / s; and the ratio of the crystallization rate of the hydrogenated microcrystalline silicon carbide to the P-type microcrystalline silicon film is 1:0.5-1.2, and the ratio of the thickness of the hydrogenated microcrystalline silicon carbide to the P-type microcrystalline silicon film, the first intrinsic amorphous silicon layer, and the N-type doped polycrystalline silicon layer is 1:4-10:1.5-3:20-100.

9. The method for manufacturing a combined passivated back contact cell with a specific P-type emitter according to claim 8, characterized in that: The volume flow rate of diborane in the first layer of the deposited P-type microcrystalline silicon film layered structure is 0.2%-1.0% of the volume flow rate of silane, and the volume flow rate of diborane in the last layer of the deposited P-type microcrystalline silicon film is 2.0%-5.0% of the volume flow rate of silane.

10. The method for manufacturing a combined passivated back contact cell with a specific P-type emitter according to claim 8 or 9, characterized in that: The deposition conditions of the hydrogenated microcrystalline silicon carbide also include: a silane flow rate of 40-200 sccm and a reaction gas pressure of 100-1000 Pa; and / or, The deposition conditions of the P-type microcrystalline silicon film also include: a preset PECVD film forming temperature of 140-200° C., a reaction gas pressure of 100-1000 Pa, a volume flow ratio of hydrogen to silane of 100-500:1, a power density of 300-500 mW / cm 2 .

11. The method for manufacturing a combined passivation back contact cell with a specific P-type emitter according to claim 8, characterized in that: The method for manufacturing the combined passivation back contact cell with a specific P-type emitter further includes: In S7, a layer of P-type amorphous silicon film is deposited on the outer surface of the P-type microcrystalline silicon film. The deposition conditions of the P-type amorphous silicon film include: a preset PECVD film forming temperature of 140-200° C., introduction of silane, diborane, and hydrogen, a reaction gas pressure of 40-100 Pa, a volume flow ratio of diborane to silane of 5%-10%, and a power density of 10-50 mW / cm 2 , the deposition rate of the P-type amorphous silicon film is 0.5-1.5A / s; the film thickness of the P-type amorphous silicon film is 2-5nm; S8, depositing an anti-reflection layer on the outer surface of the third semiconductor layer on the front side obtained in S7; S9, performing a second etching opening on a portion of the second semiconductor layer on the back side obtained in S8 to form a first semiconductor opening region spaced apart from the second semiconductor opening region, and then performing cleaning; S10, depositing a transparent conductive film layer on the back surface obtained in S9; S11, performing a third etching opening on a portion of the conductive film layer between the first semiconductor opening region and the second semiconductor opening region to form an insulating groove; S12, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

12. A combined passivated back contact cell with a specific P-type emitter, characterized in that: The battery is manufactured by the method for manufacturing a combined passivated back contact battery with a specific P-type emitter as claimed in any one of claims 8 to 11.

13. A battery assembly, characterized in that: It comprises the combined passivated back contact cell with a specific P-type emitter as claimed in any one of claims 1 to 7, or comprises the combined passivated back contact cell with a specific P-type emitter as claimed in claim 12.

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