A SAR ADC segmented capacitor array layout structure

Abstract

The application provides a SAR ADC segmented capacitor array layout structure, and belongs to the technical field of analog-digital converters. The SAR ADC segmented capacitor array layout structure comprises a sub-segment layout area, a plurality of array-arranged unit capacitors and bridge capacitors, and a redundant capacitor between the unit capacitors and the bridge capacitors in the sub-segment layout area. The unit capacitor comprises a substrate, a plurality of first metal wire layers and a plurality of second metal wire layers formed on the substrate, the plurality of first metal wire layers form upper plates of the unit capacitor, and the plurality of second metal wire layers form lower plates of the unit capacitor. The unit capacitor further comprises at least one third metal wire layer, the third metal wire layer is used as an outgoing line and is connected with the upper plate wire, in the sub-segment layout area, every two unit capacitors share one upper plate wire, and the upper plate wire is located between the two unit capacitors. Through the SAR ADC segmented capacitor array layout structure, the parasitic capacitance of the upper plate of the sub-segment capacitor array can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital converters, and in particular to a SAR ADC segmented capacitor array layout structure. Background Art

[0002] The CDAC (Capacitive Digital to Analog Converter) is a key component of the SARADC (Successive Approximation Register Analog to Digital Converter). As the number of bits in a SAR ADC increases, the CDAC's capacitance increases exponentially. A common method for reducing CDAC capacitance is to use a segmented CDAC structure. However, when designing a segmented CDAC layout, parasitic capacitance within the capacitor array can easily degrade the weight of each unit capacitor, especially the parasitic capacitance of the top plate of the sub-segment capacitor array. Summary of the Invention

[0003] The present application provides a SAR ADC segmented capacitor array layout structure, aiming to reduce the parasitic capacitance of the upper plate of the sub-segment capacitor array.

[0004] The present application embodiment provides a SAR ADC segmented capacitor array layout structure, including:

[0005] The secondary layout area includes a plurality of unit capacitors and bridge capacitors arranged in an array, and the unit capacitors of the secondary layout area and the bridge capacitors are separated by a redundant capacitor;

[0006] The unit capacitance includes:

[0007] A substrate and a multi-layer first metal wire layer and a multi-layer second metal wire layer formed on the substrate, wherein the multi-layer first metal wire layer constitutes an upper plate of the unit capacitor, and the multi-layer second metal wire layer constitutes a lower plate of the unit capacitor;

[0008] The unit capacitor further includes at least one third metal wire layer, wherein the at least one third metal wire layer is connected to the multiple first metal wire layers, and the third metal wire layer is connected to the upper plate wiring as a lead wire;

[0009] In the secondary layout area, every two unit capacitors share one upper plate trace, and the upper plate trace is located between the two unit capacitors.

[0010] Optionally, an orthographic projection of the third metal wire layer on the substrate partially overlaps with an orthographic projection of the first metal wire layer on the substrate.

[0011] Optionally, the upper plate includes a connecting portion and a plurality of interdigital portions connected to the connecting portion;

[0012] An orthographic projection of the third metal wire layer on the substrate partially overlaps with an orthographic projection of the connecting portion on the substrate.

[0013] Optionally, in the unit capacitor, the lower plate surrounds the upper plate.

[0014] Optionally, the third metal wire layer includes multiple sub-metal layers, and the sub-metal layer farthest from the substrate among the multiple sub-metal layers serves as the lead wire and is connected to the upper plate wiring.

[0015] Optionally, the layout structure further includes:

[0016] The main section layout area includes multiple unit capacitors arranged in an array;

[0017] In the main segment layout area, every two unit capacitors share an upper plate wiring, and the upper plate wiring is located between the two unit capacitors.

[0018] Optionally, the layout structure further includes:

[0019] A plurality of lower plate traces are provided, the lower plate traces being located on a side of the unit capacitor away from the upper plate trace, and the plurality of lower plate traces are connected to the lower plate switch of the layout structure.

[0020] Optionally, each of the multiple first metal wire layers is connected via an interlayer via;

[0021] The second metal wire layers in the plurality of second metal wire layers are connected to each other through interlayer vias, and the second metal wire layers are connected to the substrate through the interlayer vias.

[0022] Optionally, the material of the substrate includes silicon.

[0023] Optionally, the upper plate includes three layers of the first metal wire layers, and the lower plate includes three layers of the second metal wire layers.

[0024] Beneficial effects:

[0025] The present application provides a SAR ADC segmented capacitor array layout structure, which separates the unit capacitor from the bridge capacitor by setting a redundant capacitor between the unit capacitor and the bridge capacitor in the sub-segment layout area. At the same time, the unit capacitor includes a substrate and a multi-layer first metal wire layer, a multi-layer second metal wire layer and at least one side of a third metal wire layer formed on the substrate. The multi-layer first metal wire layer constitutes the upper plate of the unit capacitor, the multi-layer second metal layer constitutes the lower plate of the unit capacitor, and the third metal wire layer is connected to the upper plate routing as a lead line. Therefore, in the sub-segment layout area, every two unit capacitors can share an upper plate routing, and the upper plate routing is located between the two unit capacitors. This can reduce the parasitic capacitance to the AC ground in the sub-segment layout area, thereby avoiding the weight of the unit capacitor in the sub-segment layout area from being destroyed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 Schematic diagram of the planar structure of a unit capacitor in the related art;

[0028] Figure 2 yes Figure 1 Schematic diagram of the structure of the A-A' section;

[0029] Figure 3 It is a structural diagram of the secondary layout area in the related art;

[0030] Figure 4 1 is a structural diagram of a sub-segment layout area of ​​a SAR ADC segmented capacitor array layout structure proposed in one embodiment of the present application;

[0031] Figure 5 1 is a schematic diagram of a planar structure of a unit capacitor in a SAR ADC segmented capacitor array layout structure proposed in one embodiment of the present application;

[0032] Figure 6 yes Figure 5 Schematic diagram of the structure of the B-B' section;

[0033] Figure 7 This is a structural schematic diagram of a main segment layout area and a secondary segment layout area in a SAR ADC segmented capacitor array layout structure proposed in one embodiment of the present application.

[0034] Explanation of the reference numerals: 10, substrate; 20, first metal wire layer; 30, second metal wire layer; 31, cover layer; 40, third metal wire layer; 41, sub-metal layer; 50, upper plate wiring; 60, lower plate wiring. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] Reference Figure 1 and Figure 2 As shown, in the related art, the unit capacitor includes a multi-layer first metal wire layer 20 constituting the upper electrode SJ and a multi-layer second metal wire layer 30 constituting the lower electrode XJ, and the multi-layer second metal wire layer 30 includes a covering layer 31 ( Figure 1 (not shown in the figure), the covering layer 31 will cover the entire unit capacitor, so that the lower plate XJ can completely surround the upper plate SJ, thereby avoiding the weight mismatch caused by parasitic capacitance, which also causes the upper plate trace 50 connected to the upper plate SJ of the unit capacitor in the layout structure to pass through the unit capacitor.

[0037] Reference Figure 3 As shown, there is a bridge capacitor B in the sub-segment layout area CD of the SAR ADC segmented capacitor array layout structure. A redundant capacitor D needs to be inserted between the bridge capacitor B and the unit capacitor to avoid parasitic capacitance between the lower plate of the unit capacitor and the lower plate of the bridge capacitor B. However, due to the structure of the unit capacitor as described above, after the redundant capacitor D is inserted, the upper plate routing 50 of the sub-segment layout area CD will completely pass through the redundant capacitor D (the structure of the redundant capacitor D and the structure of the unit capacitor). Since the redundant capacitor D needs to be connected to a fixed level, the upper plate of the sub-segment layout area CD will have an obvious parasitic capacitance to the AC ground. This parasitic capacitance will simultaneously affect the weights of all unit capacitors in the sub-segment layout area CD.

[0038] In view of this, an embodiment of the present application proposes a SAR ADC segmented capacitor array layout structure, which separates the unit capacitor from the bridge capacitor by setting a redundant capacitor between the unit capacitor and the bridge capacitor in the sub-segment layout area. At the same time, the unit capacitor includes a substrate and a multi-layer first metal wire layer, a multi-layer second metal wire layer and at least one side of a third metal wire layer formed on the substrate. The multi-layer first metal wire layer constitutes the upper plate of the unit capacitor, and the multi-layer second metal layer constitutes the lower plate of the unit capacitor. The third metal wire layer is connected to the upper plate routing as a lead line. Therefore, in the sub-segment layout area, every two unit capacitors can share an upper plate routing, and the upper plate routing is located between the two unit capacitors. This can reduce the parasitic capacitance to the AC ground in the sub-segment layout area, thereby avoiding the destruction of the weight of the unit capacitor in the sub-segment layout area.

[0039] Reference Figure 4 As shown, a SAR ADC segmented capacitor array layout structure disclosed in an embodiment of the present application includes a sub-segment layout area CD.

[0040] Specifically, the sub-segment layout area CD includes multiple unit capacitors arranged in an array and multiple redundant capacitors surrounding the multiple unit capacitors. At the same time, there is also a bridging capacitor in the sub-segment layout area CD, and a redundant capacitor is arranged between the bridging capacitor and the unit capacitor. The redundant capacitor is used to separate the bridging capacitor from the unit capacitor, thereby avoiding the generation of parasitic capacitance between the lower plate of the unit capacitor and the lower plate of the bridging capacitor.

[0041] The sub-segment layout area of ​​the embodiment of the present application is a 3-bit ADC structure, in which the capacitors numbered 1-3 are weight capacitors, the capacitor numbered B is a bridge capacitor, and the capacitor numbered D is a redundant capacitor. In addition, the first-bit (numbered 1) weight capacitor includes 2 0 Unit capacitors, the second weight capacitor (numbered 2) includes 2 1 Unit capacitors, the third weight capacitor (numbered 3) includes 2 2 A unit capacitor.

[0042] Reference Figure 5 and Figure 6As shown, in an embodiment of the present application, a unit capacitor includes a substrate 10 and a multilayer first metal wire layer 20 and a multilayer second metal wire layer 30 formed on the substrate 10. The multilayer first metal wire layer 20 constitutes an upper plate SJ of the unit capacitor, and the multilayer second metal wire layer 30 constitutes a lower plate XJ of the unit capacitor. In the multilayer first metal wire layer 20, two adjacent first metal wire layers 20 are insulated by an insulating layer (not shown in the figure), so each first metal wire layer 20 is connected through an interlayer via; in the multilayer second metal wire layer 30, two adjacent second metal wire layers 30 are also insulated by an insulating layer (not shown in the figure), so each second metal wire layer 30 is connected through an interlayer via, and the second metal wire layer 30 is connected to the substrate 10 through an interlayer via.

[0043] In the embodiment of the present application, the first metal wire layer 20 and the second metal wire layer 30 are each provided with three layers. It is understood that the first metal wire layer 20 and the second metal wire layer 30 can be provided in the same layer, that is, the first metal wire layer 20 and the second metal wire layer 30 can be formed in the same step using the same material. Alternatively, the first metal wire layer 20 and the second metal wire layer 30 can be formed sequentially on the substrate 10. The material of the substrate 10 can be silicon, and the material of the first metal wire layer 20 and the second metal wire layer 30 can be aluminum, copper, etc. The interlayer through holes can include metal vias, etc.

[0044] Figure 5 This is a schematic diagram of the plane structure of a unit capacitor, refer to Figure 5 As shown, in this unit capacitor, the upper plate SJ includes a connecting portion LJ1 and a plurality of finger portions CZ1 connected to the connecting portion LJ1, and the lower plate XJ includes a connecting portion LJ2, a peripheral portion WK and a plurality of finger portions CZ2, wherein the plurality of finger portions CZ1 of the upper plate SJ and the plurality of finger portions CZ2 of the lower plate XJ intersect with each other, and the peripheral portion WK of the lower plate XJ surrounds the entire upper plate SJ, thereby avoiding weight mismatch caused by parasitic capacitance.

[0045] However, referring to Figure 6 As shown, in the embodiment of the present application, no covering layer is provided on the top of the upper electrode plate, that is, unlike in the related art, the upper electrode plate of the unit capacitor of the embodiment of the present application is not covered by the lower electrode plate on its top. At the same time, in the embodiment of the present application, the unit capacitor also includes at least one layer of third metal wire layer 40, and the third metal wire layer 40 is connected to the second metal wire layer 30 through an interlayer via, and the orthographic projection of the third metal wire layer 40 on the substrate 10 overlaps with the orthographic projection of the connection part LJ1 of the upper electrode plate SJ on the substrate 10. The third metal wire layer 40 can be connected to the upper electrode plate wiring 50 in the layout structure as a lead-out line YC, thereby realizing the connection between the upper electrode plate SJ of each unit capacitor and the upper electrode plate wiring 50.

[0046] It should be noted that in the layout structure, the structure of the bridging capacitor and the redundant capacitor is the same as that of the unit capacitor, except that the lower plate of the bridging capacitor will be connected to the upper plate trace of the main segment layout area to connect to the upper plate switch, and the upper plate of the bridging capacitor will be connected to the upper plate trace of the secondary segment layout area to not connect to the upper plate switch, and the redundant capacitor does not need to be connected to the upper plate trace and the lower plate trace.

[0047] In the embodiment of the present application, the upper plate SJ of the unit capacitor can be connected to the upper plate trace 50 via the third metal wire layer 40 as a lead line YC. Therefore, in the secondary layout area CD, every two unit capacitors can share a single upper plate trace 50, and the upper plate trace 50 is located between the two unit capacitors. In other words, in the embodiment of the present application, the upper plate trace 50 no longer passes through the unit capacitor, and thus the upper plate trace 50 no longer passes through the redundant capacitor located between the bridge capacitor and the unit capacitor, thereby reducing the generation of AC parasitic capacitance to ground in the secondary layout area CD.

[0048] The present embodiment also simulated the parasitic capacitance generated in the layout structure. In the simulation, each unit capacitance was set to 10fF. According to the parasitic extraction results of the Calibre software, the parasitic capacitance of the upper plate of the sub-segment CDAC in the three-digit sub-segment layout area in the related art to the AC ground is 2.4fF, while the parasitic capacitance of the upper plate of the sub-segment CDAC in the three-digit sub-segment layout area in the present embodiment is 0.9fF. It can be seen that the parasitic capacitance of the sub-segment layout area to the AC ground in the layout structure provided by the present embodiment is significantly reduced.

[0049] In one embodiment, referring to Figure 6 As shown, the third metal line layer 40 includes multiple sub-metal layers 41. The sub-metal layer 41 farthest from the substrate serves as a lead line YC connected to the top plate trace, further reducing parasitic capacitance. Adjacent sub-metal layers are connected via metal vias.

[0050] In one embodiment, referring to Figure 7 As shown, the layout structure of the embodiment of the present application also includes a main segment layout area ZD, which includes multiple unit capacitors arranged in an array and multiple redundant capacitors surrounding the unit capacitors. The main segment layout area ZD is a 9-bit ADC structure, in which capacitors numbered 0-7 are weighted capacitors, and the capacitor structure in the main segment layout area ZD is symmetrically distributed.

[0051] It is understood that in the embodiment of the present application, the structure of the unit capacitor in the main section layout area ZD is the same as the structure of the unit capacitor in the secondary section layout area CD. Therefore, in the main section layout area ZD, every two unit capacitors also share a top plate trace 51, and the top plate trace 51 is located between the two unit capacitors. That is, in the main section layout area ZD, the top plate trace 51 no longer passes through the unit capacitor. At the same time, each top plate trace 51 in the main section layout area ZD is connected to the lower plate of the bridge capacitor in the secondary section layout area CD through a total trace 52, while the top plate trace 50 in the secondary section layout area is connected to the top plate of the bridge capacitor.

[0052] At the same time, the layout structure also includes multiple lower plate traces 60. Each lower plate trace 60 is located on the side of the corresponding unit capacitor away from the upper plate trace 51, and the multiple lower plate traces 60 are connected to the lower plate switch of the layout structure. In other words, in the embodiment of the present application, for each unit capacitor, the upper plate trace 51 is located on one side of the unit capacitor, and the lower plate trace 60 is located on the other side of the unit capacitor.

[0053] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0054] It should also be noted that, in this article, the orientation or position relationship indicated by the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations, nor can they be understood as indicating or implying relative importance. Moreover, the terms "include", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device that includes a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, an element defined by the phrase "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or terminal device that includes the element.

[0055] The technical solutions provided by this application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above embodiments is only intended to help understand this application, and the contents of this specification should not be construed as limiting this application. At the same time, for those skilled in the art, according to this application, there may be various changes in the specific implementation methods and application scopes. It is not necessary and impossible to list all implementation methods here, and obvious changes or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A SAR ADC segmented capacitor array layout structure, characterized in that: include: The secondary layout area includes a plurality of unit capacitors and bridge capacitors arranged in an array, and the unit capacitors of the secondary layout area and the bridge capacitors are separated by a redundant capacitor; The unit capacitance includes: A substrate and a multi-layer first metal wire layer and a multi-layer second metal wire layer formed on the substrate, wherein the multi-layer first metal wire layer constitutes an upper plate of the unit capacitor, and the multi-layer second metal wire layer constitutes a lower plate of the unit capacitor; The unit capacitor further includes at least one third metal wire layer, wherein the at least one third metal wire layer is connected to the multiple first metal wire layers, and the third metal wire layer is connected to the upper plate wiring as a lead wire; In the sub-segment layout area, every two unit capacitors share one upper plate trace, and the upper plate trace is located between the two unit capacitors; The orthographic projection of the third metal wire layer on the substrate partially overlaps with the orthographic projection of the first metal wire layer on the substrate; The upper electrode plate includes a connecting portion and a plurality of interdigital portions connected to the connecting portion; The orthographic projection of the third metal wire layer on the substrate partially overlaps with the orthographic projection of the connecting portion on the substrate; In the unit capacitor, the lower plate surrounds the upper plate.

2. The SAR ADC segmented capacitor array layout structure according to claim 1, wherein: The third metal wire layer includes multiple sub-metal layers, and the sub-metal layer farthest from the substrate among the multiple sub-metal layers serves as the lead wire and is connected to the upper plate wiring.

3. The SAR ADC segmented capacitor array layout structure according to claim 1, wherein: The layout structure also includes: The main section layout area includes multiple unit capacitors arranged in an array; In the main segment layout area, every two unit capacitors share an upper plate wiring, and the upper plate wiring is located between the two unit capacitors.

4. The SAR ADC segmented capacitor array layout structure according to claim 3, wherein: The layout structure also includes: A plurality of lower plate traces are provided, the lower plate traces being located on a side of the unit capacitor away from the upper plate trace, and the plurality of lower plate traces are connected to the lower plate switch of the layout structure.

5. The SAR ADC segmented capacitor array layout structure according to claim 1, wherein: The first metal wire layers in the plurality of first metal wire layers are connected via interlayer vias; The second metal wire layers in the plurality of second metal wire layers are connected to each other through interlayer vias, and the second metal wire layers are connected to the substrate through the interlayer vias.

6. The SAR ADC segmented capacitor array layout structure according to claim 1, wherein: The material of the substrate includes silicon.

7. The SAR ADC segmented capacitor array layout structure according to claim 1, wherein: The upper electrode plate includes three layers of the first metal wire layers, and the lower electrode plate includes three layers of the second metal wire layers.

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