Xilinx-z7 random MAC address acquisition method and device

Abstract

The present invention discloses a Xilinx‑z7 random MAC address acquisition method and device, wherein a PS module performs the following steps: loading a basic PL image file BIT0, and after successfully loading the basic PL image file BIT0, initializing a register group; accessing the register group and configuring a PL module to acquire a device identifier FUSE_DNA in the register group; accessing the register group, determining whether the PL module successfully acquires the device identifier FUSE_DNA, and executing step S4 if the acquisition is successful, and executing step S5 if the acquisition fails; reading the device identifier FUSE_DNA from the register group, and generating a random MAC address according to the read device identifier FUSE_DNA; acquiring a system clock, and generating a random MAC address according to the system clock. FUSE_DNA is used to replace the system clock as a random number seed to generate a MAC address, thereby avoiding MAC address conflicts to the greatest extent.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method for a Xilinx-z7 chip PS to obtain a random MAC address. Background Art

[0002] The MAC address of the device network port is generally fixedly stored in the device's storable memory device. However, in a local area network, the device MAC address does not need to be connected to the public network, so it is only necessary to ensure that the MAC address is legal and does not conflict to meet the usage requirements. In this case, the MAC address is randomly generated by the software.

[0003] For Xilinx-z7 series chips, a random MAC address is generated when the UBOOT program is loaded. The generation of random MAC addresses at this time depends on the system clock. For the same model of Xilinx-z7 hardware boards, the time required from the board power-on to the acquisition of the system clock from the software is the same. Therefore, multiple hardware boards of the same model obtain the same system clock from the software, resulting in the same random number generated by the software for each hardware board of the same model. When multiple boards of the same model randomly generate the same MAC address based on the system clock of the same software, it will cause network conflicts. Summary of the invention

[0004] The purpose of the present invention is to provide a method and device for obtaining a Xilinx-z7 random MAC address. The unique device identifier FUSE_DNA of the Xilinxz7 series chip PL is used. The PS accesses the register group of the PL module through the AXI interface to obtain the device identifier FUSE_DNA, and the device identifier FUSE_DNA is used to replace the system clock as the seed for generating random numbers. Then, the system randomly generates a MAC address, thereby avoiding MAC address conflicts to the greatest extent.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] On the one hand, the present application provides a method for obtaining a random MAC address of Xilinx-z7, wherein the PS module performs the following steps:

[0007] S1, load the basic PL image file BIT0, after successfully loading the basic PL image file BIT0, initialize the register group;

[0008] S2, access the register group and configure the PL module to obtain the device identifier FUSE_DNA in the register group;

[0009] S3, access the register group to determine whether the PL module successfully obtains the device identifier FUSE_DNA, if successful, execute step S4, if failed, execute step S5;

[0010] S4, read the device identifier FUSE_DNA from the register group, and generate a random MAC address according to the read device identifier FUSE_DNA;

[0011] S5. Obtain a system clock, and generate a random MAC address according to the system clock.

[0012] In some specific implementations, the register group includes a first register, a second register, and a third register; the first register includes an address segment REG_bit0 for storing whether the device identification FUSE_DNA result is successfully obtained, an address segment REG_bit1 for configuring the PL module to obtain the device identification FUSE_DNA, and an address segment REG_bit2 for storing whether the basic PL image file BIT0 result is successfully loaded;

[0013] The second register and the third register are both used to store the acquired device identifier FUSE_DNA.

[0014] In some specific implementations, the specific process of step S3 is:

[0015] S31, load the basic PL image file BIT0, access the address segment REG_bit2 of the first register to read the loading result to determine whether the loading is successful;

[0016] S32, after successfully loading the basic PL image file BIT0, access the address segment REG_bit1 of the first register to write configuration information to the address segment REG_bit2 of the first register, so that the PL module obtains the device identifier FUSE_DNA of the current Xilinx-z7 chip;

[0017] S33 . Access the address segment REG_bit0 of the first register to determine whether the PL module successfully obtains the device identifier FUSE_DNA.

[0018] In some specific implementations, the specific process of step S4 is:

[0019] S41, access the second register and the third register, and read out the complete device identifier FUSE_DNA;

[0020] S42, calculating the hash value of the device identifier FUSE_DNA through MD5, intercepting the hash value, and obtaining a random number generation seed;

[0021] S43, inputting a random number generation seed into a random number generator to generate a random number;

[0022] S44, generating a random MAC address using the random number according to Ethernet specifications.

[0023] In some specific implementations, in step S42, the 128-bit hash value of the device identifier FUSE_DNA is calculated using MD5, and the lower 32-bit hash value of the 128-bit hash value is taken as a random number generation seed.

[0024] In some specific implementations, a 48-bit random number is randomly generated by a random number generator, and the 48-bit random number is processed according to the Ethernet specification to obtain a 48-bit random MAC address.

[0025] In some specific implementations, the storage space of the second register and the third register are both 32 bits. When the device identifier FUSE_DNA is stored, it is split into two parts and stored in the second register and the third register in sequence.

[0026] In a second aspect, the present application provides a Xilinx-z7 random MAC address acquisition device, comprising:

[0027] PS module, including:

[0028] Image loading unit, used to load the basic PL image file BIT0;

[0029] A configuration unit, used for accessing a register group through an AXI interface and configuring a PL module to obtain a device identifier FUSE_DNA in the register group;

[0030] The random number generation unit is used to access the register group through the AXI interface to determine whether the PL module successfully obtains the device identification FUSE_DNA; if successfully obtained, the device identification FUSE_DNA is read from the register group, and a random MAC address is generated according to the read device identification FUSE_DNA;

[0031] If the acquisition fails, the system clock is obtained and a random MAC address is generated based on the system clock.

[0032] The PL module is used to initialize the register group after successfully loading the basic PL image file BIT0, obtain the device identifier FUSE_DNA according to the configuration, and write it into the register group.

[0033] In some specific implementations, the register group includes a first register, a second register, and a third register; the first register includes an address segment REG_bit0 for storing whether the device identification FUSE_DNA result is successfully obtained, an address segment REG_bit1 for configuring the PL module to obtain the device identification FUSE_DNA, and an address segment REG_bit2 for storing whether the basic PL image file BIT0 result is successfully loaded;

[0034] The second register and the third register are both used to store the acquired device identifier FUSE_DNA.

[0035] In some specific implementations, the storage space of the second register and the third register are both 32 bits. When the device identifier FUSE_DNA is stored, it is split into two parts and stored in the second register and the third register in sequence.

[0036] The concept of this application is:

[0037] Currently, in the PS (processor system) of the Xilinx-z7 series chips, if you want to set a random MAC address, you usually get the system clock of the PS software, and then use the system clock as a random number seed to input into the random number generator to get a random number, and then format this random number into a normal MAC address format. However, for the same model of Xilinx-z7 hardware boards, since the time required from powering on the board to obtaining the system clock from the software is the same, the same model of hardware boards obtain the same system clock from the software, which will cause the same model of hardware boards to generate the same MAC address, resulting in network conflicts.

[0038] In this application, the unique device identifier FUSE_DNA of the Xilinx-z7 series chip PL is used to replace the system clock as the seed for random number generation to generate a MAC address. Since FUSE_DNA is unique to Xilinx chips, it is a unique device identity. This identifier is randomly generated when the chip is manufactured and solidified into the chip. This identifier is unique to each device and cannot be changed. Since FUSE_DNA is only stored in the PL module, the PS module cannot directly obtain FUSE_DNA. Therefore, in this application, by loading the basic PL image file BIT0, BIT0 is used to obtain and transfer FUSE_DNA; BIT0 obtains FUSE_DNA through the interface provided by Xilinx, and implements a set of registers. The PS module can access the register through the AXI interface to achieve the purpose of obtaining FUSE_DNA. Generate a random MAC address using the FUSE_DNA of each board, thereby avoiding MAC address conflicts to the greatest extent.

[0039] The present invention has the beneficial effects:

[0040] This application loads the basic PL image file BIT0, uses BIT0 to obtain and transfer FUSE_DNA, and implements a set of registers. The PS module can access the registers through the AXI interface to achieve the purpose of obtaining FUSE_DNA. A method for obtaining FUSE_DNA of PL under the PS module is implemented to solve the defect that PS has no FUSE_DNA;

[0041] Then, the unique device identifier FUSE_DNA of the Xilinx z7 series chip PL is used to replace the system clock as the seed for generating random numbers. The system then randomly generates a MAC address, realizing a method for obtaining a random MAC address without relying on other external resources, thereby avoiding MAC address conflicts to the greatest extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a Xilinx-z7 random MAC address acquisition method provided by an embodiment of the present invention;

[0043] Figure 2 BOOT image block diagram provided by an embodiment of the present invention;

[0044] Figure 3 A flowchart of obtaining FUSE_DNA from UBOOT provided in an embodiment of the present invention;

[0045] Figure 4 A flow chart of generating a random MAC address provided by an embodiment of the present invention;

[0046] Figure 5 A schematic diagram of the change in the data flow format from FUSE_DNA to MAC address provided in an embodiment of the present invention;

[0047] Figure 6 This is a block diagram of the Xilinx-z7 chip module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] The relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0050] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0051] Additionally, descriptions of well-known structures, functions, and configurations may be omitted for clarity and conciseness.One of ordinary skill in the art will recognize that various changes and modifications may be made to the examples described herein without departing from the spirit and scope of the present disclosure.

[0052] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0053] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0054] In order to facilitate the elaboration of the technical solution of this application, the following concepts are explained:

[0055] Xilinx-z7

[0056] The z7 series is a series of FPGA products based on the Zynq-7000 All Programmable SoC (system-on-chip) launched by Xilinx. The Zynq-7000 series integrates programmable logic (FPGA) with a dual-core or quad-core ARM Cortex-A9 processor system (PS) on a single chip, providing high-performance processing capabilities and flexible hardware programmability. The chip combines the advantages of processors and FPGAs, providing a powerful platform for embedded system designs that require high-performance computing and flexible hardware customization.

[0057] PS

[0058] Abbreviation for "Processor System". It is an integrated processing unit that usually contains one or more ARM processor cores, memory controllers, and other peripheral interfaces such as DDR memory interface, Ethernet, USB, PCIe, etc. In the z7 series, the PS part usually contains a dual-core or quad-core ARM Cortex-A9 processor for running operating systems and application code, and handling complex control and data processing tasks. In this way, the PS is combined with the programmable logic (PL) part of the FPGA to achieve the collaborative work of software and hardware on the same chip, providing high-performance, low-latency and highly integrated solutions.

[0059] PL

[0060] "Programmable Logic" programmable logic unit, including FPGA logic resources.

[0061] FUSE_DNA

[0062] Xilinx chips have a unique device ID. This ID is randomly generated when the chip is manufactured and fixed into the chip. This ID is unique to each device and cannot be changed. Xilinx also provides an interface through which PL can obtain its FUSE_DNA. For Xilinx-z7 series chips, FUSE_DNA only exists for PL, and the data is 64 bits.

[0063] AXI

[0064] PS and PL exchange data and transfer information through the AXI interface.

[0065] Example 1

[0066] like Figure 1 As shown, this embodiment provides a method for obtaining a random MAC address of Xilinx-z7, and the PS module performs the following steps:

[0067] S1, load the basic PL image file BIT0, after successfully loading the basic PL image file BIT0, initialize the register group;

[0068] Among them, the register group includes a first register, a second register and a third register; the first register includes an address segment REG_bit0 for storing whether the device identification FUSE_DNA result is successfully obtained, an address segment REG_bit1 for configuring the PL module to obtain the device identification FUSE_DNA, and an address segment REG_bit2 for storing whether the basic PL image file BIT0 result is successfully loaded; the second register and the third register are both used to store the obtained device identification FUSE_DNA.

[0069] Since the storage space of the second register and the third register is 32 bits, and the size of the device identifier FUSE_DNA is 64 bits, it is split into two parts during storage and stored in the second register and the third register in sequence.

[0070] S2, access the register group and configure the PL module to obtain the device identifier FUSE_DNA in the register group;

[0071] S3, access the register group to determine whether the PL module successfully obtains the device identifier FUSE_DNA, if successful, execute step S4, if failed, execute step S5;

[0072] Specifically, the specific process of obtaining the device identifier FUSE_DNA is as follows:

[0073] S31, load the basic PL image file BIT0, access the address segment REG_bit2 of the first register to read the loading result to determine whether the loading is successful;

[0074] S32, after successfully loading the basic PL image file BIT0, access the address segment REG_bit1 of the first register to write configuration information to the address segment REG_bit2 of the first register, so that the PL module obtains the device identifier FUSE_DNA of the current Xilinx-z7 chip;

[0075] S33. Access the address segment REG_bit0 of the first register to determine whether the PL module successfully obtains the device identifier FUSE_DNA.

[0076] S4, read the device identifier FUSE_DNA from the register group, and generate a random MAC address according to the read device identifier FUSE_DNA;

[0077] Specifically, the specific process of generating a random MAC address using the device identifier FUSE_DNA is as follows:

[0078] S41, access the second register and the third register, and read out the complete device identifier FUSE_DNA;

[0079] S42. Calculate the hash value of the device identifier FUSE_DNA through MD5, intercept the hash value, and obtain a random number generation seed; wherein, calculate the 128-bit hash value of the device identifier FUSE_DNA through MD5, and take the low 32-bit hash value of the 128-bit hash value as the random number generation seed.

[0080] S43, inputting a random number generation seed into a random number generator to generate a random number;

[0081] A 48-bit random number is randomly generated by a random number generator, and the 48-bit random number is processed according to the Ethernet specification to obtain a 48-bit random MAC address.

[0082] S44, generating a random MAC address using the random number according to Ethernet specifications.

[0083] S5. Obtain a system clock, and generate a random MAC address according to the system clock.

[0084] It can be understood that this embodiment uses the unique FUSE_DNA of the Xilinx z7 series chip PL. The PS accesses the register group through the AXI interface to read the FUSE_DNA. Then the PS calculates its hash value through the MD5 algorithm. This value replaces the system clock as the seed for random number generation. Then the system randomly generates a MAC address, thereby avoiding MAC address conflicts to the greatest extent.

[0085] For the PS module, the overall startup steps are described as follows:

[0086] 1. PS (UBOOT) obtains FUSE_DNA;

[0087] Since PS cannot directly obtain FUSE_DNA, special processing is required. The PS BOOT image contains the basic PL image file BIT0 for obtaining FUSE_DNA. UBOOT loads BIT0 by default first. After PL successfully obtains FUSE_DNA, PS obtains FUSE_DNA through the AXI interface.

[0088] PS When loading UBOOT, the BOOT image diagram is as follows Figure 2 , FSBL is the PS level 1 BOOT, used for basic CPU initialization; UBOOT completes the acquisition of FUSE_DNA and the generation of random MAC addresses; BIT0 is the PL image based on FUSE_DNA, used for the acquisition and transmission of FUSE_DNA, and BIT1 is the final business image of PL, which is optional.

[0089] In order to enable PS to obtain FUSE_DNA through the AXI interface, a set of registers can be implemented in the basic PL image file BIT0. BIT0 obtains FUSE_DNA through the interface provided by Xilinx and implements a set of registers (three registers). PS can access the register group through the AXI interface to obtain FUSE_DNA. The register group design is shown in Table 1-Table 3:

[0090] Table 1 The first register REG0

[0091]

[0092] Table 2 Second register REG1

[0093]

[0094] Table 3 The third register REG2

[0095]

[0096] like Figure 3 As shown, the specific process of PS (UBOOT) obtaining FUSE_DNA is:

[0097] Step 1.1, after UBOOT starts, load the default BIT0, and judge whether BIT0 is loaded successfully by the value of REG0_bit2. If it is loaded successfully, execute step 1.2. If it is not loaded successfully, record in PS that FUSE_DNA is not obtained. REG0-bit2 / bit0 is a read-only bit, which is set by PL. PS reads the status of PL from REG0-bit2 / bit0;

[0098] Step 1.2, PS accesses the register group, configures PL to obtain FUSE_DNA, and configures the value of REG0_bit1 to 1 to enable the PL module to obtain FUSE_DNA. After the PL module obtains FUSE_DNA, it updates the value of register REG0_bit0 to 1, and divides the obtained FUSE_DNA into two segments and writes them into REG1_bit[31:0] and REG2_bit[31:0] in sequence;

[0099] Step 1.3, PS accesses the register group and determines whether PL has obtained FUSE_DNA by reading the value of register REG0_bit0; if the read value is 1, it is determined that PL has obtained FUSE_DNA, and if the value of register REG0_bit0 is 0, it is recorded in PS that FUSE_DNA has not been obtained;

[0100] Step 1.4: If PL has obtained FUSE_DNA, PS accesses the register group, reads from REG1_bit[31:0] and REG2_bit[31:0] in sequence, and then splices them into a complete FUSE_DNA;

[0101] Step 1.5: Abnormal situation: PS record does not obtain FUSE_DNA.

[0102] 2. PS (UBOOT) generates a random MAC address through FUSE_DNA;

[0103] Specifically, Figure 4-Figure 5 As shown, the process of generating a random MAC address is:

[0104] Step 2.1, the PS module determines whether FUSE_DNA has been obtained. If not, it uses the default implementation method, that is, obtaining a random MAC address through the system clock;

[0105] Step 2.2: If FUSE_DNA has been obtained, calculate its 128-bit hash value through MD5. The value is highly discrete and there is almost no conflict.

[0106] Step 2.3, using the 128-bit hash value, take the lower 32 bits as the random number seed input of the random number generator;

[0107] Step 2.4: The 6-byte (48-bit) random number generated by the random number generator is formatted according to Ethernet and used as the random MAC address.

[0108] 3. PS (UBOOT) loads the business BIT file (if it exists).

[0109] 4. PS (UBOOT) guides the kernel to complete the startup of the operating system.

[0110] Example 2

[0111] like Figure 6 As shown, this embodiment provides a Xilinx-z7 random MAC address acquisition device, which involves PL and its FUSE_DNA. After PL obtains FUSE_DNA, it transfers FUSE_DNA to PS through AXI interface. After PS obtains FUSE_DNA, it performs subsequent software implementation. Specifically,

[0112] PS module, including:

[0113] Image loading unit, used to load the basic PL image file BIT0;

[0114] A configuration unit, used for accessing a register group through an AXI interface and configuring a PL module to obtain a device identifier FUSE_DNA in the register group;

[0115] The random number generation unit is used to access the register group through the AXI interface to determine whether the PL module successfully obtains the device identification FUSE_DNA; if successfully obtained, the device identification FUSE_DNA is read from the register group, and a random MAC address is generated according to the read device identification FUSE_DNA;

[0116] If the acquisition fails, the system clock is obtained and a random MAC address is generated based on the system clock.

[0117] The PL module is used to initialize the register group after successfully loading the basic PL image file BIT0, obtain the device identifier FUSE_DNA according to the configuration, and write it into the register group.

[0118] In some specific implementations, the register group includes a first register, a second register, and a third register; the first register includes an address segment REG_bit0 for storing whether the device identification FUSE_DNA result is successfully obtained, an address segment REG_bit1 for configuring the PL module to obtain the device identification FUSE_DNA, and an address segment REG_bit2 for storing whether the basic PL image file BIT0 result is successfully loaded;

[0119] The second register and the third register are both used to store the acquired device identifier FUSE_DNA.

[0120] In some specific implementations, the storage space of the second register and the third register are both 32 bits. When the device identifier FUSE_DNA is stored, it is split into two parts and stored in the second register and the third register in sequence.

[0121] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. According to the technical essence of the present invention, within the spirit and principles of the present invention, any simple modification, equivalent replacement and improvement made to the above embodiment still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for obtaining a random MAC address of Xilinx-z7, characterized in that: The PS module performs the following steps: S1, load the basic PL image file BIT0, after successfully loading the basic PL image file BIT0, initialize the register group; S2, access the register group and configure the PL module to obtain the device identifier FUSE_DNA in the register group; S3, access the register group to determine whether the PL module successfully obtains the device identifier FUSE_DNA, if successful, execute step S4, if failed, execute step S5; S4, read the device identifier FUSE_DNA from the register group, and generate a random MAC address according to the read device identifier FUSE_DNA; S5. Obtain a system clock, and generate a random MAC address according to the system clock.

2. A Xilinx-z7 random MAC address acquisition method according to claim 1, characterized in that: The register group includes a first register, a second register and a third register; the first register includes an address segment REG_bit0 for storing whether the device identification FUSE_DNA result is successfully obtained, an address segment REG_bit1 for configuring the PL module to obtain the device identification FUSE_DNA, and an address segment REG_bit2 for storing whether the basic PL image file BIT0 result is successfully loaded; The second register and the third register are both used to store the acquired device identifier FUSE_DNA.

3. A Xilinx-z7 random MAC address acquisition method according to claim 2, characterized in that: The specific process of step S3 is: S31, load the basic PL image file BIT0, access the address segment REG_bit2 of the first register to read the loading result to determine whether the loading is successful; S32, after successfully loading the basic PL image file BIT0, access the address segment REG_bit1 of the first register to write configuration information to the address segment REG_bit2 of the first register, so that the PL module obtains the device identifier FUSE_DNA of the current Xilinx-z7 chip; S33. Access the address segment REG_bit0 of the first register to determine whether the PL module successfully obtains the device identifier FUSE_DNA.

4. A Xilinx-z7 random MAC address acquisition method according to claim 2, characterized in that: The specific process of step S4 is: S41, access the second register and the third register, and read out the complete device identifier FUSE_DNA; S42, calculating the hash value of the device identifier FUSE_DNA through MD5, intercepting the hash value, and obtaining a random number generation seed; S43, inputting a random number generation seed into a random number generator to generate a random number; S44, generating a random MAC address using the random number according to Ethernet specifications.

5. A Xilinx-z7 random MAC address acquisition method according to claim 4, characterized in that: In step S42, the 128-bit hash value of the device identifier FUSE_DNA is calculated by MD5, and the lower 32-bit hash value of the 128-bit hash value is taken as a random number generation seed.

6. A Xilinx-z7 random MAC address acquisition method according to claim 4, characterized in that: A 48-bit random number is randomly generated by a random number generator, and the 48-bit random number is processed according to the Ethernet specification to obtain a 48-bit random MAC address.

7. A Xilinx-z7 random MAC address acquisition method according to claim 4, characterized in that: The storage space of the second register and the third register are both 32 bits. When the device identifier FUSE_DNA is stored, it is split into two parts and stored in the second register and the third register in sequence.

8. A Xilinx-z7 random MAC address acquisition device, characterized in that: include: PS module, including: Image loading unit, used to load the basic PL image file BIT0; A configuration unit, used for accessing a register group through an AXI interface and configuring a PL module to obtain a device identifier FUSE_DNA in the register group; The random number generation unit is used to access the register group through the AXI interface to determine whether the PL module successfully obtains the device identification FUSE_DNA; if successfully obtained, the device identification FUSE_DNA is read from the register group, and a random MAC address is generated according to the read device identification FUSE_DNA; If the acquisition fails, the system clock is obtained and a random MAC address is generated based on the system clock; The PL module is used to initialize the register group after successfully loading the basic PL image file BIT0, obtain the device identifier FUSE_DNA according to the configuration, and write it into the register group.

9. A Xilinx-z7 random MAC address acquisition device according to claim 8, characterized in that: The register group includes a first register, a second register and a third register; the first register includes an address segment REG_bit0 for storing whether the device identification FUSE_DNA result is successfully obtained, an address segment REG_bit1 for configuring the PL module to obtain the device identification FUSE_DNA, and an address segment REG_bit2 for storing whether the basic PL image file BIT0 result is successfully loaded; The second register and the third register are both used to store the acquired device identifier FUSE_DNA.

10. A Xilinx-z7 random MAC address acquisition device according to claim 9, characterized in that: The storage space of the second register and the third register are both 32 bits. When the device identifier FUSE_DNA is stored, it is split into two parts and stored in the second register and the third register in sequence.

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