Random number generation circuit and method of memory and memory
By introducing a random number generation circuit into the memory and using the duration information of the power-on process state machine and charge pump circuit to generate random number seeds, the problem of poor randomness in memory area address selection is solved, and the randomness and reliability of memory scanning are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-10
AI Technical Summary
In existing technologies, the address selection of storage regions in memory has poor randomness, which leads to poor randomness in memory region scanning.
By introducing a random number generation circuit into the memory, the random enable signal generation module detects the power-on duration of the power-on process state machine and the working duration of the write operation state machine control charge pump circuit, generates a random enable signal, and adjusts the frequency and phase through the clock module to generate a random number seed, ultimately generating a random number sequence.
It improves the randomness of storage area scanning, enhances the reliability of memory, does not affect the application experience at the system level, and has a low cost.
Smart Images
Figure CN121832887A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of memory technology, and more particularly to a random number generation circuit, method, and memory for a memory. Background Technology
[0002] Generating random numbers for chips is a common requirement, often applied to various systems and computing architectures.
[0003] Some systems require truly random numbers, while others only need to generate pseudo-random numbers. For pseudo-random numbers, a random number sequence can be used, typically through a pseudo-random number generator and relying on a seed. At the chip or system level, it is essentially a deterministic system. If the seed is not truly random, the generated sequence is often repeatable. If the system requirements are not high, the random number sequence uses a certain algorithm and relies on perturbations introduced by the system to generate pseudo-random numbers. For example, simple computer random numbers are generated based on system time, often yielding a pseudo-random number. If the system time is fixed, the random value obtained each time is deterministic. Introducing random inputs such as mouse movements and keyboard clicks (IO / Output) can generate truly random numbers, but the IO input remains controllable, still resulting in a deterministic "random number."
[0004] Memory is widely used in various electronic systems, communication equipment, industrial control and automotive electronics. Almost all devices that need to store a large amount of code or data require memory.
[0005] For various systems, the storage and execution of code must ensure correctness. Once the memory fails, it may affect the operation of the system or even cause the entire system to crash. Moreover, some systems, such as industrial and automotive electronic applications, have very high reliability requirements. In these cases, it is necessary to scan the memory chip's storage cells at appropriate times. If any storage cells show abnormal phenomena, they need to be scanned out and corrected in time so that the memory can work normally.
[0006] The scanning process of a memory chip should be hidden within time-consuming operations such as power-on or programming / erasing. Furthermore, only a portion of the memory area can be scanned at a time, with subsequent scans proceeding sequentially until the entire memory area is scanned. This way, the system application does not perceive a significant time change caused by the scanning process. However, some applications experience frequent power-on and power-off cycles. If the scan always starts from the area corresponding to all zeros or fixed addresses, only a fixed portion of the memory area can be scanned each time, resulting in poor randomness.
[0007] Therefore, improving the randomness of storage area scanning is a technical problem that urgently needs to be solved. Summary of the Invention
[0008] The technical problem to be solved by this disclosure is to overcome the defect of poor randomness in address selection of storage areas in the prior art, which leads to poor randomness in storage area scanning, and to provide a random number generation circuit, method and memory for memory.
[0009] This disclosure solves the above-mentioned technical problems through the following technical solution:
[0010] In a first aspect, a random number generation circuit for a memory is provided, the memory including a power-on process state machine for controlling the power-on operation of the memory, a write operation state machine for controlling the write operation of a target storage area in the memory, and a charge pump circuit for providing a write voltage for the write operation.
[0011] The random number generation circuit includes a random enable signal generation module, a clock module, and a random number generation module connected in sequence.
[0012] The random enable signal generation module is used to detect the power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation controlled by the write operation state machine, so as to obtain a random enable signal and output it to the clock module.
[0013] The random enable signal includes a power-on random enable signal or a write operation random enable signal, wherein the power-on random enable signal represents the power-on duration and the write operation random enable signal represents the working duration.
[0014] The clock module is used to adjust the frequency and phase of the random enable signal to obtain a random number seed and output it to the random number generation module;
[0015] The random number generation module is used to generate a random number sequence corresponding to the random number seed based on the random number seed.
[0016] Optionally, the random number generation circuit further includes a random number latch;
[0017] The random number latch is connected to the random number generation module;
[0018] The random number latch is used to store the random number sequence and adjust the data bit width of the random number sequence to obtain the target random number sequence;
[0019] And / or, the clock module is a ring oscillator.
[0020] Optionally, the random number generation module includes a sampling unit and an algorithm unit;
[0021] The sampling unit is used to sample the random number seed;
[0022] The algorithm unit is used to perform calculations on the random number seed based on a preset random number algorithm to output the random number sequence.
[0023] Optionally, the sampling unit includes an XOR logic gate;
[0024] The algorithm unit includes a linear feedback shift register;
[0025] The first input terminal of the XOR logic gate is connected to the output terminal of the clock module to receive the random number seed;
[0026] And / or, the second input of the XOR logic gate is connected to the output of the linear feedback shift register.
[0027] Optionally, the sampling unit includes a first XOR logic gate, a second XOR logic gate, and a third XOR logic gate;
[0028] The linear feedback shift register includes a first shift register, a second shift register, a third shift register, a fourth shift register, a fifth shift register, and a sixth shift register;
[0029] The first input terminal of the first XOR logic gate is connected to the output terminal of the clock module to receive the random number seed; the second input terminal of the first XOR logic gate is connected to the data output terminal of the sixth shift register; and the output terminal of the first XOR logic gate is connected to the data input terminal of the first shift register.
[0030] The data output terminal of the first shift register is connected to the data input terminal of the second shift register, the data output terminal of the second shift register is connected to the data input terminal of the third shift register, the data output terminal of the third shift register is connected to the data input terminal of the fourth shift register, and the data output terminal of the fourth shift register is connected to the data input terminal of the fifth shift register.
[0031] The first input terminal of the second XOR logic gate is connected to the output terminal of the clock module, the second input terminal of the second XOR logic gate is connected to the output terminal of the third XOR logic gate, and the output terminal of the second XOR logic gate is connected to the data input terminal of the sixth shift register.
[0032] The first input of the third XOR logic gate is connected to the data output of the sixth shift register, and the second input of the third XOR logic gate is connected to the data output of the fifth shift register.
[0033] The clock input port of each shift register is used to receive the clock signal of the memory, and the set port of each shift register is used to receive the reset signal of the memory.
[0034] Optionally, the preset random number algorithm corresponds to the linear feedback function of the linear feedback shift register;
[0035] The linear feedback function is expressed as: f(x) = 1 + x 5 +x 6 ;
[0036] Where, x 6 x represents the length of the linear feedback shift register. 5 This indicates that the data output port of the shift register is the tap position that participates in the feedback calculation.
[0037] Secondly, a method for generating random numbers in a memory is provided, wherein the random number generation method is implemented using the random number generation circuit of the memory described above;
[0038] The random number generation method includes:
[0039] The power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation control state machine are detected to obtain a random enable signal.
[0040] The random enable signal includes a power-on random enable signal or a write operation random enable signal, wherein the power-on random enable signal represents the power-on duration and the write operation random enable signal represents the working duration.
[0041] The frequency and phase of the random enable signal are adjusted to obtain a random number seed;
[0042] Generate a random number sequence corresponding to the random number seed based on the random number seed.
[0043] Optionally, the step of generating a random number sequence corresponding to the random number seed based on the random number seed includes:
[0044] Sampling is performed on the random number seed;
[0045] The random number seed is calculated based on a preset random number algorithm to output the random number sequence.
[0046] Thirdly, a memory is provided, the memory including a power-on process state machine for controlling the power-on operation of the memory, a write operation state machine for controlling the write operation of a target storage area in the memory, and a charge pump circuit for providing a write voltage for the write operation.
[0047] The memory also includes the random number generation circuit described above.
[0048] Optionally, the memory is Nor Flash (a type of non-volatile memory).
[0049] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.
[0050] The positive and progressive effects of this disclosure are as follows:
[0051] The random number generation circuit, method, and memory disclosed herein utilize a random enable signal generation module to detect the power-on duration of the power-on process state machine and the operating duration of the charge pump circuit during write operations controlled by the write operation state machine to obtain a random enable signal. By adjusting the frequency and phase of the random enable signal, a random number seed is obtained, and a random number sequence corresponding to the seed is generated. Since the random enable signal includes a power-on random enable signal or a write operation random enable signal, where the power-on random enable signal characterizes the power-on duration of the power-on process state machine and the write operation random enable signal characterizes the operating duration of the charge pump circuit during write operations controlled by the write operation state machine, and the operating duration of the charge pump circuit differs each time a different memory region is selected for a write operation (programming or erasing), and the power-on duration of the power-on process state machine also differs each time, the random enable signal inherent in the memory possesses excellent random characteristics. True random numbers can be generated at a relatively low cost. By specifying the address of the memory region to be scanned using true random numbers, the memory cells requiring repair can be identified, thus improving the randomness of scanning the memory region. Adding random access functionality to memory regions can significantly improve the reliability of memory without affecting the user experience at the system level. Attached Figure Description
[0052] Figure 1 A first structural schematic diagram of the random number generation circuit of the memory provided in Embodiment 1;
[0053] Figure 2 A waveform diagram of the power-on random enable signal of the random number generation circuit of the memory provided in Example 1;
[0054] Figure 3 A schematic diagram of the power-on random enable signal generation process of the random number generation circuit of the memory provided in Example 1;
[0055] Figure 4 A waveform diagram of the write operation random enable signal of the random number generation circuit of the memory provided in Example 1;
[0056] Figure 5A schematic diagram of the write operation random enable signal generation process of the random number generation circuit of the memory provided in Embodiment 1;
[0057] Figure 6 A second structural schematic diagram of the random number generation circuit of the memory provided in Embodiment 1;
[0058] Figure 7 A schematic diagram of the clock module in the random number generation circuit of the memory provided in Embodiment 1;
[0059] Figure 8 A schematic diagram of the random number generation module in the random number generation circuit of the memory provided in Embodiment 1;
[0060] Figure 9 A schematic diagram showing the analysis results of random numbers generated by the random number generation circuit of the memory provided in Example 1 through simulation software;
[0061] Figure 10 A schematic diagram showing the analysis results of random numbers actually generated by the random number generation circuit of the memory provided in Example 1 through experimental methods;
[0062] Figure 11 for Figure 10 The corresponding random number distribution chart;
[0063] Figure 12 A schematic diagram of the first process of the random number generation method for the memory provided in Embodiment 2;
[0064] Figure 13 This is a schematic diagram of the second process of the random number generation method for the memory provided in Embodiment 2. Detailed Implementation
[0065] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.
[0066] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the claims or the context of the embodiments, and should not be construed as an unnecessary limitation. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.
[0067] Example 1
[0068] This embodiment provides a random number generation circuit for a memory. The memory includes a power-on process state machine for controlling the power-on operation of the memory, a write operation state machine for controlling the write operation of a target storage area in the memory, and a charge pump circuit for providing write voltage for the write operation.
[0069] like Figure 1 As shown, the random number generation circuit includes a random enable signal generation module 1, a clock module 2, and a random number generation module 3 connected in sequence.
[0070] The random enable signal generation module 1 is used to detect the power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation control write operation of the write operation state machine, so as to obtain a random enable signal and output it to the clock module 2.
[0071] Among them, the random enable signal includes a power-on random enable signal or a write operation random enable signal. The power-on random enable signal represents the power-on duration, and the write operation random enable signal represents the working duration.
[0072] Clock module 2 is used to adjust the frequency and phase of the random enable signal to obtain a random number seed and output it to random number generation module 3;
[0073] The random number generation module 3 is used to generate a random number sequence corresponding to the random number seed.
[0074] The random number seed is generated by the clock module, which is essentially a high-frequency clock signal that has been adjusted for frequency and phase.
[0075] like Figure 2 As shown, VDD is the memory power supply voltage, POR is the power-on reset signal, Clk is the memory system clock, POR_FSM is the power-on process state machine, and Enable_Por_Random is the power-on random enable signal. The power-on reset signal POR triggers the power-on operation, the system clock Clk begins to generate, and the power-on process state machine POR_FSM begins executing the power-on operation. The power-on process state machine includes an idle phase and a power-on phase that controls the memory power-on operation. The power-on phase includes a voltage setup phase, a pattern check phase, and a data read and pattern check phase. The duration of the power-on phase in the power-on process state machine is the same as the power-on duration of the aforementioned power-on process state machine, specifically corresponding to... Figure 2The duration of the high level of the power-on random enable signal Enable_Por_Random. When the memory powers on, the power-on process state machine continuously attempts to read the actual data stored inside the memory cell. Since the voltage and temperature are constantly changing with each power-on, the power-on duration of the process state machine will vary each time. The power-on duration has excellent randomness. Based on the power-on duration of the process state machine, a unique random number sequence can be generated on the memory.
[0076] like Figure 3 As shown, the memory includes several storage areas, each containing several storage cells. The storage cells within a storage area are decoded to select data lines, which are then amplified by a signal amplifier circuit to store the actual data from the storage cells into a latch or register. Figure 3 (The circuit shown uses 32 data points as an example.) The subsequent data comparison circuit compares the actual data in the register with the expected data. If the two data match, the read address of the memory cell is incremented, and the actual data of the next memory cell is read for comparison. If the two data do not match, the read address is reset, and the power-on process state machine re-executes the power-on operation. The time for repeatedly reading the actual data in the memory cell is the high-level duration of the power-on random enable signal Enable_Por_Random (see...). Figure 2 By utilizing existing devices in the memory, a random power-on enable signal can be obtained without increasing the memory area, which can then be combined with the subsequent clock module to generate a random number seed.
[0077] like Figure 4 As shown, the output voltage of the charge pump circuit is denoted as Vpump, CSB (Chip Select Bar) is the chip select signal (active low), Clk is the memory's system clock, and the write operation includes programming and erasing operations. The write operation state machine is denoted as Program / Erase_FSM, and the write operation random enable signal is denoted as Enable_PumpRandom. The chip select signal CSB triggers the write operation, the system clock Clk begins to generate, and the write operation state machine Program / Erase_FSM begins executing the write operation. The write operation state machine includes an idle phase, a voltage setup phase, and a write operation phase. The write operation phase includes a voltage setup phase and a programming / erasing phase. The write operation state machine controls the write operation phase when a write operation is performed on a specific memory cell. The charge pump circuit provides the write voltage for the write operation on that memory cell. The operating time of the charge pump circuit during the write operation corresponds to... Figure 4The duration of the high level in Enable_Pump_Random.
[0078] The random enable signal Enable_Random includes the aforementioned power-on random enable signal Enable_Pump_Random or write operation random enable signal Enable_Pump_Random.
[0079] The memory cells of a memory chip vary due to physical manufacturing factors such as process technology. These differences result in different threshold voltages (Vt) and varying current and voltage values for different memory cells. Furthermore, the shape and size of word lines and bit lines in different memory regions differ due to manufacturing factors, and the thickness of the silicon dioxide separating word lines or bit lines also varies, ultimately leading to differences in the resistance and capacitance values of each word line and bit line. Additionally, the voltage and temperature of the memory continuously change during each write operation (programming or erasing). If the ambient temperature remains constant, the memory temperature generally rises continuously after power-on, causing changes in the circuit parameters and ultimately altering the write operation time. These factors result in varying charge pump circuit operating times when the memory chip selects different regions for write operations each time. These operating times exhibit excellent randomness, allowing the generation of unique random number sequences on the memory based on the charge pump circuit's operating time during write operations.
[0080] like Figure 5 As shown, the memory includes a charge pump, a voltage detection circuit, a voltage divider circuit, a comparator, and a buffer. During a write operation, a high-voltage signal is generated by the charge pump and output through a voltage regulator modulator. The charge pump determines its start / stop state based on the voltage detection circuit. The output voltage Vpump of the charge pump is divided by the voltage divider circuit to obtain a voltage division value, which is compared with a reference voltage. When the voltage division value is lower than the reference voltage, it indicates that the Vpump voltage is low, and the charge pump enable signal is high, meaning the charge pump is in the start (working) state. When the voltage division value is higher than the reference voltage, it indicates that the Vpump voltage is sufficiently high, and the charge pump enable signal is low, meaning the charge pump is in the stop state. Due to the differences in current and voltage in different storage areas and the duration of different write operations, the enable state of the charge pump is random. The charge pump enable signal can be directly used as the corresponding write operation random enable signal Enable_Pump_Random, or the charge pump enable signal can be buffered and used as the corresponding write operation random enable signal. The operating duration of the charge pump circuit during a write operation is the high-level duration of the write operation random enable signal (see [link]). Figure 4 By utilizing existing devices in the memory, a random enable signal for write operations can be obtained without increasing the memory area, which can then be combined with a subsequent clock module to generate a random number seed.
[0081] The random number generation circuit of the memory in this embodiment detects the power-on duration of the power-on process state machine and the operating duration of the charge pump circuit during write operations controlled by the write operation state machine through a random enable signal generation module to obtain a random enable signal. By adjusting the frequency and phase of the random enable signal, a random number seed is obtained, and a random number sequence corresponding to the random number seed is generated based on the random number seed. Since the random enable signal includes a power-on random enable signal or a write operation random enable signal, the power-on random enable signal represents the power-on duration of the power-on process state machine, and the write operation random enable signal represents the operating duration of the charge pump circuit during write operations controlled by the write operation state machine. Each time a different memory region is selected for a write operation, the operating duration of the charge pump circuit is different, and the power-on duration of the power-on process state machine is different each time. This gives the memory's unique random enable signal excellent random characteristics, allowing true random numbers to be generated at a low cost. By specifying the address of the memory region to be scanned in the memory using true random numbers, the memory cell that needs to be repaired can be found, improving the randomness of scanning the memory region. Adding random access functionality to memory regions can significantly improve the reliability of memory without affecting the user experience at the system level.
[0082] In an alternative implementation, such as Figure 6 As shown, the random number generation circuit also includes a random number latch 4;
[0083] Random number latch 4 is connected to random number generation module 3;
[0084] Random number latch 4 is used to store random number sequences and adjust the data bit width of the random number sequence to obtain the target random number sequence.
[0085] A random number latch is a set of one or more registers used to store processed random numbers. As needed, only the required data bit width can be extracted to obtain a target random number sequence that meets the data bit width requirement.
[0086] In an alternative implementation, the clock module is a ring oscillator.
[0087] The clock module uses a high-frequency oscillating clock circuit (such as a ring oscillator). The random enable signal Enable_Random is introduced into the clock module, and the start and stop times of the clock will become random. Subsequent circuits will not be able to sample a value of 0 or 1.
[0088] A simple implementation of a clock module is a ring oscillator. A ring oscillator consists of an odd number of stages (e.g., 5, 7, or 9 stages) of inverters or differential delay units connected end-to-end to form a ring. This structure is simple and regular, with a very compact and modular physical layout, occupying almost no extra area. For example... Figure 7As shown, the ring oscillator consists of five inverters connected end to end to form a ring. By delaying the signal by a certain time through inverters and delay units, the frequency and phase of the random enable signal Enable_Random are adjusted to obtain a high-frequency clock signal, namely the random number seed rand_seed.
[0089] In an alternative implementation, such as Figure 6 As shown, the random number generation module 3 includes a sampling unit 31 and an algorithm unit 32;
[0090] Sampling unit 31 is used to sample the random number seed;
[0091] The algorithm unit uses 32 to perform calculations on the random number seed based on a preset random number algorithm to output a random number sequence.
[0092] Sampling unit 31 can be referred to as a low-frequency sampling circuit. Figure 7 The random number seed rand_seed is obtained by taking one tap from the multi-stage inverter of the clock module. The random number seed is used as the input of the low-frequency sampling circuit 31. Due to the uncertainty of the random number seed, the sampled value is uncertain.
[0093] The algorithm unit 32 can be called the algorithm processing circuit. The low-frequency sampling circuit 31 may easily sample continuous 0 or 1, or the driving capability of the clock module corresponding to the random number seed cannot achieve strict equality of 0 / 1, resulting in a significantly larger proportion of 0 or 1 in the sampling result. Using the algorithm processing circuit, a uniform distribution and equal proportion of 0 and 1 can be achieved.
[0094] In an alternative implementation, such as Figure 8 As shown, the sampling unit 31 includes an XOR logic gate;
[0095] Algorithm unit 32 includes a linear feedback shift register 321;
[0096] The first input of the XOR logic gate is connected to the output of clock module 2 to receive the random number seed;
[0097] The second input of the AND / OR XOR logic gate is connected to the output of the linear feedback shift register.
[0098] Small-to-medium capacity (e.g., below 1 Gbit) memory has high requirements for area cost control. It needs to generate truly random numbers while keeping the random number generation circuit relatively simple. Existing algorithms such as SHA (Secure Hash Algorithm) or AES (Advanced Encryption Standard) can achieve a uniform distribution and proportional proportion of 0s and 1s in the random number seed collected by the sampling circuit. However, these algorithms occupy a large memory area, which does not meet the area cost requirements of small-to-medium capacity memory.
[0099] Linear feedback shift registers (LFSRs) can achieve a uniform distribution and proportional proportion of 0s and 1s, while occupying only a small area, making them very suitable for use in memory random number generation circuits.
[0100] In an alternative implementation, such as Figure 8 As shown, the sampling unit 31 includes a first XOR logic gate 311, a second XOR logic gate 312, and a third XOR logic gate 313;
[0101] The linear feedback shift register 321 includes a first shift register adr_rpgm_reg[0], a second shift register adr_rpgm_reg[1], a third shift register adr_rpgm_reg[2], a fourth shift register adr_rpgm_reg[3], a fifth shift register adr_rpgm_reg[4], and a sixth shift register adr_rpgm_reg[5].
[0102] The first input terminal of the first XOR logic gate 311 is connected to the output terminal of the clock module 2 to receive the random number seed rand_seed. The second input terminal of the first XOR logic gate 311 is connected to the data output terminal Q of the sixth shift register adr_rpgm_reg[5]. The output terminal of the first XOR logic gate 311 is connected to the data input terminal D of the first shift register adr_rpgm_reg[0].
[0103] The data output terminal Q of the first shift register adr_rpgm_reg[0] is connected to the data input terminal D of the second shift register adr_rpgm_reg[1]. The data output terminal Q of the second shift register adr_rpgm_reg[1] is connected to the data input terminal D of the third shift register adr_rpgm_reg[2]. The data output terminal Q of the third shift register adr_rpgm_reg[2] is connected to the data input terminal D of the fourth shift register adr_rpgm_reg[3]. The data output terminal Q of the fourth shift register adr_rpgm_reg[3] is connected to the data input terminal D of the fifth shift register adr_rpgm_reg[4].
[0104] The first input terminal of the second XOR logic gate 312 is connected to the output terminal of the clock module 2 to receive the random number seed rand_seed. The second input terminal of the second XOR logic gate 312 is connected to the output terminal of the third XOR logic gate 313. The output terminal of the second XOR logic gate 312 is connected to the data input terminal D of the sixth shift register adr_rpgm_reg[5].
[0105] The first input of the third XOR logic gate 313 is connected to the data output Q of the sixth shift register adr_rpgm_reg[5], and the second input of the third XOR logic gate 313 is connected to the data output Q of the fifth shift register adr_rpgm_reg[4].
[0106] The clock input port Clk of each shift register is used to receive the clock signal Clk from the memory, and the set port Set of each shift register is used to receive the reset signal POR from the memory.
[0107] Specifically, the preset random number algorithm corresponds to the linear feedback function of the aforementioned linear feedback shift register;
[0108] The linear feedback function is expressed as: f(x) = 1 + x 5 +x 6 ;
[0109] Where, x 6 This indicates the length of the linear feedback shift register, i.e., 6 shift registers, x 5 The data output port of the shift register is the tap position that participates in the feedback calculation. That is, the data output port Q of the sixth shift register adr_rpgm_reg[5] is the tap position that participates in the feedback calculation.
[0110] Figure 8 The random number generation module shown can generate a 6-bit random number sequence.
[0111] Figure 9The analysis results of random numbers generated by the random number generation circuit of the memory of this disclosure through simulation software are shown; Figure 10 The analysis results of random numbers actually generated by the random number generation circuit of the memory of this disclosure through experimental means are shown. The random number generation module can generate 3-bit random numbers, that is, 8 random results, and the random results include the case of 3 bits all 0, avoiding the case of 6 bits not all 0. Figure 11 The graph shows the distribution of random numbers after 3374 tests. As can be seen from the graph, the random numbers are relatively evenly distributed, and the same set of random numbers does not appear continuously for a long time.
[0112] Example 2
[0113] This embodiment provides a method for generating random numbers in a memory. The random number generation method is implemented using the random number generation circuit of the memory in Embodiment 1; such as Figure 12 As shown, the random number generation method includes:
[0114] S1. Detect the power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation controlled by the write operation state machine to obtain a random enable signal.
[0115] Among them, the random enable signal includes the power-on random enable signal or the write operation random enable signal. The power-on random enable signal represents the power-on duration, and the write operation random enable signal represents the charge pump operating duration.
[0116] S2. Adjust the frequency and phase of the random enable signal to obtain the random number seed.
[0117] S3. Generate a random number sequence corresponding to the random number seed based on the random number seed.
[0118] Specifically, the random enable signal generation module in the random number generation circuit detects the power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation controlled by the write operation state machine to obtain the random enable signal; the frequency and phase of the random enable signal are adjusted by the clock module to obtain the random number seed; and the random number generation module is used to generate a random number sequence corresponding to the random number seed based on the random number seed.
[0119] In an alternative implementation, such as Figure 13 As shown, step S3 above includes:
[0120] S31. Sample the random number seed.
[0121] S32. Perform calculations on the random number seed based on the preset random number algorithm to output a random number sequence.
[0122] Specifically, the random number seed is sampled by the sampling unit in the random number generation circuit, and the algorithm unit performs calculations on the random number seed based on the preset random number algorithm to output a random number sequence.
[0123] The random number generation method of the memory in this embodiment is implemented using the random number generation circuit of the memory in Embodiment 1. The random number generation circuit detects the power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation controlled by the write operation state machine through the random enable signal generation module to obtain the random enable signal. By adjusting the frequency and phase of the random enable signal, a random number seed is obtained, and a random number sequence corresponding to the random number seed is generated based on the random number seed. Because the random enable signal includes a power-on random enable signal or a write operation random enable signal, the power-on random enable signal characterizes the power-on duration of the power-on process state machine, and the write operation random enable signal characterizes the operating duration of the charge pump circuit during the write operation controlled by the write operation state machine. Since the operating duration of the charge pump circuit varies each time a different memory region is selected for a write operation (programming or erasing), and the power-on duration of the power-on process state machine also varies each time, the memory's inherent random enable signal possesses excellent random characteristics. True random numbers can be generated at a relatively low cost. These true random numbers are used to specify the address of the memory region to be scanned in the memory to find the memory cells that need repair, thus improving the randomness of the memory region scan. Adding a random scanning function to the memory region can significantly improve its reliability without affecting the user experience at the system level.
[0124] Example 3
[0125] This embodiment provides a memory, which includes a power-on process state machine for controlling the power-on operation of the memory, a write operation state machine for controlling the write operation of a target storage area in the memory, and a charge pump circuit for providing write voltage for the write operation.
[0126] The memory also includes the random number generation circuit of the memory provided in Embodiment 1.
[0127] In an alternative implementation, the memory is Nor Flash.
[0128] The memory in this embodiment includes the random number generation circuit of the memory provided in embodiment 1. The random number generation circuit detects the power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation controlled by the write operation state machine through the random enable signal generation module to obtain a random enable signal. By adjusting the frequency and phase of the random enable signal, a random number seed is obtained, and a random number sequence corresponding to the random number seed is generated based on the random number seed. Because the random enable signal includes a power-on random enable signal or a write operation random enable signal, the power-on random enable signal characterizes the power-on duration of the power-on process state machine, and the write operation random enable signal characterizes the operating duration of the charge pump circuit during the write operation controlled by the write operation state machine. Since the operating duration of the charge pump circuit varies each time a different memory region is selected for a write operation (programming or erasing), and the power-on duration of the power-on process state machine also varies each time, the memory's inherent random enable signal possesses excellent random characteristics. True random numbers can be generated at a relatively low cost. These true random numbers are used to specify the address of the memory region to be scanned in the memory to find the memory cells that need repair, thus improving the randomness of the memory region scan. Adding a random scanning function to the memory region can significantly improve its reliability without affecting the user experience at the system level.
[0129] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.
Claims
1. A random number generation circuit for a memory, characterized in that, The memory includes a power-on process state machine for controlling the power-on operation of the memory, a write operation state machine for controlling the write operation of the target storage area in the memory, and a charge pump circuit for providing the write voltage for the write operation. The random number generation circuit includes a random enable signal generation module, a clock module, and a random number generation module connected in sequence. The random enable signal generation module is used to detect the power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation controlled by the write operation state machine, so as to obtain a random enable signal and output it to the clock module. The random enable signal includes a power-on random enable signal or a write operation random enable signal, wherein the power-on random enable signal represents the power-on duration and the write operation random enable signal represents the working duration. The clock module is used to adjust the frequency and phase of the random enable signal to obtain a random number seed and output it to the random number generation module; The random number generation module is used to generate a random number sequence corresponding to the random number seed based on the random number seed.
2. The random number generation circuit according to claim 1, characterized in that, The random number generation circuit also includes a random number latch; The random number latch is connected to the random number generation module; The random number latch is used to store the random number sequence and adjust the data bit width of the random number sequence to obtain the target random number sequence; And / or, the clock module is a ring oscillator.
3. The random number generation circuit according to claim 1, characterized in that, The random number generation module includes a sampling unit and an algorithm unit; The sampling unit is used to sample the random number seed; The algorithm unit is used to perform calculations on the random number seed based on a preset random number algorithm to output the random number sequence.
4. The random number generation circuit according to claim 3, characterized in that, The sampling unit includes an XOR logic gate; The algorithm unit includes a linear feedback shift register; The first input terminal of the XOR logic gate is connected to the output terminal of the clock module to receive the random number seed; And / or, the second input of the XOR logic gate is connected to the output of the linear feedback shift register.
5. The random number generation circuit according to claim 4, characterized in that, The sampling unit includes a first XOR logic gate, a second XOR logic gate, and a third XOR logic gate; The linear feedback shift register includes a first shift register, a second shift register, a third shift register, a fourth shift register, a fifth shift register, and a sixth shift register; The first input terminal of the first XOR logic gate is connected to the output terminal of the clock module to receive the random number seed; the second input terminal of the first XOR logic gate is connected to the data output terminal of the sixth shift register; and the output terminal of the first XOR logic gate is connected to the data input terminal of the first shift register. The data output terminal of the first shift register is connected to the data input terminal of the second shift register, the data output terminal of the second shift register is connected to the data input terminal of the third shift register, the data output terminal of the third shift register is connected to the data input terminal of the fourth shift register, and the data output terminal of the fourth shift register is connected to the data input terminal of the fifth shift register. The first input terminal of the second XOR logic gate is connected to the output terminal of the clock module, the second input terminal of the second XOR logic gate is connected to the output terminal of the third XOR logic gate, and the output terminal of the second XOR logic gate is connected to the data input terminal of the sixth shift register. The first input of the third XOR logic gate is connected to the data output of the sixth shift register, and the second input of the third XOR logic gate is connected to the data output of the fifth shift register. The clock input port of each shift register is used to receive the clock signal of the memory, and the set port of each shift register is used to receive the reset signal of the memory.
6. The random number generation circuit according to claim 5, characterized in that, The preset random number algorithm corresponds to the linear feedback function of the linear feedback shift register; The linear feedback function is expressed as: f(x) = 1 + x 5 +x 6 ; Where, x 6 x represents the length of the linear feedback shift register. 5 This indicates that the data output port of the shift register is the tap position that participates in the feedback calculation.
7. A method for generating random numbers in a memory, characterized in that, The random number generation method is implemented using the random number generation circuit of the memory as described in any one of claims 1-6; The random number generation method includes: The power-on duration of the power-on process state machine and the working duration of the charge pump circuit during the write operation control state machine are detected to obtain a random enable signal. The random enable signal includes a power-on random enable signal or a write operation random enable signal, wherein the power-on random enable signal represents the power-on duration and the write operation random enable signal represents the working duration. The frequency and phase of the random enable signal are adjusted to obtain a random number seed; Generate a random number sequence corresponding to the random number seed based on the random number seed.
8. The random number generation method according to claim 7, characterized in that, The step of generating a random number sequence corresponding to the random number seed based on the random number seed includes: Sampling is performed on the random number seed; The random number seed is calculated based on a preset random number algorithm to output the random number sequence.
9. A memory, characterized in that, The memory includes a power-on process state machine for controlling the power-on operation of the memory, a write operation state machine for controlling the write operation of the target storage area in the memory, and a charge pump circuit for providing the write voltage for the write operation. The memory further includes a random number generation circuit for the memory as described in any one of claims 1-6.
10. The memory according to claim 9, characterized in that, The memory is Nor Flash.