Printed circuit board, adapter board, and electronic device

Abstract

The application provides a printed circuit board, a conversion board and an electronic device, and relates to the technical field of electronics. The printed circuit board is provided with a first mounting area, a second mounting area and a third mounting area. The first mounting area is used for mounting a system-level chip. The second mounting area is used for mounting a first memory or a first conversion board. The third mounting area is used for mounting a second memory or a second conversion board. The first mounting area is provided with first-type signal pins and second-type signal pins. The second mounting area is provided with third-type signal pins and fourth-type signal pins. The third mounting area is provided with fifth-type signal pins and sixth-type signal pins. The first-type signal pins are electrically connected to the third-type signal pins through first-type signal lines in the printed circuit board. The second-type signal pins are electrically connected to the fifth-type signal pins through second-type signal lines in the printed circuit board. The fourth-type signal pins are electrically connected to the sixth-type signal pins through third-type signal lines in the printed circuit board.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a printed circuit board, an adapter board, and an electronic device. Background Technology

[0002] Currently, there are various types of memory, such as integrated memory and discrete memory. Integrated memory refers to memory that integrates main memory and flash memory, while discrete memory refers to memory where main memory and flash memory are separate. To save costs and improve the design flexibility of electronic products, printed circuit boards (PCBs), such as motherboards, often need to be compatible with multiple types of memory. However, current technologies design separate PCBs for different types of memory, which is not only costly but also lacks flexibility. Summary of the Invention

[0003] This application provides a printed circuit board, an adapter board, and an electronic device. The printed circuit board can accommodate the installation of various types of memory, which helps to reduce the development cost of electronic products and improve the flexibility of memory selection.

[0004] In a first aspect, embodiments of this application provide a printed circuit board, which is provided with a first mounting area, a second mounting area and a third mounting area. The first mounting area is used to mount a system-on-a-chip, the second mounting area is used to mount a first memory or a first adapter board, and the third mounting area is used to mount a second memory or a second adapter board.

[0005] The first mounting area is provided with a first type of signal pin and a second type of signal pin; the second mounting area is provided with a third type of signal pin and a fourth type of signal pin; and the third mounting area is provided with a fifth type of signal pin and a sixth type of signal pin.

[0006] The first type of signal pin is electrically connected to the third type of signal pin through the first type of signal line in the printed circuit board; the second type of signal pin is electrically connected to the fifth type of signal pin through the second type of signal line in the printed circuit board; and the fourth type of signal pin is electrically connected to the sixth type of signal pin through the third type of signal line in the printed circuit board.

[0007] Wherein, when the first memory is RAM and the second memory is flash memory, the first type of signal line is used to transmit memory signals and the second type of signal line is used to transmit flash memory signals; when the first memory is flash memory and the second memory is RAM, the first type of signal line is used to transmit flash memory signals and the second type of signal line is used to transmit RAM signals; the third type of signal line is used to transmit either flash memory signals or RAM signals, and the first adapter board is used to install a third memory, which is a memory that integrates RAM and flash memory.

[0008] Secondly, embodiments of this application provide a first adapter board, the first adapter board having a first side provided with a seventh type signal pin and an eighth type signal pin, the second side of the first adapter board having a fourth mounting area, the fourth mounting area being used to mount a third memory, the fourth mounting area having a ninth type signal pin and a tenth type signal pin;

[0009] The seventh type signal pin is electrically connected to the ninth type signal pin through the fourth type signal line in the first adapter board, and the eighth type signal pin is electrically connected to the tenth type signal pin through the fifth type signal line in the first adapter board.

[0010] The first side of the first adapter board is used to mount the first adapter board to the printed circuit board. The second side of the first adapter board is opposite to the first side of the first adapter board. One of the fourth type signal line and the fifth type signal line is used to transmit memory signals, and the other is used to transmit flash memory signals. The third memory is a memory that integrates flash memory and memory.

[0011] Thirdly, embodiments of this application provide a second adapter board, the first side of which is provided with an eleventh type signal pin and a twelfth type signal pin, the eleventh type signal pin being electrically connected to the twelfth type signal pin through a sixth type signal line within the second adapter board;

[0012] The first side of the second adapter board is used to mount the second adapter board to the printed circuit board, and the sixth type signal line is used to transmit memory signals or flash memory signals.

[0013] Fourthly, embodiments of this application provide an electronic device, which includes the printed circuit board, system-on-a-chip, first memory, and second memory provided in the first aspect above;

[0014] The system-on-a-chip is mounted in the first mounting area of ​​the printed circuit board. The thirteenth type signal pin of the system-on-a-chip is electrically connected to the first type signal pin of the first mounting area, and the fourteenth type signal pin of the system-on-a-chip is electrically connected to the second type signal pin of the first mounting area.

[0015] The first memory is mounted in the second mounting area of ​​the printed circuit board, and the fifteenth type signal pin of the first memory is electrically connected to the third type signal pin of the second mounting area.

[0016] The second memory is mounted in the third mounting area of ​​the printed circuit board, and the sixteenth type signal pin of the second memory is electrically connected to the fifth type signal pin of the third mounting area.

[0017] Fifthly, embodiments of this application also provide an electronic device, which includes the printed circuit board provided in the first aspect, the first adapter board provided in the second aspect, the second adapter board provided in the second aspect, a system-on-a-chip, and a third memory;

[0018] The system-on-a-chip is mounted in the first mounting area of ​​the printed circuit board. The thirteenth type signal pin of the system-on-a-chip is electrically connected to the first type signal pin of the first mounting area, and the fourteenth type signal pin of the system-on-a-chip is electrically connected to the second type signal pin of the first mounting area.

[0019] The first adapter board is mounted on the second mounting area of ​​the printed circuit board. The seventh type signal pin of the first adapter board is electrically connected to the third type signal pin of the second mounting area, and the eighth type signal pin of the first adapter board is electrically connected to the fourth type signal pin of the second mounting area.

[0020] The second adapter board is mounted on the third mounting area of ​​the printed circuit board. The eleventh type signal pin of the second adapter board is electrically connected to the fifth type signal pin of the third mounting area, and the twelfth type signal pin of the second adapter board is electrically connected to the sixth type signal pin of the third mounting area.

[0021] The third memory is mounted in the fourth mounting area of ​​the first adapter board. The seventeenth type signal pin of the third memory is electrically connected to the ninth type signal pin of the fourth mounting area, and the eighteenth type signal pin of the third memory is electrically connected to the tenth type signal pin of the fourth mounting area.

[0022] In this embodiment, the printed circuit board (PCB) is provided with a first mounting area, a second mounting area, and a third mounting area. The first mounting area is used to mount a system-on-a-chip (SoC), the second mounting area is used to mount a first memory or a first adapter board, and the third mounting area is used to mount a second memory or a second adapter board. Therefore, discrete memories (i.e., the first and second memories) can be directly mounted on this PCB, or integrated memories (i.e., the third memory) can be mounted through the first and second adapter boards. This means the PCB supports mounting different types of memories, which helps reduce the development cost of electronic products and increases the flexibility of memory selection. Furthermore, when the first and second memories are mounted on this PCB, the signal traces reserved for the third memory (i.e., the signal lines between the fourth and sixth type signal pins) are floating and not connected to the signal lines of the first and second memories. This avoids the signal traces reserved for the third memory from affecting the signals of the first and second memories. Attached Figure Description

[0023] Figure 1a This is one of the schematic diagrams of installing an integrated memory on PCB1 provided in the embodiments of this application;

[0024] Figure 1b This is a second schematic diagram of an integrated memory mounted on PCB1 provided in an embodiment of this application;

[0025] Figure 1c This is one of the schematic diagrams of mounting a discrete memory on PCB2 provided in the embodiments of this application;

[0026] Figure 1d This is a second schematic diagram of mounting a separate memory on PCB2 according to an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of mounting a separate memory via an adapter board according to an embodiment of this application;

[0028] Figure 3 This is a side view of a printed circuit board provided in an embodiment of this application;

[0029] Figure 4a and Figure 4b This is a top view of a printed circuit board provided in an embodiment of this application;

[0030] Figure 5a This is one of the schematic diagrams of mounting a discrete memory on a printed circuit board according to an embodiment of this application;

[0031] Figure 5b This is one of the schematic diagrams of mounting an integrated memory on a printed circuit board according to an embodiment of this application;

[0032] Figure 6a This is a second schematic diagram of mounting a discrete memory on a printed circuit board according to an embodiment of this application;

[0033] Figure 6b This is a second schematic diagram of mounting an integrated memory on a printed circuit board according to an embodiment of this application;

[0034] Figure 7 This is a schematic diagram showing the distribution of the first mounting area, the second mounting area, and the third mounting area of ​​the printed circuit board provided in the embodiments of this application;

[0035] Figure 8 This is a schematic diagram of the first adapter board provided in an embodiment of this application;

[0036] Figure 9a This is a schematic diagram of the pin distribution of the first memory provided in an embodiment of this application;

[0037] Figure 9b This is a schematic diagram of the pin distribution on the first side of the first adapter board provided in the embodiments of this application;

[0038] Figure 9c This is a schematic diagram of the pin distribution of the second mounting area of ​​the printed circuit board provided in the embodiments of this application;

[0039] Figure 10 This is a schematic diagram of the second adapter board provided in an embodiment of this application;

[0040] Figure 11a This is a schematic diagram of the pin distribution of the second memory provided in an embodiment of this application;

[0041] Figure 11b This is a schematic diagram of the pin distribution on the first side of the second adapter board provided in this embodiment of the application;

[0042] Figure 11c This is a schematic diagram of the pin distribution of the third mounting area of ​​the printed circuit board provided in the embodiments of this application;

[0043] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0044] Figure 13 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0046] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0047] For ease of understanding, the following describes some aspects of the embodiments of this application:

[0048] In the design of electronic devices, such as mobile phones or tablets, flash memory and memory chips are frequently used. Different types of chips have different packages and ball maps. For example, the number of chip pins, the pin layout, the chip size, and the pin definitions may differ. For instance, a 254-ball UFS-based multi-chip package (uMCP) integrates UFS 2.2 and Low Power Double Data Rate SDRAM (LPDDR) 4X, as well as a 200-ball discrete LPDDR4X. The two have different numbers of pins, different pin layouts, and different chip sizes. Similarly, a 153-ball discrete UFS and a 153-ball discrete embedded Multimedia Card (eMMC) have the same number of pins and the same pin layout, but the definitions of each pin differ. It should be noted that the specific packaging and ball diagrams of the above-mentioned 254-ball uMCP, 200-ball discrete LPDDR4X, 153-ball discrete UFS and 153-ball discrete eMMC can be found in related technologies, and will not be elaborated on in the embodiments of this application.

[0049] Commonly used memory chips in electronic devices can be categorized by protocol into: RAM (LPDDR4X, LPDDR5, LPDDR5X); and flash memory (eMMC, UFS2.2, UFS3.1, UFS4.0, etc.). They can also be categorized by packaging into: embedded multi-chip packaging (eMCP), uMCP, discrete UFS, discrete eMMC, discrete LPDDR, and packaged on packaging (POP) LPDDR, etc.

[0050] Table 1

[0051]

[0052] In electronic product design, combinations of the material (i.e., memory) types listed in Table 1 may be used. These combinations are characterized by the same memory protocol but different packages. The circuit board design principle for this type of combination is as follows:

[0053] For example, eMCP / uMCP (LPDDR4X) and discrete LPDDR4X, both using the LPDDR4X protocol, have different packages and require the design of two separate printed circuit boards (PCBs). Figures 1a to 1d As shown, or by adding an adapter board to the same PCB board, it is possible to use them in the same electronic product. For example, as shown... Figure 2 As shown. When the paired discrete flash memory eMMC / UFS is of the same type as the flash memory in the integrated storage MCP, a signal switching circuit needs to be added to achieve corresponding signal connections. The commonly used signal switching circuit is a jumper resistor, which is implemented by surface-mounting the corresponding path resistor according to the requirements.

[0054] It should also be noted that when signal lines use a 0Ω resistor common pad design, and corresponding paths are connected via surface mount as needed, or when signal lines are connected in series with stubs, these designs suffer from drawbacks such as degraded signal quality, increased PCB area, poor path consistency, and reduced system reliability and stability, posing risks to long-term product use. Furthermore, when signal switching is achieved through a two-to-one signal switching chip, this type of design is limited by the bandwidth of the switching chip and cannot be applied to high-speed signals of 6GHz or 12GHz. It is also difficult to reduce the insertion loss and channel isolation of the switching chip. Simultaneously, the application of multiple signals increases PCB area and material costs, resulting in low feasibility.

[0055] The printed circuit board, adapter board, and electronic device provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0056] This application provides a printed circuit board, see [link]. Figure 3 , Figure 4a and Figure 4b , Figure 3 This is a side view of a printed circuit board provided in an embodiment of this application. Figure 4a and Figure 4b These are all top views of a printed circuit board provided in the embodiments of this application. It should be noted that... Figure 3 , Figure 4a and Figure 4b The printed circuit board shown is merely an example of the printed circuit board provided in the embodiments of this application and does not constitute a limitation on the printed circuit board provided in the embodiments of this application. Furthermore, in Figure 3 The short vertical lines in the diagram represent signal pins on the printed circuit board. The printed circuit board provided in this embodiment, in addition to... Figure 3 In addition to the signal pins shown, other signal pins may also be included, such as ground signal pins, power supply signal pins, etc. This embodiment does not limit this.

[0057] like Figure 3 , Figure 4a and Figure 4b As shown, the printed circuit board 10 is provided with a first mounting area 101, a second mounting area 102 and a third mounting area 103. The first mounting area 101 is used to mount system-on-a-chip, the second mounting area 102 is used to mount a first memory or a first adapter board, and the third mounting area 103 is used to mount a second memory or a second adapter board.

[0058] The first mounting area 101 is provided with a first type of signal pin 1011 and a second type of signal pin 1012, the second mounting area 102 is provided with a third type of signal pin 1021 and a fourth type of signal pin 1022, and the third mounting area 103 is provided with a fifth type of signal pin 1031 and a sixth type of signal pin 1032;

[0059] The first type of signal pin 1011 is electrically connected to the third type of signal pin 1021 through the first type of signal line 104 in the printed circuit board 10; the second type of signal pin 1012 is electrically connected to the fifth type of signal pin 1031 through the second type of signal line 105 in the printed circuit board 10; and the fourth type of signal pin 1022 is electrically connected to the sixth type of signal pin 1032 through the third type of signal line 106 in the printed circuit board 10.

[0060] Wherein, when the first memory is RAM and the second memory is flash memory, the first type of signal line 104 is used to transmit memory signals and the second type of signal line 105 is used to transmit flash memory signals; when the first memory is flash memory and the second memory is RAM, the first type of signal line 104 is used to transmit flash memory signals and the second type of signal line 105 is used to transmit RAM signals; the third type of signal line 106 is used to transmit flash memory signals or RAM signals, and the first adapter board is used to install the third memory, which is a memory that integrates RAM and flash memory.

[0061] In this embodiment, the first memory and the second memory can also be referred to as separate memory, for example, separate RAM and separate flash memory. Wherein, one of the first memory and the second memory is RAM and the other is flash memory; for example, the first memory is RAM and the second memory is flash memory, or the second memory is RAM and the first memory is flash memory. Exemplarily, the flash memory may include, but is not limited to, UFS 2.2, UFS 3.0, UFS 3.1, UFS 4.0, or eMMC. The RAM may include, but is not limited to, LPDDR 4, LPDDR4X, LPDDR5, or LPDDR5X.

[0062] The first adapter board is used to install the third memory, and the second adapter board is used to electrically connect the fifth type signal pin 1031 and the sixth type signal pin 1032.

[0063] The aforementioned third memory can also be referred to as integrated memory, which integrates flash memory and RAM. For example, the aforementioned first memory may include, but is not limited to, uMCP or eMCP4, such as uMCP4X, uMCP5, eMCP4X, or uMCP5X.

[0064] It should be noted that, when the first memory is RAM and the second memory is flash memory, the protocol type of the RAM in the third memory can be the same as or different from the protocol type of the first memory, and the protocol type of the flash memory in the third memory can be the same as or different from the protocol type of the flash memory in the second memory; when the first memory is flash memory and the second memory is RAM, the protocol type of the RAM in the third memory can be the same as or different from the protocol type of the second memory, and the protocol type of the flash memory in the third memory can be the same as or different from the protocol type of the flash memory in the first memory.

[0065] It should also be noted that the above-mentioned separate memory (i.e., the first memory and the second memory) and integrated memory (i.e., the third memory) can be reasonably configured according to the needs of this embodiment.

[0066] For ease of description, one of the first and second memories will be referred to as separate memory, the other as separate flash memory, and the third memory as integrated memory.

[0067] The following explanations will be provided for different scenarios:

[0068] Scenario 1: The first memory is discrete RAM, and the second memory is discrete flash memory. In this case, the first type of signal pin (i.e., PIN) 1011 is used to input memory signals from the SoC or to output memory signals to the SoC. The first type of signal pin 1011 may include at least one signal pin. The second type of signal pin 1012 is used to input flash memory signals from the SoC or to output flash memory signals to the SoC. The second type of signal pin 1012 may include at least one signal pin.

[0069] The aforementioned third-type signal pin 1021 is used to input memory signals from integrated memory or discrete memory, or to output memory signals to integrated memory or discrete memory. This third-type signal pin 1021 may include at least one signal pin. The aforementioned fifth-type signal pin 1031 is used to input flash memory signals from integrated memory or discrete flash memory, or to output flash memory signals to integrated memory or discrete flash memory. This fifth-type signal pin 1031 may include at least one signal pin.

[0070] The aforementioned fourth type signal pin 1022 is used to input flash memory signals from the integrated memory or to output flash memory signals to the integrated memory. The aforementioned fourth type signal pin 1022 may include at least one signal pin. The aforementioned sixth type signal pin 1032 is used to input flash memory signals from the fifth type signal pin 1031 or to output flash memory signals to the fifth type signal pin 1031.

[0071] Scenario 2: The first memory is a discrete flash memory, and the second memory is a discrete RAM. In this case, the aforementioned first type of signal pin (i.e., PIN) 1011 is used to input flash memory signals from the SoC or to output flash memory signals to the SoC. The first type of signal pin 1011 may include at least one signal pin. The aforementioned second type of signal pin 1012 is used to input memory signals from the SoC or to output memory signals to the SoC. The second type of signal pin 1012 may include at least one signal pin.

[0072] The aforementioned third-type signal pin 1021 is used to input flash memory signals from integrated memory or discrete flash memory, or to output flash memory signals to integrated memory or discrete flash memory. The third-type signal pin 1021 may include at least one signal pin. The aforementioned fifth-type signal pin 1031 is used to input memory signals from integrated memory or discrete memory, or to output memory signals to integrated memory or discrete memory. The fifth-type signal pin 1031 may include at least one signal pin.

[0073] The aforementioned fourth type signal pin 1022 is used to input memory signals from the integrated memory or to output memory signals to the integrated memory. The aforementioned fourth type signal pin 1022 may include at least one signal pin. The aforementioned sixth type signal pin 1032 is used to input memory signals from the fifth type signal pin 1031 or to output memory signals to the fifth type signal pin 1031.

[0074] It should be noted that when the first memory is installed in the second mounting area and the second memory is installed in the third mounting area, the fourth type signal pin 1022 and the sixth type signal pin 1032 are left floating. There is no electrical connection between the fourth type signal pin 1022 and the first memory, and there is no electrical connection between the sixth type signal pin 1032 and the second memory. When the first adapter board is installed in the second mounting area and the second adapter board is installed in the third mounting area, the fourth type signal pin 1022 is electrically connected to the third memory via the first adapter board, and the sixth type signal pin 1032 is electrically connected to the fifth type signal pin 1031 via the second adapter board.

[0075] Taking the fourth type signal pin 1022 and the sixth type signal pin 1032 as examples of flash memory signal pins, the fourth type signal pin 1022 and the sixth type signal pin 1032 can include pins of various signals required for flash memory operation. For example, taking UFS as an example, the fourth type signal pin 1022 and the sixth type signal pin 1032 can include, but are not limited to, signal pins such as DIN0_t, DIN0_c, DIN1_t, DIN1_c, DOUT0_t, DOUT0_c, DOUT1_t, DOUT1_c, REF_CLK, RST_n, VCC, VCCQ2, VDDIQ2, VSS, and VSF. For example, the meanings of the above signal pins can be shown in Table 2.

[0076] Table 2

[0077]

[0078] The substrate material, number of layers, order, dielectric constant, etc., of the aforementioned printed circuit board can be reasonably set according to requirements. For example, the substrate material of the aforementioned printed circuit board can be FR-4 substrate, the number of layers can be greater than or equal to 8, and the order of the aforementioned printed circuit board can be greater than or equal to 2. In addition, the design of the signal lines within the aforementioned printed circuit board can be adjusted according to signal simulation, such as line width, line spacing, ground isolation, layer spacing, and the size and position of vias, to meet the signal quality requirements at high flash memory signal speeds. For example, for UFS, its speed can reach 3GHz, 6GHz, 12GHz, etc., and for eMMC, its speed can reach 200MHz.

[0079] It should be noted that a higher order of printed circuit board (PCB) makes it easier to achieve design requirements, but also increases the cost. In some alternative embodiments, the PCB can be the motherboard of an electronic device.

[0080] The signal traces on the aforementioned printed circuit board meet the design requirements for their respective signals. These design requirements may include, but are not limited to, eye diagram, insertion loss, return loss, and impedance requirements. Taking a discrete flash memory as an example, the design of the second type of signal lines on the aforementioned printed circuit board meets the signal design requirements for discrete flash memory. For example, ... Figure 5a The design of the black signal lines shown meets the signal design requirements of discrete flash memory; the combined design of the second type signal lines of the printed circuit board, the sixth type signal lines of the second adapter board, the third type signal lines of the printed circuit board, and the fifth type signal lines of the first adapter board meets the signal design requirements of integrated memory flash memory, for example, as... Figure 5b The combination of black, yellow, and purple signal lines shown meets the signal design requirements of flash memory in integrated memory.

[0081] The aforementioned SoC, first memory, second memory, first adapter board, and second adapter board can be mounted on the aforementioned printed circuit board via surface mounting or via plug-in connection, etc., and this embodiment does not limit this.

[0082] The following examples, with reference to the accompanying drawings, illustrate the application of the printed circuit board provided in the embodiments of this application:

[0083] When choosing to mount separate memories (i.e., the first memory and the second memory) on the aforementioned printed circuit board 10, for example, as Figure 5aAs shown, the discrete memory (i.e., the first memory) 30 is mounted in the second mounting area 102 of the printed circuit board 10, and the discrete flash memory (i.e., the second memory) 40 is mounted in the third mounting area 103 of the printed circuit board 10. The red signal line (i.e., the first type of signal line) 104 represents the signal trace of the memory, the black signal line (i.e., the second type of signal line) 105 represents the signal trace of the flash memory, and the purple signal line (i.e., the third type of signal line) 106 represents the reserved signal line for connecting the flash memory signal pins; currently, there is no connection. It should be noted that in... Figure 5a In this context, the gray pin ball indicates that the discrete memory is either absent or not used by the discrete memory. In other words, the pads of the corresponding signal pins (i.e., the fourth and sixth type signal pins) are not soldered or are not used by the discrete memory. Consequently, there is no electrical connection between the signal pin and the discrete memory. Thus, the signal traces reserved for the integrated memory flash memory will not affect the signals of the discrete memory.

[0084] When choosing to mount an integrated memory on the aforementioned printed circuit board 10, for example, as Figure 5b As shown, a first adapter board 50 is mounted on the second mounting area 102 of the printed circuit board 10, and a second adapter board 60 is mounted on the third mounting area 103 of the printed circuit board 10. An integrated memory (i.e., a third memory) 70 is mounted on the first adapter board 50. Red signal lines (i.e., first-type signal lines) 104 and cyan signal lines (i.e., fourth-type signal lines) 503 represent memory signal traces, while black signal lines (i.e., second-type signal lines) 105, yellow signal lines (i.e., fifth-type signal lines 504 and sixth-type signal lines 602), and purple signal lines (i.e., third-type signal lines 106) represent flash memory signal traces. In this configuration, the sixth-type signal pin 1032 of the third mounting area 103 is electrically connected to the fifth-type signal pin 1031 via the signal lines (i.e., sixth-type signal lines 602) of the second adapter board 60, thereby enabling the flash memory of the integrated memory to conduct.

[0085] Specifically, regarding the connection path between the signal pins of the SoC and the corresponding signal pins of the integrated memory's flash memory, taking the signal from the SoC to the integrated memory's flash memory as an example, the flash memory signal ball on the SoC chip connects to the orange ball (i.e., the flash memory signal pin ball) on the second adapter board via the black signal line on the aforementioned printed circuit board. Inside the second adapter board, it connects to a purple ball (i.e., a newly added or redefined flash memory signal pin ball) via a yellow signal line. This purple ball is soldered to the aforementioned printed circuit board and then connects to another purple ball via a purple signal line, entering the first adapter board. Finally, it connects to the corresponding signal pin of the integrated memory's flash memory via a yellow signal line. The transmission path from the integrated memory's flash memory to the SoC is the reverse of the above path.

[0086] Regarding the connection path between the signal pins of the SoC and the corresponding signal pins of the integrated memory, taking the signal from the SoC to the integrated memory as an example, the memory signal ball on the SoC chip connects to the orange ball of the first adapter board via the red signal line on the printed circuit board, and then enters the first adapter board. Inside the first adapter board, it connects to the corresponding signal pin of the integrated memory via the cyan signal line. The transmission path of the signal from the integrated memory to the SoC is the reverse of the above path.

[0087] As can be seen from the above, the printed circuit board provided in this embodiment supports the installation of different types of memory, which helps to reduce the design and development costs of electronic products, increase the flexibility of material supply for electronic product production, and meet the needs of storage capacity expansion and performance differentiation.

[0088] In this embodiment, the printed circuit board (PCB) is provided with a first mounting area, a second mounting area, and a third mounting area. The first mounting area is used to mount a system-on-a-chip (SoC), the second mounting area is used to mount a first memory or a first adapter board, and the third mounting area is used to mount a second memory or a second adapter board. Therefore, discrete memories (i.e., the first and second memories) can be directly mounted on this PCB, or integrated memories (i.e., the third memory) can be mounted through the first and second adapter boards. This means the PCB supports mounting different types of memories, which helps reduce the development cost of electronic products and increases the flexibility of memory selection. Furthermore, when the first and second memories are mounted on this PCB, the signal traces reserved for the third memory (i.e., the signal lines between the fourth and sixth type signal pins) are floating and not connected to the signal lines of the first and second memories. This avoids the signal traces reserved for the third memory from affecting the signals of the first and second memories.

[0089] Optionally, when the first memory is RAM and the second memory is flash memory, the protocol type of the RAM integrated in the third memory is the same as the protocol type of the first memory, and the protocol type of the flash memory integrated in the third memory is the same as the protocol type of the second memory.

[0090] or,

[0091] When the first memory is flash memory and the second memory is RAM, the protocol type of the RAM integrated in the third memory is the same as the protocol type of the second memory, and the protocol type of the flash memory integrated in the third memory is the same as the protocol type of the first memory.

[0092] In this embodiment, the protocol type of the integrated memory is the same as that of the discrete memory, and the protocol type of the integrated memory flash memory is the same as that of the discrete flash memory. The protocol type may include the Joint Electron Device Engineering Council (JEDEC) protocol type.

[0093] For example, the combination of the above-described integrated memory and discrete memory may include any of the following:

[0094] Combination 1: Integrated memory is uMCP (UFS2.2 or UFS2.1 + LPDDR4X or LPDDR4), discrete memory is LPDDR4X or LPDDR4, and discrete flash memory is UFS2.1 or UFS2.2;

[0095] Combination 2: Integrated memory is uMCP (UFS3.1 or UFS3.0 + LPDDR5 or LPDDR5X), discrete memory is LPDDR5 or LPDDR5X, and discrete flash memory is UFS3.0 or UFS3.1;

[0096] Combination 3: Integrated memory is uMCP (UFS4.0 or UFS4.1 + LPDDR5 or LPDDR5X), discrete memory is LPDDR5 or LPDDR5X, and discrete flash memory is UFS4.0 or UFS4.1;

[0097] Combination 4: Integrated memory is eMCP (eMMC5.x + LPDDR4X or LPDDR4), discrete memory is LPDDR4X or LPDDR4, and discrete flash memory is eMMC5.x;

[0098] Combination 5: Integrated memory is eMCP (eMMC4.x + LPDDR3), discrete memory is LPDDR3, and discrete flash memory is eMMC4.x.

[0099] In this embodiment, by setting the protocol type of the integrated memory to be the same as that of the discrete memory, and the protocol type of the flash memory to be the same as that of the discrete flash memory, the integrated memory and the discrete memory can directly share the same signal pins on the printed circuit board, thereby simplifying the signal routing of the printed circuit board.

[0100] In some optional embodiments, the protocol type of the integrated memory may be different from that of the discrete memory, and the protocol type of the flash memory of the integrated memory may also be different from that of the discrete flash memory. In this case, the SoC can perform protocol conversion on the memory signals or flash memory signals. For example, when memory of the first protocol type is installed on the printed circuit board, the SoC inputs the memory signal of the first protocol type to the first type of signal pin of the printed circuit board; when memory of the second protocol type is installed on the printed circuit board, the SoC inputs the memory signal of the second protocol type to the first type of signal pin of the printed circuit board; similarly, when flash memory of the third protocol type is installed on the printed circuit board, the SoC inputs the flash memory signal of the third protocol type to the second type of signal pin of the printed circuit board; and when flash memory of the fourth protocol type is installed on the printed circuit board, the SoC inputs the flash memory signal of the fourth protocol type to the second type of signal pin of the printed circuit board. In this way, the integrated memory and the discrete memory can directly share the same signal pins on the printed circuit board, thereby simplifying the signal routing of the printed circuit board.

[0101] Optionally, the first mounting area 101, the second mounting area 102, and the third mounting area 103 are all disposed on the same side of the printed circuit board 10;

[0102] or,

[0103] The first mounting area 101 and the second mounting area 102 are both disposed on the first side of the printed circuit board 10, and the third mounting area 103 is disposed on the second side of the printed circuit board 10. The first side and the second side are two opposite sides.

[0104] In one embodiment, the first mounting area 101, the second mounting area 102, and the third mounting area 103 are all disposed on the same side of the printed circuit board, for example, as shown in the figure. Figure 5a and Figure 5b As shown, the first mounting area 101, the second mounting area 102 and the third mounting area 103 are all located on the top surface of the printed circuit board, which helps to shorten signal traces.

[0105] In another embodiment, the first mounting region 101, the second mounting region 102, and the third mounting region 103 are all disposed on two opposite surfaces of the printed circuit board, for example, as shown in the figure. Figure 6a and Figure 6b As shown, the first mounting area 101 and the second mounting area 102 are disposed on the top surface of the printed circuit board, and the third mounting area 103 is disposed on the bottom surface of the printed circuit board. This helps to avoid the memory being concentrated on the same side of the printed circuit board, thereby helping to reduce the size of the printed circuit board.

[0106] It should also be noted that, with the same signal trace length, the signal quality is better when the third mounting area 103 is located on the top surface of the printed circuit board than when it is located on the bottom surface of the printed circuit board.

[0107] In some alternative embodiments, the third mounting area 103 can be located on the second surface opposite to the fourth type of signal pin, which helps to shorten the signal trace length between the fourth type of signal pin and the sixth type of signal pin.

[0108] Optionally, the first mounting area 101 and the second mounting area 102 satisfy at least one of the following:

[0109] The second mounting area 102 is located on the first side of the first mounting area 101, and the first side is the side of the first mounting area 101 that is closest to the first type of signal pin 1011.

[0110] The distance between the first installation area 101 and the second installation area 102 is less than or equal to a first threshold.

[0111] The first threshold can be set reasonably according to actual needs. For example, the first threshold can be 1mm or 1.5mm.

[0112] In some alternative embodiments, the edges of the first mounting area 101 and the second mounting area 102 are parallel. For example, the vertical edges of the first mounting area 101 and the vertical edges of the second mounting area 102 are parallel, or the horizontal edges of the first mounting area 101 and the horizontal edges of the second mounting area 102 are parallel.

[0113] It is understandable that the relative positions of the first mounting area and the second mounting area can be determined based on the distribution of various signal pins in the first mounting area 101 and the corresponding distribution of various signal pins in the second mounting area 102.

[0114] In some optional embodiments, the lower edge of the first mounting area 101 in the horizontal direction may be aligned with the lower edge of the second mounting area 102 in the horizontal direction; or, the upper edge of the first mounting area 101 in the horizontal direction may be aligned with the upper edge of the second mounting area 102 in the horizontal direction; or, the center point of the first mounting area 101 and the center point of the second mounting area 102 may be located on the same horizontal line.

[0115] For example, such as Figure 7 As shown, when the first type of signal pin 1011 is located to the right of the first mounting area 101, the second mounting area 102 is located to the right of the first mounting area 101. The edge of the second mounting area 102 is parallel to that of the first mounting area 101, and the center point of the second mounting area 102 is on the same horizontal line as the center point of the first mounting area 101. This layout helps to shorten the signal traces between the first mounting area 101 and the second mounting area 102, thereby helping to ensure signal quality.

[0116] Optionally, the third mounting region 103 and the second mounting region 102 satisfy at least one of the following:

[0117] The third mounting area 103 is located on the second side of the second mounting area 102, and the second side is the side of the second mounting area 102 that is closest to the fourth type of signal pin 1022.

[0118] The distance between the third installation area 103 and the second installation area 102 is less than or equal to the second threshold.

[0119] The second threshold can be set reasonably according to actual needs. For example, the second threshold can be 1mm or 1.5mm.

[0120] In some alternative embodiments, the edge of the third mounting region 103 and the edge of the second mounting region 102 are parallel. For example, the vertical edge of the third mounting region 103 and the vertical edge of the second mounting region 102 are parallel, or the horizontal edge of the third mounting region 103 and the horizontal edge of the second mounting region 102 are parallel.

[0121] It is understandable that the relative positions of the third mounting area and the second mounting area can be determined based on the distribution of various signal pins in the third mounting area 103 and the corresponding distribution of various signal pins in the second mounting area 102.

[0122] In some optional embodiments, the lower edge of the third mounting area 103 in the horizontal direction may be aligned with the lower edge of the second mounting area 102 in the horizontal direction, or the upper edge of the third mounting area 103 in the horizontal direction may be aligned with the upper edge of the second mounting area 102 in the horizontal direction, or the center point of the third mounting area 103 and the center point of the second mounting area 102 may be located on the same vertical line.

[0123] For example, such as Figure 7 As shown, when the fourth type of signal pin 1022 is located below the second mounting area 102, the third mounting area 103 is located below the second mounting area 102, i.e., at position 1. The edge of the third mounting area 103 is parallel to the edge of the second mounting area 102. This layout helps to shorten the signal traces between the third mounting area 103 and the second mounting area 102, thereby helping to ensure signal quality. It should be noted that for positions 1 to 4 located on the same surface, the signal quality is worse the farther away from position 1. For example, the signal quality ranking at each position can be: position 1 is better than position 2, position 2 is better than position 3, and position 3 is better than position 4.

[0124] In some alternative embodiments, the fifth type signal pin 1031 of the third mounting area 103 can be positioned as close as possible to the second type signal pin 1012 of the first mounting area 101 to shorten the signal traces between the first mounting area 101 and the third mounting area 103.

[0125] Optionally, the first memory is RAM and the second memory is flash memory.

[0126] In this embodiment, the discrete memory is installed in the second installation area, that is, the discrete memory is close to the SoC setup, and the discrete flash memory is installed in the third installation area, for example, as shown below. Figure 5a As shown, this layout helps reduce the length of memory signal traces. Since memory signal traces are often shorter than flash memory signal traces, this layout helps to ensure the signal quality of both memory and flash memory simultaneously.

[0127] It should also be noted that the embodiments of this application... Figure 5a , Figure 5b , Figure 6a and Figure 6b The colored portions shown are only for distinguishing different types of devices, different types of signal lines, and different types of signal pin balls, and do not constitute a limitation on the printed circuit board provided in the embodiments of this application. Furthermore, the above... Figure 5a , Figure 5b , Figure 6a and Figure 6bThe small spheres shown represent the solder balls corresponding to the signal pins.

[0128] This application embodiment also provides a first adapter board. Figure 8 This is a side view of a first adapter plate provided in an embodiment of this application. It should be noted that... Figure 8 The first adapter board shown is merely an example of the first adapter board provided in the embodiments of this application and does not constitute a limitation on the first adapter board provided in the embodiments of this application. Furthermore, in Figure 8 The short vertical lines in the diagram represent signal pins on the first adapter board. The first adapter board provided in this embodiment, in addition to... Figure 8 In addition to the signal pins shown, other signal pins may also be included, such as ground signal pins, power supply signal pins, etc. This embodiment does not limit this.

[0129] See Figure 8 The first adapter board 50 provided in this application embodiment has a first surface 501 provided with a seventh type signal pin 5011 and an eighth type signal pin 5012, and a second surface 502 provided with a fourth mounting area 5021. The fourth mounting area 5021 is used to mount a third memory, and the fourth mounting area 5021 is provided with a ninth type signal pin 5022 and a tenth type signal pin 5023.

[0130] The seventh type signal pin 5011 is electrically connected to the ninth type signal pin 5022 through the fourth type signal line 503 in the first adapter board 50, and the eighth type signal pin 5012 is electrically connected to the tenth type signal pin 5023 through the fifth type signal line 504 in the first adapter board 50.

[0131] The first side 501 of the first adapter board 50 is the side for mounting the first adapter board 50 to the printed circuit board. The second side 502 of the first adapter board 50 is opposite to the first side 501 of the first adapter board 50. One of the fourth type signal line 503 and the fifth type signal line 504 is used to transmit memory signals, and the other is used to transmit flash memory signals. The third memory is a memory that integrates flash memory and memory.

[0132] The printed circuit board and the first memory involved in this embodiment can be found in the relevant descriptions of the aforementioned printed circuit board embodiment, and will not be repeated here.

[0133] Specifically, the seventh type signal pin 5011 is used to electrically connect to the third type signal pin of the printed circuit board, and the eighth type signal pin 5012 is used to electrically connect to the fourth type signal pin of the printed circuit board.

[0134] Specifically, the seventh type signal pin 5011 is used to electrically connect with the third type signal pin of the printed circuit board, and the eighth type signal pin 5012 is used to electrically connect with the fourth type signal pin of the printed circuit board. For example, when the first adapter board is installed on the printed circuit board, the seventh type signal pin 5011 is soldered to the third type signal pin of the printed circuit board, and the eighth type signal pin 5012 is soldered to the fourth type signal pin of the printed circuit board.

[0135] It should be noted that when the aforementioned seventh-type signal pin 5011 is soldered together with the third-type signal pin of the printed circuit board, the connection between the aforementioned seventh-type signal pin 5011 and the third-type signal pin of the printed circuit board can be illustrated as follows: Figure 5b The orange ball shown; when the aforementioned eighth-type signal pin 5012 is soldered together with the fourth-type signal pin of the printed circuit board, the aforementioned eighth-type signal pin 5012 and the fourth-type signal pin of the printed circuit board can be schematically represented as follows: Figure 5b The purple ball shown.

[0136] The material, number of layers, number of orders, and dielectric constant of the first adapter board can be reasonably set according to requirements. For example, the material of the first adapter board can be FR-4, and it can be a material with a medium glass transition temperature (Tg) or a high Tg. The number of layers of the first adapter board can be greater than or equal to 6, and the number of orders can be greater than or equal to 2, or it can be any order. It should be noted that when the first adapter board is 6 layers of any order, the design difficulty is lower, the PCB area is smaller, and the overall cost is optimal.

[0137] The dimensions of the aforementioned first adapter board can also be reasonably set according to requirements. For example, the dimensions of the first adapter board can be the same as the larger of the dimensions of the first memory and the third memory, or each side of the first memory and the third memory can be larger than a preset length, for example, 0.2mm, which facilitates the application of fixing glue and the cutting of the board during the fabrication of the first adapter board. For the solder on the first side of the aforementioned first adapter board, pre-plating of solder can be performed, which facilitates soldering and the application of fixing glue. Optionally, a stencil can be used to brush solder through a reflow oven to achieve the preset solder height; or a solder ball can be used to achieve the solder plating.

[0138] Furthermore, the design of the signal lines within the aforementioned first adapter board can be adjusted based on signal simulation to include line width, line spacing, ground isolation, layer spacing, and the size and location of vias, in order to meet the signal quality requirements at high flash memory signal speeds. For example, for UFS, the speed can reach 3GHz, 6GHz, 12GHz, etc., and for eMMC, the speed can reach 500MHz.

[0139] It is understood that the signal pins on the first side of the first adapter board correspond to the signal pins on the second mounting area of ​​the printed circuit board, and the signal pins on the second side of the first adapter board correspond to the signal pins on the third memory.

[0140] Specifically, when the first adapter board is mounted in the second mounting area of ​​the printed circuit board, the seventh type signal pin is electrically connected to the third type signal pin of the printed circuit board, and the eighth type signal pin is electrically connected to the fourth type signal pin of the printed circuit board. When the fifth type signal pin and the sixth type signal pin on the printed circuit board are electrically connected through the second adapter board mounted in the third mounting area of ​​the printed circuit board, communication between the SoC and the integrated memory can be realized.

[0141] As can be seen from the above, based on the first adapter board provided in this embodiment, the integrated memory can be installed on the printed circuit board without the traces reserved for the integrated memory on the printed circuit board affecting the signal of the discrete memory.

[0142] Optionally, the eighth type signal pin 5012 of the first surface 501 of the first adapter board 50 is correspondingly set with the fourth type signal pin of the printed circuit board, and the arrangement of the target pins of the first surface 501 of the first adapter board 50 is the same as the arrangement of the pins of the first surface of the first memory.

[0143] Wherein, the target pin of the first surface 501 of the first adapter board 50 is the pin portion of the first surface 501 of the first adapter board 50 that is the same as the pin of the first surface of the first memory, and the first surface of the first memory is the surface used to mount the first memory to the printed circuit board.

[0144] It is understood that, since the second mounting area of ​​the aforementioned printed circuit board is compatible with mounting the first memory and the first adapter board, the first side of the aforementioned first adapter board may include pins identical to those on the first side of the first memory. Furthermore, the first side of the aforementioned first adapter board also includes additional pins, namely the aforementioned eighth-type signal pin 5012, which corresponds to the fourth-type signal pins of the printed circuit board. It should also be noted that the pin arrangement of the second mounting area of ​​the aforementioned printed circuit board may be a mirror image of the pin arrangement of the first side of the aforementioned first adapter board.

[0145] For example, taking a 200-ball discrete LPDDR4X memory as an example, the pin distribution diagram of the first memory can be as follows: Figure 9a As shown in the diagram, the pin distribution on the first side of the first adapter board can be illustrated as follows: Figure 9bAs shown, a schematic diagram of the pin distribution in the second mounting area of ​​the printed circuit board can be obtained as follows: Figure 9c As shown, the pin distribution on the first side of the first adapter board, compared to the pin distribution of the first memory, adds an eighth type signal pin 5012, and the pin distribution on the first side of the first adapter board is a mirror image of the pin distribution of the second mounting area of ​​the printed circuit board.

[0146] In this embodiment, the target pin arrangement on the first side of the first adapter board is the same as the pin arrangement on the first side of the first memory, and the eighth type signal pin on the first side of the first adapter board corresponds to the fourth type signal pin on the printed circuit board. This makes it convenient to install the first adapter board and the first memory on the same location on the printed circuit board.

[0147] In some alternative embodiments, the aforementioned eighth type signal pins may be configured to correspond to reserved pins or undefined pins in the first memory. In this case, the pin arrangement on the first side of the first adapter board may be exactly the same as the pin arrangement on the first side of the first memory.

[0148] This application also provides a second adapter board. Figure 10 This is a side view of a second adapter plate provided in an embodiment of this application. It should be noted that... Figure 10 The second adapter board shown is merely an example of the second adapter board provided in the embodiments of this application and does not constitute a limitation on the second adapter board provided in the embodiments of this application. Furthermore, in Figure 10 The short vertical lines in the diagram represent signal pins on the second adapter board. The second adapter board provided in this embodiment, in addition to... Figure 10 In addition to the signal pins shown, other signal pins may also be included, such as ground signal pins, power supply signal pins, etc. This embodiment does not limit this.

[0149] See Figure 10 The first surface 601 of the second adapter board 60 provided in this application embodiment is provided with an eleventh type signal pin 6011 and a twelfth type signal pin 6012. The eleventh type signal pin 6011 is electrically connected to the twelfth type signal pin 6012 through a sixth type signal line 602 in the second adapter board 60.

[0150] The first surface 601 of the second adapter board 60 is used to mount the second adapter board 60 to a printed circuit board, and the sixth type signal line 602 is used to transmit memory signals or flash memory signals.

[0151] The printed circuit board and second memory involved in this embodiment can be found in the relevant description of the aforementioned printed circuit board embodiment, and will not be repeated here.

[0152] Specifically, the eleventh type signal pin 6011 is used to electrically connect to the fifth type signal pin of the printed circuit board, and the twelfth type signal pin 6012 is used to electrically connect to the sixth type signal pin of the printed circuit board.

[0153] Specifically, the eleventh type signal pin 6011 is used to electrically connect with the fifth type signal pin of the printed circuit board, and the twelfth type signal pin 6012 is used to electrically connect with the sixth type signal pin of the printed circuit board. For example, when the second adapter board is installed in the third mounting area of ​​the printed circuit board, the eleventh type signal pin 6011 is soldered together with the fifth type signal pin of the printed circuit board, and the twelfth type signal pin 6012 is soldered together with the sixth type signal pin of the printed circuit board.

[0154] It should be noted that when the aforementioned eleventh-type signal pin 6011 is soldered together with the fifth-type signal pin of the printed circuit board, the connection between the aforementioned eleventh-type signal pin 6011 and the fifth-type signal pin of the printed circuit board can be illustrated as follows: Figure 5b The orange ball shown; when the aforementioned twelfth type signal pin 6012 is soldered together with the sixth type signal pin of the printed circuit board, the aforementioned twelfth type signal pin 6012 and the sixth type signal pin of the printed circuit board can be schematically represented as follows: Figure 5b The purple ball shown.

[0155] For the sixth type of signal line mentioned above, when the second memory is flash memory, the sixth type of signal line is used to transmit flash memory signals; when the second memory is RAM, the sixth type of signal line is used to transmit RAM signals.

[0156] The material, number of layers, number of orders, and dielectric constant of the aforementioned second adapter board can be reasonably set according to requirements. For example, the material of the second adapter board can be FR-4, and it can be a material with a medium glass transition temperature (Tg) or a high Tg. The number of layers of the second adapter board can be greater than or equal to 6, and the number of orders can be greater than or equal to 2, or it can be any order. It should be noted that when the second adapter board is 6 layers of any order, the design difficulty is lower, the PCB area is smaller, and the overall cost is optimal.

[0157] The dimensions of the aforementioned second adapter board can also be reasonably set according to requirements. For example, the dimensions of the second adapter board can be the same as the dimensions of the second memory, or it can be a preset length larger than each side of the second memory, for example, 0.2mm. This facilitates the application of fixing adhesive and the separation and cutting of the second adapter board during manufacturing. For the solder on the first side of the aforementioned second adapter board, pre-plating of solder can be performed, which facilitates soldering and the application of fixing adhesive. Optionally, a stencil can be used to brush solder through a reflow oven to achieve the preset solder height; or solder balls can be used to achieve solder plating.

[0158] Furthermore, the design of the signal lines within the aforementioned second adapter board can be adjusted based on signal simulation to include line width, line spacing, ground isolation, layer spacing, and the size and location of vias, in order to meet the signal quality requirements at high flash memory signal speeds. For example, for UFS, the speed can reach 3GHz, 6GHz, 12GHz, etc., and for eMMC, the speed can reach 500MHz.

[0159] It is understood that the signal pins on the first side of the second adapter board are configured to correspond to the signal pins on the third mounting area of ​​the printed circuit board.

[0160] Specifically, when the second adapter board is mounted in the third mounting area of ​​the printed circuit board, the eleventh type signal pin is electrically connected to the fifth type signal pin of the printed circuit board, and the twelfth type signal pin is electrically connected to the sixth type signal pin of the printed circuit board. This enables the fifth type signal pin and the sixth type signal pin on the printed circuit board to be electrically connected, so that the SOC can communicate with the integrated memory via the first adapter board.

[0161] Optionally, the twelfth type signal pin 6012 of the first surface 601 of the second adapter board 60 is correspondingly set with the sixth type signal pin of the printed circuit board, and the pin arrangement of the first surface 601 of the second adapter board 60 is the same as the pin arrangement of the first surface of the second memory; or, the arrangement of the target pins of the first surface 601 of the second adapter board 60 is the same as the pin arrangement of the first surface of the second memory.

[0162] Wherein, the target pin of the first surface 601 of the second adapter board 60 is the pin portion of the first surface 601 of the second adapter board 60 that is the same as the pin of the first surface 601 of the second memory, and the first surface 601 of the second memory is the surface for mounting the second memory to the printed circuit board.

[0163] It is understood that, since the third mounting area of ​​the aforementioned printed circuit board is compatible with mounting the second memory and the second adapter board, the first side of the aforementioned second adapter board may include pins identical to those on the first side of the second memory. Specifically, when the aforementioned twelfth type signal pin corresponds to a reserved pin or an undefined pin of the second memory, the pin arrangement of the first side of the aforementioned second adapter board may be the same as the pin arrangement of the first side of the aforementioned second memory; when the aforementioned twelfth type signal pin is a newly added pin, the target pin arrangement of the first side of the aforementioned second adapter board may be the same as the pin arrangement of the first side of the aforementioned second memory. Furthermore, the aforementioned twelfth type signal pin corresponds to the sixth type signal pin of the printed circuit board. It should also be noted that the pin arrangement of the third mounting area of ​​the aforementioned printed circuit board may be a mirror image of the pin arrangement of the first side of the aforementioned second adapter board.

[0164] For example, taking a 153-ball discrete UFS as the second memory, the pin distribution diagram of the second memory can be as follows: Figure 11a As shown, orange ball401 represents a reserved or undefined pin. A schematic diagram of the pin distribution on the first side of the second adapter board described above can be seen as follows: Figure 11b As shown, the ball outlined in yellow represents the Class 12 signal pin 6012. A schematic diagram of the pin distribution in the third mounting area of ​​the printed circuit board is shown below. Figure 11c As shown, the ball outlined in yellow represents the sixth type signal pin 1032. Therefore, it can be seen that the pin distribution on the first side of the second adapter board is the same as the pin distribution of the second memory, and the pin distribution on the first side of the second adapter board is a mirror image of the pin distribution of the second mounting area of ​​the printed circuit board.

[0165] In this embodiment, the pin arrangement of the first side of the second adapter board is the same as the pin arrangement of the first side of the second memory, or the target pin arrangement of the first side of the second adapter board is the same as the pin arrangement of the first side of the second memory, and the twelfth type signal pin of the first side of the second adapter board is correspondingly set with the sixth type signal pin of the printed circuit board. This makes it convenient to install the second adapter board and the second memory in the same position on the printed circuit board.

[0166] It should be noted that the first and second adapter boards mentioned above can be made of suitable PCB materials, stack-up, dielectric constant, etc. The design of the signal lines in the PCB can be adjusted according to signal simulation, such as line width, line spacing, ground isolation, layer spacing, hole size and position, etc., to achieve the signal quality requirements of UFS signal high speed (such as 3GHz, 6GHz, 12GHz).

[0167] The design of the printed circuit board, the first adapter board, and the second adapter board according to embodiments of this application will be described below with reference to examples:

[0168] For the routing of flash memory signals within the aforementioned printed circuit boards, first adapter board, and second adapter board, taking UFS flash memory as an example, according to the signal quality requirements of the current highest speed UFS 4.0 devices (12GHz), the total length of the signal lines should be as uniform as possible with minimal variation. For example, the maximum length within a differential pair should be 0.1mm, and the maximum length between differential pairs should be 3mm. The impedance design is 80Ω~100Ω for differential and 40Ω~50Ω for single-ended. The shorter the total length of the signal lines and the lower the insertion loss, the better, at least meeting the UFS standard protocol requirements. The spacing between UFS signal lines and other signal lines should be greater than or equal to the target value, where the target value can be the minimum of twice the signal line width and three times the PCB layer height. The aforementioned other signal lines can include transmit signal lines (TX) and receive signal lines (RX), etc. UFS signal lines should be preferentially grounded to ensure that crosstalk meets the requirements of SoC manufacturers and memory manufacturers. When routing and drilling holes in the PCB design, there should be accompanying ground vias reaching the same layer. The above design can ensure that insertion loss, return loss, crosstalk, impedance, etc. meet the requirements of SoC and memory devices, and ultimately guarantee that the signal eye diagram quality meets the standards.

[0169] UFS devices use differential serial signals for their data signals, typically with two lanes and four signal lines per lane (two for TX and two for RX). The signal quality requirements for UFS vary depending on the signal rate. eMMC uses single-ended parallel signals for its data signals, typically with eight lines. The signal rate is lower than UFS, with a maximum of 200MHz, and the corresponding signal quality requirements also differ from UFS. Separate LPDDR devices have a wider variety of signal types and a greater number of signals, including both differential serial and single-ended parallel signals. LPDDR4X has a maximum speed of 2133MHz, while LPDDR5X has a maximum speed of 4266MHz or higher, and the corresponding signal quality requirements also differ.

[0170] For the memory signal traces within the aforementioned printed circuit board, first adapter board, and second adapter board, taking LPDDR memory as an example, the design requirements vary depending on the LPDDR type. The basic principle is to ensure that the total length of the signal lines is as similar as possible with minimal differences. The impedance design is 80Ω~100Ω for differential and 40Ω~50Ω for single-ended. The shorter the total length of the signal lines, the lower the insertion loss. LPDDR signal lines of the same type should maintain a spacing of more than one line width, and signal lines of different types should be grounded, maintaining a spacing of more than one line width between them to ensure that crosstalk meets the requirements of SoC manufacturers and memory manufacturers. When routing and drilling traces on the PCB, there should be accompanying ground vias reaching the same layer. Through the above design, the insertion loss, return loss, crosstalk, and impedance can meet the requirements of SOC and memory devices, ultimately ensuring that the signal eye diagram quality meets the standards.

[0171] In summary, this embodiment can achieve high signal quality requirements for multiple high-speed signals with a rate of at least 12GHz by selecting the substrate material, layering design, signal line design, and via design, while also making the area occupied by the printed circuit board relatively small.

[0172] This application also provides an electronic device. Figure 12 This is a schematic diagram of an electronic device provided in an embodiment of this application. See also... Figure 12 The electronic device 1 includes a printed circuit board 10, a system-on-a-chip 20, a first memory 30, and a second memory 40 provided in any of the above embodiments;

[0173] The system-on-a-chip 20 is mounted on the first mounting area 101 of the printed circuit board 10. The thirteenth type signal pin 2011 of the system-on-a-chip 20 is electrically connected to the first type signal pin 1011 of the first mounting area 101, and the fourteenth type signal pin 2012 of the system-on-a-chip 20 is electrically connected to the second type signal pin 1012 of the first mounting area 101.

[0174] The first memory 30 is mounted on the second mounting area 102 of the printed circuit board 10, and the fifteenth type signal pin 3011 of the first memory 30 is electrically connected to the third type signal pin 1021 of the second mounting area 102.

[0175] The second memory 40 is mounted in the third mounting area 103 of the printed circuit board 10, and the sixteenth type signal pin 4011 of the second memory 40 is electrically connected to the fifth type signal pin 1031 of the third mounting area 103.

[0176] Specifically, the printed circuit board 10 is provided with a first mounting area 101, a second mounting area 102, and a third mounting area 103. A system-on-a-chip (SoC) 20 is mounted in the first mounting area 101 of the SoC 10. The thirteenth type signal pin 2011 of the SoC 20 is electrically connected to the first type signal pin 1011 of the first mounting area 101. The first type signal pin 1011 of the first mounting area 101 is electrically connected to the third type signal pin 1021 of the second mounting area 102 via a first type signal line 104 within the SoC 10. The fourteenth type signal pin 2012 of the SoC 20 is electrically connected to the second type signal pin 1012 of the first mounting area 101. The second type signal pin 1012 of the first mounting area 101 is electrically connected to the fifth type signal pin 1031 of the third mounting area 103 via a second type signal line 105 within the SoC 10. A first memory 30 is mounted in a second mounting area 102 of the printed circuit board 10, and a fifteenth type signal pin 3011 of the first memory 30 is electrically connected to a third type signal pin 1021 of the second mounting area 102. A second memory 40 is mounted in a third mounting area 103, and a sixteenth type signal pin 4011 of the second memory 40 is electrically connected to a fifth type signal pin 1031 of the third mounting area 103.

[0177] One of the aforementioned thirteenth-type and fourteenth-type signal pins is used for inputting or outputting memory signals, and the other is used for inputting or outputting flash memory signals. The thirteenth-type signal pin of the system-on-chip 20 is electrically connected to the first-type signal pin of the first mounting area, and the fourteenth-type signal pin of the system-on-chip 20 is electrically connected to the second-type signal pin of the first mounting area. For example, the thirteenth-type signal pin of the system-on-chip 20 is soldered to the first-type signal pin of the first mounting area, and the fourteenth-type signal pin of the system-on-chip 20 is soldered to the second-type signal pin of the first mounting area.

[0178] The fifteenth type signal pin of the first memory is electrically connected to the third type signal pin of the second mounting area. For example, the fifteenth type signal pin of the first memory is soldered together with the third type signal pin of the second mounting area.

[0179] The sixteenth type signal pin of the second memory is electrically connected to the fifth type signal pin of the third mounting area. For example, the sixteenth type signal pin of the second memory is soldered together with the fifth type signal pin of the third mounting area.

[0180] It should be noted that when the first memory is mounted in the second mounting area of ​​the printed circuit board and the second memory is mounted in the third mounting area of ​​the printed circuit board, the fourth and sixth signal pins on the printed circuit board are in a floating state. In this way, the signal traces reserved for the third memory will not affect the signals of the first and second memories.

[0181] It should also be noted that the details of the printed circuit board, the first memory, and the second memory in this embodiment can be found in the relevant descriptions of the foregoing embodiments, and will not be repeated here.

[0182] This application also provides an electronic device. Figure 13 This is a schematic diagram of an electronic device provided in an embodiment of this application. See also... Figure 13 The electronic device 2 includes a printed circuit board 10 provided in any of the above embodiments, a first adapter board 50 provided in any of the above embodiments, a second adapter board 60 provided in any of the above embodiments, a system-on-a-chip 20, and a third memory 70;

[0183] The system-on-a-chip 20 is mounted on the first mounting area 101 of the printed circuit board 10. The thirteenth type signal pin 2011 of the system-on-a-chip 20 is electrically connected to the first type signal pin 1011 of the first mounting area 101, and the fourteenth type signal pin 2012 of the system-on-a-chip 20 is electrically connected to the second type signal pin 1012 of the first mounting area 101.

[0184] The first adapter board 50 is mounted on the second mounting area 102 of the printed circuit board 10. The seventh type signal pin 5011 of the first adapter board 50 is electrically connected to the third type signal pin 1021 of the second mounting area 102, and the eighth type signal pin 5012 of the first adapter board 50 is electrically connected to the fourth type signal pin 1022 of the second mounting area 102.

[0185] The second adapter board 60 is mounted on the third mounting area 103 of the printed circuit board 10. The eleventh type signal pin 6011 of the second adapter board 60 is electrically connected to the fifth type signal pin 1031 of the third mounting area 103, and the twelfth type signal pin 6012 of the second adapter board 60 is electrically connected to the sixth type signal pin 1032 of the third mounting area 103.

[0186] The third memory 70 is mounted in the fourth mounting area 5021 of the first adapter board 50. The seventeenth type signal pin 7011 of the third memory 70 is electrically connected to the ninth type signal pin 5022 of the fourth mounting area 5021, and the eighteenth type signal pin 7012 of the third memory 70 is electrically connected to the tenth type signal pin 5023 of the fourth mounting area 5021.

[0187] Specifically, the printed circuit board 10 is provided with a first mounting area 101, a second mounting area 102, and a third mounting area 103. A system-on-a-chip (SoC) 20 is mounted in the first mounting area 101 of the SoC 10. The thirteenth type signal pin 2011 of the SoC 20 is electrically connected to the first type signal pin 1011 of the first mounting area 101. The first type signal pin 1011 of the first mounting area 101 is electrically connected to the third type signal pin 1021 of the second mounting area 102 via a first type signal line 104 within the SoC 10. The fourteenth type signal pin 2012 of the SoC 20 is electrically connected to the second type signal pin 1012 of the first mounting area 101. The second type signal pin 1012 of the first mounting area 101 is electrically connected to the fifth type signal pin 1031 of the third mounting area 103 via a second type signal line 105 within the SoC 10.

[0188] A first adapter board 50 is mounted on the second mounting area 102 of the printed circuit board 10. The seventh signal pin of the first adapter board 50 is electrically connected to the third signal pin of the second mounting area 102, and the eighth signal pin of the first adapter board 50 is electrically connected to the fourth signal pin of the second mounting area 102. A third memory 70 is mounted on the fourth mounting area 5021 of the first adapter board 50. The seventeenth signal pin 7011 of the third memory 70 is electrically connected to the ninth signal pin 5022 of the fourth mounting area 5021, and the eighteenth signal pin 7012 of the third memory 70 is electrically connected to the tenth signal pin 5023 of the fourth mounting area 5021.

[0189] The second adapter board 60 is mounted on the third mounting area 103 of the printed circuit board 10. The eleventh type signal pin 6011 of the second adapter board 60 is electrically connected to the fifth type signal pin of the third mounting area 103. The eleventh type signal pin 6011 of the second adapter board 60 is connected to the twelfth type signal pin 6012 of the second adapter board 60 through the sixth type signal line 602 in the second adapter board 60. The twelfth type signal pin 6012 of the second adapter board 60 is electrically connected to the sixth type signal pin 1032 of the third mounting area 103. The sixth type signal pin 1032 of the third mounting area 103 is electrically connected to the fourth type signal pin in the printed circuit board 10 through the third type signal line 106 in the printed circuit board 10.

[0190] The seventh type signal pin 5011 of the first adapter board 50 is electrically connected to the third type signal pin 1021 of the second mounting area 102, and the eighth type signal pin 5012 of the first adapter board 50 is electrically connected to the fourth type signal pin 1022 of the second mounting area 102. For example, the seventh type signal pin 5011 of the first adapter board 50 is soldered together with the third type signal pin 1021 of the second mounting area 102, and the eighth type signal pin 5012 of the first adapter board 50 is soldered together with the fourth type signal pin 1022 of the second mounting area 102.

[0191] The eleventh type signal pin 6011 of the second adapter board 60 is electrically connected to the fifth type signal pin of the third mounting area 103, and the twelfth type signal pin 6012 of the second adapter board 60 is electrically connected to the sixth type signal pin 1032 of the third mounting area 103. For example, the eleventh type signal pin 6011 of the second adapter board 60 is soldered together with the fifth type signal pin of the third mounting area 103, and the twelfth type signal pin 6012 of the second adapter board 60 is soldered together with the sixth type signal pin 1032 of the third mounting area 103.

[0192] The seventeenth type signal pin 7011 of the third memory 70 is electrically connected to the ninth type signal pin 5022 of the fourth mounting area 5021, and the eighteenth type signal pin 7012 of the third memory 70 is electrically connected to the tenth type signal pin 5023 of the fourth mounting area 5021. For example, the seventeenth type signal pin 7011 of the third memory 70 is soldered together with the ninth type signal pin 5022 of the fourth mounting area 5021, and the eighteenth type signal pin 7012 of the third memory 70 is soldered together with the tenth type signal pin 5023 of the fourth mounting area 5021.

[0193] It should be noted that the detailed contents of the printed circuit board, the first adapter board, the second adapter board, the system-on-a-chip, and the third memory in this embodiment can be found in the relevant descriptions of the foregoing embodiments, and will not be repeated here.

[0194] It should be noted that the aforementioned electronic devices can be mobile phones, tablets, laptops, handheld computers, in-vehicle electronic devices, mobile internet devices (MID), augmented reality (AR) / virtual reality (VR) devices, robots, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc. They can also be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. The embodiments of this application do not impose specific limitations.

[0195] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0196] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A printed circuit board, characterized in that, The printed circuit board is provided with a first mounting area, a second mounting area and a third mounting area. The first mounting area is used to mount a system-on-a-chip, the second mounting area is used to mount a first memory or a first adapter board, and the third mounting area is used to mount a second memory or a second adapter board. The first mounting area is provided with a first type of signal pin and a second type of signal pin; the second mounting area is provided with a third type of signal pin and a fourth type of signal pin; and the third mounting area is provided with a fifth type of signal pin and a sixth type of signal pin. The first type of signal pin is electrically connected to the third type of signal pin through the first type of signal line in the printed circuit board; the second type of signal pin is electrically connected to the fifth type of signal pin through the second type of signal line in the printed circuit board; and the fourth type of signal pin is electrically connected to the sixth type of signal pin through the third type of signal line in the printed circuit board. Wherein, when the first memory is RAM and the second memory is flash memory, the first type of signal line is used to transmit memory signals and the second type of signal line is used to transmit flash memory signals; when the first memory is flash memory and the second memory is RAM, the first type of signal line is used to transmit flash memory signals and the second type of signal line is used to transmit RAM signals; the third type of signal line is used to transmit either flash memory signals or RAM signals, and the first adapter board is used to install a third memory, which is a memory that integrates RAM and flash memory.

2. The printed circuit board according to claim 1, characterized in that, The first mounting area, the second mounting area, and the third mounting area are all located on the same side of the printed circuit board; or, The first mounting area and the second mounting area are both disposed on the first side of the printed circuit board, and the third mounting area is disposed on the second side of the printed circuit board. The first side and the second side are two opposite sides.

3. The printed circuit board according to claim 2, characterized in that, The first installation area and the second installation area satisfy at least one of the following: The second mounting area is located on the first side of the first mounting area, and the first side is the side of the first mounting area that is closest to the first type of signal pin. The distance between the first installation area and the second installation area is less than or equal to a first threshold.

4. The printed circuit board according to claim 2, characterized in that, The third mounting area and the second mounting area satisfy at least one of the following: The third mounting area is located on the second side of the second mounting area, and the second side is the side of the second mounting area that is closest to the fourth type of signal pin. The distance between the third installation area and the second installation area is less than or equal to the second threshold.

5. The printed circuit board according to claim 1, characterized in that, The first memory is RAM, and the second memory is flash memory.

6. An electronic device, characterized in that, Includes the printed circuit board, system-on-a-chip, first memory, and second memory as described in any one of claims 1 to 5; The system-on-a-chip is mounted in the first mounting area of ​​the printed circuit board. The thirteenth type signal pin of the system-on-a-chip is electrically connected to the first type signal pin of the first mounting area, and the fourteenth type signal pin of the system-on-a-chip is electrically connected to the second type signal pin of the first mounting area. The first memory is mounted in the second mounting area of ​​the printed circuit board, and the fifteenth type signal pin of the first memory is electrically connected to the third type signal pin of the second mounting area. The second memory is mounted in the third mounting area of ​​the printed circuit board, and the sixteenth type signal pin of the second memory is electrically connected to the fifth type signal pin of the third mounting area.

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