Semiconductor device and method for manufacturing the same

Abstract

Provided are a method for preparing a semiconductor device and a semiconductor device prepared by the method. The method comprises: providing a substrate, the substrate comprising an array region and a peripheral region, the array region being formed with storage node contact pads; forming a first wiring layer in the peripheral region, the storage node contact pads and the surface of the first wiring layer being formed with a first protective layer; forming a first dielectric layer on the substrate surface, the first dielectric layer having through holes formed at positions corresponding to the first wiring layer, the first wiring layer being exposed in the through holes; forming a continuous first metal layer on the first dielectric layer and in the through holes; patterning the first metal layer and the first dielectric layer to form a second wiring pattern located in the peripheral region, exposing the first protective layer in the array region; forming a second protective pattern between the second wiring patterns; removing the exposed first protective layer to expose the storage node contact pads; forming a storage node connected to the storage node contact pads in the array region, and forming a planarization layer in the peripheral region, the planarization layer having contact plugs in contact with the second wiring pattern.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor device, a dynamic random access memory, and a selection control circuit. Background Art

[0002] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As semiconductor device structures shrink in size, the requirements for process yield gradually increase. The circuit lead structure process in the peripheral area becomes more complex, while ensuring that the process of the array area is not affected. Therefore, the development of new semiconductor structure fabrication methods is urgent. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:

[0004] Providing a substrate, the substrate comprising an array region and a peripheral region, wherein a storage node contact pad is formed in the array region; a first wiring layer is formed in the peripheral region, and a first protective layer is formed on the surface of the storage node contact pad and the first wiring layer;

[0005] forming a first dielectric layer on the surface of the substrate, wherein the first dielectric layer has a through hole formed at a position corresponding to the first wiring layer, and the first wiring layer is exposed in the through hole;

[0006] forming a continuous first metal layer on the first dielectric layer and in the through hole;

[0007] patterning the first metal layer and the first dielectric layer to form a second wiring pattern in the peripheral area, exposing the first protection layer in the array area;

[0008] forming a second protection pattern between the second wiring patterns;

[0009] removing the exposed first protection layer to expose the storage node contact pad;

[0010] A storage node connected to the storage node contact pad is formed in the array region, and a planar layer is formed in the peripheral region. A contact plug contacting the second wiring pattern is formed in the planar layer.

[0011] In some embodiments, forming the second protection pattern between the second wiring patterns includes:

[0012] A second protection layer is formed, and the second protection layer is patterned, and the second protection layer located between the second wiring patterns is retained to form a second protection pattern.

[0013] In some embodiments, the thickness of the second protection layer in the array region is less than half of the sum of the thickness of the first dielectric layer and the thickness of the first metal layer.

[0014] In some embodiments, the second protective layer is formed by a method selected from spin coating or deposition.

[0015] In some embodiments, the method of patterning the second protective layer is selected from dry etching.

[0016] In some embodiments, patterning the first metal layer and the first dielectric layer to form a second wiring pattern in the peripheral region, exposing the first protection layer in the array region, further comprises:

[0017] At least a portion of the first protection layer is exposed between the second wiring patterns.

[0018] In some embodiments, the second protection pattern covers the first protection layer exposed between the second wiring patterns.

[0019] In some embodiments, after removing the exposed first protection layer to expose the storage node contact pad, the method further includes: removing the second protection pattern.

[0020] In some embodiments, the material of the second protection pattern is selected from spin-on hard mask or carbon.

[0021] According to a second aspect of an embodiment of the present disclosure, a semiconductor device is manufactured according to the aforementioned semiconductor device manufacturing method.

[0022] As the size of peripheral circuits decreases, the difficulty of aligning them directly with contact plugs increases, thus affecting the yield of semiconductor devices. The provision of a second wiring pattern improves the yield of peripheral circuit leads, and the addition of a second protection pattern during the manufacturing process allows the semiconductor device to be manufactured without damaging the peripheral circuits, thus ensuring the performance of the peripheral circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1-Figure 7 is a schematic diagram of a substrate structure in a certain step of a method for manufacturing a semiconductor device according to an exemplary embodiment;

[0024] Figure 8 The figure is a schematic diagram of a semiconductor device in a certain step of a method for manufacturing a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0025] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0027] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0028] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0029] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0030] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0031] According to a first aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:

[0032] A substrate is provided, comprising an array region and a peripheral region, wherein a storage node contact pad is formed in the array region; a first wiring layer is formed in the peripheral region, and a first protective layer is formed on the surface of the storage node contact pad and the first wiring layer; a first dielectric layer is formed on the surface of the substrate, wherein the first dielectric layer has through holes formed at positions corresponding to the first wiring layer, and the first wiring layer is exposed in the through holes; a continuous first metal layer is formed on the first dielectric layer and in the through holes; the first metal layer and the first dielectric layer are patterned to form a second wiring pattern located in the peripheral region, exposing the first protective layer in the array region; a second protective pattern is formed between the second wiring patterns; the exposed first protective layer is removed to expose the storage node contact pad; a storage node connected to the storage node contact pad is formed in the array region, and a planarization layer is formed in the peripheral region, wherein a contact plug contacting the second wiring pattern is formed in the planarization layer.

[0033] Steps: Provide a substrate, the substrate includes an array area and a peripheral area, the array area is formed with a storage node contact pad; the peripheral area is formed with a first wiring layer, and a first protective layer is formed on the surface of the storage node contact pad and the first wiring layer. Specifically, provide Figure 1 The substrate 10 shown includes an array area A and a peripheral area P. A storage node contact pad 200 is formed in the array area, a first wiring layer 300 is formed in the peripheral area, and a first protective layer 400 is formed on the surface of the storage node contact pad and the first wiring layer. Specifically, the substrate also includes a base plate 100. Optionally, the base plate is made of semiconductor materials such as single crystal silicon, silicon germanium, silicon carbide, etc. Optionally, the substrate also includes a transistor structure (not shown) arranged in the base plate or on the surface of the base plate. Optionally, an array transistor structure is provided in the substrate corresponding to the array area, and the storage node contact pad is connected to one end of the array transistor structure. Optionally, a peripheral transistor structure is provided on the surface of the substrate corresponding to the peripheral area, and the first wiring layer is connected to one end of the peripheral transistor structure to form a peripheral circuit. Optionally, the storage node contact pad and the first wiring layer are formed by the same metal layer in the front-end process. Optionally, the subsequent processes in the array region and the peripheral region may be the same or different. When the subsequent processes are different, the first protective layer covering the surface of the storage node contact pad and the first wiring layer can be used to protect the storage node contact pad and the first wiring layer from being affected by the process in the other region. That is, when the peripheral region is prepared, the first protective layer in the array region protects the storage node contact pad from being affected by the peripheral region preparation process; when the array region is prepared, the first protective layer in the peripheral region protects the first wiring layer from being affected by the array region preparation process. Optionally, the material of the first protective layer is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. Optionally, the method for forming the first protective layer is selected from spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace deposition, etc.

[0034] Step: forming a first dielectric layer on the surface of the substrate, forming a through hole in the first dielectric layer at a position corresponding to the first wiring layer, and exposing the first wiring layer in the through hole. Figure 2As shown, a first dielectric layer 500 is formed on the surface of the substrate. Optionally, the material of the first dielectric layer is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. Optionally, the material of the first dielectric layer may be the same as or different from the material of the first protective layer. Preferably, the material of the first dielectric layer is different from the material of the first protective layer. Optionally, the method for forming the first dielectric layer is selected from spin coating, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Optionally, a first dielectric layer material layer is first formed by the aforementioned method, and then the first dielectric layer material layer is flattened to form the first dielectric layer. The flattening can be achieved by chemical mechanical polishing (CMP). A through hole V1 is formed in the first dielectric layer. Optionally, the method for forming the through hole includes forming a patterned mask through a composition process, and transferring the mask pattern to the first dielectric layer through an etching process to form the through hole. Specifically, the composition process includes forming a photoresist layer, exposing the photoresist layer, and developing it to form a patterned photoresist layer. Optionally, the patterned photoresist layer is used as a mask to perform an etching process on the first dielectric layer, or the pattern of the photoresist layer is transferred to another hard mask, and the hard mask is used as a mask to perform an etching process on the first dielectric layer. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching. Preferably, the etching process is selected from dry etching. The through hole is etched through the first dielectric layer, and then etching is continued until the first wiring layer is exposed. Optionally, the etching process has a high etching selectivity ratio between the mask and the first dielectric layer. Optionally, the etching process has a high etching selectivity ratio between the mask and the first protective layer.

[0035] Step: forming a continuous first metal layer on the first dielectric layer and in the through hole. Figure 3As shown, a first metal layer M1 is formed on the surface of a first dielectric layer having a through hole. The first metal layer covers the first dielectric layer and the through hole to form a continuous first metal layer. The first metal layer in the through hole is connected to the first wiring layer. Optionally, the first metal layer is formed by a method selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace deposition, or Damascus process. Optionally, the material of the first metal layer may include metal, metal nitride, metal oxide, metal silicide, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or non-metallic materials such as polysilicon, gallium indium tin oxide, and indium tin oxide, or combinations thereof. Optionally, the method for forming the first metal layer includes depositing a first metal layer material layer and then planarizing the layer to obtain the first metal layer. Specifically, the planarization can be achieved by chemical mechanical polishing (CMP).

[0036] Step: Patterning the first metal layer and the first dielectric layer to form a second wiring pattern in the peripheral area, exposing the first protective layer in the array area. Figure 4As shown, the first metal layer and the first dielectric layer are patterned, and portions of the first metal layer and the first dielectric layer are removed, and the remaining portions of the first dielectric layer 601 and the first metal layer 602 are used to form a second wiring pattern 600. Optionally, the patterning method includes forming a patterned photoresist layer through a composition process, and etching the first metal layer and the first dielectric layer using the patterned photoresist layer as a mask through an etching process to form a second wiring pattern. Optionally, the patterning process includes forming a photoresist layer, exposing the photoresist layer, and developing the photoresist layer to form a patterned photoresist layer. Optionally, the patterning method includes forming a patterned photoresist layer through a composition process, transferring the photoresist layer pattern to a hard mask, and etching the first metal layer and the first dielectric layer through the patterned hard mask to form a second wiring pattern. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching. Preferably, the etching process is selected from dry etching. In order to facilitate subsequent process manufacturing, the first dielectric layer and the first metal layer in the array area are completely etched to expose the first protective layer. Optionally, the first metal layer that needs to be removed in the peripheral area is completely etched, but because the pattern spacing of the first wiring layer is larger than the storage node contact pad gap in the array area, the first protective layer will have a recess between the patterns of the first wiring layer. Therefore, some of the first dielectric layer material may remain, resulting in the first protective layer in the peripheral area not covered by the second wiring pattern being partially exposed and partially covered by the remaining first dielectric layer material. Optionally, the first dielectric layer between the second wiring patterns in the peripheral area is partially etched, leaving some of the first dielectric layer material to cover the first protective layer.

[0037] Step: forming a second protection pattern between the second wiring patterns. Specifically, Figure 5-6As shown, a second protective pattern 800 is formed between the second wiring patterns. Optionally, the method for forming the second protective pattern includes forming a second protective layer 700 on a substrate having a second wiring pattern formed thereon, and patterning the second protective layer to form a second protective pattern. Optionally, the method for forming the second protective layer is selected from spin coating, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace deposition, etc. Preferably, the method for forming the second protective layer is selected from spin coating or deposition. Optionally, the material of the second protective layer is selected from a material having a larger etching selectivity ratio with the first protective layer. Preferably, the material of the second protective layer is selected from a spin-on hard mask or a carbon material. Optionally, the method for patterning the second protective layer includes etching to form a second protective pattern through a patterning process. Optionally, the patterning method includes forming a patterned photoresist layer through a patterning process, and etching the second protective layer through an etching process using the patterned photoresist layer as a mask to form a second protective pattern. Optionally, the patterning process includes forming a photoresist layer, exposing the photoresist layer, and developing the photoresist layer to form a patterned photoresist layer. Optionally, the patterning method includes forming a patterned photoresist layer through a patterning process, transferring the photoresist layer pattern to a hard mask, and etching the second protective layer through the patterned hard mask to form a second protective pattern. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching. Preferably, the etching process is selected from dry etching.

[0038] In some embodiments, when the second protective layer material is selected from a spin-on hard mask or a carbon material, the method for patterning the second protective layer is to directly perform an etching process; since the gap between the second wiring patterns is small, the spin-on hard mask or the carbon material has slightly poor conformality, and more second protective layer material will accumulate in the gap relative to the array area and the second wiring pattern surface. Therefore, when the second protective layer is etched by the etching process, within the same etching time, the second protective layer on the array area and the second wiring pattern surface will be completely etched, but some second protective layer material will still remain between the second wiring patterns, thereby forming a second protective pattern. In order to more easily form the second protective pattern and ensure that the formed second protective pattern has a better protective effect, the thickness of the second protective layer cannot be too thick. Preferably, the thickness of the second protective layer in the array area is less than half of the sum of the thickness of the first dielectric layer and the thickness of the first metal layer, that is, the thickness of the second protective layer in the array area is less than half of the thickness of the second wiring pattern in the peripheral area, that is, as Figure 5 As shown in , d1<1 / 2(d2+d3).

[0039] In some embodiments, when a portion of the first dielectric layer material remains between the second wiring patterns and the first protective layer between the second wiring patterns is completely obscured, the second protective pattern is formed on the remaining first dielectric layer material. Preferably, a portion of the first protective layer is exposed between the second wiring patterns, and the second protective pattern obscures the exposed first protective layer.

[0040] Step: remove the exposed first protection layer to expose the storage node contact pad. Figure 7 As shown, an etching process is performed on the substrate formed with the second protective pattern to remove the exposed first protective layer, so that the storage node contact pads in the array area are exposed. Since the first protective layer between the second wiring patterns is blocked by the second protective pattern, it will not be affected when the etching process is performed. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching. Preferably, the etching process is selected from dry etching. Optionally, after removing the exposed first protective layer and exposing the storage node contact pads, it also includes removing the second protective pattern to avoid the second protective pattern from remaining in the substrate.

[0041] In some embodiments, after patterning the first metal layer and the first dielectric layer to form a second wiring pattern located in the peripheral area and exposing the first protective layer in the array area, the second protective pattern is not made after the step, and the step of removing the exposed first protective layer to expose the storage node contact pad is directly performed. In this embodiment, since part of the first protective layer is exposed between the second wiring patterns in the peripheral area, the exposed first protective layer will be damaged during the step of removing the exposed first protective layer and exposing the storage node contact pad, resulting in the exposure of the first wiring layer. Even if part of the first dielectric layer material remains between the second wiring patterns, it is not enough to protect the first protective layer because the first dielectric layer will be removed during the process of removing the exposed first protective layer. In subsequent process steps, the exposed first wiring layer will be damaged or the material of the first wiring layer will diffuse into adjacent structures, causing leakage and other defects, affecting the yield of the product.

[0042] In some embodiments, after patterning the first metal layer and the first dielectric layer to form a second wiring pattern located in the peripheral area, exposing the first protective layer in the array area, the second protective pattern is not formed after this step, but the first protective layer material layer is deposited again on the entire substrate to protect the second wiring pattern. Then, the step of removing the exposed first protective layer to expose the storage node contact pad is performed, that is, removing the first protective layer material layer deposited for the second time and the first protective layer in contact with it. In this embodiment, although the side of the second wiring pattern in the peripheral area is protected, there is an additional layer of the first protective layer material. In order to fully open the storage node contact pad, the etching time needs to be increased, resulting in the first protective layer between the second wiring patterns still being etched away, exposing the first wiring layer. Even if some of the first dielectric layer material remains between the second wiring patterns, it is not enough to protect the first protective layer because the first dielectric layer will be removed in the process of removing the exposed first protective layer. In subsequent process steps, the exposed first wiring layer will be damaged or the material of the first wiring layer will diffuse into adjacent structures, causing leakage and other defects, affecting the yield of the product.

[0043] Steps: forming a storage node connected to the storage node contact pad in the array region, forming a planar layer in the peripheral region, and forming a contact plug in the planar layer that contacts the second wiring pattern. Specifically, Figure 8 As shown, a storage node C1 is formed in the array region and connected to the storage node contact pad 200. Optionally, the storage node includes one or more of a capacitor, a magnetoresistive memory, a phase change memory, and a ferroelectric memory.

[0044] In some embodiments, the storage node is a storage capacitor, and the specific manufacturing method includes alternately depositing a support layer and a sacrificial layer in the array area exposing the storage node contact pad, making a capacitor hole at the corresponding position of the storage node contact pad by a patterning method, then depositing the storage capacitor lower electrode, then removing the sacrificial layer, and successively depositing a capacitor dielectric layer and an upper electrode on the lower electrode. Optionally, a common electrode layer is formed between the storage capacitors to lead out the upper electrode and support the storage capacitor at the same time. Optionally, the deposition method is selected from spin coating, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Optionally, the patterning method includes forming a patterned photoresist layer by a composition process, and etching the support layer and the sacrificial layer by an etching process using the patterned photoresist layer as a mask to form a capacitor hole. Optionally, the composition process includes forming a photoresist layer, exposing the photoresist layer, and developing to form a patterned photoresist layer. Optionally, the patterning method includes forming a patterned photoresist layer by a composition process, transferring the photoresist layer pattern to a hard mask, and etching the support layer and the sacrificial layer through the patterned hard mask to form a capacitor hole pattern. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching. Preferably, the etching process is selected from dry etching. Optionally, after forming the common electrode layer, the common electrode layer is also planarized. Specifically, the planarization can be achieved by chemical mechanical polishing (CMP).

[0045] In some embodiments, in order to balance the height difference of the substrate surface, a flat layer E1 is formed in the peripheral area, and a contact plug 900 is formed in the flat layer to contact the second wiring pattern. The contact plug is connected to the second wiring pattern to lead out the peripheral area circuit to form a semiconductor device 20. Because the second wiring pattern can disperse and enlarge the small-sized contact pads of the first wiring layer again, it is convenient to ensure good electrical contact when making the contact plug. Especially when the storage node is a capacitor, in order to ensure the performance of the device, it is necessary to make a capacitor with a large aspect ratio. The corresponding flat layer in the peripheral area needs to be made thicker, and the aspect ratio of the contact plug will be very large, making it difficult to align the contact plug with the peripheral circuit. Especially after the size is miniaturized to a certain extent, the process window will be very small. Therefore, the second wiring pattern can be used to enlarge the contact pad size, reduce the difficulty of contact plug alignment, expand the process window, and improve product yield.

[0046] Optionally, the method for forming the flat layer is selected from spin coating, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace deposition, etc. Optionally, forming the flat layer also includes flattening by chemical mechanical polishing (CMP). Optionally, forming the contact plug includes patterning a contact plug hole in the flat layer and forming a contact plug in the contact plug hole. Optionally, the patterning method includes forming a patterned photoresist layer through a composition process, and etching the support layer and the sacrificial layer through an etching process using the patterned photoresist layer as a mask to form a contact plug hole. Optionally, the composition process includes forming a photoresist layer, exposing the photoresist layer, and developing it to form a patterned photoresist layer. Optionally, the patterning method includes forming a patterned photoresist layer by a composition process, transferring the photoresist layer pattern to a hard mask, and etching the support layer and the sacrificial layer through the patterned hard mask to form a contact plug hole pattern. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching. Preferably, the etching process is selected from dry etching. Optionally, the method for forming the contact plug includes spin coating, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Optionally, the method for forming the contact plug also includes planarization by chemical mechanical polishing (CMP).

[0047] According to a second aspect of the embodiments of the present disclosure, a semiconductor device prepared by the above-mentioned semiconductor device preparation method is provided. Figure 8 As shown, the semiconductor device 20 includes an array area and a peripheral area. The peripheral area includes a first wiring layer 300 and a second wiring pattern 600. A portion of the first metal layer 602 in the second wiring pattern is connected to the first wiring layer, and a portion of the first dielectric layer 601 is disposed between the two. The peripheral area also includes a contact plug 900 to lead out the peripheral circuit. A first protective layer is also included between a portion of the first dielectric layer and the first wiring layer, and the first protective layer corresponding to the position between the second wiring patterns is not etched. Therefore, the metal of the first wiring layer is well protected and will not diffuse into the flat layer, and no leakage will occur. The semiconductor device has better stability and a higher yield.

[0048] The various semiconductor devices described in this embodiment can be used in electronic devices with storage functions. The electronic devices can be terminal devices such as mobile phones, tablet computers, smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in the electronic devices can be implemented using the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM), or resistive access memory (RRAM).

[0049] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region, wherein the array region is formed with storage node contact pads; A first wiring layer is formed in the peripheral area, and a first protection layer is formed on the surface of the storage node contact pad and the first wiring layer; forming a first dielectric layer on the surface of the substrate, wherein the first dielectric layer has a through hole formed at a position corresponding to the first wiring layer, and the first wiring layer is exposed in the through hole; forming a continuous first metal layer on the first dielectric layer and in the through hole; patterning the first metal layer and the first dielectric layer to form a second wiring pattern located in the peripheral area, exposing the first protection layer in the array area; forming a second protection pattern between the second wiring patterns; removing the exposed first protection layer to expose the storage node contact pad; A storage node connected to the storage node contact pad is formed in the array region, and a planar layer is formed in the peripheral region. A contact plug contacting the second wiring pattern is formed in the planar layer.

2. The method for preparing a semiconductor device according to claim 1, wherein: forming a second protection pattern between the second wiring patterns, comprising: A second protection layer is formed, and the second protection layer is patterned, and the second protection layer located between the second wiring patterns is retained to form a second protection pattern.

3. The method for preparing a semiconductor device according to claim 2, wherein: The thickness of the second protection layer in the array area is less than half of the sum of the thickness of the first dielectric layer and the thickness of the first metal layer.

4. The method for preparing a semiconductor device according to claim 2, wherein: The second protective layer is formed by spin coating or deposition.

5. The method for preparing a semiconductor device according to claim 2, wherein: The method of patterning the second protective layer is selected from dry etching.

6. The method for preparing a semiconductor device according to claim 1, wherein: Patterning the first metal layer and the first dielectric layer to form a second wiring pattern located in the peripheral area, exposing the first protection layer in the array area, further comprising: At least a portion of the first protection layer is exposed between the second wiring patterns.

7. The method for preparing a semiconductor device according to claim 6, wherein: The second protection pattern covers the first protection layer exposed between the second wiring patterns.

8. The method for preparing a semiconductor device according to claim 1, wherein: After removing the exposed first protection layer to expose the storage node contact pad, the method further includes: removing the second protection pattern.

9. The method for preparing a semiconductor device according to claim 1, wherein: The material of the second protection pattern is selected from a spin-on hard mask or carbon.

10. A semiconductor device, characterized in that: Prepared according to the method for preparing a semiconductor device according to any one of claims 1 to 9.

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