Power amplifier semiconductor device

Abstract

A power amplifier semiconductor device (100) operates at a frequency of 3 GHz or more, comprising: a substrate (101); a semiconductor layer (102) disposed on the front surface of the substrate (101) and comprising a plurality of unit HEMTs; a connection layer (L1) disposed on the semiconductor layer (102) and comprising a source electrode (301), a drain electrode (302) and a gate electrode (303) of the unit HEMT; a terminal layer (L2) comprising a source pad (701a), a drain pad (702) and a gate electrode (303) disposed on the connection layer (L1); and a power amplifier semiconductor device (100) operating at a frequency of 3 GHz or more. 702a) and a gate pad (703a); a back electrode (103) arranged on the back side of the substrate (101) and set to a source potential; a substrate via (901) penetrating the substrate (101) and having a shielding wiring layer (503) on the inner wall. The power amplifier semiconductor device (100) also has a drain collecting portion (702) and a gate collecting portion (703). In a plan view, the drain collecting portion (702) and the gate collecting portion (703) are surrounded by the substrate via (901) on one or both sides.

Description

Technical Field

[0001] The present disclosure relates to a power amplification semiconductor device. Background Art

[0002] Among III-V compound semiconductors, especially arsenic-based GaAs or AlGaAs, nitride-based GaN or AlGaN, heterostructures such as AlGaAs / GaAs and AlGaN / GaN can be easily formed. In the case of III-V nitride semiconductors, in addition to the difference in band gap, the spontaneous polarization caused by the difference in ion radius and the fixed charge caused by the piezoelectric polarization caused by the difference in lattice constants between AlGaN and GaN can generate high mobility on the GaAs side of AlGaAs / GaAs and the GaN layer side of the AlGaN / GaN interface, that is, a channel (two-dimensional electron gas (2DEG: Dimensional Electron Gas)) with high concentration of electrons can be generated. By controlling the two-dimensional electron gas channel, a high electron mobility transistor (HEMT: High Electron Mobility Transistor) can be formed. By making full use of the high-speed operation through this high mobility, high-frequency devices such as amplifiers and / or switching elements are widely used.

[0003] In recent years, high-frequency amplifiers have been increasingly used in mobile phone base stations, and as the communication generations of mobile phones advance, the operating frequency and output power are expected to increase. By performing flip-chip mounting on such semiconductor devices, it is expected that the flexibility of chip mounting in a higher-frequency environment will be improved, and the high-frequency amplifier will be expected to be multifunctional.

[0004] However, the increase in operating frequency and / or output power leads to an increase in noise signals generated by the device itself used as a high-frequency amplifier. Therefore, various studies have been conducted on suppressing the influence of noise signals (for example, see Patent Document 1).

[0005] (Prior art literature)

[0006] (Patent Document)

[0007] Patent Document 1: Japanese Patent Application Publication No. 2004-260082 Summary of the invention

[0008] Problems to be solved by the invention

[0009] However, in the conventional technology described in Patent Document 1, only a countermeasure is taken against the noise signal generated by the electrode pad of the chip, and there is still room for improvement in suppressing the influence of the noise signal.

[0010] Therefore, the present disclosure provides a power amplifier semiconductor device that can suppress the influence of noise signals more than the conventional technology.

[0011] Means for solving problems

[0012] A power amplification semiconductor device according to one embodiment of the present disclosure is a power amplification semiconductor device that operates at a frequency of 3 GHz or higher in which a plurality of unit HEMTs are connected in parallel, wherein the HEMT is a High Electron Mobility Transistor, and comprises: a substrate; a semiconductor layer that is provided on the front surface of the substrate and includes the plurality of unit HEMTs; a connection layer that is provided on the semiconductor layer and includes source electrodes, drain electrodes, and gate electrodes of the unit HEMTs; a terminal layer that is provided on the connection layer and includes a source pad, a drain pad, and a gate pad that are connected to the source electrode, the drain electrode, and the gate electrode via a first portion of a wiring layer; a back electrode that is provided on the back surface of the substrate and whose potential is set to be the same as that of the source electrode; and a substrate through-hole. A hole passes through the substrate, a shielding wiring layer is provided on the inner wall of the substrate via hole, the shielding wiring layer is the second part of the wiring layer set to the source potential, the drain electrode and the gate electrode are respectively multiple corresponding to the unit HEMT, the power amplification semiconductor device has: a drain collection part, the drain collection part is used for the multiple drain electrodes to be collectively connected to the wiring at the third part of the wiring layer; and a gate collection part, the gate collection part is used for the multiple gate electrodes to be collectively connected to the wiring at the fourth part of the wiring layer, in the plan view of the substrate, either or both of the drain collection part and the gate collection part are surrounded by the substrate via hole.

[0013] Effects of the Invention

[0014] According to one aspect of the present disclosure, it is possible to realize a power amplifier semiconductor device that can suppress the influence of noise signals more than the conventional technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a diagram showing the structure of the power amplifying semiconductor device according to the first embodiment.

[0016] Figure 2This is a plan view showing an example of arrangement of substrate vias and semiconductor layer vias in a power amplifying semiconductor device according to a modification of the first embodiment.

[0017] Figure 3 This is a diagram showing the structure of a power amplifying semiconductor device according to the second embodiment.

[0018] Figure 4 This is a diagram showing the structure of a power amplifying semiconductor device according to the third embodiment.

[0019] Figure 5 This is a diagram showing the configuration of a power amplifying semiconductor device according to a modified example of the third embodiment.

[0020] Figure 6 It is a plan view showing the structure of a power amplifying semiconductor device according to a fourth embodiment.

[0021] Figure 7 It is a plan view showing an example of arrangement of substrate vias and semiconductor layer vias in the power amplifying semiconductor device according to the fourth embodiment.

[0022] Fig. 8A This is a plan view showing a first example of arrangement examples of substrate vias and semiconductor layer vias in a power amplifying semiconductor device according to a modification of the fourth embodiment.

[0023] Figure 8B This is a plan view showing a second example of the arrangement of substrate vias and semiconductor layer vias in the power amplifying semiconductor device according to the modification of the fourth embodiment.

[0024] Fig. 9 It is a plan view showing an example of arrangement of substrate via holes and bump openings in the power amplifying semiconductor device according to the fifth embodiment.

[0025] Fig.10 So Fig. 9 A cross-sectional view of the power amplifying semiconductor device according to Embodiment 5 cut along each section line.

[0026] Fig.11A This is a plan view showing a first example of the arrangement of substrate via holes and bump openings in the power amplifying semiconductor device according to the first modification of the fifth embodiment.

[0027] Fig. 11B 1 is a plan view showing a second example of the arrangement of substrate vias and bump openings in the power amplifying semiconductor device according to the first modification of the fifth embodiment.

[0028] Fig. 11CIt is a plan view showing a third example of the arrangement example of the substrate via holes and the bump openings in the power amplifying semiconductor device according to the first modification of the fifth embodiment.

[0029] Fig.11D 1 is a plan view showing a fourth example of the arrangement of substrate vias and bump openings in the power amplifying semiconductor device according to the first modification of the fifth embodiment.

[0030] Fig.12 This is a diagram showing the structure of a power amplifying semiconductor device according to a second variation of the fifth embodiment.

[0031] Fig.13 This is a diagram showing the structure of a power amplifying semiconductor device according to a third variation of the fifth embodiment.

[0032] Fig.14 This is a diagram showing the structure of a power amplification semiconductor device according to a fourth variation of the fifth embodiment.

[0033] Fig.15 This is a diagram showing the structure of a power amplification semiconductor device according to a fifth modification of the fifth embodiment.

[0034] Fig.16 It is a plan view showing the structure of a power amplifying semiconductor device according to a sixth embodiment.

[0035] Fig.17 It is a plan view showing a first example of the structure of a power amplifying semiconductor device according to a modification of the sixth embodiment.

[0036] Fig.18 It is a plan view showing a second example of the structure of the power amplifying semiconductor device according to the modification of the sixth embodiment.

[0037] Fig.19 It is a plan view showing a third example of the structure of the power amplifying semiconductor device according to the modification of the sixth embodiment.

[0038] Fig. 20A This is a first cross-sectional view for explaining the method for manufacturing the power amplifying semiconductor device according to the first embodiment.

[0039] Fig. 20B This is a second cross-sectional view for explaining the method for manufacturing the power amplifying semiconductor device according to the first embodiment.

[0040] Fig. 20C This is a third cross-sectional view for explaining the method for manufacturing the power amplifying semiconductor device according to the first embodiment.

[0041] Fig.20DThis is a fourth cross-sectional view for explaining the method for manufacturing the power amplifying semiconductor device according to the first embodiment.

[0042] Fig.21 1 is a cross-sectional view showing a power amplifying semiconductor device according to each embodiment mounted on a mounting substrate. DETAILED DESCRIPTION

[0043] The present disclosure relates to a power amplifier semiconductor device, and more particularly to a chip structure capable of suppressing the influence of noise from the outside, self-oscillation within the chip, and the influence of noise on peripheral chips in a flip-chip mounted semiconductor device.

[0044] As described in the "Background Art", the increase in operating frequency and / or output power is associated with an increase in noise signals generated by the device itself used as a high-frequency amplifier. For this reason, the noise signals generated by the working device will affect the surrounding components and may cause problems such as self-oscillation. Therefore, the suppression of noise signals is essential for high-frequency amplifiers installed in flip chips. However, the technology of Patent Document 1 does not disclose countermeasures for the influence of noise signals generated from the side of the chip on the surrounding components. In addition, the technology of Patent Document 1 is not sufficient for the countermeasures to avoid receiving noise signals from surrounding components.

[0045] Therefore, the present disclosure provides a power amplifier semiconductor device, which covers the ground potential in the active area of ​​the transistor and the periphery of each terminal through a bump, a substrate via structure, and a back electrode, thereby being able to suppress the noise generated by the transistor itself and avoid (suppress) the influence of noise from external components.

[0046] The following describes the embodiments of the present disclosure with reference to the accompanying drawings. In addition, the embodiments to be described below are all preferred specific examples of the present disclosure. Therefore, the numerical values, shapes, materials, constituent elements, configuration positions of constituent elements and connection methods, steps (processes) and the order of steps (processes) shown in the following embodiments are all examples, and their purpose is not to limit the present disclosure. Therefore, the constituent elements of the following embodiments that are not recorded in the independent technical solutions showing the highest concept of the present disclosure will be described as arbitrary constituent elements.

[0047] Furthermore, each figure is a schematic diagram, not a strict illustration. Therefore, the scales and the like in each figure are not necessarily the same. In each figure, substantially the same components are given the same reference numerals, and repeated descriptions are omitted or simplified.

[0048] In addition, in this specification and the accompanying drawings, the X-axis, Y-axis, and Z-axis represent three axes of a right-handed three-dimensional orthogonal coordinate system. In each embodiment, the Z-axis direction is set as the stacking direction of each layer of the power amplifying semiconductor device. In addition, the "plan view" in this specification refers to a view of the power amplifying semiconductor device along the stacking direction (Z-axis direction) of the power amplifying semiconductor device.

[0049] Furthermore, in this specification, terms such as parallel and orthogonal that indicate the relationship between elements, terms such as rectangle that indicate the shape of an element, and numerical values ​​and numerical ranges are not merely strict definitions but also include substantially equivalent ranges, for example, a difference of about a few percent (or about 10%).

[0050] Furthermore, in this specification, the terms "00 on (e.g., on a substrate)", "above" and "below" do not refer to the upper direction (vertically above) and the lower direction (vertically below) in absolute spatial recognition, but are terms defined by relative positional relationships based on the stacking order in the stacking structure. Furthermore, the terms "00 on (e.g., on a substrate)", "above" and "below" are not only applicable to the case where two components are arranged with a gap between them and there is another component between them, but also to the case where two components are arranged close to each other and are in contact with each other.

[0051] (Implementation Method 1)

[0052] [1-1. Configuration of Power Amplifier Semiconductor Device]

[0053] First, use Figure 1 The power amplifying semiconductor device 100 according to the first embodiment will be described. Figure 1 1 is a diagram showing a configuration of a power amplifying semiconductor device 100 according to the first embodiment. Figure 1 (a) shows a plan view of the power amplifying semiconductor device 100, Figure 1 (b) shows Figure 1 A cross-sectional view of the power amplifier semiconductor device 100 according to the first embodiment cut along the Ib-Ib section line of (a), Figure 1 (c) shows that Figure 1A cross-sectional view of the power amplifier semiconductor device 100 according to Embodiment 1 cut along the Ic-Ic section line of (a). The power amplifier semiconductor device 100 is a semiconductor device (semiconductor chip) that operates at a high frequency and is formed by connecting a plurality of unit HEMTs (High Electron Mobility Transistors) in parallel. High frequency refers to, for example, a frequency of 3 GHz or more, but is not limited thereto. High frequency is an electric wave, for example, including millimeter waves and electromagnetic waves. In addition, the unit HEMT includes one source electrode 301 (finger electrode), one drain electrode 302 (finger electrode), and one gate electrode 303 (finger electrode).

[0054] like Figure 1 As shown in (a) to (c), the power amplifier semiconductor device 100 includes: a substrate 101, a semiconductor epitaxial layer 102, a first insulating layer 201, a second insulating layer 202, a third insulating layer 203, a fourth insulating layer 204, a fifth insulating layer 205, a source electrode 301, a drain electrode 302, a gate electrode 303, a field plate electrode 304, an active region 401, an inactive region 402, a first wiring layer 501, a second wiring layer 502, a shielding wiring layer 503, an electrode-wiring opening connection portion 601, a wiring-wiring opening connection portion 602, a via-wiring opening connection portion 603, a source collecting portion 701, a drain collecting portion 702, a gate collecting portion 703, a source bump opening portion 801, a drain bump opening portion 802, a gate bump opening portion 803, a shielding bump opening portion 804, a substrate via 901, a semiconductor layer via 902, and a back electrode 103.

[0055] In addition, in this embodiment, the connection layer L1 including the source electrode 301, the drain electrode 302, and the gate electrode 303 constituting the unit HEMT is formed by the metal layer of the first insulating layer 201, the second insulating layer 202, the third insulating layer 203, and the fourth insulating layer 204 formed on the semiconductor epitaxial layer 102. In addition, in this embodiment, the terminal layer L2 including the source pad 701a, the drain pad 702a, and the gate pad 703a connected to the source electrode 301, the drain electrode 302, and the gate electrode 303 at a part of the wiring layer is formed by the metal layer of the fifth insulating layer 205 provided on the connection layer L1.

[0056] The substrate 101 is, for example, a substrate made of Si. A semiconductor epitaxial layer 102 is formed on a first main surface (front surface) of the substrate 101, and a back electrode 103 is formed on a second main surface (back surface) opposite to the first main surface. The substrate 101 is not limited to a substrate made of Si, and may also be a substrate made of sapphire, SiC, GaN, AlN, etc.

[0057] The semiconductor epitaxial layer 102 is formed on the front surface of the substrate 101 and is a layer for forming a plurality of unit HEMTs. The semiconductor epitaxial layer 102 can also be said to be a layer including a plurality of unit HEMTs. The semiconductor epitaxial layer 102 is an example of a semiconductor layer.

[0058] The semiconductor epitaxial layer 102 is, for example, a nitride semiconductor layer composed of a plurality of stacked structures of AlN and AlGaN with a thickness of 2 μm. The semiconductor epitaxial layer 102 has a two-dimensional electron gas layer (not shown) in the layer that becomes the carrier of the transistor. The formation of the carrier of the transistor can be achieved by ion implantation or doping based on the conditions for forming the epitaxial layer. In addition to the above-mentioned materials, the semiconductor epitaxial layer 102 can also be composed of semiconductor materials such as GaN, InGaN, InAlGaN, Si, SiC, GaAs, AlGaAs, InGaAs, InP, InN, etc.

[0059] The back electrode 103 is disposed on the back side of the substrate 101, and its potential is set to the same source potential as the source electrode 301. The back electrode 103 is an electrode in the form of a solid pattern (substantially a uniformly continuous planar (i.e. solid) pattern without gaps) covering the back side of the substrate 101, for example, covering the entire area of ​​the back side. The back electrode 103 can be, for example, any one of Ti, Al, W, Ta, Cu, Ni, Au, Sn, Ag, etc., or an alloy including at least one of them. Furthermore, the back electrode 103 can be a single-layer electrode film consisting of a single-layer structure, or a multi-layer electrode film consisting of a stacked structure in which a plurality of metal layers are stacked. In addition, being set to the source potential means that the source potential is provided.

[0060] The first insulating layer 201 is formed on the semiconductor epitaxial layer 102. The first insulating layer 201 is composed of SiN with a thickness of 30 nm, for example. Alternatively, the first insulating layer 201 may be composed of at least one of SiN, SiO2, SiON, SiC, C (diamond), AlN, and Al2O3.

[0061] The source electrode 301 and the drain electrode 302 are opened on the first insulating layer 201, so as to be disposed on the semiconductor epitaxial layer 102 in a manner facing each other. The source electrode 301 and the drain electrode 302 are, for example, a multilayer electrode film composed of a stacked structure in which a Ti film and an Al film are stacked in this order, but are not limited thereto. The source electrode 301 and the drain electrode 302 may be, for example, any one of Ti, Al, Ni, Au, Ta, W, Pd, Cu, etc., or an alloy including at least one of them. Furthermore, the source electrode 301 and the drain electrode 302 may also be a single-layer electrode film composed of a single-layer structure.

[0062] Furthermore, the source electrode 301 and the drain electrode 302 form ohmic contact with carriers of the transistor formed in the semiconductor epitaxial layer 102 .

[0063] Furthermore, a plurality of drain electrodes 302 are provided corresponding to the unit HEMTs.

[0064] The gate electrode 303 is disposed on the semiconductor epitaxial layer 102 and is located between the source electrode 301 and the drain electrode 302. The gate electrode 303 is, for example, a multilayer electrode film composed of a stacked structure in which a Ni film and an Au film are stacked in this order, but is not limited thereto. The gate electrode 303 may be, for example, any one of Ti, TiN, Ta, TaN, W, Ni, Pd, Au, Al, Cu, etc., or an alloy including at least one of them. Furthermore, the gate electrode 303 may be a single-layer electrode film composed of a single-layer structure.

[0065] The gate electrode 303 has a function of controlling the current flowing between the source electrode 301 and the drain electrode 302 by applying a voltage or current to the gate electrode 303 for carriers formed in the semiconductor epitaxial layer 102, and it can be a Schottky contact type through an opening of the first insulating layer 201, or a so-called MIS structure of a metal-insulator-semiconductor (Metal-Insulator-Semiconductor) without an opening on the first insulating layer 201. In addition, a plurality of gate electrodes 303 are provided corresponding to the unit HEMT.

[0066] The second insulating layer 202 is provided on the source electrode 301, the drain electrode 302, and the gate electrode 303, and is composed of, for example, SiN or SiO2 with a thickness of 150 nm. In addition, the second insulating layer 202 may also be composed of at least one of SiN, SiO2, SiON, SiC, C (diamond), AlN, and Al2O3.

[0067] The field plate electrode 304 is disposed on the second insulating layer 202, and is located on the drain electrode 302 side (positive side of the X axis) rather than the source electrode 301 side relative to the gate electrode 303 in a plan view, and is parallel to the long side direction (Y axis direction) of the gate electrode 303 in a plan view. The field plate electrode 304 is, for example, a multilayer electrode film composed of a stacked structure in which a Ti film and an Al film are stacked in this order, but is not limited thereto. The field plate electrode 304 can be, for example, any one of Ti, TiN, Ta, TaN, W, Ni, Pd, Au, Al, Cu, etc., or an alloy including at least one of them. Furthermore, the field plate electrode 304 can also be a single-layer electrode film composed of a single-layer structure.

[0068] In addition, although the field plate electrode 304 is Figure 1 Although it is connected to the same potential as the source electrode 301 , it may be connected to the same potential as the gate electrode 303 .

[0069] The third insulating layer 203 is disposed on the field plate electrode 304 and is composed of, for example, SiN or SiO2 with a thickness of 300 nm. In addition, the third insulating layer 203 may be composed of at least one of SiN, SiO2, SiON, SiC, C (diamond), AlN, and Al2O3.

[0070] The first wiring layer 501 is provided on the third insulating layer 203 and is a metal layer for connecting the electrodes. The first wiring layer 501 is, for example, a multilayer electrode film composed of a stacked structure in which a Ti film and an Al film are stacked in this order, but is not limited thereto. The first wiring layer 501 may also be composed of at least one of Al, Au, Cu, Ti, W, Ta, etc.

[0071] The electrode-wiring opening connection portion 601 is an opening on the second insulating layer 202 and the third insulating layer 203, and is used to connect the source electrode 301 and the first wiring layer 501, the drain electrode 302 and the first wiring layer 501, the gate electrode 303 and the first wiring layer 501, and the field plate electrode 304 and the first wiring layer 501 respectively.

[0072] The fourth insulating layer 204 is disposed on the first wiring layer 501 and is composed of, for example, SiN or SiO2 with a thickness of several μm (eg, 1 μm). The fourth insulating layer 204 may also be composed of at least one of SiN, SiO2, SiON, SiC, C (diamond), AlN, and Al2O3.

[0073] The second wiring layer 502 is disposed on the fourth insulating layer 204, and is, for example, a multilayer electrode film composed of a stacked structure in which a Ti film and an Al film are stacked in this order, but the invention is not limited thereto. The second wiring layer 502 may also be composed of at least one of Al, Au, Cu, Ti, W, Ta, etc. Furthermore, although the second wiring layer 502 is composed of the same metal as the first wiring layer 501, it may also be composed of a metal different from the first wiring layer 501.

[0074] The wiring-to-wiring opening connection portion 602 is an opening provided in the fourth insulating layer 204 and is used to connect the first wiring layer 501 and the second wiring layer 502 .

[0075] The source collecting portion 701 collects the potential of the source electrode 301 in the first wiring layer 501 and the second wiring layer 502 via the electrode-wiring opening connection portion 601 and the wiring-wiring opening connection portion 602. In the source collecting portion 701, a plurality of source electrodes 301 are collectively connected to the wiring (that is, a plurality of source electrodes 301 are collected and connected via the wiring). That is, the source collecting portion 701 is electrically connected to each of the plurality of source electrodes 301, and can provide the same potential to each of the plurality of source electrodes 301. In this embodiment, the source collecting portion 701 is within the active region 401, and in the first wiring layer 501 and the second wiring layer 502, the source electrode 301 and the field plate electrode 304 are collected via the electrode-wiring opening connection portion 601 and the wiring-wiring opening connection portion 602.

[0076] Furthermore, the source collecting portion 701 is provided on the connection layer L1, and has a source pad 701a connected to the source electrode 301, the drain electrode 302, and the gate electrode 303, respectively, at a portion of the wiring layer. The source pad 701a is a portion of the source collecting portion 701 that is exposed through the source bump opening 801, and the source bump opening 801 is an opening formed in the fifth insulating layer 205, and the source pad 701a is a portion that is electrically connected to a mounting substrate or a semiconductor package outside the chip through a bump metal disposed in the source bump opening 801.

[0077] The drain collecting portion 702 collects the potential of the drain electrode 302 in the first wiring layer 501 and the second wiring layer 502 via the electrode-wiring opening connection portion 601 and the wiring-wiring opening connection portion 602. In the drain collecting portion 702, a plurality of drain electrodes 302 are collectively connected to wiring in a part of the wiring layer (i.e., they are collectively connected through wiring in a part of the wiring layer). That is, the drain collecting portion 702 is electrically connected to each of the plurality of drain electrodes 302, and can provide the same potential to each of the plurality of drain electrodes 302.

[0078] Furthermore, the drain collecting portion 702 is within the inactive region 402 in a direction (Y-axis direction) parallel to the long side direction of the gate electrode 303 within the active region 401 when viewed from the source collecting portion 701, and in the first wiring layer 501 and the second wiring layer 502, the drain electrode 302 is collected via the electrode-wiring opening connection portion 601 and the wiring-wiring opening connection portion 602.

[0079] Furthermore, the drain collecting portion 702 is provided on the connection layer L1, and has a drain pad 702a connected to the source electrode 301, the drain electrode 302, and the gate electrode 303, respectively, at a part of the wiring layer. The drain pad 702a is a portion of the drain collecting portion 702 that is exposed through the drain bump opening 802 formed in the fifth insulating layer 205, and is a portion that is electrically connected to the mounting substrate outside the chip through the bump metal disposed in the drain bump opening 802.

[0080] The gate collection portion 703 is a portion that collects the potential of the gate electrode 303 via the electrode-wiring opening connection portion 601 and the wiring-wiring opening connection portion 602 in the first wiring layer 501 and the second wiring layer 502. In the gate collection portion 703, a plurality of gate electrodes 303 are collectively connected to wiring in a part of the wiring layer (i.e., they are collectively connected through wiring in a part of the wiring layer). That is, the gate collection portion 703 is electrically connected to each of the plurality of gate electrodes 303, and can provide the same potential to each of the plurality of gate electrodes 303.

[0081] Furthermore, the gate collection portion 703 is within the inactive region 402 in the Y-axis direction opposite to the drain collection portion 702 when viewed from the source collection portion 701, and in the first wiring layer 501 and the second wiring layer 502, the gate electrode 303 is collected via the electrode-wiring opening connection portion 601 and the wiring-wiring opening connection portion 602.

[0082] Furthermore, the gate collecting portion 703 has a gate pad 703a provided on the connection layer L1 and connected to a portion of the wiring layer of the source electrode 301, the drain electrode 302, and the gate electrode 303. The gate pad 703a is a portion of the gate collecting portion 703 that is exposed through the gate bump opening 803 formed in the fifth insulating layer 205, and is a portion that is electrically connected to the mounting substrate outside the chip through the bump metal disposed in the gate bump opening 803.

[0083] In addition, although the source collecting portion 701 , the drain collecting portion 702 , and the gate collecting portion 703 are rectangular in plan view, they are not limited thereto.

[0084] The fifth insulating layer 205 is provided on the second wiring layer 502, and is formed by laminating, for example, an organic resin film having a thickness of 6 μm on SiN having a thickness of 800 nm. In addition, the fifth insulating layer 205 may also be formed by at least one of SiN, SiO2, SiON, SiC, C (diamond), AlN, and Al2O3.

[0085] The fifth insulating layer 205 is formed with: a source bump opening 801 opened on the fifth insulating layer 205 to expose the source collecting portion 701 , a drain bump opening 802 opened on the fifth insulating layer 205 to expose the drain collecting portion 702 , and a gate bump opening 803 opened on the fifth insulating layer 205 to expose the gate collecting portion 703 .

[0086] The shield wiring layer 503 has the function of shielding noise (electromagnetic shielding), and is composed of a first wiring layer 501 and a second wiring layer 502. The shield wiring layer 503 is a wiring layer having the same potential as the source electrode 301. The shield wiring layer 503 is provided in a manner to surround at least one of the drain collecting portion 702 and the gate collecting portion 703 in a plan view at the position of the connection layer in the vertical direction (Z-axis direction) relative to the surface of the substrate 101. Furthermore, the shield wiring layer 503 is provided in a manner to surround at least one of the drain pad 702a and the gate pad 703a in a plan view.

[0087] The via-to-wiring opening connection portion 603 is opened on the first insulating layer 201 , the second insulating layer 202 , and the third insulating layer 203 , and connects the first wiring layer 501 and the semiconductor layer via 902 .

[0088] The shield bump opening 804 is a portion opened in the fifth insulating layer 205 to expose the shield wiring layer 503 , and is a portion electrically connected to a ground electrode of a mounting substrate outside the chip via a bump metal arranged in the shield bump opening 804 .

[0089] The substrate via 901 is arranged in a manner to surround at least one of the drain collecting portion 702 and the gate collecting portion 703 (for example, in four directions) in a plan view. In the present embodiment, it is arranged to surround the gate collecting portion 703 in the inactive region 402. The substrate via 901 is a through hole that opens on the substrate 101 and reaches the back electrode 103, and is configured to include a portion of the wiring layer set to the source potential, namely, a shielding wiring layer (for example, at least one of the first wiring layer 501 and the second wiring layer 502) on its inner wall. The plan view shape of the substrate via 901 is, for example, a rectangle, but is not limited thereto. In addition, for example, a plurality of substrate vias 901 are arranged.

[0090] like Figure 1 As shown in (a), the substrate vias 901 under the shield wiring layer 503 are arranged discontinuously. In the plan view, the opening contour of the substrate via 901 has a discontinuous portion 911. In other words, the substrate vias 901 are not arranged in a manner to continuously surround the gate collection portion 703. For example, around the gate collection portion 703, the substrate vias 901 and the discontinuous portions 911 are alternately arranged. In addition, at least one discontinuous portion 911 may be provided.

[0091] The semiconductor layer via 902 is arranged to surround at least one of the drain collecting portion 702 and the gate collecting portion 703 in a plan view. In this embodiment, the semiconductor layer via 902 penetrates the semiconductor epitaxial layer 102 and has a shield wiring layer 503 on the inner wall. The semiconductor layer via 902 is a through hole that opens on the semiconductor epitaxial layer 102 and reaches the substrate 101. In this embodiment, the semiconductor layer via 902 is formed in a ring shape surrounding the gate collecting portion 703. And the semiconductor layer via 902 is configured in plurality, for example.

[0092] The power amplifying semiconductor device 100 having the above-described structure is divided into an active region 401 having a two-dimensional electron gas layer formed in the semiconductor epitaxial layer 102 and an inactive region 402 having no two-dimensional electron gas layer.

[0093] The active region 401 is a region where a two-dimensional electron gas layer exists in a plan view (region on the substrate 101 ). A HEMT (high frequency amplification amplifier) ​​including at least a source electrode 301 , a drain electrode 302 , and a gate electrode 303 is formed in the active region 401 .

[0094] The inactive region 402 is a region on the substrate 101 outside the active region 401, and is a region where the two-dimensional electron gas layer does not exist. The inactive region 402 can be formed by, for example, injecting molecules including any one of He, B, H, F, and Fe. In addition, the meaning of the absence of a two-dimensional electron gas layer includes not only the complete absence of electrons, but also the case where electrons substantially do not exist.

[0095] [1-2. Effects, etc.]

[0096] As described above, the power amplifier semiconductor device 100 according to the first embodiment is a power amplifier semiconductor device that operates at a frequency of 3 GHz or higher, in which a plurality of unit HEMTs (High Electron Mobility Transistors) are connected in parallel, and includes: a substrate 101; a semiconductor epitaxial layer 102 (an example of a semiconductor layer), which is provided on the surface of the substrate 101 and includes a plurality of unit HEMTs; a connection layer L1, which is provided on the semiconductor epitaxial layer 102 and includes a source electrode 301, a drain electrode 302, and a gate electrode 303 of the unit HEMT; a terminal layer L2, which is provided on the connection layer L1 and includes a source pad 701a, a drain pad 702a, and a gate pad 703a connected to the source electrode 301, the drain electrode 302, and the gate electrode 303 via a first portion of a wiring layer; and a back electrode 103, which is provided on the back surface of the substrate 101 and has a potential set The power amplifier semiconductor device 100 has a source potential that is the same as that of the source electrode 301; and a substrate via 901 that passes through the substrate 101, and a shielding wiring layer 503 is provided on the inner wall of the substrate via 901, and the shielding wiring layer 503 is the second part of the wiring layer set to the source potential. The drain electrode 302 and the gate electrode 303 are respectively multiple corresponding to the unit HEMT, and the power amplifier semiconductor device 100 has: a drain collection part 702, which is used for the multiple drain electrodes 302 to be collectively connected to the wiring at the third part of the wiring layer; and a gate collection part 703, which is used for the multiple gate electrodes 303 to be collectively connected to the wiring at the fourth part of the wiring layer. In the plan view of the substrate 101, the drain collection part 702 and the gate collection part 703 are surrounded by the substrate via 901.

[0097] According to this, when the substrate via 901 is arranged so as to surround the gate collecting portion 703, it is possible to suppress the noise received by the gate collecting portion 703 through the substrate 101. Furthermore, when the substrate via 901 is arranged so as to surround the drain collecting portion 702, it is possible to suppress the noise radiated from the drain collecting portion 702 through the substrate 101, thereby suppressing the transmission of noise to the gate collecting portion 703 or the radiation of noise to components outside the power amplifier semiconductor device 100. According to this, the power amplifier semiconductor device 100 can suppress the influence of noise signals compared with the related art.

[0098] Furthermore, the power amplifying semiconductor device 100 may include a semiconductor layer via 902 that penetrates the semiconductor epitaxial layer 102, and a shielding wiring layer 503 is provided on the inner wall of the semiconductor layer via 902, and in a plan view, either or both of the drain collecting portion 702 and the gate collecting portion 703 are surrounded by the semiconductor layer via 902.

[0099] According to this, when the semiconductor layer via 902 is arranged so as to surround the gate collection portion 703, it is possible to suppress the noise transmitted through the semiconductor epitaxial layer 102 and received by the gate collection portion 703. Furthermore, when the semiconductor layer via 902 is arranged so as to surround the drain collection portion 702, it is possible to suppress the noise transmitted through the semiconductor epitaxial layer 102 and radiated from the drain collection portion 702, thereby suppressing the transmission of noise to the gate collection portion 703 or the radiation of noise to components outside the power amplifier semiconductor device 100. According to this, the power amplifier semiconductor device 100 can suppress the influence of noise signals compared with the related art.

[0100] Furthermore, at the position of the connection layer L1 in the vertical direction with respect to the front surface of the substrate 101 , one or both of the drain collection portion 702 and the gate collection portion 703 may be surrounded by the shield wiring layer 503 in a plan view.

[0101] According to this, when the shield wiring layer 503 is arranged so as to surround the gate collection portion 703, it is possible to suppress the noise received by the gate collection portion 703 through the fourth insulating layer 204 from the first insulating layer 201. Furthermore, when the shield wiring layer 503 is arranged so as to surround the drain collection portion 702, it is possible to suppress the noise radiated from the drain collection portion 702 through the fourth insulating layer 204 from the first insulating layer 201, thereby suppressing the transmission of noise to the gate collection portion 703 or the radiation of noise to components outside the power amplifier semiconductor device 100. According to this, the power amplifier semiconductor device 100 can further suppress the influence of noise signals compared with the related art.

[0102] Furthermore, in a plan view, one or both of the drain pad 702 a and the gate pad 703 a may be surrounded by the shield wiring layer 503 .

[0103] According to this, when the shield bump opening 804 is arranged so as to surround the gate collection part 703, since the bump metal arranged in the shield bump opening 804 surrounds the gate collection part 703, it is possible to suppress the noise received by the gate collection part 703 through the fifth insulating layer 205. In addition, when the shield bump opening is arranged so as to surround the drain collection part 702, since the bump metal arranged in the shield bump opening 804 surrounds the drain collection part 702, it is possible to suppress the noise radiated from the drain collection part 702 through the fifth insulating layer 205, thereby suppressing the noise transmission to the gate collection part 703 or the noise radiation to the components outside the power amplifier semiconductor device 100. According to this, the power amplifier semiconductor device 100 can further suppress the influence of the noise signal compared with the related art.

[0104] Furthermore, in a plan view, the opening contour of the substrate via hole 901 may have a discontinuous portion 911 (an example of a first discontinuous portion).

[0105] Accordingly, since the substrate vias 901 under the shield wiring layer 503 are arranged discontinuously, when the substrate vias 901 surround the gate collection section 703 or the drain collection section 702 , the gate collection section 703 and the drain collection section 702 can be prevented from falling off the substrate 101 .

[0106] (Variation of Implementation Example 1)

[0107] The following reference Figure 2 A power amplifier semiconductor device according to a modification of the first embodiment will be described. Figure 2 1 is a plan view showing an example of arrangement of substrate vias 901 and semiconductor layer vias 902 in a power amplifying semiconductor device according to a modification of Embodiment 1. In addition, the following description will focus on the differences from Embodiment 1, and the description of the same or similar contents as Embodiment 1 will be omitted or simplified. The power amplifying semiconductor device according to this modification is different from the power amplifying semiconductor device 100 according to Embodiment 1 in the arrangement of the semiconductor layer vias 902.

[0108] like Figure 2 As shown, in the power amplifying semiconductor device involved in this variation, the semiconductor layer via 902 under the shield wiring layer 503 is also non-continuously configured as the substrate via 901. In the plan view, the opening contour of the semiconductor layer via 902 has a non-continuous portion 912. In other words, the semiconductor layer via 902 is not configured in a manner to continuously surround the gate collecting portion 703. For example, the semiconductor layer via 902 may be configured corresponding to the substrate via 901, and the non-continuous portion 912 may be configured corresponding to the non-continuous portion 911. For example, in the plan view, the semiconductor layer via 902 may be configured in a manner to at least partially overlap with the substrate via 901, and the non-continuous portion 912 may be configured in a manner to at least partially overlap with the non-continuous portion 911.

[0109] Furthermore, in a plan view, the opening contour of the semiconductor layer via hole 902 has a discontinuous portion 912 (an example of a second discontinuous portion).

[0110] This can prevent the gate collecting portion 703 and the drain collecting portion 702 from falling off the substrate 101. Furthermore, since the shield bump openings 804 are arranged discontinuously, bumps such as ball bumps that cannot be arranged in a continuous pattern can be used.

[0111] (Implementation Method 2)

[0112] [2-1. Configuration of power amplifier semiconductor device]

[0113] Next, use Figure 3 A power amplifying semiconductor device 200 according to Embodiment 2 will be described. In this embodiment, detailed description of components common to those in Embodiment 1 will be omitted. Figure 3 This is a diagram showing the configuration of a power amplifying semiconductor device 200 according to the second embodiment. Figure 3 (a) is a plan view of the power amplifier semiconductor device 200. Figure 3 (b) is based on Figure 3 A cross-sectional view of the power amplifier semiconductor device 200 according to the second embodiment cut along the IIIb-IIIb section line of (a), Figure 3 (c) is based on Figure 3 1 is a cross-sectional view of the power amplifying semiconductor device 200 according to Embodiment 2 cut along the IIIc-IIIc section line of (a). The power amplifying semiconductor device 200 is different from the power amplifying semiconductor device 100 according to Embodiment 1 in that the substrate via 901 is arranged to surround the drain collecting portion 702.

[0114] like Figure 3 As shown, the power amplifier semiconductor device 200 comprises: a back electrode 103 formed on the back side of the substrate 101; a substrate via 901 arranged in the inactive region 402 so as to surround the drain collecting portion 702 and opening on the substrate 101 to reach the back electrode 103; a semiconductor layer via 902 opening on the semiconductor epitaxial layer 102 and reaching the substrate 101; a via-wiring opening connection portion 603 opening on the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 to connect the first wiring layer 501 and the semiconductor layer via 902; a shielding wiring layer 503 composed of the first wiring layer 501 and the second wiring layer 502; and a shielding bump opening portion 804 opening on the fifth insulating layer 205 to expose the shielding wiring layer 503.

[0115] Thus, the substrate via 901, the semiconductor layer via 902 and the shield wiring layer 503 can be arranged to surround the drain collecting portion 702 in a plan view. Alternatively, at least one of the substrate via 901, the semiconductor layer via 902 and the shield wiring layer 503 can be arranged to surround the drain collecting portion 702.

[0116] According to this, noise transmitted through the substrate 101 and received by the gate collecting portion 703 can be suppressed, and noise transmitted through the substrate 101 and radiated from the drain collecting portion 702 can be suppressed.

[0117] (Implementation method 3)

[0118] [3-1. Configuration of power amplifier semiconductor device]

[0119] Next, use Figure 4 A power amplifying semiconductor device 300 according to the third embodiment will be described. Figure 4 This is a diagram showing the configuration of a power amplifying semiconductor device 300 according to the third embodiment. Figure 4 (a) is a plan view of the power amplifier semiconductor device 300. Figure 4 (b) is based on Figure 4 A cross-sectional view of the power amplifier semiconductor device 300 according to the third embodiment cut along the IVb-IVb section line of (a), Figure 4 (c) is based on Figure 4 1 is a cross-sectional view of the power amplifying semiconductor device 300 according to Embodiment 3 cut along the IVc-IVc section line of (a). The power amplifying semiconductor device 300 is different from the power amplifying semiconductor device 100 according to Embodiment 1 in that the substrate via 901 and the like are arranged so as to surround the drain collecting portion 702 and the gate collecting portion 703, respectively.

[0120] like Figure 4 As shown, the power amplifier semiconductor device 300 comprises: a back electrode 103 formed on the back side of the substrate 101; a substrate via 901 arranged in the inactive region 402 to surround the gate collecting portion 703 and the drain collecting portion 702, and opening on the substrate 101 to reach the back electrode 103; a semiconductor layer via 902 opening on the semiconductor epitaxial layer 102 to reach the substrate 101; a via-wiring opening connection portion 603 opening on the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 to connect the first wiring layer 501 and the semiconductor layer via 902; a shielding wiring layer 503 composed of the first wiring layer 501 and the second wiring layer 502; and a shielding bump opening portion 804 opening on the fifth insulating layer 205 to expose the shielding wiring layer 503.

[0121] The substrate via 901, the semiconductor layer via 902, and the shield wiring layer 503 may also be arranged to surround the drain collecting portion 702 and the gate collecting portion 703 in a plan view. Alternatively, at least one of the substrate via 901, the semiconductor layer via 902, and the shield wiring layer 503 may be arranged to surround the drain collecting portion 702 and the gate collecting portion 703.

[0122] [3-2. Effects, etc.]

[0123] As described above, in the power amplifying semiconductor device 300 according to the third embodiment, the drain collection portion 702 and the gate collection portion 703 may be surrounded by the substrate via 901 in a plan view.

[0124] According to this, since the substrate via 901 is arranged so as to surround the drain collecting portion 702 and the gate collecting portion 703, it is possible to suppress the noise transmitted through the substrate 101 and received by the gate collecting portion 703, and it is possible to suppress the emission of noise from the drain collecting portion 702. The suppression of noise emission is related to the suppression of noise emission from the power amplifier semiconductor device 300 to external components.

[0125] Furthermore, in a plan view, the drain collecting portion 702 and the gate collecting portion 703 may be surrounded by the semiconductor layer via 902 .

[0126] Accordingly, since the semiconductor layer via 902 is arranged to surround the drain collecting portion 702 and the gate collecting portion 703 , it is possible to suppress noise from being received by the gate collecting portion 703 through the semiconductor epitaxial layer 102 , and suppress noise from being radiated from the drain collecting portion 702 .

[0127] Furthermore, in a plan view, the drain collection portion 702 and the gate collection portion 703 may be surrounded by the shield wiring layer 503 .

[0128] Thus, since the shield wiring layer 503 is arranged to surround the gate collection portion 703 and the drain collection portion 702 , it is possible to prevent noise from being received by the gate collection portion 703 through the fourth insulating layer 204 from the first insulating layer 201 and being radiated from the drain collection portion 702 .

[0129] Furthermore, in a plan view, the drain pad 702 a and the gate pad 703 a may be surrounded by the shield wiring layer 503 .

[0130] Accordingly, since the shielding bump opening portion 804 is configured in a manner of surrounding the gate collecting portion 703 and the drain collecting portion 702, the bump metal configured in the shielding bump opening portion 804 can surround the gate collecting portion 703 and the drain collecting portion 702, thereby suppressing noise from being received by the gate collecting portion 703 through the fifth insulating layer 205 and being radiated from the drain collecting portion 702.

[0131] (Variation of Implementation Example 3)

[0132] The following use Figure 5 A power amplifier semiconductor device according to a modification of the third embodiment will be described. Figure 5This is a diagram showing a configuration of a power amplifying semiconductor device 400 according to a modification of the third embodiment. Figure 5 (a) is a plan view of the power amplifier semiconductor device 400. Figure 5 (b) is based on Figure 5 A cross-sectional view of a power amplifier semiconductor device 400 according to a modification of the third embodiment, taken along the Vb-Vb section line of (a); Figure 5 (c) is based on Figure 5 1 is a cross-sectional view of a power amplifying semiconductor device 400 according to a modification of Embodiment 3 cut along the Vc-Vc section line of (a). The power amplifying semiconductor device 400 is different from the power amplifying semiconductor device 300 according to Embodiment 3 in that, in addition to the drain collecting portion 702 and the gate collecting portion 703, a substrate via 901 and the like are arranged so as to surround the source collecting portion 701.

[0133] like Figure 5 As shown, the substrate via 901 , the semiconductor layer via 902 and the shield wiring layer 503 may also be arranged to surround the source collecting portion 701 , the drain collecting portion 702 and the gate collecting portion 703 respectively in a plan view.

[0134] As a result, the same effects as those of the power amplifying semiconductor device 400 according to the third embodiment can be obtained.

[0135] (Implementation 4)

[0136] [4-1. Configuration of power amplifier semiconductor device]

[0137] Next, use Figure 6 as well as Figure 7 A power amplifying semiconductor device according to a fourth embodiment will be described. Figure 6 It is a plan view showing the structure of a power amplifying semiconductor device 500 according to the fourth embodiment. Figure 7 1 is a plan view showing an example of arrangement of substrate vias 901 and semiconductor layer vias 902 in the power amplifying semiconductor device 500 according to the fourth embodiment.

[0138] The power amplifying semiconductor device 500 is different from the power amplifying semiconductor device 400 according to the modification of the third embodiment in that the substrate via 901 and the semiconductor layer via 902 are formed in duplicate. In addition, although the arrangement example of the substrate via 901 and the semiconductor layer via 902 according to the present embodiment is described below using the power amplifying semiconductor device 400 according to the modification of the third embodiment, the arrangement example of the substrate via 901 and the semiconductor layer via 902 according to the present embodiment can also be applied to the above-mentioned embodiments and modifications.

[0139] like Figure 6 As shown, the power amplifier semiconductor device 500 is configured such that, in a plan view, the plurality of substrate vias 901 are formed into two or more substrate via columns. In a plan view, the squares formed by the substrate vias 901 of the source collecting portion 701, the drain collecting portion 702, and the gate collecting portion 703 can also be said to be formed into a plurality of columns.

[0140] like Figure 7 As shown, the two or more substrate via columns include a first substrate via column 921a and a second substrate via column 921b. In addition, there may be three or more substrate via columns. Also, the semiconductor layer via 902 is similar to the substrate via 901. In a plan view, the semiconductor layer via 902 is configured such that the plurality of semiconductor layer vias 902 are formed into two or more semiconductor layer via columns.

[0141] The first substrate via array 921a and the second substrate via array 921b are arranged so that when the inner central position (e.g., the central position of any one of the source collecting portion 701, the drain collecting portion 702, and the gate collecting portion 703) is viewed from the outer position of two or more substrate via arrays (e.g., the position on the negative side of the X-axis), the discontinuous portions 911a and 911b of each via array do not overlap with each other. The substrate vias 901 of the first substrate via array 921a and the second substrate via array 921b are arranged in an alternating (zigzag) manner. Furthermore, the substrate vias 901 under the shielding wiring layer 503 are arranged discontinuously and staggered with each other in multiple layers.

[0142] Furthermore, the substrate via holes 901 of the first substrate via hole row 921a and the second substrate via hole row 921b are arranged in the via hole row arrangement direction ( Figure 7 For example, the length of the substrate via hole 901 in the Y-axis direction may be longer than the length of the discontinuous portions 911a and 911b in the Y-axis direction.

[0143] The first semiconductor layer via hole column 922a and the second semiconductor layer via hole column 922b are arranged so that when the inner central position (for example, the central position of any one of the source collecting portion 701, the drain collecting portion 702 and the gate collecting portion 703) is viewed from the outer position of two or more via hole columns (for example, the position on the negative side of the X axis), the discontinuous portions 912a and 912b of each via hole column do not overlap each other. The semiconductor layer via holes 902 of the first semiconductor layer via hole column 922a and the second semiconductor layer via hole column 922b are arranged alternately (in a zigzag shape). In addition, the semiconductor layer via holes 902 can also be said to be arranged discontinuously and staggered in multiple layers.

[0144] Furthermore, the semiconductor layer via holes 902 of the first semiconductor layer via hole column 922a and the second semiconductor layer via hole column 922b are arranged in the arrangement direction of the via hole columns ( Figure 7 For example, the length of the semiconductor layer via 902 in the Y-axis direction may be longer than the length of the discontinuous portions 912a and 912b in the Y-axis direction.

[0145] Furthermore, for example, the shield bump openings 804 may be similarly arranged in multiple numbers in a discontinuous and staggered manner.

[0146] [4-2. Effects, etc.]

[0147] As described above, in the power amplifying semiconductor device 500 involved in the fourth embodiment, in a plan view, each collecting portion is surrounded by substrate vias 901 arranged in a plurality of rows, and when the inner central position is viewed from the outer position of the substrate vias 901 arranged in a plurality of rows, the plurality of rows of substrate vias 901 are arranged in such a manner that the discontinuous portions 911a and 911b (an example of a first discontinuous portion) of each row do not overlap with each other.

[0148] According to this, since the substrate vias 901 under the shield wiring layer 503 are arranged in multiple numbers in a discontinuous and staggered manner, there is an effect of suppressing the leakage or intrusion of noise through the gaps of the discontinuous substrate vias 901 .

[0149] Furthermore, in a planar view, each gathering portion is surrounded by semiconductor layer vias 902 arranged in multiple columns, and when an inner central position is viewed from an outer position of the semiconductor layer vias 902 arranged in multiple columns, the semiconductor layer vias 902 are arranged in multiple columns in such a manner that the non-continuous portions 912a and 912b (an example of a second non-continuous portion) of each column do not overlap with each other.

[0150] According to this, since the shield bump openings 804 are arranged discontinuously and in a multi-staggered manner, there is an effect of suppressing the leakage or intrusion of noise through the gaps of the bump metal arranged inside the discontinuous shield bump openings 804 .

[0151] (Variation of Implementation Example 4)

[0152] Next, use Fig. 8A as well as Figure 8B A power amplifier semiconductor device according to a modification of the fourth embodiment will be described. Fig. 8A as well as Figure 8B The diagrams are plan views showing examples of arrangement of substrate vias and semiconductor layer vias in a power amplifying semiconductor device according to a modification of the fourth embodiment.

[0153] like Fig. 8AAs shown, the plan view shape (shape of the opening portion outline) of the substrate via 901a has one or more curved portions 901a1, which are curved portions. In this way, the substrate via 901a can be arranged relative to the arrangement direction of the substrate vias 901a in the substrate via column ( Fig. 8A In the example, it is formed by a combination of a portion parallel to the Y-axis direction) and a portion bent relative to the arrangement direction.

[0154] The bent portion 901a1 is bent in a direction that intersects (e.g., is orthogonal to) the parallel partial direction and is bent toward the other substrate via column side. For example, the bent portion 901a1 of the substrate via 901a included in the first substrate via column 921a is bent toward the second substrate via column 921b side ( Fig. 8A In the example, the bending is on the positive side of the X-axis).

[0155] The bent portion 901a1 bends from the ends (e.g., both ends) of the parallel portion toward the other substrate via row. Also, the bent portion 901a1 of the substrate via 901a in the first substrate via row 921a and the bent portion 901a1 of the substrate via 901a in the second substrate via row 921b at least partially face each other.

[0156] Furthermore, the plan view shape of the substrate vias 901a in the first substrate via hole row 921a and the plan view shape of the substrate vias 901a in the second substrate via hole row 921b are, for example, point-symmetrical shapes.

[0157] And, if Fig. 8A As shown, the plan view shape (shape of the opening outline) of the semiconductor layer via 902a is the same as that of the substrate via 901a, and has one or more curved portions 902a1, which are curved portions. In this way, the semiconductor layer via 902a can be arranged relative to the arrangement direction ( Fig. 8A In the example, it is formed by a combination of a portion parallel to the Y-axis direction) and a portion bent relative to the arrangement direction.

[0158] The bent portion 902a1 is bent in a direction intersecting the parallel portion in a plan view and is bent toward the other semiconductor layer via column side. For example, the bent portion 902a1 of the semiconductor layer via 902a in the second semiconductor layer via column 922b is bent toward the second semiconductor layer via column 922b side ( Fig. 8A In the example, the bending is on the positive side of the X-axis).

[0159] The bent portion 902a1 bends from the ends (e.g., both ends) of the parallel portion toward the other semiconductor layer via column side. Furthermore, the bent portion 902a1 of the semiconductor layer via 902a in the first semiconductor layer via column 922a and the bent portion 902a1 of the semiconductor layer via 902a in the second semiconductor layer via column 922b at least partially face each other.

[0160] Furthermore, the plan view shape of the semiconductor layer vias 902a in the first semiconductor layer via column 922a and the plan view shape of the semiconductor layer vias 902a in the second semiconductor layer via column 922b are, for example, point-symmetrical shapes.

[0161] Furthermore, the substrate via 901 a and the semiconductor layer via 902 a have corresponding shapes (shapes having a curved portion), and are arranged so as to at least partially overlap each other in a plan view.

[0162] like Figure 8B As shown, the plan view shape (shape of the opening portion outline) of the substrate via 901b has one or more branch portions 901b1, and the one or more branch portions 901b1 are branched portions. In this way, the substrate via 901b can be arranged relative to the arrangement direction of the substrate via 901b in the substrate via column ( Figure 8B In the example, it is formed by a combination of a portion parallel to the Y-axis direction) and branch portions 901b1 that branch off and protrude from both ends of the parallel portion.

[0163] The branch portions 901b1 branch from the ends (e.g., both ends) of the parallel portions in a plan view to form a Y-shape. Also, the branch portions 901b1 of the substrate vias 901b in the first substrate via array 921a and the branch portions 901b1 of the substrate vias 901b in the second substrate via array 921b at least partially face each other.

[0164] And if Figure 8B As shown, the plan view shape (shape of the opening outline) of the semiconductor layer via 902b is the same as that of the substrate via 901b, and has one or more branch portions 902b1, which are branched portions. In this way, the semiconductor layer via 902b can be arranged relative to the arrangement direction of the semiconductor layer via 902b in the semiconductor layer via column ( Fig. 8A In the example, it is formed by a combination of a portion parallel to the Y-axis direction) and branch portions 902b1 that branch off and protrude from both ends of the parallel portion.

[0165] The branch portions 902b1 protrude from the ends (e.g., both ends) of the parallel portions in a plan view to form a Y-shape. Furthermore, the branch portions 902b1 of the semiconductor layer vias 902b in the first semiconductor layer via array 922a and the branch portions 902b1 of the semiconductor layer vias 902b in the second semiconductor layer via array 922b at least partially face each other.

[0166] As described above, in the power amplifying semiconductor device according to the modification of Embodiment 4, the opening contour of the substrate vias 901a and 901b may have a plurality of curved portions 901a1 or a plurality of branch portions 901b1 in a plan view. Also, the opening contour of the semiconductor layer vias 902a and 902b may have a plurality of curved portions 902a1 or a plurality of branch portions 902b1 in a plan view.

[0167] According to this, the effect of suppressing the leakage of noise or the intrusion of noise can be enhanced by the combination of meander patterns or the combination of branch patterns.

[0168] (Implementation method 5)

[0169] [5-1. Configuration of power amplifier semiconductor device]

[0170] Next, use Fig. 9 as well as Fig.10 A power amplifying semiconductor device according to the fifth embodiment will be described. Fig. 9 1 is a plan view showing an example of arrangement of substrate vias 901 and shield bump openings 804 in the power amplifying semiconductor device according to the fifth embodiment.

[0171] like Fig. 9 As shown, in the power amplifying semiconductor device according to the fifth embodiment, the substrate vias 901 under the shield wiring layer 503 (including the second wiring layer 502) are arranged in multiple numbers in a non-continuous and staggered manner, and the shield bump openings 804 are arranged in multiple numbers in a non-continuous and staggered manner. The power amplifying semiconductor device according to the fifth embodiment has the power amplifying semiconductor device 500 according to the fourth embodiment, and further has shield bump openings 804 arranged in a staggered manner (zigzag shape) in the first substrate via column 921a and the second substrate via column 921b.

[0172] In the first substrate via hole row 921a and the second substrate via hole row 921b, the arrangement intervals of the substrate via holes 901 and the arrangement intervals of the shield bump openings 804 are different. Therefore, the area where only the substrate via holes 901 are arranged, the area where only the shield bump openings 804 are arranged, and the area where both the substrate via holes 901 and the shield bump openings 804 overlap are mixed in the plan view.

[0173] Thus, in the plan view, the shielding wiring layer 503 surrounding either or both of the drain collecting portion 702 and the gate collecting portion 703 has a first area R1 where the shielding wiring layer 503 is continuously arranged between the terminal layer L2 and the substrate 101, and a second area R2 where the shielding wiring layer 503 is not continuously arranged.

[0174] Fig.10 yes Fig. 9 A cross-sectional view of the power amplifying semiconductor device according to Embodiment 5 taken on each section line of FIG. Fig.10 (a) is based on Fig. 9 A cross-sectional view of the power amplifier semiconductor device according to Embodiment 5 cut along the Xa-Xa section line shown in FIG. Fig.10 (b) is based on Fig. 9 A cross-sectional view of the power amplifier semiconductor device according to Embodiment 5 cut along the Xb-Xb section line shown in FIG. Fig.10 (c) is based on Fig. 9 A cross-sectional view of the power amplifying semiconductor device according to the fifth embodiment is shown taken along the Xc-Xc section line.

[0175] like Fig.10 As shown in (a), at the position of the Xa-Xa section line, in each of the two substrate via columns, the shielding wiring layer 503 (specifically, the first wiring layer 501 and the second wiring layer 502) is continuously arranged from the terminal layer L2 to the substrate 101, and a shielding bump opening portion 804 is formed in each of the two substrate via columns.

[0176] In addition, continuous arrangement means that the metal layer for suppressing noise is formed from the terminal layer L2 to the substrate 101. In addition, non-continuous arrangement means that the metal layer for suppressing noise is formed in a part between the terminal layer L2 and the substrate 101.

[0177] like Fig.10 As shown in (b), at the position of the Xb-Xb section line, in each of the two substrate via columns, the shielding wiring layer 503 (specifically, the first wiring layer 501 and the second wiring layer 502) is continuously arranged between the terminal layer L2 and the substrate 101, and a shielding bump opening portion 804 is formed in the substrate via column of one of the two substrate via columns.

[0178] like Fig.10 As shown in (c), at the position of the Xc-Xc section line, in one of the two substrate via columns, the shield wiring layer 503 (specifically, the first wiring layer 501 and the second wiring layer 502) is continuously arranged from the terminal layer to the substrate 101 ( Fig.10In the first region R1 shown in (c), in the other substrate via array of the two substrate via arrays, only the terminal layer (fifth insulating layer 205) is provided with a shield wiring layer 503 (specifically, the second wiring layer 502) from the terminal layer to the substrate 101 ( Fig.10 In addition, the shield bump opening 804 is formed in the second region R2. That is, the shield bump opening 804 is formed in a region where the shield wiring layer 503 is not continuously arranged.

[0179] Thus, the portion of the second wiring layer 502 exposed through the shield bump opening 804 can be made flat. When the power amplifier semiconductor device is mounted on a mounting substrate by flip-chip method using solder balls or the like, it is possible to prevent the solder balls from being sucked into the vias and causing poor conduction due to insufficient solder.

[0180] Alternatively, it can be said that the first region R1 is a region where the substrate via 901, the semiconductor layer via 902, and the shield bump opening 804 under the shield wiring layer 503 are continuously connected in the cross-sectional view, and the second region R2 is a region where the substrate via 901, the semiconductor layer via 902, and the shield bump opening 804 are discontinuous in the cross-sectional view (for example, the substrate via 901, the semiconductor layer via 902, and the shield bump opening 804 are not formed). In the power amplifier semiconductor device according to the fifth embodiment, the first region R1 and the second region R2 are arranged in a mixed manner.

[0181] [5-2. Effects, etc.]

[0182] As described above, in the power amplification semiconductor device involved in embodiment 5, the shielding wiring layer 503 surrounding either or both of the drain collection portion 702 and the gate collection portion 703 in a plan view has an area (for example, a first area R1) where the shielding wiring layer 503 is continuously configured and an area (for example, a second area R2) where the shielding wiring layer 503 is not continuously configured between the terminal layer L2 and the substrate 101.

[0183] Accordingly, in the cross-sectional view, since the areas where the substrate via 901, the semiconductor layer via 902, and the shielding bump opening 804 under the shielding wiring layer 503 are continuously connected and the areas where they are not continuously connected are mixed, the effect of suppressing the noise influence of the bump metal configured inside the shielding wiring layer 503, the substrate via 901, the semiconductor layer via 902, and the shielding bump opening 804, and the effect of facilitating the adjustment of the design freedom in the configuration of the vias, etc. can be achieved.

[0184] (Variation 1 of Implementation Example 5)

[0185] Next, use FIG. 11A to FIG. 11D A power amplifier semiconductor device according to a first variation of the fifth embodiment will be described. FIG. 11A to FIG. 11D 1 and 2 are plan views showing various examples of arrangement examples of substrate via holes and shield bump openings 804 in the power amplifying semiconductor device according to Modification 1 of Embodiment 5. FIG.

[0186] like Fig.11A As shown, the shield bump opening 804 may be formed in a manner that includes each of the plurality of substrate vias 901 a in two or more substrate via columns.

[0187] like Fig. 11B As shown, the shield bump opening 804 may also be formed in a manner including each of the plurality of substrate vias 901 b in two or more substrate via columns.

[0188] like Fig. 11C As shown, the shielding bump opening 804 may also be arranged to be parallel to two or more substrate via columns including a plurality of substrate vias 901a. The shielding bump opening 804 may also be arranged in a direction parallel to the extending direction of the substrate via column (in Fig. 11C In the example, it extends in a direction parallel to the Y-axis direction).

[0189] like Fig.11D As shown, the shielding bump opening 804 may also be arranged to be parallel to two or more substrate via columns including a plurality of substrate vias 901b. The shielding bump opening 804 may also be arranged in a direction parallel to the extending direction of the substrate via column (in Fig.11D In the example, it extends in a direction parallel to the Y-axis direction).

[0190] like Fig.11A as well as Fig. 11B As shown, the substrate via and the shielding bump opening 804 may be configured in an overlapping manner in a plan view, such as Fig. 11C as well as Fig.11D As shown, the substrate via and the shield bump opening 804 may be arranged so as not to overlap in a plan view. Even with such an arrangement of the substrate via and the shield bump opening 804, the same effects as those of the power amplifier semiconductor device according to the fifth embodiment can be achieved.

[0191] (Variation 2 of Implementation Example 5)

[0192] Next, use Fig.12 A power amplifier semiconductor device according to a second variation of the fifth embodiment will be described. Fig.12 The configuration of a power amplifying semiconductor device according to a second variation of the fifth embodiment is shown. Fig.12(a) is a plan view showing an example of arrangement of substrate vias 901 and shield bump openings 804 in a power amplifying semiconductor device according to a second modification of the fifth embodiment. Fig.12 (b) is based on Fig.12 A cross-sectional view of the power amplifying semiconductor device according to the second variation of the fifth embodiment, cut along the XIIb-XIIb section line of (a).

[0193] like Fig.12 As shown, in the power amplification semiconductor device involved in the variant example 2 of the embodiment 5, in the plan view, the shielding bump opening portion 804 is configured in a manner that does not overlap with the substrate via 901 and the semiconductor layer via 902 under the shielding wiring layer 503 (the first wiring layer 501 and the second wiring layer 502).

[0194] In the power amplifier semiconductor device according to the second variation of the fifth embodiment, the via columns in which the substrate vias 901 and the semiconductor layer vias 902 are arranged side by side, and the bump columns in which the shielding bump openings 804 are arranged side by side are different from each other. Furthermore, there are more than one via column and one bump column respectively. Although they are arranged in two columns in this variation, there is no special limitation on their number. Furthermore, the substrate vias 901 and the semiconductor layer vias 902 in the two via columns are arranged alternately (in a zigzag shape), and the shielding bump openings 804 in the two bump columns are arranged alternately (in a zigzag shape).

[0195] Regardless of Fig.12 From which position in the Y-axis direction shown in (a) is the arrangement direction of the via column and the bump column viewed? Fig.12 In the example of the X-axis direction), at least one substrate via 901 and a semiconductor layer via 902, and at least one shielding bump opening 804 are configured.

[0196] Accordingly, in the plan view, since the shielding bump opening 804 is configured in a manner that does not overlap with the substrate via 901 and the semiconductor layer via 902 under the shielding wiring layer 503, the surface shape of the second wiring layer 502 around the shielding bump opening 804 can be made flat, thereby simplifying the bump process conditions in the subsequent process.

[0197] (Variation 3 of Implementation Example 5)

[0198] Next, use Fig.13 A power amplifier semiconductor device according to a third variation of the fifth embodiment will be described. Fig.13 The configuration of a power amplifying semiconductor device according to a third variation of the fifth embodiment is shown. Fig.13(a) is a plan view showing an example of arrangement of substrate vias 901 and shield bump openings 804 in a power amplifying semiconductor device according to Modification 3 of Embodiment 5. Fig.13 (b) is based on Fig.13 A cross-sectional view of the power amplifying semiconductor device according to the third variation of the fifth embodiment, taken along the XIIIb-XIIIb section line of (a). Fig.13 (c) is based on Fig.13 (a) is a cross-sectional view of the power amplification semiconductor device according to the third variation of the fifth embodiment, taken along the XIIIc-XIIIc section line. Fig.13 (b) is a cross-sectional view of the position where the shielding bump opening 804 is configured. Fig.13 (c) is a cross-sectional view of the position where the substrate via hole 901 is configured.

[0199] like Fig.13 As shown, the substrate vias 901 and the shielding bump openings 804 may also be alternately arranged to form a straight line in a plan view. In this case, the substrate vias 901 and the shielding bump openings 804 are arranged in a manner that they do not overlap each other in a plan view.

[0200] According to this, even in a configuration where only one substrate via row is provided, the surface shape of the second wiring layer 502 around the shield bump opening 804 can be made flat, thereby simplifying the bump process conditions in the subsequent steps.

[0201] (Variation 4 of Implementation Method 5)

[0202] Next, use Fig.14 A power amplification semiconductor device according to a fourth variation of the fifth embodiment will be described. Fig.14 The configuration of a power amplifying semiconductor device according to a fourth variation of the fifth embodiment is shown. Fig.14 (a) is a plan view showing an example of arrangement of substrate vias 901 and shield bump openings 804 in a power amplifying semiconductor device according to Modification 4 of Embodiment 5. Fig.14 (b) is based on Fig.13 A cross-sectional view of the power amplifying semiconductor device according to the fourth variation of the fifth embodiment, taken along the XIVb-XIVb section line of (a).

[0203] like Fig.14 As shown, in the power amplifier semiconductor device according to this modification, in a plan view, the substrate vias 901 and the shield bump openings 804 are alternately arranged in a straight line, and in the extending direction of the line ( Fig.14 In the example, the Y-axis direction) is perpendicular to the direction ( Fig.14In this case, the plurality of substrate vias 901 and the plurality of shield bump openings 804 are arranged so as not to overlap each other in a plan view.

[0204] Furthermore, the power amplifier semiconductor device according to this modification has a shield pad 704a connected to the shield wiring layer 503 (second wiring layer 502). The shield pad 704a is a portion of the second wiring layer 502 exposed through the shield bump opening 804. The shield pad 704a is configured such that the pad area ( Fig.14 The area of ​​the shielding bump opening 804 shown in (a) does not overlap with the opening area of ​​the substrate via 901 ( Fig.14 The rectangular area of ​​the substrate via 901 shown in (a) is repeated.

[0205] As described above, the power amplifying semiconductor device according to the fourth variation of the fifth embodiment includes the shielding pad 704a connected to the shielding wiring layer 503, and in a plan view, the pad region of the shielding pad 704a does not overlap with the opening region of the substrate via 901. For example, the pad region is arranged at a position that does not overlap with the opening region in a plan view.

[0206] Accordingly, even in a configuration where substrate vias 901 and shield bump openings 804 are alternately arranged in a plurality of straight lines, the surface shape of the second wiring layer 502 around the shield bump openings 804 can be made flat, thereby simplifying the bump process conditions in subsequent steps.

[0207] (Variation 5 of Implementation Example 5)

[0208] Next, use Fig.15 A power amplifier semiconductor device according to a fifth variation of the fifth embodiment will be described. Fig.15 The structure of a power amplifying semiconductor device according to a fifth modification of the fifth embodiment is shown. Fig.15 (a) is a plan view showing an example of arrangement of substrate vias 901 and shield bump openings 804 in a power amplifying semiconductor device according to a fifth modification of the fifth embodiment. Fig.15 (b) is based on Fig.15 A cross-sectional view of a power amplifying semiconductor device according to a fifth variation of the fifth embodiment, cut along the XVb-XVb section line in (a).

[0209] like Fig.15As shown, when the shielding wiring layer 503 is composed of a plurality of layers, namely, the first wiring layer 501 and the second wiring layer 502, it can be configured so that in a plan view, the width of the upper second wiring layer 502 is different from that of the lower first wiring layer 501. For example, the shielding wiring layer 503 includes: a first shielding wiring layer (e.g., the first wiring layer 501) provided in the connection layer L1, and a second shielding wiring layer (e.g., the second wiring layer 502) provided in the terminal layer L2. The first shielding wiring layer and the second shielding wiring layer are connected, for example, in the fourth insulating layer 204.

[0210] The second wiring layer 502 is arranged in a portion of the first wiring layer 501 where the substrate via 901 and the semiconductor layer via 902 are not arranged in a planar view, that is, in a portion where the surface of the first wiring layer 501 on the positive side of the Z axis is flat.

[0211] In plan view, the first shield wiring layer and the second shield wiring layer have different wiring widths surrounding one or both of the drain collection portion 702 and the gate collection portion 703. The wiring width W1 of the first shield wiring layer is larger than the wiring width W2 of the second shield wiring layer.

[0212] Furthermore, in this modification, the substrate via 901 and the semiconductor layer via 902 are arranged so as not to overlap with the second wiring layer 502 in a plan view.

[0213] As described above, the shielding wiring layer 503 of the power amplifying semiconductor device involved in the variant example 5 of the embodiment 5 may include a first shielding wiring layer arranged on the connection layer L1, and a second shielding wiring layer arranged on the terminal layer L2, and the first shielding wiring layer and the second shielding wiring layer in the plan view may have different wiring widths (wiring widths W1, W2) in the parts surrounding either or both of the drain collection part 702 and the gate collection part 703.

[0214] Accordingly, in the case where the shielding wiring layer 503 is composed of multiple layers including a first wiring layer 501 and a second wiring layer 502, since it is configured in a manner such that the widths of the upper second wiring layer 502 and the lower first wiring layer 501 are different in a plan view, the design freedom of the positional relationship of the shielding bump opening 804 relative to the substrate via 901 and the semiconductor layer via 902 can be improved.

[0215] (Implementation 6)

[0216] [6-1. Configuration of power amplifier semiconductor device]

[0217] Next, use Fig.16A power amplifier semiconductor device according to a sixth embodiment will be described. Fig.16 is a plan view showing the structure of a power amplifying semiconductor device 400 according to Embodiment 6. Fig.16 In the plan view of FIG. 1 , finger electrodes such as the source electrode 301 , the drain electrode 302 , the gate electrode 303 , and the field plate electrode 304 , and a bus electrode for collecting the finger electrodes are indicated by solid lines. Fig.16 The connection method between each finger electrode and the pad corresponding to the finger electrode is described.

[0218] like Fig.16 As shown, the source electrode 301 is connected to the source pad 701a (for example, see Figure 1 The source pad 701a is formed just above the source electrode 301. The field plate electrode 304 is also connected to the source collecting portion 701 via the connecting portion C2.

[0219] The collecting electrode portion 712a (bus electrode) extends in the arrangement direction (X-axis direction) of the plurality of drain electrodes 302 and is electrically connected to the plurality of drain electrodes 302. The collecting electrode portion 712a is connected to the drain collecting portion 702 by collecting wiring (for example, three collecting wirings) via one or more connection portions C3 near the transistor. The collecting electrode portion 712a is arranged near the transistor in a plan view.

[0220] That is, the drain electrode 302 is connected to the collecting electrode portion 712a, and the collecting electrode portion 712a is located near the transistor, and the collecting electrode portion 712a is connected to the drain pad 702a ( Fig.16 The portion of "D" shown) is connected in the drain pad 702a area.

[0221] The collecting electrode portion 713a extends in the arrangement direction (X-axis direction) of the plurality of gate electrodes 303 and is electrically connected to the plurality of gate electrodes 303. The collecting electrode portion 713a collects the plurality of gate electrodes 303 and is connected to the gate collecting portion 703 via one or more connecting portions C4 near the transistor. The collecting electrode portion 713a is arranged near the transistor in a plan view. Furthermore, the collecting electrode portion 713a and the gate collecting portion 703 are connected by a collecting wiring (for example, one collecting wiring).

[0222] That is, the gate electrode 303 is connected to the collecting electrode portion 713a, the collecting electrode portion 713a is located near the transistor, and the collecting electrode portion 713a is connected to the gate pad 703a ( Fig.16 The "G" portion shown) is connected in the gate pad 703a area.

[0223] (Variation of Implementation Example 6)

[0224] Next, use Figure 17 to Figure 19 Another example of the connection method between each finger electrode and the pad corresponding to the finger electrode in the power amplifying semiconductor device according to the modification of the sixth embodiment will be described. Figure 17 to Figure 19 1 are plan views showing various examples of the configuration of a power amplifying semiconductor device according to a modification of the sixth embodiment. Fig.17 In the first layer wiring (e.g., equivalent to Fig.16 The second wiring layer 502 shown in FIG. 1 is indicated by oblique lines, and the second wiring layer (e.g., equivalent to Fig.16 The first wiring layer 501 shown in the figure is not shaded. In addition, since the connection of the source electrode 301 is the same as that in the sixth embodiment, the description thereof will be omitted.

[0225] like Fig.17 As shown, in the power amplifier semiconductor device 400a, the connection portion C3 is arranged on the source pad 701a (for example, see Figure 1 In the region of the drain electrode 302, the drain electrode 302 is connected to the collection wiring 702b via the connection portion C3 directly above the drain electrode 302. Furthermore, the drain electrode 302 is connected to the drain pad 702a (for example, see Figure 1 etc.) areas are gathered.

[0226] Furthermore, in the power amplifier semiconductor device 400a, the connection portion C4 is arranged in the source pad 701a region, and the gate electrode 303 and the collection wiring 703b are connected via the connection portion C4 directly above the gate electrode 303. Furthermore, the gate electrode 303 is connected to the gate pad 703a (for example, see Figure 1 etc.) areas are gathered.

[0227] Fig.18 It is a plan view showing the structure of a power amplifying semiconductor device 400b according to a modification of the sixth embodiment.

[0228] like Fig.18 As shown, in power amplifier semiconductor device 400b, connection portion C3 is arranged near the transistor, drain electrode 302 and collection wiring 702b are connected near the transistor, and drain electrode 302 is collected in drain pad 702a region (drain collection portion 702) via collection wiring 702b.

[0229] Furthermore, in the power amplifier semiconductor device 400b, the connection portion C4 extends in the arrangement direction (X-axis direction) of the plurality of gate electrodes 303, and is arranged in the collecting electrode portion 713a electrically connected to the plurality of gate electrodes 303, and the gate electrodes 303 and the collecting electrode portion 713a are connected near the transistor. Furthermore, the gate electrodes 303 are collected at the collecting electrode portion 713a (i.e., near the transistor) via the connection portion C4. Furthermore, the collecting electrode portion 713a is connected to the gate collecting portion 703 via the collecting wiring 703b.

[0230] Fig.19 1 is a plan view showing the structure of a power amplifying semiconductor device 400 c according to a modification of the sixth embodiment.

[0231] like Fig.19 As shown, the drain electrode 302 and the drain pad 702a (for example, see Figure 1 etc.) can be connected with Fig.16 The power amplifier semiconductor device 400 shown in FIG. 1 is similar to the gate electrode 303 and the gate pad 703a (for example, see Figure 1 etc.) can be connected with Fig.18 The same is true of the power amplifying semiconductor device 400b shown.

[0232] As described above, there are various methods and combinations for connecting each finger electrode to the pad corresponding to the finger electrode, and these methods can be appropriately determined.

[0233] (Manufacturing method)

[0234] Next, use Figures 20A to 20D A method for manufacturing the above-mentioned power amplifying semiconductor device will be described. Hereinafter, a method for manufacturing the power amplifying semiconductor device 100 according to the first embodiment will be described as an example. Figures 20A to 20D The sectional views are for explaining the method for manufacturing the power amplifying semiconductor device 100 according to Embodiment 1. The method for manufacturing power amplifying semiconductor devices other than the power amplifying semiconductor device 100 according to Embodiment 1 is the same as that of Embodiment 1, and thus the description thereof is omitted.

[0235] like Fig. 20AAs shown in (a), a semiconductor epitaxial layer 102 is grown on a substrate 101 composed of Si by using an organic metal chemical vapor deposition method (MOCVD: Metal Organic Chemical Vapor Deposition). The semiconductor epitaxial layer 102 has a thickness of several μm (for example, 2 μm) and is composed of a stacked structure including AlN, GaN and AlGaN, and has a two-dimensional electron gas layer near the heterojunction surface of AlGaN and GaN. Furthermore, as the formation of an active region 401 and an inactive region 402 that will be a transistor formation region described later, the inactive region 402 is formed by inactivating the two-dimensional electrons in the semiconductor epitaxial layer 102 by using ion implantation of F and BF2.

[0236] Then, if Fig. 20A As shown in (b), a first insulating layer 201 composed of SiN with a thickness of about 30 nm is formed on the semiconductor epitaxial layer 102 by CVD (Chemical Vapor Deposition), and an opening is opened in the first insulating layer 201, and Ti and Al patterned by photoresist are evaporated to stack 20 nm and 200 nm in sequence. After patterning by a lift-off process, alloying treatment is performed by heat treatment, thereby forming a source electrode 301 and a drain electrode 302 in ohmic contact with the two-dimensional electron gas in the semiconductor epitaxial layer 102 in the active region 401.

[0237] Then as Fig. 20A As shown in (c), an opening is made on the first insulating layer 201, Ni and Au patterned by photoresist are evaporated to be stacked in sequence of 50nm and 500nm, and patterned by a lift-off process, so that a gate electrode 303 in contact with the two-dimensional electron gas Schottky in the semiconductor epitaxial layer 102 is formed between the source electrode 301 and the drain electrode 302 in the active region 401.

[0238] Then as Fig. 20B As shown in (a), a second insulating layer 202 composed of SiN with a thickness of about 150 nm is formed on the source electrode 301, the drain electrode 302 and the gate electrode 303 by CVD, and on the drain side of the gate electrode terminal on the source side relative to the gate electrode 303, Ti and Al patterned by photoresist are evaporated to cover the gate electrode 303 to stack 50nm and 500nm in sequence, and a field plate electrode 304 patterned by a lift-off process is formed.

[0239] Then as Fig. 20BAs shown in (b), a third insulating layer 203 of SiN with a thickness of about 300 nm is formed on the field plate electrode 304 by CVD, and an electrode-wiring opening connection portion 601 is formed to expose a portion of the source electrode 301, the drain electrode 302, the gate electrode 303, and the field plate electrode 304. And in the inactive region 402, in the region where the semiconductor layer via 902 and the substrate via 901 are to be formed later, a via-wiring opening connection portion 603 is formed to expose a portion of the semiconductor epitaxial layer 102.

[0240] Then as Fig. 20B As shown in (c), the semiconductor epitaxial layer 102 is opened inside the via-inter-wiring opening connection portion 603, and a semiconductor layer via hole 902 exposing the substrate 101 is formed by dry etching.

[0241] Then as Fig. 20C As shown in (a), inside the semiconductor layer via hole 902, the substrate 101 is dug down by about 150 μm by dry etching to form the substrate via hole 901.

[0242] Then as Fig. 20C As shown in (b), Ti and Al are deposited in order of about 100 nm and about 2 μm by sputtering, and the first wiring layer 501 is formed by patterning using a photoresist and dry etching.

[0243] Then as Fig. 20C As shown in (c), a fourth insulating layer 204 of about 1 μm thick made of SiO2 is formed by CVD, and after forming a wiring-wiring opening connection portion 602 that exposes a portion of the first wiring layer 501 by dry etching, Ti and Al are deposited in 100 nm and 4 μm in sequence by sputtering, and a second wiring layer 502 is formed by patterning using a photoresist. Furthermore, a shielding wiring layer 503 including the first wiring layer 501 and the second wiring layer 502 is formed in the area where the substrate via 901 and the semiconductor layer via 902 are formed. Furthermore, in Fig. 20C Although not shown in FIG. 1 , the source collection portion 701 , the drain collection portion 702 , and the gate collection portion 703 are formed by the first wiring layer 501 and the second wiring layer 502 .

[0244] Then as Fig.20DAs shown in (a), the fifth insulating layer 205 is formed by CVD and spin coating using a photosensitive organic resin film represented by SiN and polyimide with a film thickness of about 800 nm, and various bump openings are formed on the fifth insulating layer 205 to expose the second wiring layer 502. Shielding bump openings 804 are formed on the shielding wiring layer 503 (for example, the first wiring layer 501 and the second wiring layer 502).

[0245] In addition, a source bump opening 801 is formed to open the source collection portion 701, and a drain bump opening 802 is formed to open the drain collection portion 702 (see Figure 1 ), and the gate bump opening 803 (refer to Figure 1 ).

[0246] Then as Fig.20D As shown in (b), after grinding and polishing the back side of the substrate 101, a back electrode 103 stacked with Ti, Ni, and Au is formed. In this way, the power amplifier semiconductor device 100 is manufactured.

[0247] In addition, although the dry etching for forming the substrate via 901 and the dry etching for forming the semiconductor layer via 902 in the above-described example are performed on the same side of the substrate 101, they may be performed from the opposite side. For example, the dry etching for forming the substrate via 901 may be performed from the positive side (back side) of the Z axis of the substrate 101, and the dry etching for forming the semiconductor layer via 902 may be performed from the negative side (front side) of the Z axis of the substrate 101. The same is true for the deposition of metal materials by sputtering or the like. Accordingly, a power amplifier semiconductor device having a structure in which the substrate via 901 and the semiconductor layer via 902 are arranged at a position where they do not overlap in a plan view can be manufactured.

[0248] (Explanation of noise suppression by bump metal)

[0249] Reference Fig.21 Noise suppression by bump metal is described. Fig.21 1 is a cross-sectional view showing a mounting substrate on which a power amplifier semiconductor device according to each embodiment is mounted. Fig.21 As an example, the power amplifier semiconductor device 400 according to the modification of the third embodiment is mounted on the mounting substrate 1000 via the bump metal 1100, and the power amplifier semiconductor devices according to other embodiments or modifications can be considered similar. Fig.21In FIG. 1 , only the noise suppressed by the bump metal 1100 is indicated by arrows. The solid arrows indicate the noise radiated from the drain collection portion 702 , and the dotted arrows indicate the noise entering the gate collection portion 703 .

[0250] like Fig.21 As shown, the power amplifying semiconductor device 400 is mounted on the mounting substrate 1000 or the like with the surfaces of the pads facing downward (toward the positive side of the Z axis), that is, mounted on the mounting substrate 1000 by so-called face-down mounting. Furthermore, the mounting method of the power amplifying semiconductor device 400 on the mounting substrate 1000 is not particularly limited, and for example, a ball grid array package (BGA) or a land grid array package (LGA) may be used.

[0251] The source pad 701a, the drain pad 702a, the gate pad 703a, and the shield pad 704a are each connected to the mounting substrate 1000 via a bump metal 1100. The bump metal 1100 disposed on the shield pad 704a may be connected to a GND pattern on the mounting substrate 1000, for example.

[0252] As described above, the shield pad 704a is formed to surround the drain collection portion 702 and the gate collection portion 703 in a plan view. Therefore, the bump metal 1100 arranged on the shield pad 704a is also arranged to surround the drain collection portion 702 and the gate collection portion 703 in a plan view.

[0253] According to this, since the noise radiated from the drain collection portion 702 can be shielded by the bump metal 1100 around the drain collection portion 702, it is possible to suppress the noise from being radiated to the external components of the power amplifying semiconductor device 100. In addition, since the noise radiated from the external components or the drain collection portion 702 is shielded by the bump metal 1100 around the gate collection portion 703, it is possible to suppress the noise from the external components or the drain collection portion 702 from entering the gate collection portion 703.

[0254] In this way, the bump metal 1100 plays a function of shielding against noise (electromagnetic shielding).

[0255] (Other Embodiments)

[0256] Although the power amplifier semiconductor device involved in one or more embodiments of the present disclosure is described above based on various embodiments, the present disclosure is not limited to the above-mentioned embodiments, etc. Various modifications that can be thought of by a person skilled in the art are performed on the present embodiment within the scope of the present disclosure, and the methods of combining the constituent elements in different embodiments are all included in the scope of one or more embodiments of the present disclosure.

[0257] For example, in each of the above-mentioned embodiments, although an example in which a power amplifying semiconductor device has two wiring layers, namely, a first wiring layer and a second wiring layer, is described, it is not limited thereto, and may also be a configuration having a single wiring layer. A single wiring layer is a layer formed by a single film forming process. In this case, a portion of a single wiring layer formed on the first insulating layer to the third insulating layer constitutes a connecting layer, and a portion of a single wiring layer formed on the fourth insulating layer constitutes a terminal layer. The connecting layer includes a source electrode, a drain electrode, and a gate electrode, as well as wiring that connects these electrodes to the electrodes of the terminal layer. As described above, the present disclosure can be applied to a power amplifying semiconductor device having a single wiring layer.

[0258] Furthermore, for example, in the above-mentioned embodiments, although an example is described in which the substrate via and the semiconductor layer via are arranged in overlapping positions in a plan view, the present invention is not limited to this, and the substrate via and the semiconductor layer via may also be arranged in non-overlapping positions in a plan view.

[0259] Industrial Applicability

[0260] The power amplifier semiconductor device according to the present disclosure has excellent characteristics for suppressing the generation of noise and the influence of external noise, and is therefore useful for a communication amplifier that is prone to noise generation and needs to be protected from the influence of external noise.

[0261] Description of Reference Numerals

[0262] 100, 200, 300, 400, 400a, 400b, 400c, 500 Power amplifier semiconductor device 101 Substrate

[0263] 102 semiconductor epitaxial layer (semiconductor layer)

[0264] 103 back electrode

[0265] 201 first insulation layer

[0266] 202 second insulation layer

[0267] 203 third insulation layer

[0268] 204 Fourth insulation layer

[0269] 205 Fifth Insulation Layer

[0270] 301 source electrode

[0271] 302 drain electrode

[0272] 303 gate electrode

[0273] 304 Field Plate Electrode

[0274] 401 Active Area

[0275] 402 Inactive Region

[0276] 501 first wiring layer

[0277] 502 Second wiring layer

[0278] 503 shielded wiring layer

[0279] 601 electrode-wiring opening connection

[0280] 602 Wiring-Wiring Opening Connection

[0281] 603 via-opening connection between wiring

[0282] 701 source collection unit

[0283] 701a Source pad

[0284] 702 drain collection part

[0285] 702a Drain pad

[0286] 702b, 703b collection wiring

[0287] 703 grid collection part

[0288] 703a Gate pad

[0289] 704a Shielding Pad

[0290] 712a, 713a Collecting electrode portion

[0291] 801 Source bump opening

[0292] 802 Drain bump opening

[0293] 803 Gate bump opening

[0294] 804 shielding bump opening

[0295] 901, 901a, 901b substrate vias

[0296] 901a1, 902a1 bending part

[0297] 901b1, 902b1 branch

[0298] 902, 902a, 902b semiconductor layer vias

[0299] 911, 911a, 911b, 912, 912a, 912b non-continuous part

[0300] 921a First substrate via hole array

[0301] 921b Second substrate via row

[0302] 922a First semiconductor layer via hole array

[0303] 922b Second semiconductor layer via hole array

[0304] 1000 Mounting Base Plate

[0305] 1100 bump metal

[0306] C1, C2, C3, C4, L1 connection layer

[0307] L2 terminal layer

[0308] R1 first area

[0309] R2 Second Area

[0310] Wiring width of W1 and W2

Claims

1. A power amplification semiconductor device, wherein a plurality of unit HEMTs are connected in parallel, wherein the HEMT is a High Electron Mobility Transistor, The power amplifier semiconductor device comprises: substrate; A semiconductor layer, which is disposed on the front surface of the substrate and includes the plurality of unit HEMTs; a connection layer, which is disposed on the semiconductor layer and includes a source electrode, a drain electrode and a gate electrode of the unit HEMT; a terminal layer disposed on the connection layer and including a source pad, a drain pad, and a gate pad connected to the source electrode, the drain electrode, and the gate electrode via a first portion of a wiring layer; a back electrode, which is disposed on the back side of the substrate and has a potential set to be the same as that of the source electrode; as well as a substrate via hole penetrating the substrate, and having a shielding wiring layer on the inner wall of the substrate via hole, wherein the shielding wiring layer is the second part of the wiring layer set to the source potential, The drain electrode and the gate electrode are respectively provided in plural numbers corresponding to the unit HEMTs. The power amplifying semiconductor device comprises: a drain collecting portion for collectively connecting the plurality of drain electrodes at the third portion of the wiring layer; as well as A gate collecting portion for collectively connecting the plurality of gate electrodes to wiring at a fourth portion of the wiring layer, In a plan view of the substrate, one or both of the drain collecting portion and the gate collecting portion are surrounded by the substrate via.

2. The power amplifier semiconductor device according to claim 1, The power amplifying semiconductor device comprises a semiconductor layer via hole penetrating the semiconductor layer, and the shield wiring layer is provided on the inner wall of the semiconductor layer via hole. In the plan view, one or both of the drain collecting portion and the gate collecting portion are surrounded by the semiconductor layer via.

3. The power amplifier semiconductor device according to claim 1 or 2, At the position of the connection layer in the vertical direction relative to the front side of the substrate, In the plan view, one or both of the drain collection portion and the gate collection portion are surrounded by the shield wiring layer.

4. The power amplifier semiconductor device according to claim 1 or 2, In the plan view, one or both of the drain pad and the gate pad are surrounded by the shield wiring layer.

5. The power amplifier semiconductor device according to claim 1 or 2, In the plan view, an opening profile of the substrate via hole has a first discontinuous portion.

6. The power amplifier semiconductor device according to claim 5, In the plan view, the periphery is surrounded by the substrate vias arranged in a plurality of rows, When the inner center position is viewed from the outer position of the substrate via holes arranged in the plurality of rows, the substrate via holes in the plurality of rows are arranged so that the first discontinuous portions of the respective rows do not overlap with each other.

7. The power amplifier semiconductor device according to claim 2, In the plan view, an opening contour of the semiconductor layer via hole has a second discontinuous portion.

8. The power amplifier semiconductor device according to claim 7, In the plan view, the periphery is surrounded by the semiconductor layer vias arranged in multiple rows, The semiconductor layer vias in the plurality of rows are arranged so that the second discontinuous portions of the rows do not overlap each other when the inner center position is viewed from the outer position of the semiconductor layer vias arranged in the plurality of rows.

9. The power amplifier semiconductor device according to claim 6, In the plan view, the opening profile of the substrate via hole has a plurality of curved portions or a plurality of branch portions.

10. The power amplifying semiconductor device according to claim 8, In the plan view, the opening profile of the semiconductor layer via hole has a plurality of curved portions or a plurality of branch portions.

11. The power amplifier semiconductor device according to any one of claims 1, 2, 7, 8, and 10, In the plan view, the shield wiring layer surrounding the periphery of either or both of the drain collecting portion and the gate collecting portion has an area where the shield wiring layer is continuously arranged and an area where the shield wiring layer is not continuously arranged between the terminal layer and the substrate.

12. The power amplifier semiconductor device according to any one of claims 1, 2, 7, 8, and 10, The power amplifying semiconductor device has a shield pad connected to the shield wiring layer. In the plan view, a pad area of ​​the shielding pad does not overlap with an opening area of ​​the substrate via.

13. The power amplifier semiconductor device according to any one of claims 1, 2, 7, 8, and 10, The shield wiring layer includes a first shield wiring layer provided at the connection layer, and a second shield wiring layer provided at the terminal layer. In the plan view, the first shield wiring layer and the second shield wiring layer have different wiring widths in portions surrounding the periphery of one or both of the drain collection portion and the gate collection portion.

14. The power amplifier semiconductor device according to any one of claims 1, 2, 7, 8, and 10, In the plan view, the drain collecting portion and the gate collecting portion are surrounded by the substrate via.

15. The power amplifying semiconductor device according to claim 2, In the plan view, the drain collecting portion and the gate collecting portion are surrounded by the semiconductor layer via hole.

16. The power amplifying semiconductor device according to any one of claims 1, 2, 7, 8, 10 and 15, In the plan view, the drain collection portion and the gate collection portion are surrounded by the shield wiring layer.

17. The power amplifying semiconductor device according to any one of claims 1, 2, 7, 8, 10 and 15, In the plan view, the drain pad and the gate pad are surrounded by the shield wiring layer.

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