AXI bus test stimulus source and chip function verification method thereof

Abstract

The invention discloses an AXI bus test stimulus source and a chip function verification method thereof, and relates to the field of simulation testing, wherein a parameter configuration module of the test stimulus source performs parameter configuration, and triggers a write operation start signal and a read operation start signal after completing the parameter configuration; after receiving the write operation start signal and detecting that there is a write operation ID in an unoccupied state, the write operation module allocates a target write ID for this write operation, changes the target write ID to an occupied state, and sends the write data of this write operation to a target device under test according to the target write address and target write ID of this write operation obtained; the read operation module reads the corresponding write data from the target device under test according to the target read address and target read ID of this read operation obtained, and after the read operation ends, performs data correctness verification according to the read write data and a preset write value. The present invention can provide a test stimulus with outstanding>1, thereby meeting the verification requirements of high throughput and data verification.

Description

Technical Field

[0001] The present invention relates to the technical field of simulation testing, and in particular to an AXI bus test stimulus source and a chip function verification method thereof. Background Art

[0002] In the process of functional verification of the chip, it is usually necessary to conduct detailed verification of the communication delay and data throughput of key data nodes to ensure that the chip can meet the required performance requirements after tape-out. Among them, key data nodes usually include on-chip network (NoC, Network On Chip), DDR controller (DDR Controller), cache memory (Cache), etc. The bus is usually an AXI bus. The test process will initiate different test stimuli (such as different Burst Length, Outstanding) to the IP core of the module under test to verify whether the module under test can meet the communication delay indicators and data throughput indicators required by the design while meeting the data correctness. This link is one of the key items in the chip functional verification process and plays a decisive role in the successful tape-out of high-performance chips.

[0003] The chip function verification process usually includes soft simulation, emulator verification and FPGA verification. Different links provide different verification speeds and signal observability, and it is difficult to replace each other. Emulator verification and FPGA verification require that the bus stimulus source used in the test must be synthesizable RTL code, otherwise it will cause code compilation failure. However, compared with soft simulation code, synthesizable RTL code has lower code flexibility, higher writing difficulty, and requires more R&D cycles to achieve the same function. Therefore, the existing emulator verification solutions and FPGA verification solutions only provide simple test stimuli, or no test stimuli, which require users to write them by themselves.

[0004] The existing Emulator verification scheme and FPGA verification scheme cannot meet the test stimulus sources required for high-performance chip verification. Taking Xilinx's Vivado tool as an example, although the traffic generator of the Vivado tool can generate stimulus sources with different burst lengths for the AXI bus, the existing verification scheme still has the following problems: 1. The existing verification scheme cannot verify whether the read data matches the written data, that is, it cannot verify the data correctness of the module under test; 2. The existing verification scheme only supports the scenario of Outstanding = 1. This limitation will cause the test stimulus to be initiated when the communication delay is high. The next data transmission must wait until the previous data transmission is completed before it can be initiated, thereby affecting the evaluation of the data throughput index and failing to obtain the true limit of the module under test during functional testing. Summary of the invention

[0005] The present invention provides an AXI bus test stimulus source and a chip function verification method thereof, which can provide a test stimulus of outstanding>1, thereby meeting the verification requirements of high throughput and data verification.

[0006] In order to achieve the above object, the present invention adopts the following technical scheme:

[0007] In a first aspect, the present invention provides an AXI bus test stimulus source, the test stimulus source comprising a parameter configuration module, a write operation module and a read operation module;

[0008] The parameter configuration module is used to perform parameter configuration on the write operation module and the read operation module according to the received configuration parameters, and trigger a write operation start signal and a read operation start signal accordingly after completing the parameter configuration;

[0009] The write operation module is used to allocate a target write ID for this write operation after receiving the write operation start signal and detecting that there is a write operation ID in an unoccupied state, change the target write ID to an occupied state, and send the write data of this write operation to the target device under test according to the acquired target write address of this write operation and the target write ID, and change the target write ID back to an unoccupied state after the write operation is completed;

[0010] The read operation module is used to, upon receiving the read operation start signal and after detecting that there is a read operation ID in an unoccupied state, allocate a target read ID for this read operation, change the target read ID to an occupied state, and read corresponding write data from the target device under test according to the acquired target read address of this read operation and the target read ID, and change the target read ID back to an unoccupied state after the read operation ends;

[0011] The read operation module is further used to perform data correctness verification based on the read write data and a preset write value after the read operation is completed.

[0012] In one possible implementation, the configuration parameters include: a read operation start address or end address, a write operation start address or end address, a continuous transmission length parameter, an Outstanding parameter, a read / write mode parameter, a read / write cycle number parameter, a write operation data Pattern setting parameter, and whether to perform a read operation data verification parameter.

[0013] In a possible implementation, the write operation module includes:

[0014] A write address controller, configured to obtain a write operation ID in an unoccupied state after receiving the write operation start signal, assign the write operation ID as a target write ID to the AWID of the AXI bus write address channel, and assign the continuous transmission length parameter to the AWLEN of the AXI bus write address channel;

[0015] The write address controller is also used to change the target write ID to an occupied state after detecting that the write address operation of this write operation is completed;

[0016] A data generator, configured to generate write data corresponding to the target write ID according to the write operation start address or end address and the write operation data Pattern setting parameters;

[0017] A write data controller, used to obtain the write data corresponding to the target write ID, and send the write data corresponding to the target write ID to the target device under test according to the timing specified by the AXI bus protocol according to the continuous transmission length parameter;

[0018] A write response controller is used to change the target write ID back to an unoccupied state after receiving a target write response signal from the target device under test for write data corresponding to the target write ID; the target write response signal is the BVALID signal, BREADY signal and BRESP signal of the AXI bus write response channel being pulled high at the same time.

[0019] In a possible implementation, the write address controller is further configured to change the target write ID to an occupied state after detecting that the write address operation of the current write operation is completed, specifically:

[0020] The write address controller is also used to detect the AWVALID signal and the AWREADY signal of the AXI bus write address channel, and after detecting that the AWVALID signal and the AWREADY signal are pulled high at the same time, it is considered that the write address operation of this write operation is completed, and the target write ID is changed to an occupied state.

[0021] In a possible implementation, the write operation module further includes:

[0022] A first register is used to store a write operation ID; the maximum storage quantity of the write operation ID is equal to the maximum preset Outstanding parameter;

[0023] The second register is used to store a target write ID for which no write data is sent; the target write ID for which no write data is sent is a write operation ID in an occupied state.

[0024] In a possible implementation, the read operation module includes:

[0025] A read address controller, configured to obtain a read operation ID in an unoccupied state after receiving the read operation start signal, assign the read operation ID as a target read ID to the ARID of the AXI bus read address channel, and assign the continuous transmission length parameter to the ARLEN of the AXI bus read address channel;

[0026] The read address controller is also used to change the target read ID to an occupied state after detecting that the read address operation of this read operation is completed;

[0027] A read data controller, configured to read corresponding write data from the target device under test according to the target read address of the current read operation and the target read ID acquired according to the timing specified by the AXI bus protocol, and change the target read ID back to an unoccupied state after receiving a target read response signal corresponding to the target read ID from the target device under test; the target write response signal is a RVALID signal, a RREADY signal, and a RLAST signal of the AXI bus read data channel being pulled high at the same time;

[0028] A data verifier is used to verify the correctness of the data based on the read write data and the preset write value after the read operation is completed when the read operation data verification parameter is yes; the preset write value is determined according to the write operation data Pattern setting parameter.

[0029] In a possible implementation, the read operation module further includes:

[0030] A third register is used to store a read operation ID; the maximum storage quantity of the read operation ID is equal to the maximum preset Outstanding parameter;

[0031] The fourth register is used to store a read operation ID in an unoccupied state.

[0032] In a second aspect, the present invention provides a chip function verification method based on an AXI bus test stimulus source, the method comprising:

[0033] Perform parameter configuration on the write operation module and the read operation module according to the received configuration parameters, and trigger a write operation start signal and a read operation start signal accordingly after completing the parameter configuration;

[0034] After receiving the write operation start signal and detecting that there is a write operation ID in an unoccupied state, assigning a target write ID to the current write operation, changing the target write ID to an occupied state, and sending the write data of the current write operation to the target device under test according to the acquired target write address of the current write operation and the target write ID, and changing the target write ID back to an unoccupied state after the current write operation is completed;

[0035] After receiving the read operation start signal and detecting that there is a read operation ID in an unoccupied state, assigning a target read ID to this read operation, changing the target read ID to an occupied state, and reading corresponding write data from the target device under test according to the acquired target read address of this read operation and the target read ID, and changing the target read ID back to an unoccupied state after the read operation ends;

[0036] After the read operation is completed, the data correctness is verified based on the read write data and the preset write value.

[0037] In a possible implementation, after performing data correctness verification according to the read write data and the preset write value, the method further includes:

[0038] Determine the communication delay of the data transmission process according to the acquired end time of the write operation and the end time of the read operation;

[0039] The data throughput of this data transmission is determined according to the amount of written data written into the target device under test within the acquired target time period.

[0040] In a third aspect, the present invention provides an electronic device comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the chip function verification method of the AXI bus test stimulus source in any of the above items.

[0041] In a fourth aspect, the present invention provides a computer-readable storage medium, which stores at least one instruction, at least one program, a code set or an instruction set. The at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by a processor to implement the chip function verification method of the AXI bus test stimulus source in any of the above items.

[0042] The read operation module of the AXI bus test stimulus source provided by the embodiment of the present invention can verify the correctness of the data written by the write operation before the read operation during the read operation, thereby verifying the data correctness of the target device under test; the AXI bus test stimulus source of the present invention distinguishes multiple different transmission requests through the write operation ID and the read operation ID, and the data transmission process has an exclusive ID number before a transmission is completed. At this time, if it is necessary to initiate the next transmission request, a different ID number must be selected, and in the data reading process, since the returned data may be different from the order of initiating the request, the read operation module can distinguish according to the responded ID number, avoid confusing the data correspondence, and realize the scenario of Outstanding>1, thereby meeting the verification requirements of high throughput and data verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 An overall structural block diagram of an AXI bus test stimulus source provided by an embodiment of the present invention;

[0044] Figure 2 A flowchart of a chip function verification method based on an AXI bus test stimulus source is provided in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values ​​may be based on additional conditions or values ​​beyond the described values ​​in practice.

[0047] The present invention provides an AXI bus test stimulus source and a chip function verification method thereof, which can provide a test stimulus of outstanding>1, thereby meeting the verification requirements of high throughput and data verification.

[0048] like Figure 1 As shown, in a first aspect, an embodiment of the present invention provides an AXI bus test stimulus source, which includes a parameter configuration module, a write operation module and a read operation module.

[0049] The AXI bus has a total of 5 channels, of which the write channel includes the write address channel (AW), the write data channel (W) and the write response channel (B). The write channel is responsible for writing data to the target device under test to verify the performance of processing the write operation of the target device under test; the read channel includes the read address channel (AR) and the read data channel (R). The read channel is responsible for reading data from the target device under test to verify the performance of the target device under test in processing the read operation.

[0050] When outstanding is equal to 1, the host's read operation sequence is: read address command -> wait for read data return -> read address command -> wait for read data return -> ... and so on; the host's write operation sequence is: write address -> write data -> wait for write response return -> write address -> write data -> wait for write response return -> ... and so on. That is to say, when outstanding is equal to 1, each new data transmission needs to wait for the previous data transmission to end, and the bus utilization rate is low.

[0051] When outstanding is N>1, N read address commands can be sent continuously during read operations. If read data is not returned during this period, you need to wait for the read data to return. If read data is returned, you can send several more. In other words, the maximum number of read commands "on the way" can be N. During write operations, N write address commands can be sent continuously. If write responses are received, you can send several more. In other words, the maximum number of write responses "on the way" can be N.

[0052] The parameter configuration module is used to perform parameter configuration on the write operation module and the read operation module according to the received configuration parameters, and trigger a write operation start signal and a read operation start signal accordingly after completing the parameter configuration.

[0053] The parameter configuration module is a state machine used to control bus verification. This module is mainly used to receive configuration parameters sent by an external terminal and configure the parameters of the write operation module and the read operation module according to the configuration parameters. After completing the parameter configuration of the write operation module, the write operation start signal is automatically triggered; after completing the parameter configuration of the read operation module, the read operation start signal is automatically triggered.

[0054] In order to ensure the correctness of the read data, during the verification process, the read operation needs to be later than the write operation to prevent the data from being read out before being written into the target device under test, thereby affecting the correctness of the verification result.

[0055] The write operation module is used to assign a target write ID to this write operation after receiving a write operation start signal and detecting that there is a write operation ID in an unoccupied state, change the target write ID to an occupied state, and send the write data of this write operation to the target device under test based on the acquired target write address and target write ID of this write operation, and change the target write ID back to an unoccupied state after the write operation is completed.

[0056] The number of write operation IDs is equal to the maximum setting number of the Outstanding parameter, that is, a plurality of write operation requests sent continuously are distinguished by the write operation IDs.

[0057] The write operation ID includes two states: unused and used. When a write operation ID is marked as unused, it means that the write operation ID is in an idle state and no write operation request has been initiated. The write operation ID can be used to initiate a new write operation request. When a write operation ID is marked as used, it means that the write operation ID is being used for write operations and the same write operation ID is not allowed to initiate a write request.

[0058] After allocating a write operation ID in an unoccupied state to a certain write operation, the mark of the write operation ID is changed to an occupied state; after the write data corresponding to the write operation is sent to the target device under test, the mark of the corresponding write operation ID is changed to an unoccupied state.

[0059] The read operation module is used to assign a target read ID to this read operation after receiving a read operation start signal and detecting that there is a read operation ID in an unoccupied state, change the target read ID to an occupied state, and read the corresponding write data from the target device under test based on the acquired target read address and target read ID of this read operation, and change the target read ID back to an unoccupied state after the read operation is completed.

[0060] The number of read operation IDs is equal to the maximum setting number of the Outstanding parameter, that is, a plurality of read operation requests sent continuously are distinguished by the read operation IDs.

[0061] The read operation ID includes two states: unused and used. When a read operation ID is marked as unused, it means that the read operation ID is in an idle state and no read operation request has been initiated. The read operation ID can be used to initiate a new read operation request. When a read operation ID is marked as used, it means that the read operation ID is being used for read operations and the same read operation ID is not allowed to initiate a read request.

[0062] After a read request is initiated for a read operation ID in an unoccupied state, the flag of the read operation ID is changed to an occupied state; after the read operation is completed, the corresponding read operation ID is changed to an unoccupied state.

[0063] The read operation module is also used to perform data correctness verification based on the read write data and the preset write value after the current read operation is completed.

[0064] That is to say, after the read operation is completed, the read operation module will check whether all the received data matches the preset write value. If they match, the correctness check is passed; otherwise, the correctness check is failed.

[0065] The read operation module of the AXI bus test stimulus source provided by the embodiment of the present invention can verify the correctness of the data written by the write operation before the read operation during the read operation, thereby verifying the data correctness of the target device under test.

[0066] The AXI bus test stimulus source of the present invention distinguishes multiple different transmission requests through write operation ID and read operation ID. Before a transmission is completed, the data transmission process has an exclusive ID number. At this time, if it is necessary to initiate the next transmission request, a different ID number must be selected. In the data reading process, since the returned data may be different from the order of initiating the request, the read operation module can distinguish according to the responded ID number to avoid confusing the data correspondence, thereby realizing the scenario of Outstanding>1, thereby meeting the verification requirements of high throughput and data verification.

[0067] Furthermore, in an embodiment of the present invention, the configuration parameters include: a start address or an end address for a read operation, a start address or an end address for a write operation, a continuous transmission length parameter (Burst Lenth parameter), an Outstanding parameter, a read / write mode parameter, a read / write cycle number parameter, a write operation data Pattern setting parameter, and a parameter on whether to perform a read operation data verification.

[0068] Furthermore, the write operation module includes a write address controller, a data generator, a write data controller, a write response controller, a first register and a second register.

[0069] Among them, when the parameter configuration module is performing parameter configuration, the configuration parameters passed to the write address controller include the write operation start address or end address, continuous transmission length parameter and Outstanding parameter; the parameters passed to the data generator include read and write mode parameters and write operation data Pattern setting parameters.

[0070] The write address controller, the write data controller and the write response controller are used to generate or receive stimuli for corresponding channels.

[0071] The first register is used to store a write operation ID.

[0072] The maximum number of write operation IDs that can be stored is equal to the maximum preset Outstanding parameter.

[0073] The second register is used to store the target write ID for which no write data is sent.

[0074] The target write ID to which write data is not sent is a write operation ID in an occupied state.

[0075] That is, both the first register and the second register are used to record the Outstanding operation status, and the storage depth of the first register and the second register is equal to the maximum Outstanding parameter required for this test.

[0076] The write operation ID in the first register can be marked as unoccupied and occupied. When the target write operation ID is in unoccupied state, it means that the target write operation ID is not occupied in the write channel and can be used for subsequent transmission operations; when the target write operation ID is in occupied state, it means that the target write operation ID is being used for write operations, and the same ID is not allowed to initiate a write request.

[0077] The write address controller is used to obtain the write operation ID in the unoccupied state after receiving the write operation start signal, assign the write operation ID as the target write ID to the AWID of the AXI bus write address channel, and assign the continuous transmission length parameter to the AWLEN of the AXI bus write address channel.

[0078] Specifically, when the write address controller receives the write operation start signal, it obtains the write operation ID in the unoccupied state from the first register, and assigns the write operation ID to the AWID signal of the AXI bus write address channel, and assigns the continuous transmission length parameter to the AWLEN signal of the AXI bus write address channel. The AWLEN signal is used to determine the burst length of the write transmission.

[0079] The write address controller is further configured to change the target write ID to an occupied state after detecting that the write address operation of this write operation is completed.

[0080] Specifically, after the write address operation of this write operation is completed, the write operation ID of this write operation is written back to the first register, and the write operation ID is modified to the occupied state. At the same time, the write operation ID and the start address of the write operation of this transmission are also passed to the second register for identification of the write data channel.

[0081] The data generator is used to generate write data corresponding to the target write ID according to the write operation start address or end address and the write operation data Pattern setting parameters.

[0082] Specifically, the data generator is used to generate write data for the write data channel. When generating write data, it is necessary to set parameters according to the write operation data Pattern. When the write operation data Pattern is set to a fixed data mode, the generated write data is fixed data; when the write operation data Pattern is set to an incremental number mode, the generated write data is incremental data.

[0083] The write data controller is used to obtain the write data corresponding to the target write ID, and send the write data corresponding to the target write ID to the target device under test according to the timing specified by the AXI bus protocol based on the continuous transmission length parameter.

[0084] Specifically, when detecting the write data channel, if an unsent write operation ID is found in the second register, it means that there is a write request that has been sent in the write address channel, and the write data channel needs to send write data. At this time, the write data controller obtains the write data to be sent from the data generator, and then sends the write data to the target device under test according to the set continuous transmission length parameter and the timing specified by the AXI bus protocol.

[0085] After the write data corresponding to the current write operation ID is sent, the corresponding write operation ID in the second register is cleared.

[0086] A write response controller is used to change the target write ID back to an unoccupied state after receiving a target write response signal from the target device under test for write data corresponding to the target write ID,

[0087] The target write response signal is the BVALID signal, BREADY signal and BRESP signal of the AXI bus write response channel, which are pulled high at the same time. The BVALID signal indicates that the write response is valid, the BREADY signal indicates that the response end is ready to start transmitting the response information, and the BRESP signal indicates the write response status signal.

[0088] Specifically, the target write response signal is sent by the target device under test. The write response controller receives the write response operation according to the timing requirements of the AXI bus. When the BVALID signal, the BREADY signal, and the BRESP signal are pulled high at the same time, it means that a write response operation has been completed. At the same time, the corresponding write operation ID is transmitted to the first register, and the write operation ID is modified back to the unoccupied state.

[0089] Furthermore, the write address controller is further configured to change the target write ID to an occupied state after detecting that the write address operation of this write operation is completed, specifically:

[0090] The write address controller is also used to detect the AWVALID signal and AWREADY signal of the AXI bus write address channel, and after detecting that the AWVALID signal and the AWREADY signal are pulled high at the same time, it is considered that the write address operation of this write operation is completed, and the target write ID is changed to the occupied state.

[0091] Among them, the AWVALID signal indicates that the host write address is valid, and the AWREADY signal indicates the handshake signal corresponding to the write address channel. Only when the AWVALID signal and the AWREADY signal are detected to be pulled high at the same time, the write address operation is considered to be completed.

[0092] Furthermore, the read operation module includes a read address controller, a read data controller, a data checker, a third register and a fourth register.

[0093] Among them, when the parameter configuration module is performing parameter configuration, the configuration parameters passed to the read address controller include the start address or end address of the read operation, the continuous transmission length parameter and the Outstanding parameter; the parameters passed to the data verifier include the read and write mode parameters, the read and write cycle number parameters and the write operation data Pattern setting parameters.

[0094] The read address controller and the read data controller are used to generate or receive excitations for corresponding channels.

[0095] The third register is used to store a read operation ID.

[0096] The maximum number of read operation IDs that can be stored is equal to the maximum preset Outstanding parameter.

[0097] The fourth register is used to store a read operation ID in an unoccupied state.

[0098] That is, the third register and the fourth register are both used to record the Outstanding operation status, and the storage depth of the third register and the fourth register is equal to the maximum Outstanding parameter required for this test.

[0099] The read operation ID in the third register can be marked as unoccupied and occupied. When the target read operation ID is in unoccupied state, it means that the target read operation ID is not occupied in the read channel and can be used for subsequent transmission operations; when the target read operation ID is in occupied state, it means that the target read operation ID is being used for read operation, and the same ID is not allowed to initiate a read request.

[0100] The read address controller is used to obtain the read operation ID in the unoccupied state after receiving the read operation start signal, assign the read operation ID as the target read ID to the ARID of the AXI bus read address channel, and assign the continuous transmission length parameter to the ARLEN of the AXI bus read address channel.

[0101] Specifically, when the read address controller receives the read operation start signal, it obtains the read operation ID in the unoccupied state from the third register, and assigns the read operation ID to the ARID signal in the AXI bus read address channel, and assigns the continuous transmission length parameter to the ARLEN signal in the AXI bus read address channel. The ARLEN signal is used to determine the burst length of the read transmission.

[0102] The read address controller is further configured to change the target read ID to an occupied state after detecting that the read address operation of this read operation is completed.

[0103] Specifically, when it is detected that the ARVALID signal and the ARREADY signal of the AXI bus read address channel are pulled high at the same time, it is considered that the read address operation of this read operation is completed.

[0104] Among them, the ARVALID signal represents that the host read address is valid, and the ARREADY signal represents the handshake signal corresponding to the read address channel.

[0105] The read data controller is used to read the corresponding write data from the target device under test according to the timing specified by the AXI bus protocol and the target read address and target read ID of this read operation, and after receiving the target read response signal corresponding to the target read ID from the target device under test, change the target read ID back to an unoccupied state.

[0106] Among them, the target write response signal is that the RVALID signal, RREADY signal and RLAST signal of the AXI bus read data channel are pulled high at the same time.

[0107] Specifically, the read data controller responds to the read data fed back by the target device under test according to the timing requirements specified by the AXI bus protocol. When it detects that the RVALID signal, RREADY signal and RLAST signal are pulled high at the same time, it means that a read operation has been completed, and the corresponding write operation ID is transmitted to the third register, and the state of the write operation ID in the third register is changed to an unoccupied state, and the corresponding write operation ID in the fourth register is cleared.

[0108] The data verifier is used to verify the correctness of the data based on the read write data and the preset write value after the read operation is completed when the read operation data verification parameter is yes.

[0109] The preset write value is determined according to the write operation data Pattern setting parameter.

[0110] Specifically, when the write operation data Pattern setting parameter is a fixed data mode, the preset write value is a preset fixed value, and the data verifier will check whether all the read write data is equal to the preset write value. If they are equal, it is considered that the target device under test has passed the data correctness check; otherwise, it is considered that the target device under test has not passed the data correctness check.

[0111] When the write operation data Pattern setting parameter is in the incremental mode, you need to first calculate the preset write value X using the following formula:

[0112] X=cycle_check_start_value+(ar_addr_record[M_AXI_RID]-read_addr_low) / (C_M_AXI_DATA_WIDTH / 8)+r_bl_record[M_AXI_RID];

[0113] Among them, cycle_check_start_value represents the initial value at the beginning of each round of write operation, corresponding to the number of cycles parameter in the configuration parameters, ar_addr_record[M_AXI_RID] represents the write operation start address of the corresponding write operation ID, read_addr_low represents the start address of the read operation, C_M_AXI_DATA_WIDTH represents the bit width of the data bus, and r_bl_record[M_AXI_RID] represents the number of burst transfer operations (Burst operation) in this read operation.

[0114] When the data returned by the read channel matches the calculated preset write value X, it is considered that the target device under test has passed the data correctness check; otherwise, it is considered that the target device under test has failed the data correctness check.

[0115] Furthermore, the data correctness check result is sent to the parameter configuration module. After the last read operation of the read channel is completed, it means that the data correctness check operation is completed. The external terminal can read the data check result of the target device under test from the parameter configuration module.

[0116] like Figure 2 As shown, in a second aspect, an embodiment of the present invention further provides a chip function verification method based on an AXI bus test stimulus source, the method comprising:

[0117] Step 101: configure the write operation module and the read operation module according to the received configuration parameters, and trigger a write operation start signal and a read operation start signal accordingly after completing the parameter configuration.

[0118] Step 102: After receiving the write operation start signal and detecting the existence of a write operation ID in an unoccupied state, a target write ID is assigned to this write operation, the target write ID is changed to an occupied state, and the write data of this write operation is sent to the target device under test based on the acquired target write address and target write ID of this write operation. After the write operation is completed, the target write ID is changed back to an unoccupied state.

[0119] Step 103: After receiving the read operation start signal and detecting the existence of a read operation ID in an unoccupied state, a target read ID is assigned to this read operation, the target read ID is changed to an occupied state, and the corresponding write data is read from the target device under test based on the acquired target read address and target read ID of this read operation, and the target read ID is changed back to an unoccupied state after the read operation is completed.

[0120] Step 104: After the current read operation is completed, data correctness verification is performed based on the read write data and the preset write value.

[0121] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the method described above can refer to the specific working process of the aforementioned systems, devices and units, and will not be repeated here.

[0122] Further, after performing data correctness verification according to the read write data and the preset write value, the chip function verification method of the AXI bus test stimulus source also includes:

[0123] The communication delay of the data transmission process is determined according to the acquired end time of the current write operation and the end time of the current read operation.

[0124] Specifically, after the communication delay of the target device under test in the current data transmission process is determined, the communication delay function of the target device under test can be verified by comparing the communication delay with a preset communication delay value.

[0125] The data throughput of the target device under test is determined according to the amount of written data written into the target device under test within the acquired target time period.

[0126] Data throughput refers to the rate at which data is written to the disk, and is also measured in the amount of data written per second.

[0127] Specifically, the target time period may be 1 second. After determining the data throughput of the target device under test, the data throughput function of the target device under test may be verified by comparing the data throughput with a preset data throughput value.

[0128] The design scheme of the present invention is designed based on synthesizable RTL codes, so the present invention can be applied to the scenarios of soft simulation, emulator verification, and FPGA verification.

[0129] Among them, in emulator verification and FPGA verification, since both the stimulus and the target device under test are synthesizable designs, compared with the soft simulation scenario, the present invention can cover more test cases and more verification cycles.

[0130] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, at least one program, a code set or an instruction set is loaded and executed by the processor to implement the chip function verification method of the AXI bus test stimulus source in the embodiment of the present invention.

[0131] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, in which at least one instruction, at least one program, code set or instruction set is stored, and at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor to implement the chip function verification method of the AXI bus test stimulus source in an embodiment of the present invention.

[0132] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by the computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0133] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An AXI bus test stimulus source, characterized in that: It includes parameter configuration module, write operation module and read operation module; The parameter configuration module is used to perform parameter configuration on the write operation module and the read operation module according to the received configuration parameters, and trigger a write operation start signal and a read operation start signal accordingly after completing the parameter configuration; The write operation module is used to allocate a target write ID for this write operation after receiving the write operation start signal and detecting that there is a write operation ID in an unoccupied state, change the target write ID to an occupied state, and send the write data of this write operation to the target device under test according to the acquired target write address of this write operation and the target write ID, and change the target write ID back to an unoccupied state after the write operation is completed; The read operation module is used to, upon receiving the read operation start signal and after detecting that there is a read operation ID in an unoccupied state, allocate a target read ID for this read operation, change the target read ID to an occupied state, and read corresponding write data from the target device under test according to the acquired target read address of this read operation and the target read ID, and change the target read ID back to an unoccupied state after the read operation ends; The read operation module is further used to perform data correctness verification based on the read write data and a preset write value after the read operation is completed.

2. The AXI bus test stimulus source according to claim 1, characterized in that: The configuration parameters include: a read operation start address or end address, a write operation start address or end address, a continuous transmission length parameter, an Outstanding parameter, a read / write mode parameter, a read / write cycle number parameter, a write operation data Pattern setting parameter, and whether to perform a read operation data verification parameter.

3. The AXI bus test stimulus source according to claim 2, characterized in that: The write operation module comprises: A write address controller, configured to obtain a write operation ID in an unoccupied state after receiving the write operation start signal, assign the write operation ID as a target write ID to the AWID of the AXI bus write address channel, and assign the continuous transmission length parameter to the AWLEN of the AXI bus write address channel; The write address controller is also used to change the target write ID to an occupied state after detecting that the write address operation of this write operation is completed; A data generator, configured to generate write data corresponding to the target write ID according to the write operation start address or end address and the write operation data Pattern setting parameters; A write data controller, used to obtain the write data corresponding to the target write ID, and send the write data corresponding to the target write ID to the target device under test according to the timing specified by the AXI bus protocol according to the continuous transmission length parameter; A write response controller is used to change the target write ID back to an unoccupied state after receiving a target write response signal from the target device under test for write data corresponding to the target write ID; the target write response signal is the BVALID signal, BREADY signal and BRESP signal of the AXI bus write response channel being pulled high at the same time.

4. The AXI bus test stimulus source according to claim 3, characterized in that: The write address controller is also used to change the target write ID to an occupied state after detecting that the write address operation of this write operation is completed, specifically: The write address controller is also used to detect the AWVALID signal and the AWREADY signal of the AXI bus write address channel, and after detecting that the AWVALID signal and the AWREADY signal are pulled high at the same time, it is considered that the write address operation of this write operation is completed, and the target write ID is changed to an occupied state.

5. The AXI bus test stimulus source according to claim 3, characterized in that: The write operation module also includes: A first register is used to store a write operation ID; the maximum storage quantity of the write operation ID is equal to the maximum preset Outstanding parameter; The second register is used to store a target write ID for which no write data is sent; the target write ID for which no write data is sent is a write operation ID in an occupied state.

6. The AXI bus test stimulus source according to claim 2, characterized in that: The read operation module comprises: A read address controller, configured to obtain a read operation ID in an unoccupied state after receiving the read operation start signal, assign the read operation ID as a target read ID to the ARID of the AXI bus read address channel, and assign the continuous transmission length parameter to the ARLEN of the AXI bus read address channel; The read address controller is also used to change the target read ID to an occupied state after detecting that the read address operation of this read operation is completed; A read data controller, configured to read corresponding write data from the target device under test according to the target read address of the current read operation and the target read ID acquired according to the timing specified by the AXI bus protocol, and change the target read ID back to an unoccupied state after receiving a target read response signal corresponding to the target read ID from the target device under test; the target write response signal is a RVALID signal, a RREADY signal, and a RLAST signal of the AXI bus read data channel being pulled high at the same time; A data verifier is used to verify the correctness of the data based on the read write data and the preset write value after the read operation is completed when the read operation data verification parameter is yes; the preset write value is determined according to the write operation data Pattern setting parameter.

7. The AXI bus test stimulus source according to claim 6, characterized in that: The read operation module also includes: A third register is used to store a read operation ID; the maximum storage quantity of the read operation ID is equal to the maximum preset Outstanding parameter; The fourth register is used to store a read operation ID in an unoccupied state.

8. A chip function verification method based on the AXI bus test stimulus source according to any one of claims 1 to 7, characterized in that: include: Perform parameter configuration on the write operation module and the read operation module according to the received configuration parameters, and trigger a write operation start signal and a read operation start signal accordingly after completing the parameter configuration; After receiving the write operation start signal and detecting that there is a write operation ID in an unoccupied state, assigning a target write ID to the current write operation, changing the target write ID to an occupied state, and sending the write data of the current write operation to the target device under test according to the acquired target write address of the current write operation and the target write ID, and changing the target write ID back to an unoccupied state after the current write operation is completed; After receiving the read operation start signal and detecting that there is a read operation ID in an unoccupied state, assigning a target read ID to this read operation, changing the target read ID to an occupied state, and reading corresponding write data from the target device under test according to the acquired target read address of this read operation and the target read ID, and changing the target read ID back to an unoccupied state after the read operation ends; After the read operation is completed, the data correctness is verified based on the read write data and the preset write value.

9. The chip function verification method of the AXI bus test stimulus source according to claim 8, characterized in that: After performing data correctness verification according to the read write data and the preset write value, the method further includes: Determine the communication delay of the data transmission process according to the acquired end time of the write operation and the end time of the read operation; The data throughput of this data transmission is determined according to the amount of written data written into the target device under test within the acquired target time period.

10. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the chip function verification method of the AXI bus test stimulus source as claimed in claim 8 or 9.

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