An isochronous design method, device, medium, program product, and memory architecture

Abstract

The present invention discloses an isochronous design method, device, medium, program product and memory architecture, relating to the field of circuit design. It solves the problem that the isochronous requirement cannot be achieved only by controlling the physical length. Specifically, by determining the topological structure of the target signal and identifying multiple key factors affecting the transmission delay of the target signal, this method quantifies each influencing factor into a target parameter related to the delay. There is a preset relationship between these target parameters and the transmission delay. According to the strict isochronous requirement, an isochronous design is carried out by comprehensively considering all target parameters, so as to ensure the precise isochronous requirement of DDR signals under complex wiring conditions, especially when it is difficult for the address signals of the same group of control commands to exit from the same layer.

Description

Technical Field

[0001] The present invention relates to the field of circuit design, and particularly to an isochronous design method, device, medium, program product, and memory architecture. Background Art

[0002] In the design of server DDR (Double Data Rate) signals, due to timing relationships, there are equal-length requirements between different signal groups of DDR signals (such as data signals, control command address signals, data signals and DQS (Data Strobe) signals, control command address signals and clock signals). With the increase in the signal rate of DDR5, these equal-length requirements become more stringent. It is generally desired that the signals in the same group are routed on the same layer, and the pin delays inside the chip package are not very different.

[0003] However, in the actual PCB (Printed Circuit Board) design, due to the limitations of chip pin distribution and routing space, especially for the same group of control command address signals, it is very difficult to route out from the same layer. Facing the strict equal-length requirements, simply controlling the physical length cannot achieve the isochronous requirements. Especially in the case where the isochronous requirements are very strict, it becomes extremely difficult to achieve the isochronous requirements of DDR signals.

[0004] Therefore, it is very necessary to provide a solution that takes into account the variable factors during routing on different layers to more accurately achieve the isochronous requirements of DDR signals. Summary of the Invention

[0005] The purpose of the present invention is to provide an isochronous design method, device, medium, program product, and memory architecture to ensure the accurate isochronous requirements of DDR signals under complex routing conditions, especially when it is difficult for the same group of control command address signals to route out from the same layer.

[0006] On the one hand, the present application provides an isochronous design method, including: determining the topological structure of the target signal; determining at least one influencing factor affecting the delay of the target signal in the transmission link of the target signal according to the topological structure; quantifying each influencing factor into a target parameter, where there is a preset relationship between the target parameter and the delay of the target signal; and performing isochronous design on the transmission link of the target signal according to the determined isochronous requirements and all the target parameters.

[0007] Among them, quantifying each influencing factor into a target parameter includes: determining the topological structure parameters where each influencing factor is located; and performing quantization processing on the influencing factor according to the topological structure parameters to obtain the target parameter.

[0008] Among them, the topological structure of the target signal includes a chip substrate; determining the topological structure parameters where each of the influencing factors is located, including: obtaining the pin delay parameters of the chip substrate, and the pin delay parameters include the pin length of each pin and the transmission time delay of the target signal on the pin; performing quantization processing on the influencing factors according to the topological structure parameters to obtain the target parameters, including: calculating the first transmission rate of the target signal on each pin according to the pin length and the transmission time delay of the target signal on the pin.

[0009] Among them, the topological structure includes the wiring layer of the target signal, and when the target signal is wired on at least two signal layers; determining the topological structure parameters where each of the influencing factors is located, including: determining the dielectric constant of the adjacent dielectric layer of the signal layer where the target signal is located; performing quantization processing on the influencing factors according to the topological structure parameters to obtain the target parameters, including: determining the second transmission rate of the target signal on the signal layer according to the dielectric constant, the speed of light, and the magnetic permeability.

[0010] Among them, the design structures of the adjacent dielectric layers of the signal layer where the target signal is located are the same; the design structure at least includes a dielectric material and a dielectric thickness.

[0011] Among them, the topological structure includes the wiring layer of the target signal, and when the target signal is wired on at least two signal layers, the topological structure further includes vias, and the vias are used to connect the two signal layers; determining the topological structure parameters where each of the influencing factors is located, including: determining the size of the via, and the size of the via includes the drilling size, the pad size, the anti-pad size, and the dielectric thickness; performing quantization processing on the influencing factors according to the topological structure parameters to obtain the target parameters, including: constructing a via simulation model according to the size of the via; determining the third transmission rate of the target signal at the via according to the via simulation model.

[0012] Among them, determining the third transmission rate of the target signal at the via according to the via simulation model includes: performing simulation on the via simulation model at a preset step within a preset frequency range to obtain a scattering parameter model; performing time-domain simulation on the scattering parameter model to obtain the transmission time delay of the target signal at the via; determining the third transmission rate according to the transmission time delay at the via and the size of the via.

[0013] Among them, determining the size of the via includes: determining the drill hole size, pad size, anti-pad size, and at least two different dielectric thicknesses; constructing a via simulation model according to the size of the via, including: constructing at least two of the via simulation models according to the drill hole size, the pad size, the anti-pad size, and at least two different dielectric thicknesses; determining the third transmission rate of the target signal at the via according to the via simulation model, including: determining the sub-transmission delay of the target signal at the via with different dielectric thicknesses according to each of the via simulation models; determining the third transmission rate according to all the sub-transmission delays and the size of the via.

[0014] Among them, determining the third transmission rate according to all the sub-transmission delays and the size of the via includes: determining the corresponding third sub-transmission rate according to each of the sub-transmission delays and the corresponding via size; calculating the average value of all the third sub-transmission rates to obtain the average transmission rate; using the average transmission rate as the third transmission rate.

[0015] Among them, determining the third transmission rate according to all the sub-transmission delays and the size of the via includes: obtaining the delay difference between every two of the sub-transmission delays; calculating the dielectric thickness difference corresponding to every two of the sub-transmission delays; determining the third transmission rate according to the delay difference and the dielectric thickness difference.

[0016] On the other hand, the present application provides an isochronous design system, including: a structure determination unit for determining the topological structure of a target signal; an influence factor determination unit for determining at least one influence factor that affects the delay of the target signal in the transmission link of the target signal according to the topological structure; a parameter quantization unit for quantifying each of the influence factors into a target parameter, and there is a preset relationship between the target parameter and the delay of the target signal; a design unit for performing isochronous design on the transmission link of the target signal according to the determined isochronous requirements and all the target parameters.

[0017] On the other hand, the present application provides an isochronous design device, including: a memory for storing a computer program; a processor for implementing the steps of the above-mentioned isochronous design method when executing the computer program.

[0018] On the other hand, the present application provides a non-volatile storage medium, on which a computer program is stored, and the computer program realizes the steps of the above-mentioned isochronous design method when executed by a processor.

[0019] On the other hand, the present application provides a computer program product, including a computer program / instructions, and the computer program / instructions realize the steps of the above-mentioned isochronous design method when executed by a processor.

[0020] On the other hand, the present application provides a memory architecture designed according to the isochronous design method as described above.

[0021] The present invention provides an isochronous design method, device, medium, program product, and memory architecture in the field of circuit design. It solves the problem that the isochronous requirement cannot be achieved only by controlling the physical length. Specifically, by determining the topological structure of the target signal and identifying multiple key factors affecting the transmission delay of the target signal, this method quantifies each influencing factor into a target parameter related to the delay. There is a preset relationship between these target parameters and the transmission delay. According to the strict isochronous requirement, all target parameters are comprehensively considered for isochronous design, so as to ensure the precise isochronous requirement of DDR signals under complex wiring conditions, especially when it is difficult for the address signals of the same group of control commands to exit from the same layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 It is a flowchart of an isochronous design method provided by the present invention;

[0024] Figure 2 It is a schematic structural diagram of a 62 - mil via provided by the present invention;

[0025] Figure 3 It is a schematic structural diagram of a 182 - mil via provided by the present invention;

[0026] Figure 4 It is a schematic diagram of the simulation delay result of the left - hand single - ended via in a 182 - mil via provided by the present invention;

[0027] Figure 5 It is a schematic diagram of the simulation delay result of the right - hand single - ended via in a 182 - mil via provided by the present invention;

[0028] Figure 6 It is a schematic diagram of the simulation delay result of the left - hand single - ended via in a 62 - mil via provided by the present invention;

[0029] Figure 7 It is a schematic diagram of the simulation delay result of the right - hand single - ended via in a 62 - mil via provided by the present invention;

[0030] Figure 8Schematic diagram of an isochronous design device provided by the present invention;

[0031] Figure 9 Schematic diagram of a non - volatile storage medium provided by the present invention. Detailed implementation manners

[0032] The core of the present invention is to provide an isochronous design method, device, medium, program product and memory architecture to ensure the precise isochronous requirements of DDR signals under complex wiring conditions, especially when it is difficult for the address signals of the same - group control commands to exit from the same layer.

[0033] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] On the one hand, as Figure 1 shown, the present application provides an isochronous design method, including:

[0035] S11: Determine the topological structure of the target signal.

[0036] In actual PCB design, in order to achieve the isochronous design of DDR signals, it is first necessary to determine the topological structure of the target signal. The purpose of this step is to understand the specific layout and connection method of the target signal in the entire transmission path. The topological structure refers to the wiring layer of the target signal on the printed circuit board and its connection relationship with each relevant component, including but not limited to the wiring path after the signal comes out of the chip pin, the number and position of vias, the length and path of each layer of wiring, and the destination where the signal finally arrives. By determining the topological structure of the target signal, the signal transmission path and possible influencing factors can be comprehensively understood, providing basic data and a basis for subsequent delay analysis and optimization design. This step ensures that all relevant factors can be comprehensively and accurately considered during analysis, thus laying a foundation for achieving high - precision isochronous design.

[0037] Among them, the process of determining the topological structure of the target signal includes:

[0038] Circuit function analysis: It is necessary to clarify the function and role of the target signal in the circuit. This includes determining the starting point (source) and ending point (destination) of the signal, as well as the transmission path and role of the signal in the circuit;

[0039] Signal layer planning: Determine the signal layer on which the target signal should be routed based on the hierarchical structure of the circuit board and the characteristics of the signal. This may involve choosing between inner and outer signal layers and the routing methods between different signal layers;

[0040] Routing path planning: Determine the routing path of the target signal, including the physical path from the source to the destination. This usually requires considering factors such as the shortest routing path, the transmission direction of the signal, and avoiding electromagnetic interference and crosstalk;

[0041] Selection of signal layer: Select a suitable signal layer for routing according to the design requirements of the circuit board and the characteristics of the target signal. For example, high-speed signals may need to be routed on an inner layer close to the ground plane to reduce transmission losses and interference;

[0042] Via and connection design: If the target signal needs to cross different signal layers or connect to other circuit board components, the position, size, and layout of the vias need to be considered. The design of the vias should meet the transmission requirements of the signal and avoid having a negative impact on the signal quality;

[0043] Interface and connector design: Determine the types of interfaces and connectors for the target signal to ensure its compatibility and stability with other circuit board components. This includes the selection and layout of sockets and connectors, as well as the way of leading out the signal lines;

[0044] Consideration of environmental factors: Consider the potential impact of environmental factors in the PCB layout, such as temperature changes, humidity, and mechanical vibration, on the transmission and layout of the target signal.

[0045] S12: Determine at least one influencing factor that affects the time delay of the target signal in the transmission link of the target signal according to the topological structure.

[0046] During the isochronous design process, this step is based on the topological structure of the target signal to determine which factors in the transmission link will affect the target signal, and these factors will have a direct or indirect impact on the delay of the target signal. First, it is necessary to identify all the physical and electrical characteristics in the transmission path of the target signal that may affect the signal transmission delay. These influencing factors include but are not limited to: the pindelay (pin delay) of the chip carrier board, which determines the starting delay of the signal from the chip pin to the PCB; the transmission rate differences between different signal layers, which are mainly determined by the dielectric constant of the PCB material and the dielectric thickness of each layer; the transmission rate of the signal in the via, which is different from that on the transmission line because the electrical characteristics of the via are different from those of the planar wiring. In addition, it is also necessary to consider the length of each section of the transmission line in the signal path and the specific wiring environment of each section of the line, including whether there are problems such as crossovers, interferences, and reflections. By analyzing and determining these influencing factors in detail, the impact of each factor on the signal delay can be quantified, providing accurate data support for the delay calculation and isochronous design in the subsequent steps. This step ensures that all influencing factors are fully considered and accurately quantified during the isochronous design, thus achieving precise delay control of the target signal.

[0047] S13: Quantify each influencing factor into a target parameter, and there is a preset relationship between the target parameter and the delay of the target signal.

[0048] During the isochronous design process, this step is to quantify each of the previously determined influencing factors into specific target parameters and establish the relationship between these target parameters and the delay of the target signal. First, for each influencing factor, a method that can accurately represent its impact on the signal delay needs to be found. For example, the pindelay of the chip carrier board can obtain its corresponding delay value through measurement or simulation, the transmission rate of the transmission line can be calculated through parameters such as the dielectric constant and the dielectric thickness, and the transmission delay of the via can be calculated through its physical length and a specific transmission rate.

[0049] The values obtained from these calculations are the so-called target parameters. Next, these target parameters need to be converted into a unified delay unit to ensure that all parameters are compared and superimposed within the same delay framework. For example, all physical lengths can be converted into time units through the known transmission rate. Through this method, the influencing factors of different parts such as the chip carrier board, the transmission line, and the via can be quantified into delay parameters. Then, based on these delay parameters, an overall delay model is established, which can accurately reflect the actual delay situation of the target signal in the transmission link. This process is not just a simple numerical conversion, but also needs to consider the interaction and comprehensive impact between various parameters to ensure that the final delay model can truly reflect the transmission delay of the target signal, thus providing reliable basic data support for the subsequent isochronous design.

[0050] S14: Perform isochronous design on the transmission link of the target signal according to the determined isochronous requirements and all target parameters.

[0051] In the process of isochronous design, this step is to perform isochronous design on the transmission link of the target signal according to the determined isochronous requirements and all target parameters. First, it is necessary to clarify the isochronous requirements, which are the benchmarks for the entire design process. For example, for DDR signals, the isochronous requirements may include that the time difference of the same group of signals arriving at the receiving end cannot exceed a certain range. Then, use all the target parameters quantified in the previous steps, including the pindelay of the chip carrier board, the transmission rate of the transmission line, and the transmission delay of the via. By combining these parameters, a complete transmission link delay model can be established.

[0052] When performing isochronous design, first calculate the total delay of each transmission link. This can be obtained by adding the delays of each part in the link. For each link, it is necessary to ensure that its total delay meets the isochronous requirements. For example, if the delay of a certain link is too long, its physical length can be adjusted, its routing layer can be changed, or the via design can be optimized to reduce its delay. On the contrary, if the delay of a certain link is too short, its physical length can be increased or the routing path can be adjusted to increase its delay.

[0053] In addition, it is also necessary to ensure the consistency of the signal transmission rate between different layers. This can be achieved by using the same dielectric constant material and the same dielectric thickness to reduce the difference in transmission rates between different layers. In this way, it can be ensured that the transmission delays between different signal groups are as consistent as possible, thereby achieving the overall isochronous design.

[0054] Finally, through repeated simulation and optimization, ensure that the delay of each transmission link is within the allowable range and meets the overall isochronous requirements. Through this process, the problems brought by the chip pin distribution and wiring space limitations can be effectively solved, ensuring that the DDR signal can work stably under strict isochronous requirements. This not only improves the reliability of the design, but also simplifies the design process and improves work efficiency.

[0055] Based on the above embodiments:

[0056] In one embodiment, each influencing factor is quantified into target parameters, including: determining the topological structure parameters where each influencing factor is located; and quantifying the influencing factor according to the topological structure parameters to obtain the target parameters.

[0057] In one embodiment, the process of quantifying each influencing factor into target parameters includes the following two main steps: determining the topological structure parameters where each influencing factor is located, and quantifying the influencing factor according to the topological structure parameters to obtain the target parameters.

[0058] First, determine the topological structure parameters where each influencing factor is located. The purpose of this step is to accurately identify and describe the factors affecting signal delay and their positions in the signal transmission link. These influencing factors usually include the pin delay (pindelay) of the chip carrier board, the transmission rate of the transmission line, the transmission delay of the via, etc. When determining these influencing factors, the specific wiring structure of the PCB needs to be considered. For example, for the pin delay of the chip carrier board, it is necessary to understand the distribution of the chip pins and the specific positions of their physical connections. For the transmission rate of the transmission line, the dielectric constant, dielectric thickness of each layer of wiring, and the specific path of the trace need to be considered. Similarly, for the via transmission delay, it is necessary to understand the physical length of the via and its position in the entire transmission link.

[0059] Next, quantify the influencing factors into target parameters according to the determined topological structure parameters. The purpose of this step is to convert the physical properties of each influencing factor into quantization parameters that can be directly used for delay calculation. For example, for the pin delay of the chip carrier board, if the physical length of the pin and the transmission rate of the carrier board material are known, the physical length can be converted into a time delay. Similarly, for the transmission rate of the transmission line, according to the structural parameters of the PCB, such as the dielectric constant and dielectric thickness, the transmission delay per unit length can be calculated, and the physical length of the trace can be converted into the corresponding time delay. For the via transmission delay, it can be converted into a time delay according to the physical length of the via and its transmission rate. In this way, the physical properties of each influencing factor are quantified into target parameters related to time.

[0060] Throughout the process, there are certain preset relationships among the quantified target parameters, and these relationships reflect the comprehensive influence of each influencing factor on the signal transmission time. Through this quantization and calculation, the complex physical wiring structure and the time delays of various influencing factors can be accurately represented as numerical parameters, providing accurate basic data for subsequent isochronous design. This method not only improves the design accuracy but also enables more systematic and efficient isochronous design of the signal transmission link, ensuring that DDR signals can be transmitted stably and efficiently under strict delay requirements.

[0061] In one embodiment, when the topological structure of the target signal includes a chip substrate; determine the topological structure parameters where each influencing factor is located, including: obtaining the pin delay parameters of the chip substrate, and the pin delay parameters include the pin length of each pin and the transmission delay of the target signal on the pin; perform quantization processing on the influencing factors according to the topological structure parameters to obtain target parameters, including: calculating the first transmission rate of the target signal on each pin according to the pin length and the transmission delay of the target signal on the pin.

[0062] In one embodiment, the topology of the target signal mainly involves the layout of the chip substrate and the signal transmission path. First, it is necessary to determine the topology structure parameters where each influencing factor is located in order to accurately quantify the impact of these factors on the transmission delay of the target signal.

[0063] Specifically, first obtain the pin delay parameters of the chip substrate. These parameters include the pin length of each pin and the transmission delay of the target signal within the pin. The pin length refers to the physical distance from the starting point to the ending point of the chip pin, and the transmission delay of the target signal within the pin depends on the propagation speed and distance of the signal within the pin. Usually, the chip manufacturer provides the geometric layout of the pins and the typical transmission characteristics of each pin, and this information is the basis for determining the pin delay parameters.

[0064] Secondly, quantify the influencing factors into target parameters according to the determined topology structure parameters. In this step, using the known pin length and the transmission delay of the target signal within the pin, calculate the first transmission rate of the target signal on each pin. This first transmission rate reflects the initial transmission performance of the target signal after entering the chip pin and is one of the key factors affecting the signal transmission delay.

[0065] For example, Propagation Velocity = 614.78mil / 92.72724474ps = 6.63mil / ps, where 6.63mil / ps = 1.68402×10 8 m / s. Among them, Propagation Velocity is the first transmission rate, 614.78mil is the pin length, and 92.72724474ps is the time for the target signal to be transmitted on the pin.

[0066] By quantifying each influencing factor, such as pin delay, into target parameters, the complex characteristics of the signal transmission path on the chip substrate can be accurately described. These quantified parameters not only help to understand the specific contributions of each factor to the signal delay but also provide basic data for subsequent isochronous design. In actual PCB design, through this method, the signal transmission link can be effectively optimized to ensure that the target signal can be transmitted stably and reliably under high-speed and strict delay requirements.

[0067] In one embodiment, when the topology includes the wiring layer of the target signal and the target signal is routed on at least two signal layers; determine the topology structure parameters where each influencing factor is located, including: determining the dielectric constant of the adjacent dielectric layer of the signal layer where the target signal is located;

[0068] Perform quantization processing on the influencing factors according to the topology structure parameters to obtain target parameters, including:

[0069] Determine the second transmission rate of the target signal in the signal layer based on the dielectric constant, the speed of light, and the magnetic permeability.

[0070] In one embodiment, the topology refers to the routing manner of the target signal on the PCB, especially in the case where the target signal is routed on at least two signal layers. To achieve isochronous design, it is first necessary to determine the topology parameters where each influencing factor is located.

[0071] Specifically, the first step is to determine the dielectric constant of the adjacent dielectric layer of the signal layer where the target signal is located. The dielectric constant is a physical quantity that describes the influence of the medium on the propagation speed of electromagnetic waves. Different dielectric constants will result in differences in the propagation speed of signals in different media. In PCB design, different signal layers usually use media with different dielectric constants.

[0072] The second step is to quantify the influencing factor into a target parameter according to the topology parameters. In this step, physical quantities such as the determined dielectric constant, the speed of light (the propagation speed of electromagnetic waves in a vacuum), and the magnetic permeability (describing the properties of electromagnetic wave propagation in a medium) are used to calculate the second transmission rate of the target signal within the signal layer. The second transmission rate reflects the actual propagation speed of the target signal in a specific medium, taking into account the influencing factors of the medium on the propagation of electromagnetic waves.

[0073] The calculation formula for the second transmission rate is: ; where is the second transmission rate, is the speed of light in a vacuum, is the dielectric constant, is the magnetic permeability.

[0074] By quantifying each influencing factor, such as the dielectric constant, into a target parameter, it is possible to more accurately predict and control the time delay of the target signal during transmission between different signal layers. This method not only helps to optimize the transmission performance of the signal but also meets the strict requirements for isochronism during high-speed signal transmission, ensuring the stable and reliable transmission of the signal in a complex PCB layout.

[0075] In one embodiment, the design structures of the adjacent dielectric layers of the signal layer where the target signal is located are the same; the design structure includes at least the dielectric material and the dielectric thickness.

[0076] In one embodiment, the design structure of the signal layer where the target signal is located includes adjacent dielectric layers. During design, the structures of these dielectric layers are designed to be the same. The design structure includes at least two important parameters: the dielectric material and the dielectric thickness.

[0077] First, the dielectric material determines the speed and characteristics of signal propagation in the dielectric layer. Different dielectric materials have different dielectric constants and other electromagnetic characteristics, which directly affect the signal propagation speed. In high-speed signal transmission, selecting an appropriate dielectric material can effectively control signal delay and loss, ensuring stable signal transmission. Secondly, the dielectric thickness affects the signal transmission delay and impedance matching. Dielectric layers with different thicknesses will result in different reflection, refraction, and coupling effects during signal propagation, thus affecting signal stability and transmission quality. During the design process, by keeping the design structures of adjacent dielectric layers the same, especially unifying the dielectric material and thickness, the variables in signal transmission can be reduced, and the design consistency and reliability can be improved. For example, if the DDR control command signal routing layer is three layers, it is necessary to keep these three signal layer stacks consistent (if L3, L5, and L7 layers are all signal layers, then the thickness, material, etc. of these three layers should be the same).

[0078] Therefore, by ensuring that the adjacent dielectric layers of the signal layer where the target signal is located have the same design structure, especially the same dielectric material and dielectric thickness, the influence difference of different dielectric layers on the signal propagation speed can be effectively reduced, thus better meeting the isochronous design requirements in high-speed signal transmission and ensuring stable signal transmission and high-quality performance in complex PCB layouts.

[0079] As Figure 2 shown, in one embodiment, the topology includes the routing layer of the target signal. When the target signal is routed on at least two signal layers, the topology further includes vias for connecting the two signal layers; determining the topology structure parameters where each influencing factor is located, including: determining the size of the via, and the size of the via includes the drill size, pad size, anti-pad size, and dielectric thickness; performing quantization processing on the influencing factor according to the topology structure parameters to obtain target parameters, including: constructing a via simulation model according to the size of the via; determining the third transmission rate of the target signal at the via according to the via simulation model. In one embodiment, determining the third transmission rate of the target signal at the via according to the via simulation model includes: simulating the via simulation model at a preset step within a preset frequency range to obtain a scattering parameter model; performing time-domain simulation on the scattering parameter model to obtain the transmission delay of the target signal at the via; determining the third transmission rate according to the transmission delay at the via and the size of the via.

[0080] In this embodiment, the topology includes routing the target signal on at least two signal layers and involves the use of vias for connecting these different signal layers. The size of the via is one of the influencing factors, and its specific parameters include the drill size, pad size, anti-pad size, and the thickness of the dielectric layer. These parameters directly affect the transmission performance and characteristics of the signal when passing through the via.

[0081] First, in order to quantify these influencing factors as target parameters, a via simulation model needs to be constructed. The via simulation model takes into account the geometric shape of the via and the characteristics of the surrounding medium, such as the dielectric constant and thickness of the medium. Through these parameters, a simulation model can be established to accurately describe the transmission characteristics of the via.

[0082] Second, perform simulation analysis using the established via simulation model. Within a preset frequency range, with a preset step size (e.g., preset frequency range: 0 - 60 GHz, preset step size: 10 MHz. The frequency range of 0 - 60 GHz covers the typical operating frequencies of modern high - speed digital signals and radio - frequency signals. For example, high - speed serial links and many radio - frequency applications operate within this frequency range. Therefore, choosing this frequency range can ensure that the simulation results are representative of most practical application scenarios. The choice of the step size (10 MHz) needs to find a balance between simulation accuracy and computational resources. A smaller step size can provide higher simulation accuracy but will increase the calculation time and resource consumption. A 10 - MHz step size can provide sufficient accuracy in most cases while maintaining reasonable computational efficiency), simulate the via simulation model to obtain the scattering parameter model of the via. These scattering parameters describe the reflection, transmission, and scattering of signals at the via, which are crucial for understanding the entire process of signal transmission. Then, perform time - domain simulation analysis based on the scattering parameter model. Through time - domain simulation, the transmission delay of the target signal at the via can be obtained. The transmission delay reflects the delay situation of the signal passing through the via, taking into account the speed and path of the signal propagating in different media.

[0083] Finally, based on the transmission delay at the via and the known via size parameters, the third transmission rate of the target signal at the via can be determined. This step combines the quantitative analysis of physical dimensions and electromagnetic characteristics to ensure accurate evaluation and optimization of the signal transmission performance during the design process.

[0084] Therefore, through the above steps, the accurate modeling and analysis of the transmission characteristics of the target signal passing through vias in a complex PCB layout are achieved, providing key technical support and methods for isochronous design.

[0085] In one embodiment, determining the size of the via includes: determining the drill size, pad size, anti - pad size, and at least two different dielectric thicknesses; constructing a via simulation model according to the size of the via, including: constructing at least two via simulation models according to the drill size, pad size, anti - pad size, and at least two different dielectric thicknesses; determining the third transmission rate of the target signal at the via according to the via simulation model, including: determining the sub - transmission delay of the target signal at the via with different dielectric thicknesses according to each via simulation model; determining the third transmission rate according to all sub - transmission delays and the size of the via.

[0086] In this embodiment, determining the via size is a crucial step in PCB design as it directly affects the performance and stability of signal transmission. The via size includes the drill size, pad size, and anti-pad size, while considering at least two different dielectric thicknesses. The drill size refers to the actual hole diameter through the PCB board, the pad size is the diameter of the metal ring for soldering the via, and the anti-pad size is the diameter of the circular area outside the soldering area, which is used to prevent the soldering material from flowing to areas that should not be soldered, thus avoiding short circuits or other electrical problems.

[0087] Based on these size parameters, it is necessary to construct a via simulation model to accurately simulate and analyze the transmission characteristics of signals under different conditions. Specifically, multiple via simulation models need to be constructed according to the actual size parameters of each via and at least two different dielectric thicknesses. Different dielectric thicknesses will result in different electromagnetic field characteristics and transmission rates when signals are transmitted, so each simulation model needs to consider these changes.

[0088] After constructing the via simulation model, detailed analysis is required to determine the third transmission rate of the target signal at the via. This includes the following steps: First, perform simulations for each via simulation model to obtain the sub-transmission delays of the target signal under different dielectric thicknesses. These sub-transmission delays reflect the delay situation of the signal when passing through the via, considering the speed and path of electromagnetic waves propagating in different dielectrics. Second, integrate and analyze all the sub-transmission delays with the corresponding via size parameters. By comprehensively considering the data obtained from each simulation model, the comprehensive transmission delay of the target signal at the via under different dielectric thicknesses can be determined. This comprehensive transmission delay is the result based on the actual via design parameters and reflects the actual transmission performance of the signal passing through the via in a complex PCB layout.

[0089] Among them, the drill size is 8 mil, the pad size is 16 mil, and the anti-pad size is 24 mil, which is the size for avoiding other signals. The via pitch S:G:S:G = 31.5 mil (where S is the signal via and G is the ground via), and the via length is 62 mil (as Figure 2 shown). Another dielectric thickness is increased by 120 mil (as Figure 3 shown) (here 120 mil is just a preferred value, and its specific value can be between 50 mil and 200 mil), making the via length 182 mil.

[0090] In summary, through the above steps and methods, the impact of via size on the transmission characteristics of the target signal can be effectively quantified and analyzed, providing the necessary technical support and methods for isochronous design in PCB design. This method can ensure meeting strict isochronous requirements in high-speed signal transmission design and improve the reliability and stability of signal transmission.

[0091] In one embodiment, determining the third transmission rate according to all sub - transmission delays and the size of the vias includes: determining the corresponding third sub - transmission rate according to each sub - transmission delay and the corresponding via size; calculating the average value of all the third sub - transmission rates to obtain the average transmission rate; and taking the average transmission rate as the third transmission rate.

[0092] In this embodiment, determining the third transmission rate of the target signal at the via involves multiple steps and calculation processes to ensure accuracy and reliability. First, according to each sub - transmission delay and the corresponding via size obtained from the aforementioned via simulation model, each sub - transmission rate can be calculated. Each sub - transmission rate is the actual transmission delay obtained based on the specific via design parameters and the simulation model, reflecting the transmission performance of the signal when passing through the via under different conditions.

[0093] Next, all the third sub - transmission rates are summarized and considered comprehensively. This step includes calculating the comprehensive result of all the third sub - transmission rates to determine the third transmission rate of the target signal at the via. Specifically, a weighted average or a simple average calculation method may be used, depending on the specific requirements of the design and the method selection. After the weighted average or simple average calculation is completed, the obtained result is the third transmission rate of the target signal at the via. This transmission rate is based on the comprehensive calculation result of all sub - transmission rates, taking into account the influence of each simulation model and via design parameter, providing a practical and operable value. This method ensures that in PCB design, the isochronous performance of signal transmission can be accurately evaluated and optimized. Especially in high - speed signal transmission, it can effectively meet strict isochronous requirements.

[0094] Among them, by using different dielectric thicknesses, the simulation model can more realistically reflect the physical structure on the actual PCB. The simulation model for each thickness will calculate the transmission delay of the target signal at the via. These delays reflect the effects such as reflection, dispersion, and loss that the signal may encounter when passing through different dielectric thicknesses, thus providing a more accurate evaluation of signal transmission performance. Multiple simulation models constructed based on different dielectric thicknesses can provide opportunities for comparison and verification. By comparing the simulation results under different thickness conditions, design engineers can better understand and analyze the physical phenomena in the signal transmission process and optimize the design to meet the isochronous requirements.

[0095] In summary, through the above steps and methods, the actual transmission rate of the target signal passing through the via in a complex PCB layout can be effectively determined, providing key technical support and data reference for design engineers to ensure the reliability of the design and performance optimization.

[0096] In one embodiment, determining a third transmission rate based on all sub - transmission time delays and the size of the via includes: obtaining the time - delay difference between every two sub - transmission time delays; calculating the difference in medium thickness corresponding to every two sub - transmission time delays; and determining the third transmission rate based on the time - delay difference and the difference in medium thickness.

[0097] In this embodiment, the process of determining the third transmission rate based on all sub - transmission time delays can be explained in detail as follows: First, obtain the sub - transmission time delays under every two different medium thicknesses. These time delays represent the transmission delays of the target signal passing through the via under different medium conditions. Suppose we have two medium thicknesses, h1 and h2, and the corresponding sub - transmission time delays are t1 and t2 respectively. Second, calculate the time - delay difference Δt = t2 - t1. The time - delay difference reflects the difference in the transmission speed of the target signal under two different medium thicknesses. Then, calculate the difference in medium thickness Δh = h2 - h1. The difference in medium thickness represents the physical thickness difference between the two media. Finally, determine the third transmission rate based on the time - delay difference Δt and the difference in medium thickness Δh.

[0098] As Figure 4 and Figure 5 , Figure 4 in, m7 and m8 correspond to the input waveform and output waveform of the left single - ended via with a size of 182 mil respectively. The arrow positions in m7 and m8 are the input time point (135.9 ps) and output time point (197.9 ps) of 0.499 V respectively. Subtracting the output time point from the input time point corresponding to the left single - ended via can obtain the transmission time of the left single - ended via in the 182 - mil differential via. Similarly, Figure 5 in, m5 and m6 correspond to the input waveform and output waveform of the right single - ended via with a size of 182 mil respectively. The arrow positions in m5 and m6 are the input time point (135.9 ps) and output time point (197.9 ps) of 0.499 V respectively. Subtracting the output time point from the input time point corresponding to the right single - ended via can obtain the transmission time of the right single - ended via in the 182 - mil differential via. In summary, the transmission time delay of the 182 - mil via can be obtained: delay_182mil_via = 62 ps.

[0099] As Figure 6 and Figure 7 , Figure 6Among them, m3 and m4 correspond to the input waveform and output waveform of the left single-ended via with a size of 62 mil respectively. The arrow positions in m3 and m4 are the input time point (135.8 ps) and output time point (163.2 ps) of 0.498 V respectively. Subtracting the output time point from the input time point corresponding to the left single-ended via can obtain the transmission time of the left single-ended via in the 62 mil differential via. Similarly, Figure 7 Among them, m1 and m2 correspond to the input waveform and output waveform of the right single-ended via with a size of 182 mil respectively. The arrow positions in m1 and m2 are the input time point (136.1 ps) and output time point (163.5 ps) of 0.502 V respectively. Subtracting the output time point from the input time point corresponding to the right single-ended via can obtain the transmission time of the right single-ended via in the 62 mil differential via. In summary, the transmission delay of the 62 mil via can be obtained: delay_62mil_via = 27.4 ps.

[0100] Thus, the transmission rate of the via can be obtained: 120 mil / (62 ps - 27.4 ps) = 3.468 mil / ps.

[0101] In summary, by obtaining the difference between the two sub-transmission delays and combining the differences in the thicknesses of the two media, the transmission rate of the target signal under the thickness of the third media can be effectively determined. This method utilizes the differences in transmission characteristics under different media conditions, thereby improving the accurate evaluation of the transmission performance of the target signal in complex PCB layouts.

[0102] In a specific embodiment, after quantifying all the transmission rates of the factors affecting the isochronous design of DDR signals above, PCB isochronous design is carried out. Taking one of the links as an example: for example, the control signal link on layer L8. This link includes a control chip substrate and 5 DRAM (Dynamic Random Access Memory) chips, and the link adopts a fly-by topology. When performing signal isochronous design, it is necessary to integrate the transmission delays of all parts of the link, that is, the pin delay pindelay of the chip substrate + the transmission line delay of the link + the via delay on the link.

[0103] Among them, the calculation of the pin delay of the chip substrate: If the pin delay of the chip substrate is in length units, according to the first transmission rate calculation method calculated above, the physical length is converted into time (specifically, the calculation method of the above first transmission rate can be referred to).

[0104] Among them, the calculation of the transmission line delay: For the transmission lines of the top layer and the L8 layer, the transmission rate is determined by the PCB structure (including the dielectric thickness of the upper and lower layers, the dielectric constant of the dielectric, and the transmission). After the physical length of each layer is determined, it is converted into a delay according to the transmission speed and the physical length (specifically, the calculation method of the second transmission rate can be referred to).

[0105] The transmission rate formula of the transmission line in the PCB. Among them, the calculation of the via transmission delay: For this link with multiple vias, after the physical length and the transmission rate of the vias are known, they can be converted into via delays (specifically, the calculation method of the third transmission rate above can be referred to).

[0106] Then, the transmission delays of each part of the link are superimposed to obtain the transmission delay of the entire link. By using the same method for the same group of signals to obtain the transmission delays of their respective links, it is convenient for the staff to perform isochronous design. For this design, to reduce variables, the same group of control command signals are stacked and designed with the same stack structure, and the dielectric thickness and dielectric material of the upper and lower dielectric layers of the signal layer are the same, reducing the variable of different transmission rates of the transmission lines and simplifying the design. The above is the method for calculating the delay based on the known physical length. When calculating the physical length based on the known transmission delay, it is exactly the opposite, and this application will not elaborate here.

[0107] On the other hand, this application provides an isochronous design system, including: a structure determination unit for determining the topological structure of the target signal; an influence factor determination unit for determining at least one influence factor that affects the delay of the target signal in the transmission link of the target signal according to the topological structure; a parameter quantization unit for quantifying each of the influence factors into a target parameter, and there is a preset relationship between the target parameter and the delay of the target signal; a design unit for performing isochronous design on the transmission link of the target signal according to the determined isochronous requirements and all the target parameters. For other introductions to the isochronous design system, please refer to the above embodiments, and this application will not elaborate here.

[0108] On the other hand, as Figure 8 shown, this application provides an isochronous design device, including: a memory 31 for storing a computer program; a processor 32 for implementing the steps of the above isochronous design method when executing the computer program.

[0109] For other introductions to the isochronous design device, please refer to the above embodiments, and this application will not elaborate here.

[0110] On the other hand, as Figure 9 shown, this application provides a non - volatile storage medium 41, on which a computer program 42 is stored, and when the computer program 42 is executed by a processor, the steps of the above isochronous design method are implemented.

[0111] For other introductions to the non-volatile storage medium 41, please refer to the above embodiments, and details are not described herein again in this application.

[0112] On the other hand, this application provides a computer program product, including a computer program / instructions, which implement the steps of the above isochronous design method when executed by a processor.

[0113] For other introductions to the computer program product, please refer to the above embodiments, and details are not described herein again in this application.

[0114] On the other hand, this application provides a memory architecture designed according to the isochronous design method as described above.

[0115] For other introductions to the memory architecture, please refer to the above embodiments, and details are not described herein again in this application.

[0116] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0117] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An isochronous design method, characterized in that: include: Determine the topology of the target signal; Determine at least one influencing factor affecting the delay of the target signal in the transmission link of the target signal according to the topological structure; quantifying each of the influencing factors into a target parameter, wherein the target parameter has a preset relationship with the time delay of the target signal; Performing isochronous design on the transmission link of the target signal according to the determined isochronous requirement and all the target parameters; Wherein, the influencing factors include the size of the via, and quantifying each of the influencing factors into a target parameter includes: Determine the size of the via, construct a via simulation model based on the size of the via, and simulate the via simulation model within a preset frequency range and with a preset step size to determine a target transmission rate of the target signal at the via; wherein the preset frequency range is determined based on the operating frequency of the high-speed digital signal and the radio frequency signal; and the preset step size is determined based on simulation accuracy and computing resources.

2. The isochronous design method according to claim 1, characterized in that: Quantify each of the impact factors into target parameters, including: Determine the topological structure parameters where each of the influencing factors is located; The influencing factor is quantified according to the topological structure parameter to obtain the target parameter.

3. The isochronous design method according to claim 2, characterized in that: The topological structure of the target signal includes a chip substrate; determining the topological structure parameters of each influencing factor includes: Acquire a pin delay parameter of the chip substrate, wherein the pin delay parameter includes a pin length of each pin and a transmission delay of the target signal at the pin; The influencing factor is quantified according to the topological structure parameter to obtain the target parameter, including: A first transmission rate at which the target signal is transmitted on each pin is calculated according to the pin length and the transmission delay of the target signal on the pin.

4. The isochronous design method according to claim 2, characterized in that: The topology structure includes a routing level of the target signal, and the target signal is routed in at least two signal layers; Determine the topological structure parameters of each influencing factor, including: Determine the dielectric constant of a dielectric layer adjacent to the signal layer where the target signal is located; The influencing factor is quantified according to the topological structure parameter to obtain the target parameter, including: A second transmission rate of the target signal in the signal layer is determined according to the dielectric constant, the speed of light, and the magnetic permeability.

5. The isochronous design method according to claim 4, characterized in that: The design structures of the dielectric layers adjacent to the signal layer where the target signal is located are the same; The design structure at least includes dielectric material and dielectric thickness.

6. The isochronous design method according to any one of claims 2 to 5, characterized in that: The topological structure includes a wiring level of the target signal, and when the target signal is wired in at least two signal layers, the topological structure further includes a via hole, and the via hole is used to connect the two signal layers; Determine the topological structure parameters of each influencing factor, including: Determine the size of the via hole, wherein the size of the via hole includes the drilling size, the pad size, the anti-pad size and the dielectric thickness; The influencing factor is quantified according to the topological structure parameter to obtain the target parameter, including: Constructing a via simulation model according to the size of the via; A third transmission rate of the target signal at the via is determined according to the via simulation model.

7. The isochronous design method according to claim 6, characterized in that: Determining a third transmission rate of the target signal at the via according to the via simulation model includes: Simulating the via simulation model within a preset frequency range with a preset step size to obtain a scattering parameter model; Performing time domain simulation on the scattering parameter model to obtain a transmission delay of the target signal at the via hole; The third transmission rate is determined according to the transmission delay at the via and the size of the via.

8. The isochronous design method according to claim 6, characterized in that: Determining the size of the via includes: Determining the drilling size, the pad size, the anti-pad size, and at least two different dielectric thicknesses; A via simulation model is constructed according to the size of the via, including: Constructing at least two via simulation models according to the drilling hole size, the pad size, the anti-pad size and at least two different dielectric thicknesses; Determining a third transmission rate of the target signal at the via according to the via simulation model includes: Determine the sub-transmission delay of the target signal at the vias with different dielectric thicknesses according to each via simulation model; The third transmission rate is determined according to all the sub-transmission delays and the size of the via.

9. The isochronous design method according to claim 8, characterized in that: Determining the third transmission rate according to all the sub-transmission delays and the size of the via hole includes: Determine a corresponding third sub-transmission rate according to each of the sub-transmission delays and a corresponding via size; Calculating an average value of all the third sub-transmission rates to obtain an average transmission rate; The average transmission rate is used as the third transmission rate.

10. The isochronous design method according to claim 8, characterized in that: Determining the third transmission rate according to all the sub-transmission delays and the size of the via hole includes: Obtaining a delay difference between every two of the sub-transmission delays; Calculating the difference in dielectric thickness corresponding to each two of the sub-transmission delays; The third transmission rate is determined according to the delay difference and the medium thickness difference.

11. An isochronous design system, characterized in that: include: A structure determination unit, used for determining the topological structure of the target signal; an impact factor determination unit, configured to determine, according to the topology structure, at least one impact factor affecting the delay of the target signal in the transmission link of the target signal; A parameter quantization unit, used for quantizing each of the influencing factors into a target parameter, wherein the target parameter has a preset relationship with the time delay of the target signal; A design unit, configured to perform isochronous design on a transmission link of a target signal according to the determined isochronous requirement and all the target parameters; Wherein, the influencing factors include the size of the via, and quantifying each of the influencing factors into a target parameter includes: Determine the size of the via, construct a via simulation model based on the size of the via, and simulate the via simulation model within a preset frequency range and with a preset step size to determine a target transmission rate of the target signal at the via; wherein the preset frequency range is determined based on the operating frequency of the high-speed digital signal and the radio frequency signal; and the preset step size is determined based on simulation accuracy and computing resources.

12. An isochronous design device, characterized in that: include: Memory for storing computer programs; A processor, used to implement the steps of the isochronous design method as described in any one of claims 1 to 10 when executing a computer program.

13. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the isochronous design method according to any one of claims 1 to 10 are implemented.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the isochronous design method according to any one of claims 1 to 10 are implemented.

15. A memory architecture, characterized in that: The memory architecture is designed according to the isochronous design method as described in any one of claims 1-10.

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