Method, apparatus, device, storage medium and program product for determining SAS base address

Abstract

The embodiment of the present application provides a method, device, equipment, storage medium and program product for determining a SAS base address. The method includes: a method for determining a SAS base address, the method is applied to a hard disk storage expansion management chip, the method includes: obtaining a MAC address stored in a CPLD register and obtaining pin level information; the MAC address is the MAC address of the BMC chip; the pin level information represents the level high and low information of a designated pin on the hard disk storage expansion management chip; the designated pin is the pin used on the hard disk storage expansion management chip to connect to other hardware connected to the hard disk storage expansion management chip; based on the MAC address, pin level information and the chip identifier of the hard disk storage expansion management chip, the SAS base address of the hard disk storage expansion management chip is generated. The method is used to achieve the effect of saving the hardware cost of the hard disk storage expansion management chip.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, apparatus, device, storage medium, and program product for determining a SAS base address. Background Art

[0002] In a Just a Bunch of Disks (JBOD) system, multiple expander chips are deployed. These expander chips are independent of computers and servers, and the Serial Attached SCSI (SAS) base address of the expander chips is required.

[0003] In the prior art, for each hard disk storage expansion management chip, an electrically erasable programmable read only memory (EEPROM) is deployed in the hard disk storage expansion management chip, and the media access control (MAC) address of the hard disk storage expansion management chip is stored in the EEPROM; the MAC address is used to calculate the SAS base address of the hard disk storage expansion management chip.

[0004] However, in the above method, an EEPROM needs to be deployed in each hard disk storage expansion management chip, and the MAC address of the hard disk storage expansion management chip stored in the EEPROM increases the hardware cost. Summary of the Invention

[0005] The embodiments of the present application provide a method, apparatus, device, storage medium, and program product for determining a SAS base address, so as to achieve the effect of saving the hardware cost of a hard disk storage expansion management chip.

[0006] In a first aspect, an embodiment of the present application provides a method for determining a SAS base address, the method being applied to a hard disk storage expansion management chip, the method comprising:

[0007] Obtaining a media access control (MAC) address stored in a register of a complex programmable logic device (CPLD) and obtaining pin level information; wherein the MAC address is the MAC address of an embedded management controller (BMC) chip; the pin level information represents the level information of a designated pin on a hard disk storage expansion management chip; the designated pin is a pin used on the hard disk storage expansion management chip to connect to other hardware connected to the hard disk storage expansion management chip;

[0008] A serial attached SCSI interface SAS base address of the hard disk storage expansion management chip is generated according to the MAC address, the pin level information and the chip identifier of the hard disk storage expansion management chip.

[0009] In a possible implementation, generating a SAS base address of the hard disk storage expansion management chip according to the MAC address, the pin level information, and the chip identifier of the hard disk storage expansion management chip includes:

[0010] The SAS base address of the hard disk storage expansion management chip is composed according to the chip identifier of the hard disk storage expansion management chip, the MAC address, the pin level information, and the preset reserved bit.

[0011] In a possible implementation manner, the chip identifier of the hard disk storage expansion management chip in the SAS base address of the hard disk storage expansion management chip occupies 0.5 bytes;

[0012] The MAC address in the SAS base address of the hard disk storage expansion management chip occupies 6 bytes;

[0013] The SAS base address of the hard disk storage expansion management chip and the pin level information occupy 0.5 bytes;

[0014] The preset reserved bit in the SAS base address of the hard disk storage expansion management chip occupies 1 byte.

[0015] In a possible implementation manner, the MAC address stored in the CPLD register is sent by the BMC chip to the CPLD register after the BMC chip is started.

[0016] In a possible implementation, the hard disk storage expansion management chip communicates with the CPLD register via a two-wire serial bus IIC channel corresponding one-to-one to the hard disk storage expansion management chip;

[0017] The pin level information is generated after the CPLD register controls the high and low levels of the designated pins on the hard disk storage expansion management chip.

[0018] In one possible implementation, the method further includes:

[0019] The SAS base address of the hard disk storage expansion management chip is sent to the BMC chip.

[0020] In a possible implementation, the pin level information obtained by the CPLD register is also used to be transmitted to the BMC chip; the BMC chip is used to generate a SAS base address of the hard disk storage expansion management chip based on the MAC address, the pin level information and the pre-stored chip identifier of the hard disk storage expansion management chip.

[0021] In a second aspect, an embodiment of the present application provides a device for determining a SAS base address, the device being applied to a hard disk storage expansion management chip, the device comprising:

[0022] A first acquisition module is used to acquire a media access control MAC address stored in a register of a complex programmable logic device (CPLD); wherein the MAC address is a MAC address of an embedded management controller (BMC) chip;

[0023] A second acquisition module is configured to acquire pin level information, wherein the pin level information represents the level of a designated pin on the hard disk storage expansion management chip; the designated pin is a pin used by the hard disk storage expansion management chip to connect to other hardware connected to the hard disk storage expansion management chip;

[0024] A generating module is used to generate a serial attached SCSI interface SAS base address of the hard disk storage expansion management chip according to the MAC address, the pin level information and the chip identifier of the hard disk storage expansion management chip.

[0025] In a possible implementation, the generating module is specifically configured to:

[0026] The SAS base address of the hard disk storage expansion management chip is composed according to the chip identifier of the hard disk storage expansion management chip, the MAC address, the pin level information, and the preset reserved bit.

[0027] In a possible implementation manner, the chip identifier of the hard disk storage expansion management chip in the SAS base address of the hard disk storage expansion management chip occupies 0.5 bytes;

[0028] The MAC address in the SAS base address of the hard disk storage expansion management chip occupies 6 bytes;

[0029] The SAS base address of the hard disk storage expansion management chip and the pin level information occupy 0.5 bytes;

[0030] The preset reserved bit in the SAS base address of the hard disk storage expansion management chip occupies 1 byte.

[0031] In a possible implementation manner, the MAC address stored in the CPLD register is sent by the BMC chip to the CPLD register after the BMC chip is started.

[0032] In a possible implementation, the hard disk storage expansion management chip communicates with the CPLD register via a two-wire serial bus IIC channel corresponding one-to-one to the hard disk storage expansion management chip;

[0033] The pin level information is generated after the CPLD register controls the high and low levels of the designated pins on the hard disk storage expansion management chip.

[0034] In a possible implementation, the device further includes:

[0035] The sending module is used to send the SAS base address of the hard disk storage expansion management chip to the BMC chip.

[0036] In a possible implementation, the pin level information obtained by the CPLD register is also used to be transmitted to the BMC chip; the BMC chip is used to generate a SAS base address of the hard disk storage expansion management chip based on the MAC address, the pin level information and the pre-stored chip identifier of the hard disk storage expansion management chip.

[0037] In a third aspect, an embodiment of the present application provides a hard disk storage expansion management chip, comprising: a memory, a processor;

[0038] The memory stores computer-executable instructions;

[0039] The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method provided in the first aspect and any embodiment of the first aspect.

[0040] In a fourth aspect, an embodiment of the present application provides a JBOD system, comprising: a hard disk storage expansion management chip as provided in the third aspect; and further comprising: a complex programmable logic device (CPLD) register and an embedded management controller (BMC) chip;

[0041] The hard disk storage expansion management chip is connected to the CPLD register and the BMC chip respectively.

[0042] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method provided in the first aspect and any embodiment of the first aspect.

[0043] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the method provided in the first aspect and any implementation method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0045] Figure 1 Schematic diagram of the process of determining the SAS base address provided in the embodiment of the present application Figure 1 ;

[0046] Figure 2 Schematic diagram of the process of determining the SAS base address provided in the embodiment of the present application Figure 2 ;

[0047] Figure 3 A schematic diagram of the structure of a JBOD system provided in an embodiment of the present application;

[0048] Figure 4 Schematic diagram of the structure of the SAS base address determination device provided in the embodiment of the present application Figure 1 ;

[0049] Figure 5 Schematic diagram of the structure of the SAS base address determination device provided in the embodiment of the present application Figure 2 ;

[0050] Figure 6 A schematic diagram of the structure of the hard disk storage expansion management chip provided in an embodiment of the present application.

[0051] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0052] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0053] The JBOD system architecture deploys multiple expander chips. These chips function as independent intelligent units, operating independently of any external computer or server system. To ensure efficient and orderly communication between the chips, the SAS (Serial Attached SCSI) base address of each expander chip must be precisely located. This serves as the gateway to the high-speed data transmission network.

[0054] In current technology, to address this need, each hard drive storage expansion management chip has a built-in EEPROM. This innovative design cleverly utilizes the non-volatile storage properties of EEPROM to securely store each chip's MAC address. As the chip's unique identifier, the MAC address not only ensures network communication security but also, through a specific algorithm, converts it into a SAS base address, enabling seamless and accurate data exchange between chips.

[0055] However, while this solution is highly effective, it comes at a cost. Specifically, equipping each hard drive's storage expansion management chip with a separate EEPROM undoubtedly increases hardware complexity and costs. As the storage system scales, this cumulative cost effect becomes increasingly significant, becoming a significant factor affecting the overall economic viability of the system.

[0056] Therefore, the SAS base address determination method, apparatus, device, storage medium, and program product provided in this application can solve the above-mentioned problem.

[0057] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0058] Figure 1 Schematic diagram of the process of determining the SAS base address provided in the embodiment of the present application Figure 1 ,like Figure 1 As shown, the method is applied to a hard disk storage expansion management chip; the method includes:

[0059] 101. Obtain a MAC address stored in a CPLD register, where the MAC address is the MAC address of the BMC chip.

[0060] For example, in the JBOD system architecture, multiple hard disk storage expansion management chips are deployed; in addition, complex programmable logic device (CPLD) registers and embedded management controller (BMC) chips are deployed in the JBOD system architecture. The hard disk storage expansion management chip is also connected to other hardware, such as hard disks, input and output (IO) interfaces, etc.; the hard disk storage expansion management chip is used to manage hardware such as hard disks and IO interfaces. In addition, the above-mentioned other hardware can also be connected to the CPLD registers.

[0061] The CPLD register stores a MAC address, which is the MAC address of the BMC chip. Furthermore, the CPLD register can send the stored MAC address of the BMC chip to the hard disk storage expansion management chip.

[0062] 102. Obtain pin level information; wherein the pin level information represents the level information of a designated pin on the hard disk storage expansion management chip; the designated pin is a pin used on the hard disk storage expansion management chip to connect to other hardware connected to the hard disk storage expansion management chip.

[0063] For example, when the hard disk storage expansion management chip is connected to other hardware, it is connected to the other hardware through the designated pins of the hard disk storage expansion management chip. For example, the hard disk storage expansion management chip is connected to the hard disk through the pins on the hard disk storage expansion management chip. For another example, the hard disk storage expansion management chip is connected to the IO interface through the pins on the hard disk storage expansion management chip. As a result, the designated pins on which the hard disk storage expansion management chip is connected to other hardware will have high and low level signals, that is, level information; the level information is a high level signal or a low level signal. The CPLD register can control the level information on the above-mentioned designated pins, and then the hard disk storage expansion management chip can know its own pin signal, and the CPLD register can also know the pin signal of each hard disk storage expansion management chip.

[0064] The value of the pin level information can be called a Board ID.

[0065] The above-mentioned designated pins on the hardware storage expansion management chip are general purpose input and output (GPIO).

[0066] Each GPIO has two states, namely, high and low level information. By combining multiple GPIOs, multiple states can be expressed. For example, if there are N GPIOs, there are 2N states. After the Expander is installed in the system, the corresponding GPIO will be set to a unique state on each Expander. For example, there are 3 Expanders, one of which is used as an input / output (IO) board, and the other two are used as backplanes (BP). As shown in Table 1, Table 1 is the pin level information received by the hard disk storage expansion management chip. As shown in Table 1, for Expander0 used as an IO board, the pin level information received includes the information that the value of pin GPIO65 is 0 and the value of pin GPIO66 is 0; that is, the pin level information of Expander0 is 00 (that is, the Board ID of Expander0 is 00). For Expander1, which functions as a BP board, the received pin level information includes information that pin GPIO65 is set to 0 and pin GPIO66 is set to 1; that is, Expander1's pin level information is 01 (i.e., Expander1's Board ID is 01). For Expander2, which functions as a BP board, the received pin level information includes information that pin GPIO65 is set to 1 and pin GPIO66 is set to 0; that is, Expander2's pin level information is 10 (i.e., Expander2's Board ID is 10).

[0067] Table 1 Pin level information received by the hard disk storage expansion management chip

[0068] GPIO65 GPIO66 Board ID Expander 0 0 0 00 Expander 1 0 1 01 Expander 2 1 0 10

[0069] 103. Generate a SAS base address of the hard disk storage expansion management chip according to the MAC address, pin level information, and the chip identifier of the hard disk storage expansion management chip.

[0070] Exemplarily, a chip identifier is pre-stored in the hard disk storage expansion management chip. The chip identifier is a unique identifier of the hard disk storage expansion management chip. The hard disk storage expansion management chip generates a SAS base address of the hard disk storage expansion management chip based on the MAC address and pin level information of the BMC chip and the chip identifier of the hard disk storage expansion management chip.

[0071] The embodiment of the present application provides a method, wherein the hard disk storage expansion management chip receives the MAC address and pin level information of the BMC chip sent by the CPLD register; wherein the pin level information represents the level high and low information of the designated pin on the hard disk storage expansion management chip; the level high and low information of the designated pin is controlled by the CPLD register; then, the hard disk storage expansion management chip generates a SAS base address based on the MAC address, pin level information of the above-mentioned BMC chip, and the chip identifier of the hard disk storage expansion management chip. Thus, the SAS base address can be generated by the above-mentioned software method, and there is no need to deploy an EEPROM in the hard disk storage expansion management chip to store the MAC address of the hard disk storage expansion management chip used to generate the SAS base address, that is, the EEPROM is removed; thereby saving hardware costs. Moreover, since the EEPROM used to store the "MAC address of the hard disk storage expansion management chip used to generate the SAS base address" in each hard disk storage expansion management chip is removed, only one BMC chip is required to store the MAC address of the BMC chip, thereby simplifying the production process, reducing costs, and improving efficiency. Furthermore, based on the solution provided in this embodiment, the hard disk storage expansion management chip can generate a SAS base address, that is, it is ensured that the SAS base address of the hard disk storage expansion management chip can be generated, maintaining functional integrity.

[0072] Figure 2 Schematic diagram of the process of determining the SAS base address provided in the embodiment of the present application Figure 2 ,like Figure 2 As shown, the method is applied to a hard disk storage expansion management chip; the method includes:

[0073] 201. Obtain a MAC address stored in a CPLD register, where the MAC address is the MAC address of the BMC chip.

[0074] In one example, the MAC address stored in the CPLD register is sent by the BMC chip to the CPLD register after the BMC chip is started.

[0075] In one example, the hard disk storage expansion management chip communicates with the CPLD registers through a two-wire serial bus (Inter-Integrated Circuit, IIC) channel that corresponds one-to-one with the hard disk storage expansion management chip. The hard disk storage expansion management chip communicates with the BMC chip through an IIC channel that corresponds one-to-one with the hard disk storage expansion management chip.

[0076] For example, in the architecture of the JBOD system, multiple hard disk storage expansion management chips are deployed; and CPLD registers and BMC chips are deployed in the architecture of the JBOD system, wherein a corresponding independent communication link is established between the hard disk storage expansion management chip and the CPLD register. This communication link is realized through a two-wire serial bus (Inter-Integrated Circuit, IIC) channel, and this IIC channel is specially designed for a one-to-one correspondence between each hard disk storage expansion management chip and the CPLD register, ensuring the independence and accuracy of the communication. The hard disk storage expansion management chip is also linked to other hardware, for example, other hardware is a hard disk, IO interface, etc.; the hard disk storage expansion management chip is used to manage hardware such as hard disks and IO interfaces. In addition, the above-mentioned other hardware can also be connected to the CPLD register.

[0077] When the JBOD system starts, the BMC chip starts first, followed by the hard disk storage expansion management chip. After the BMC starts, it sends its MAC address to the CPLD register via the IIC channel. The CPLD register stores the received BMC chip's MAC address.

[0078] Therefore, the CPLD register sends the stored MAC address of the BMC chip to each hard disk storage expansion management chip through an independent IIC channel.

[0079] Thus, through the above process, the hard disk storage expansion management chip can obtain the MAC address of the BMC chip, and then use it to generate the SAS base address.

[0080] 202. Obtain pin level information. The pin level information is generated after the CPLD register controls the high and low levels of designated pins on the hard disk storage expansion management chip.

[0081] The pin level information represents the level information of a designated pin on the hard disk storage expansion management chip; the designated pin is a pin used on the hard disk storage expansion management chip to connect to other hardware connected to the hard disk storage expansion management chip.

[0082] For example, for each hard disk storage expansion management chip, using CPLD registers, the level state of the designated pins of the connected hard disk storage expansion management chip can be precisely controlled, that is, whether these pins are at a high or low level. This control process is achieved by directly pulling up or down the level signal of the designated pins of the hard disk storage expansion management chip through the CPLD register. Because the CPLD register is directly involved in the level adjustment process, it not only knows and determines the level state of the expansion chip pins, but also has a clear understanding of the current level signal status of these pins. These pin level signals exist in binary form, representing "0" and "1" in digital logic.

[0083] 203. A SAS base address of the hard disk storage expansion management chip is formed according to the chip identifier, MAC address, pin level information, and preset reserved bits of the hard disk storage expansion management chip.

[0084] In one example, the chip identifier of the hard disk storage expansion management chip in the SAS base address of the hard disk storage expansion management chip occupies 0.5 bytes.

[0085] The MAC address in the SAS base address of the hard disk storage expansion management chip occupies 6 bytes.

[0086] The SAS base address and pin level information of the hard disk storage expansion management chip occupy 0.5 bytes.

[0087] The reserved bit preset in the SAS base address of the hard disk storage expansion management chip occupies 1 byte.

[0088] For example, the chip ID of a hard drive storage expansion management chip refers to the chip's unique identifier or model code. This ID is used to distinguish different chip types and ensure accurate identification of the target chip during configuration or programming. When constructing the SAS base address, the chip ID serves as a foundational piece of information, helping the system or software correctly identify and manage the chip.

[0089] In one example, the composition structure of the SAS base address of the hard disk storage expansion management chip includes the chip identifier, MAC address, pin level information and preset reserved bit of the hard disk storage expansion management chip. In the SAS base address, 0.5 bytes of space are allocated for the chip identifier of the hard disk storage expansion management chip. This 0.5 bytes is used to uniquely identify the management chip to ensure identifiability in the SAS network. The chip identifier of the hard disk storage expansion management chip is 5. 6 bytes of space are allocated for the MAC address. The MAC address is globally unique and is used to identify the physical address of the device in the network. These 6 bytes ensure the integrity and uniqueness of the MAC address. 0.5 bytes of space are allocated for the pin level information. This 0.5 bytes is used to indicate the high and low level status of a specific pin on the hard disk storage expansion management chip, which is related to the connection or configuration of other hardware. 1 byte of space is allocated for the preset reserved bit. This 1-byte reserved bit can be used to mark the extension bit of the hard disk on the hard disk storage expansion management chip. The preset reserved bit is 7f.

[0090] by Figure 3 For example, the JBOD system deploys three hard disk storage expansion management chips (Expanders), namely Expander0, Expander1, and Expander2. Among them, Expander0 serves as an Expander connected to the IO interface, Expander1 serves as an Expander connected to the BP board, and Expander2 serves as an Expander connected to the BP board. The JBOD system deploys CPLD registers and BMC chips. Each Expander is connected to the BMC chip through the IIC channel corresponding to the Expander; and each Expander is connected to the CPLD register through the IIC channel corresponding to the Expander. The above three Expanders can provide services for 118 hard disks. The EEPROM in the JBOD system is used to store the MAC address of the BMC chip, wherein the EEPROM is connected to the BMC chip through the IIC channel. Specifically, Expander0 is responsible for connecting to the host bus adapter (HBA) as the IO board, Expander1 is responsible for connecting to the IO board and BP-1 board, and Expander2 is responsible for connecting to the IO board and BP-2 board. The BP-1 board is configured to connect to 60 hard disks, and the BP-2 board is configured to connect to 58 hard disks.

[0091] The BMC chip uses the IIC channel to write its built-in MAC address (for example, aabbccddeeff) into the CPLD register. Each expander obtains the BMC chip's MAC address from the CPLD register through an independent IIC channel. Each expander obtains the board ID from the CPLD register. Specifically, the pin level information for Expander0 is 00, which converts to hexadecimal as 0; the pin level information for Expander1 is 01, which converts to hexadecimal as 1; and the pin level information for Expander2 is 10, which converts to hexadecimal as 2. The expander's chip identifier, MAC address, pin level information, and preset reserved bits are combined to form the expander's SAS base address. Table 2 shows the expander's SAS base address. Specifically, the SAS base address for Expander0 is 0x5aabbccddeeff07f; the SAS base address for Expander1 is 0x5aabbccddeeff17f; and the SAS base address for Expander2 is 0x5aabbccddeeff27f.

[0092] Table 2 Expander SAS base address

[0093] Expander Expander SAS base address Expander 0 0x5aabbccddeeff07f Expander 1 0x5aabbccddeeff17f Expander 2 0x5aabbccddeeff27f

[0094] 204. Send the SAS base address of the hard disk storage expansion management chip to the BMC chip.

[0095] Exemplarily, the hard disk storage expansion management chip may further send the SAS base address to the BMC chip; furthermore, the BMC chip may store the SAS base address of the hard disk storage expansion management chip.

[0096] In one example, the pin level information obtained by the CPLD register is also used to transmit to the BMC chip; the BMC chip is used to generate the SAS base address of the hard disk storage expansion management chip according to the MAC address, the pin level information and the chip identifier of the pre-stored hard disk storage expansion management chip.

[0097] For example, using the IIC communication protocol, the BMC chip can access and obtain the pin information about the hard disk storage expansion management chip stored in the CPLD register. After receiving the pin level information from the hard disk storage expansion management chip, the BMC chip uses this information, combined with a pre-stored MAC address and the hard disk storage expansion management chip's chip identifier, to generate the hard disk storage expansion management chip's SAS base address. In this case, the hard disk storage expansion management chip does not need to generate the SAS base address.

[0098] The embodiment of the present application provides a method, which uses the MAC address of the BMC chip and the pin level information of the hard disk storage expansion management chip sent by the receiving CPLD register; then, the BMC chip generates a SAS base address based on the above-mentioned MAC address, the pin level information and chip identification of the hard disk storage expansion management chip, and the preset reserved bit. Thus, the SAS base address can be generated by the above-mentioned software method, and the hard disk storage expansion management chip does not need to be used to generate the SAS base address. That is, the BMC chip can directly generate the SAS base address of the hard disk storage expansion management chip and manage it, thereby facilitating the management and maintenance of the SAS base address by R&D and operation and maintenance. Because the MAC of the BMC chip is unique, the SAS base address of the generated hard disk storage expansion management chip is also unique, which effectively avoids the occurrence of the phenomenon that the hard disk storage expansion management chip and the hard disk cannot be identified due to SAS base address conflicts.

[0099] Figure 4 Schematic diagram of the structure of the SAS base address determination device provided in the embodiment of the present application Figure 1 ,like Figure 4 As shown, the device is applied to a hard disk storage expansion management chip. The SAS base address determination device 40 provided in this embodiment includes:

[0100] The first acquisition module 41 is configured to acquire a MAC address stored in a CPLD register; wherein the MAC address is the MAC address of the BMC chip.

[0101] The second acquisition module 42 is used to obtain pin level information; wherein the pin level information represents the level information of the designated pin on the hard disk storage expansion management chip; the designated pin is the pin used on the hard disk storage expansion management chip to connect with other hardware connected to the hard disk storage expansion management chip.

[0102] The generating module 43 is used to generate a serial attached SCSI interface SAS base address of the hard disk storage expansion management chip according to the MAC address, pin level information and the chip identifier of the hard disk storage expansion management chip.

[0103] The device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0104] Figure 5 Schematic diagram of the structure of the SAS base address determination device provided in the embodiment of the present application Figure 2 ,like Figure 5 As shown, the device is applied to a hard disk storage expansion management chip. The SAS base address determination device 50 provided in this embodiment includes:

[0105] The first acquisition module 51 is configured to acquire a MAC address stored in a CPLD register; wherein the MAC address is the MAC address of the BMC chip.

[0106] The second acquisition module 52 is configured to acquire pin level information. The pin level information represents the level of a designated pin on the hard disk storage expansion management chip. The designated pin is a pin on the hard disk storage expansion management chip that is connected to other hardware connected to the hard disk storage expansion management chip. The pin level information is generated by the CPLD register controlling the high and low levels of the designated pin on the hard disk storage expansion management chip.

[0107] The generating module 53 is used to generate a serial attached SCSI interface SAS base address of the hard disk storage expansion management chip according to the MAC address, the pin level information and the chip identifier of the hard disk storage expansion management chip.

[0108] In one example, the generating module 53 is specifically configured to:

[0109] The SAS base address of the hard disk storage expansion management chip is composed according to the chip identification, MAC address, pin level information, and preset reserved bits of the hard disk storage expansion management chip.

[0110] In an example, the chip identifier of the hard disk storage expansion management chip in the SAS base address of the hard disk storage expansion management chip occupies 0.5 bytes; the MAC address in the SAS base address of the hard disk storage expansion management chip occupies 6 bytes; the pin level information in the SAS base address of the hard disk storage expansion management chip occupies 0.5 bytes; the preset reserved bit in the SAS base address of the hard disk storage expansion management chip occupies 1 byte.

[0111] In one example, the MAC address stored in the CPLD register is sent by the BMC chip to the CPLD register after the BMC chip is started.

[0112] In one example, the hard disk storage expansion management chip communicates with the CPLD register through a two-wire serial bus IIC channel that corresponds one-to-one with the hard disk storage expansion management chip.

[0113] In one example, the apparatus provided in the embodiment of the present application further includes:

[0114] The sending module 54 is used to send the SAS base address of the hard disk storage expansion management chip to the BMC chip.

[0115] In one example, the pin level information obtained by the CPLD register is also used to transmit to the BMC chip; the BMC chip is used to generate the SAS base address of the hard disk storage expansion management chip according to the MAC address, the pin level information and the chip identifier of the pre-stored hard disk storage expansion management chip.

[0116] The device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail in this embodiment.

[0117] Figure 6 This is a schematic diagram of the structure of the hard disk storage expansion management chip provided in the embodiment of this application. Figure 6 As shown, the hard disk storage expansion management chip 60 provided in this embodiment includes: at least one processor 601 and a memory 602. Optionally, the device 60 also includes a communication component 603. The processor 601, the memory 602, and the communication component 603 are connected via a bus 604.

[0118] During the specific implementation process, at least one processor 601 executes the computer-executable instructions stored in the memory 602, so that the at least one processor 601 performs the above method.

[0119] The specific implementation process of the processor 601 can be found in the above method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0120] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the present invention may be directly implemented by a hardware processor or implemented by a combination of hardware and software modules in the processor.

[0121] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk memory.

[0122] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be classified into address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0123] An embodiment of the present application also provides a JBOD system, which includes: the hard disk storage expansion management chip provided in the above embodiment; and the system also includes: a CPLD register and a BMC chip; the hard disk storage expansion management chip is connected to the CPLD register and the BMC chip respectively.

[0124] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0125] An embodiment of the present application further provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above-mentioned method is implemented.

[0126] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0127] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0128] The division of units is merely a logical functional division; actual implementations may employ alternative divisions, such as combining or integrating multiple units or components into another system, or omitting or disabling certain features. Furthermore, any direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units, either through an interface, electrical, mechanical, or other means.

[0129] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0130] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0131] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program code.

[0132] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0133] Finally, it should be noted that those skilled in the art will readily identify other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The present invention is not limited to the precise structure described above and illustrated in the accompanying drawings, and various modifications and variations may be made without departing from the scope thereof. The scope of the present invention is limited solely by the appended claims.

Claims

1. A method for determining a SAS base address, characterized in that: The method is applied to a hard disk storage expansion management chip, and the method includes: Obtaining a media access control (MAC) address stored in a register of a complex programmable logic device (CPLD) and obtaining pin level information; wherein the MAC address is the MAC address of an embedded management controller (BMC) chip; the pin level information represents the level information of a designated pin on a hard disk storage expansion management chip; the designated pin is a pin used on the hard disk storage expansion management chip to connect to other hardware connected to the hard disk storage expansion management chip; A serial attached SCSI interface SAS base address of the hard disk storage expansion management chip is generated according to the MAC address, the pin level information and the chip identifier of the hard disk storage expansion management chip.

2. The method according to claim 1, characterized in that Generating a SAS base address of the hard disk storage expansion management chip according to the MAC address, the pin level information, and the chip identifier of the hard disk storage expansion management chip includes: The SAS base address of the hard disk storage expansion management chip is composed according to the chip identifier of the hard disk storage expansion management chip, the MAC address, the pin level information, and the preset reserved bit.

3. The method according to claim 2, characterized in that The chip identifier of the hard disk storage expansion management chip in the SAS base address of the hard disk storage expansion management chip occupies 0.5 bytes; The MAC address in the SAS base address of the hard disk storage expansion management chip occupies 6 bytes; The SAS base address of the hard disk storage expansion management chip and the pin level information occupy 0.5 bytes; The preset reserved bit in the SAS base address of the hard disk storage expansion management chip occupies 1 byte.

4. The method according to claim 1, wherein The MAC address stored in the CPLD register is sent by the BMC chip to the CPLD register after the BMC chip is started.

5. The method according to claim 1, wherein The hard disk storage expansion management chip communicates with the CPLD register via a two-wire serial bus IIC channel corresponding to the hard disk storage expansion management chip; The pin level information is generated after the CPLD register controls the high and low levels of the designated pins on the hard disk storage expansion management chip.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: The SAS base address of the hard disk storage expansion management chip is sent to the BMC chip.

7. The method according to claim 5, characterized in that The pin level information obtained by the CPLD register is also used to be transmitted to the BMC chip; the BMC chip is used to generate the SAS base address of the hard disk storage expansion management chip according to the MAC address, the pin level information and the pre-stored chip identifier of the hard disk storage expansion management chip.

8. A device for determining a SAS base address, characterized in that: The device is applied to a hard disk storage expansion management chip, and the device includes: A first acquisition module is used to acquire a media access control MAC address stored in a register of a complex programmable logic device (CPLD); wherein the MAC address is a MAC address of an embedded management controller (BMC) chip; A second acquisition module is configured to acquire pin level information, wherein the pin level information represents the level of a designated pin on the hard disk storage expansion management chip; the designated pin is a pin used by the hard disk storage expansion management chip to connect to other hardware connected to the hard disk storage expansion management chip; A generating module is used to generate a serial attached SCSI interface SAS base address of the hard disk storage expansion management chip according to the MAC address, the pin level information and the chip identifier of the hard disk storage expansion management chip.

9. A hard disk storage expansion management chip, characterized in that: include: Memory, processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 7.

10. A JBOD system, characterized in that: The system comprises: the hard disk storage expansion management chip according to claim 9; and the system further comprises: a complex programmable logic device (CPLD) register and an embedded management controller (BMC) chip; The hard disk storage expansion management chip is connected to the CPLD register and the BMC chip respectively.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.

12. A computer program product, characterized in that The computer program product comprises a computer program, which implements the method according to any one of claims 1 to 7 when executed by a processor.

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