Method for Determining Thermal Stability Limit Line of SOA of Power MOSFET Device

Abstract

The present application provides a method for determining the SOA thermal stability limit line of a power MOSFET device, comprising the following steps: using a semiconductor thermal analysis device to perform junction calibration, junction-case steady-state thermal resistance R th(jc) Measurement and heating characterization measurement, obtain transient thermal response data of DUT through thermal simulation; draw DUT shell temperature T through calculation c Ideal SOA curve at 25°C; measured DUT case temperature T c The thermal instability limit line at 25°C; the thermal instability limit line is moved downward by 30% to 40% to obtain the thermal stability limit line of the DUT; irrelevant points and lines on the SOA are trimmed to obtain a complete SOA curve containing the thermal stability limit line. This application calibrates each maximum power limit line in the SOA based on experimental data and provides more safety margins. The SOA curve of the power MOSFET device containing the thermal stability limit line thus determined reflects the actual power handling capability of the device, improves the reliability of the device, and reduces the user's use risk.

Description

Technical Field

[0001] The present application relates to the field of power semiconductor technology, and in particular to a method for determining a SOA thermal stability limit line of a power MOSFET device. Background Art

[0002] The statements in this section merely provide background technical information related to the present application and do not necessarily constitute prior art.

[0003] Metal oxide semiconductor field effect transistor (MOSFET) was first introduced in the 1970s and is widely used in DC-DC conversion circuits and high-speed switching circuits of various spacecraft and ground support equipment. With the rapid development of my country's aerospace industry, the demand for high-reliability and high-performance power MOSFET devices is increasing.

[0004] In pursuit of higher switching speeds and lower on-resistance, newly designed power MOSFETs from 1998 to the present have achieved most of these goals. Unfortunately, with good comes bad, namely thermal instability under forward bias. Newly designed power MOSFETs allow areas dominated by carrier concentration to become important and enter the safe operating area (SOA). As temperature rises, areas on the chip dominated by carrier concentration allow more current to flow. Higher temperatures generate more current, leading to the beginning of thermal runaway. Although the problem may start with the entire device, as thermal runaway develops, hot spots begin to form and then become smaller in size. As smaller areas are subjected to more power, the temperature of the hot spots rises higher and faster. Smaller hot spots generate higher temperatures, and temperatures above 450°C anywhere on the chip will cause metal migration, resulting in a fatal short circuit.

[0005] At present, the SOA curves disclosed by high-reliability power MOSFET device manufacturers are Figure 1 Generally, the shell temperature (T c ) is kept at 25℃ and calculated with transient thermal resistance and plotted on the log-log coordinate plane. There is a lack of description of thermal (in)stability, and the SOA given is greater than the actual processing capability of the device. When users use the device at a reduced rating, the margin left is lower than expected, which is prone to failure. In order to overcome the shortcomings of the existing technology, it is urgent to determine the SOA thermal stability limit line of power MOSFET devices, improve product reliability, and reduce user risks. Summary of the invention

[0006] In order to solve the problem in the background technology, the present application proposes a method for determining a SOA thermal stability limit line of a power MOSFET device.

[0007] The method for determining the SOA thermal stability limit line of the power MOSFET device proposed in this application includes the following steps:

[0008] In the first step, use a semiconductor thermal analysis device to perform junction calibration on the device under test (DUT), measure the junction-to-case steady-state thermal resistance R th(jc) and perform heating characterization measurement, and obtain the transient thermal response data of the DUT through thermal simulation;

[0009] In the second step, draw the ideal SOA curve graph of the DUT case temperature T c at 25°C, which is enveloped by the on-resistance limit line, maximum current limit line, maximum power limit line, and breakdown voltage limit line;

[0010] In the third step, measure the thermal instability limit line of the DUT case temperature T c at 25°C;

[0011] In the fourth step, move the above thermal instability limit line downward parallel by 30% - 40% to obtain the thermal stability limit line of the DUT;

[0012] In the fifth step, trim the irrelevant points and lines on the SOA to obtain a complete SOA curve graph containing the thermal stability limit line.

[0013] Preferably, in the first step, use a semiconductor thermal analysis device to perform junction calibration on the DUT in an oil bath and perform junction-to-case steady-state thermal resistance R th(jc) measurement and heating characterization measurement on a special liquid-cooled temperature control fixture.

[0014] Preferably, in the second step, the maximum current limit line and the maximum power limit line are divided into a DC part and a pulse part.

[0015] Preferably, in the third step, the measurement method of the thermal instability limit line includes:

[0016] (1) Install the DUT into the thermal runaway test circuit and adjust T c to 25°C, measure the electrical parameters of the DUT with an electrical parameter test system and formulate the failure criterion of the DUT accordingly;

[0017] (2) Control the turn-on and turn-off of the DUT with the pulse shown in the ideal SOA curve graph, monitor the drain-source voltage V ds and the drain current I d ;

[0018] Adjust the gate-source voltage V gs and the drain-source voltage V ds , so that the coordinate points (V ds(t) , I d(t)) are within the coordinate ranges of each maximum power limit line. After each test pulse, the electrical parameters of the DUT are measured by an electrical parameter test system and compared with the failure criteria. The test pulse coordinate points at which the DUT fails or meets the failure criteria are recorded as thermal instability failure points (V ds(i) , I d(i) ), where i is a natural number satisfying 1 < i < n, and n is the number of thermal instability failure points;

[0019] (3) Plot all the measured thermal instability failure points (V ds(i) , I d(i) ) in the ideal SOA curve graph. Through all the thermal instability failure points (V ds(i) , I d(i) ) corresponding to each pulse, draw the best-fit line, and the corresponding line is the thermal instability limit line of each pulse.

[0020] Preferably, in step (2), the thermal instability failure points of the DC current of the device are measured directly using a pulse current with a pulse width of 1000 ms.

[0021] Preferably, in step (2), when measuring the failure points, V ds(t) first gradually decreases from the drain-source breakdown voltage V (br)dss to the minimum voltage of the maximum power limit line to the left, keeping the pulse width of the test pulse current I d(t) unchanged, and approaching the maximum power limit line step by step in the amplitude of I d(t) until the DUT fails, and record the failure point.

[0022] Preferably, according to the drain-source voltage span of each maximum power limit line, select the number of thermal instability failure points to be measured, generally 2 ≤ n ≤ 7.

[0023] Preferably, in step (3), the best-fit line should at least pass through the lowest thermal instability failure point, its high-current direction intersects with the maximum power limit line or the maximum current limit line, and its low-current direction intersects with the breakdown voltage limit line.

[0024] Compared with the prior art, the beneficial effects of this application are:

[0025] (1) This application calibrates each maximum power limit line in the SOA based on experimental data and provides more safety margins. The SOA curve graph of the power MOSFET device containing the thermal stability limit line determined thereby reflects the true power handling ability of the device, improves the reliability of the device, and reduces the user's usage risk.

[0026] (2) In this application, the reference point temperatures for different pulse widths and DC currents are uniformly set to 25°C and efficient heat dissipation is configured, making the method for determining the thermal stability limit line of the power MOSFET device simple and easy to implement and with more safety margins. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings forming a part of this application are used to provide a further understanding of this application. The schematic embodiments and descriptions thereof of this application are used to explain this application and do not constitute an improper limitation to this application.

[0028] Figure 1 Schematic diagram of the process for determining the thermal stability limit line of the power MOSFET device in the embodiment of this application,

[0029] Figure 2 Schematic diagram of the transient thermal response curve of the power MOSFET device in the embodiment of this application,

[0030] Figure 3 Schematic diagram of the ideal SOA curve of the power MOSFET device in the embodiment of this application,

[0031] Figure 4 Schematic diagram of the principle of thermal runaway test of the power MOSFET device in the embodiment of this application,

[0032] Figure 5 Schematic diagram of the thermal instability failure point and the best-fit straight line of the power MOSFET device in the embodiment of this application,

[0033] Figure 6 Schematic diagram of the transfer characteristic curve of the power MOSFET device in the embodiment of this application,

[0034] Figure 7 Schematic diagram of the SOA curve of the power MOSFET device in the embodiment of this application containing the thermal stability limit line.

[0035] In the figure: The illustrated sample is the G-grade TO-257 metal package P-channel power MOSFET device LYPM4905. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The following further describes this application in conjunction with the accompanying drawings and embodiments.

[0037] It should be noted that the terms used herein are only for describing the specific embodiments and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or their combinations.

[0038] In the present disclosure, terms such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "side", "bottom", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only relational terms determined for the convenience of describing the structural relationship of each component or element of the present disclosure, and do not specifically refer to any component or element in the present disclosure, and should not be construed as a limitation to the present disclosure.

[0039] Embodiment 1

[0040] As Figures 1 to 7 shown, the present application provides a method for determining the SOA thermal stability limit line of a power MOSFET device, including the following steps:

[0041] First step, select a power MOSFET device as the device under test (DUT), perform junction calibration on the DUT in an oil bath using a semiconductor thermal analysis device, and perform junction-to-case steady-state thermal resistance R th(jc) measurement and heating characterization measurement, and obtain the transient thermal response data of the DUT through computer thermal simulation, as Figure 2 shown;

[0042] Second step, draw an ideal SOA curve graph of the DUT case temperature T c at 25°C. The SOA curve graph is enveloped by the on-resistance limit line, the maximum current limit line, the maximum power limit line, and the breakdown voltage limit line. The maximum current limit line and the maximum power limit line are divided into DC parts and pulse parts, as Figure 3 shown;

[0043] Third step, measure the thermal instability limit line of the DUT case temperature T c at 25°C;

[0044] Fourth step, parallelly move the above thermal instability limit line downward by 30% to 40% to obtain the thermal stability limit line of the DUT;

[0045] Fifth step, trim the irrelevant points and lines on the SOA to obtain a complete SOA curve graph containing the thermal stability limit line.

[0046] Specifically, in the third step, the measurement method of the thermal instability limit line includes:

[0047] (1) As Figure 4 shown, install the DUT into the thermal runaway test circuit and adjust T c to 25°C, measure the electrical parameters of the DUT using an electrical parameter test system and formulate the failure criterion of the DUT accordingly;

[0048] (2) Control the turn-on and turn-off of the DUT with the pulses shown in the ideal SOA curve diagram, and monitor the drain-source voltage V ds and the drain current I d ;

[0049] As Figure 3 shown, adjust the gate-source voltage V gs and the drain-source voltage V ds such that the coordinate points (V ss(t) , I d(t) ) of each applied test pulse are within the coordinate range of each maximum power limit line;

[0050] As Figure 5 shown, after each test pulse, measure the electrical parameters of the DUT with an electrical parameter test system and compare them with the failure criterion. The coordinate points of the test pulses at which the DUT fails or meets the failure criterion are recorded as thermal instability failure points (V ss(i) , I d(i) ), where i is a natural number satisfying 1 < i < n, and n is the number of thermal instability failure points;

[0051] (3) Plot all the measured thermal instability failure points (V ds(i) , I d(i) ) in the ideal SOA curve diagram. Draw the best-fit line through all the thermal instability failure points (V ds(i) , I d(i) ) corresponding to each pulse. The corresponding line is the thermal instability limit line of each pulse.

[0052] Specifically, in the step (2), the maximum power limit line of DC direct current is determined by the temperature difference and thermal resistance of the DUT. The cumulative thermal resistance of the DUT at the longest time point is always equal to the steady-state thermal resistance of the device. As Figure 2 shown, directly use the pulse current with a pulse width of 1000 ms to measure the thermal instability failure points of the device's DC current.

[0053] Specifically, as Figure 6 shown, the thermal runaway of the MOSFET device occurs in the positive temperature coefficient region with lower I d and V gs . Moreover, according to the Spilito Effect, the thermal runaway that is prone to occur in the DUT at high V ds and low I d reduces the available SOA. Therefore, when measuring the failure points, V ds(t) first gradually decreases from the drain-source breakdown voltage V (br)dss to the minimum voltage of the maximum power limit line (at the left end abscissa V ds1 or V ds3) to keep the pulse width of the test pulse current I flowing through the drain unchanged, while the amplitude of I d(t) gradually approaches the maximum power limit line until the DUT fails, and record this failure point. d(t) By repeated measurements, the thermal instability failure points (V

[0054] , I ds(i) , I d(i) )(i is a natural number where 1 < i < n) of all pulse currents are finally obtained. Select the number of thermal instability failure points to be measured according to the horizontal axis coordinate span of each maximum power limit line. Generally, 2 ≤ n ≤ 7, as Figure 5 shown.

[0055] The SOA curve graph of the device is created by assuming that T c is fixed at 25 °C by a radiator that cannot be perfect. If the device T c increases, the power that the device can handle will decrease, that is, the SOA will shrink. For most power MOSFET devices, it takes about 10 ms for the chip heat to pass through the silicon wafer, solder, substrate, and heat sink to reach the surrounding environment. Transient heating events with a pulse width less than 10 ms will not cause a significant increase in the device's T c ; while transient heating events with a pulse width greater than 10 ms will significantly heat T c as the pulse width increases; in other words, for pulses with a pulse width greater than 10 ms, the actual T c of the DUT after applying the pulse will be higher than 25 °C. Therefore, the thermal instability failure points measured when T c is set to 25 °C also include a certain incidental safety margin.

[0056] As Figure 5 shown, in the step (3), plot all the measured thermal instability failure points (V ss(i) , I d(i) ) in the ideal SOA curve graph. Draw the best-fit line through all the thermal instability failure points (V ds(i) , I d(i) ) corresponding to each pulse. The line should at least pass through the lowest thermal instability failure point. The high-current direction of the line generally intersects with the maximum power limit line or the maximum current limit line, and the low-current direction of the line generally intersects with the breakdown voltage limit line. These lines are the thermal instability limit lines of each pulse current.

[0057] As Figure 5 shown, in the fourth step, move each thermal instability limit line downward parallel by 30% - 40% to obtain the thermal stability limit line of the DUT. The manufacturer can adjust this ratio according to the consistency of the power MOSFET device to obtain thermal stability limit lines with different safety margins.

[0058] As Figure 7 shown, in the fifth step, the irrelevant points and lines in the SOA are trimmed to obtain the SOA curve diagram of the complete power MOSFET device containing the thermal stability limit line.

[0059] Table 1. Verification data table of thermal stability limit line

[0060]

[0061] To verify the reliability of the thermal stability limit line of the power MOSFET device SOA determined by the above method, the gold-sealed LYPM4905 is used as a sample for the reliability verification of the thermal stability limit line below. In its SOA curve diagram containing the thermal stability limit line, relative to the pulsed current, the thermal stability limit line of the DC current contains T c > 25 °C with the attached and downward-translated thermal instability limit line to form a superimposed safety margin. Therefore, it is more scientific and reasonable to preferentially select the pulsed (10 ms) current with a lower safety margin and a shorter pulse width for verification. The verification data is shown in Table 1 above. It can be seen from Table 1 that none of the 9 verification points failed, indicating that the thermal stability limit line of the power MOSFET device SOA determined by the method of the present invention is safe and reliable. In the table, P indicates no failure and F indicates failure.

[0062] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0063] Although the specific implementation manners of the present application are described above in conjunction with the accompanying drawings, it is not a limitation on the protection scope of the present application. Those skilled in the art should understand that based on the technical solutions of the present application, various modifications or deformations that can be made without creative efforts by those skilled in the art are still within the protection scope of the present application.

Claims

1. Method for determining the thermal stability limit line of the SOA of a power MOSFET device, characterized in that, It includes the following steps: First step, perform junction calibration and junction-case steady-state thermal resistance R measurement and heating characterization measurement on the device under test (DUT) using a semiconductor thermal analysis device, and obtain the transient thermal response data of the DUT through thermal simulation; th(jc) ​ Step 2: Draw the DUT case temperature T by calculation c The ideal SOA curve at 25°C is enveloped by the on-resistance limit line, the maximum current limit line, the maximum power limit line, and the breakdown voltage limit line; Step 3, measure the DUT case temperature T c Thermal instability limit line at 25 °C; Step 4: Move the above-mentioned thermal instability limit line downward in parallel by 30% - 40%, which is the thermal stability limit line of the DUT; Step 5: Trim the irrelevant points and lines on the SOA to obtain a complete SOA curve graph containing the thermal stability limit line; In the first step, the DUT is subjected to junction calibration in an oil bath using a semiconductor thermal analysis device, and the junction-to-case steady-state thermal resistance R th(jc) measurement and heating characterization measurement are carried out on a dedicated liquid-cooled temperature-controlled fixture; In the second step, the maximum current limit line and the maximum power limit line are divided into a DC part and a pulse part; In the third step, the measurement method of the thermal instability limit line includes: (1) Install the DUT into the thermal runaway test circuit and configure efficient heat dissipation for the DUT. Uniformly set the reference point temperature to 25°C so that T c remains unchanged at 25°C; Measure the electrical parameters of the DUT using an electrical parameter test system and formulate the failure criterion for the DUT based on this; (2) Control the turn-on and turn-off of the DUT with the pulses shown in the ideal SOA curve, and monitor the drain-source voltage V ds and the drain current I d ; Adjust the gate-source voltage V gs and the drain-source voltage V ds such that the coordinate points (V ds(t) , I d(t) ) of each applied test pulse are within the coordinate range of each maximum power limit line. After each test pulse, measure the electrical parameters of the DUT using an electrical parameter test system and compare them with the failure criterion. The coordinate points of the test pulses at which the DUT fails or meets the failure criterion during measurement are recorded as thermal instability failure points (V ds(i) , I d(i) ), where i is a natural number satisfying 1 < i < n, and n is the number of thermal instability failure points; (3) Plot all the thermally unstable failure points (V ds(i) , I d(i) ) measured in the ideal SOA curve, and draw the best-fit line through all the thermally unstable failure points (V ds(i) , I d(i) ) corresponding to each pulse. The corresponding line is the thermally unstable limit line of each pulse; In the step (2), directly use a pulse current with a pulse width of 1000 ms to measure the thermal instability failure point of the device's DC current; In the step (2), when measuring the failure point, first gradually decrease from the drain-source breakdown voltage to the minimum voltage of the maximum power limit line to the left, keep the pulse width of the test pulse current flowing through the drain unchanged, and gradually approach the maximum power limit line in terms of amplitude until the DUT fails, and record this failure point.

2. The method for determining the thermal stability limit line of the SOA of the power MOSFET device according to claim 1, characterized in that: Select the number of thermal instability failure points to be measured according to the drain-source voltage span of each maximum power limit line, generally 2 ≤ n ≤ 7.

3. The method for determining the thermal stability limit line of the SOA of the power MOSFET device according to claim 1, characterized in that: In the step (3), the best-fit straight line should at least pass through the lowest thermal instability failure point, intersect with the maximum power limit line or the maximum current limit line in its high-current direction, and intersect with the breakdown voltage limit line in its low-current direction.

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