An ARM-based SSI absolute encoder

Abstract

This invention discloses an ARM-based SSI absolute encoder, including at least one MCU processor. The MCU processor's MISO pin outputs a data signal on the second edge of the clock, with the clock phase and polarity set to CPHA=0 and CPOL=1, respectively. The transmission bit length between the clock and the main controller is configured to 8 bits, the data mode is set to MSB, and the SPI interrupt is enabled. Data packets are then grouped and transmitted according to the required number of data bits. The SPI_DATA register is assigned a value within the SPI interrupt. After the last transmission, SPI is disabled, and a timer is enabled to pull the MCU processor's MISO pin low. When the count reaches the timeout period Tm, MISO is pulled high to enable SPI and the timer is disabled. The advantage of this invention is that it is suitable for applications requiring high-precision position measurement.

Description

Technical Field

[0001] This invention relates to the field of absolute encoders, specifically to an ARM-based SSI absolute encoder. Background Technology

[0002] With the widespread application of encoders in servo systems, industrial automation, mechanical control, medical equipment and other fields, the requirements for high-speed synchronization rate of encoder information are becoming increasingly higher. Due to its characteristics such as synchronization, one-way communication, variable bit depth and high anti-interference, the research and development of encoders based on the SSI protocol interface has important practical significance and application value.

[0003] Most processors have a synchronous serial bus interface (SPI), and the communication protocol is similar to that of the SSI bus. When used directly with an encoder, it lacks the ability to support high resolution in applications that require high-precision position measurement. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art; to this end, the present invention proposes an ARM-based SSI absolute encoder to solve the technical problem that the prior art lacks the ability to support high resolution in application scenarios that require high-precision position measurement.

[0005] To achieve the above objectives, the present invention provides an ARM-based SSI absolute encoder, including at least one MCU processor;

[0006] The MCU processor and the main controller are electrically connected via an RS422 signal converter, and the MCU processor and the main controller communicate using SSI communication software.

[0007] The SSI communication software is initialized as follows: the MISO pin of the MCU processor is set to output the data signal on the second edge of the clock, the clock phase and clock polarity are set to CPHA=0 and CPOL=1 respectively, the transmission bit between the clock and the main controller is configured to 8 bits, the data mode is set to MSB, and the SPI interrupt is enabled.

[0008] Next, the MCU processor and the main controller are configured to transmit 12-bit multi-turn and 16-bit single-turn data. Four 8-bit buffers are created, and packets are grouped and transmitted according to the actual number of bits of data to be transmitted. The SPI_DATA register is assigned a value within the SPI interrupt. At the same time, after the last transmission, SPI is turned off, and the timer is turned on to pull the MISO pin of the MCU processor low. When the count reaches the timeout period Tm, MISO is pulled high to turn on SPI and the timer is turned off. This process of assigning values ​​to the SPI_DATA register is repeated to achieve SSI communication.

[0009] Furthermore: the peripherals of the MCU processor are configured in SPI_SLAVE mode;

[0010] The SCK pin of the MCU processor receives the clock signal from the main controller through an RS422 signal converter; the MISO pin of the MCU processor outputs the data signal and sends it to the main controller through an RS422 signal converter.

[0011] The purpose is to utilize RS422 differential signal transmission capability, enhance the signal's anti-interference ability, and allow for data transmission over longer distances.

[0012] Furthermore: the MCU processor receives a pulse sequence from the main controller requesting the encoder's position and status data by sending it to the clock input;

[0013] In the MCU processor, the clock signal always starts from a high level. The first falling edge of the clock signal latches the last available position data. On the first rising edge of the clock signal, the most significant bit of the position data is output to the data output. Then, data can be read and output on the next falling or rising edge. Subsequent bits are transmitted on subsequent rising edges of the clock signal.

[0014] After the last clock signal is transmitted, the data output goes low, and the reading termination time is maintained at t. M When t M When the time is up, the data output goes high again; and before the next data read, this high level must be maintained for at least t. P When reading data, the clock cycle t CL It must not exceed twice the amount of t. M .

[0015] Furthermore, the purpose of activating the timer is to prevent accidental external operation, and the specific method is as follows:

[0016] The MCU interrupt program is triggered by the I / O level signal. That is, after the MCU triggers the falling edge interrupt, it starts the timer. When the timer reaches the timeout period Tm, Tm = 3s, the timer interrupt is triggered. The level signal is obtained within the timer interrupt, and the encoder is controlled accordingly.

[0017] Furthermore, the encoder control rule is as follows: if the level signal obtained within the timer interrupt is still a low level signal, a zeroing operation or an inversion operation needs to be performed, specifically:

[0018] When the I / O level signal is introduced by the interrupt source CTL, a zero-reset operation is performed.

[0019] When the I / O level signal is introduced by the interrupt source DIR, the operation is reversed.

[0020] Furthermore, the MCU processor performs AD sampling, magnetic signal acquisition communication, high-speed rotation count calculation, SSI communication processing, zeroing, and rotation direction control functions.

[0021] The advantages of this invention are: it supports high resolution, up to 24-bit, 25-bit, 30-bit, or 32-bit, making it suitable for applications requiring high-precision position measurement; it transmits data serially, requiring only two lines (clock and data) even with a high encoder resolution, simplifying wiring and reducing installation costs; and it reads data synchronously based on the clock frequency given by the SSI counting section, improving the consistency and accuracy of data transmission. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention and the prior art, the drawings used in the description of the embodiments and the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram illustrating the operation of the present invention;

[0024] Figure 2 This is the SSI time diagram of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0026] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0027] Unless otherwise specified, all embodiments and optional embodiments of this application can be combined to form new technical solutions.

[0028] To better understand the solutions of the embodiments of this application, some related terms and concepts that may be involved in the embodiments of this application will be introduced below.

[0029] (1) (Second edge of the clock): This usually refers to the falling edge of the clock signal, that is, the change from high level to low level. In digital circuit design, it is a common requirement to use the two edges of the clock (rising edge and falling edge) to trigger different operations.

[0030] (2) (MSB: Most Significant Bit): Represents the most significant bit. During data transmission or storage, the bit with the highest weight in the binary number is processed or displayed first. This is typically used to ensure that high-order information is identified and processed first. The concept of MSB is very important in computer science and digital signal processing. For example, in a binary number, the MSB is the leftmost bit with a weight of 2^(n-1), where n is the total number of bits. For example, in the four-bit binary number "1001", the leftmost "1" is the MSB, which has the greatest impact on the value and represents 9 in decimal. MSB can have different meanings in different application scenarios. For example, in a multi-byte sequence, MSB can also refer to the byte with the highest weight. In addition, in the SPI communication protocol, data transmission is performed by default in MSB-first mode. In summary, setting the data mode to MSB means that the bit with the highest weight is considered or transmitted first during data processing. This setting ensures that critical information can be captured and utilized first, making it particularly important in many applications.

[0031] (3)(Buff): This is an integer array with a length of 8, specifically a buffer array with each element occupying 8 binary bits.

[0032] (4) (SPI Interrupt): This is a mechanism for handling Serial Peripheral Interface (SPI) communication, which triggers an interrupt request when specific events occur. These events include data transmission completion, an empty transmit buffer, and a full receive buffer. In embedded systems, configuring and managing SPI interrupts can improve system response speed and efficiency.

[0033] (5) (SPI_SLAVE Mode): This is a working mode in the SPI protocol, namely Slave mode. In this mode, the slave device receives and sends data using the clock signal (SCK) provided by the master device. The master device is responsible for providing the clock signal and selecting a specific slave device for communication using the chip select signal (Slave Select, SS).

[0034] (6)(CTL): refers to a specific position in the port control register used to configure the function of the pin.

[0035] (7)(CTL): Direction Pin, which indicates the direction of encoder rotation. Specifically, this pin outputs a high level when the encoder rotates forward and a low level when the encoder rotates in reverse. This design allows users to determine the direction of encoder rotation by reading the level of this pin and perform corresponding control accordingly.

[0036] (8)(CTL): refers to a specific position in the port control register used to configure the function of the pin.

[0037] Please see Figure 1 This is a schematic diagram of the present invention, including at least one MCU processor;

[0038] The MCU processor and the main controller are electrically connected via an RS422 signal converter. The MCU processor and the main controller communicate using SSI communication software. During SSI communication software initialization, the following steps are performed: the MCU processor's MISO pin outputs a data signal on the second edge of the clock, with the clock phase and polarity set to CPHA=0 and CPOL=1 respectively. The transmission bit length between the clock and the main controller is configured to 8 bits, the data mode is set to MSB, and the SPI interrupt is enabled. Then, the MCU processor and the main controller are configured to transmit 12-bit multi-turn and 16-bit single-turn data, creating four 8-bit buffers. Data is packetized and transmitted according to the required number of bits. The SPI_DATA register is assigned a value within the SPI interrupt. After the last transmission, SPI is disabled, and a timer is enabled to pull the MCU processor's MISO pin low. When the count reaches the timeout period Tm, MISO is pulled high to enable SPI, and the timer is disabled. This process of assigning values ​​to the SPI_DATA register is repeated to achieve SSI communication.

[0039] Specifically:

[0040] While the controller generates a clock signal, the encoder needs to synchronously return a data signal in real time. This encoder mode is similar to an SPI slave, that is, the MCU peripheral is configured as SPI_SLAVE mode, the controller clock signal is connected to the SCK pin, and the MCU outputs the data signal through the MISO pin. Then, the RS422 conversion chip converts SCK and MISO into CLK+, CLK-, DATA+, and DATA- and pushes them to the master controller.

[0041] Since there is no external communication method to communicate with the encoder, an I / O level signal is used to trigger an MCU interrupt routine to prompt the MCU to perform operation. Specifically, the MCU starts a timer after triggering a falling edge interrupt. The purpose of starting the timer is to prevent accidental external operation. The specific method is as follows: The MCU starts a timer after triggering a falling edge interrupt. When the timer reaches its timeout period Tm (Tm = 3s), a timer interrupt is triggered. The encoder control is then performed by acquiring the level signal within the timer interrupt. The encoder control rule is: if the acquired level signal is still low within the timer interrupt, a zeroing operation or an inversion operation is required. Specifically: when the I / O level signal interrupt source is CTL, a zeroing operation is performed; when the I / O level signal interrupt source is DIR, an inversion operation is performed.

[0042] Please see Figure 2As shown in the SSI timing diagram of this invention, the MCU processor receives a pulse sequence from the main controller requesting the encoder's position and status data via a clock input, as indicated by the SSI timing diagram. In this SSI timing diagram, the clock signal in the MCU processor always starts at a high level. The first falling edge of the clock signal latches the last available position data. Furthermore, on the first rising edge of the clock signal, the most significant bit of the position data is output to the data output. Data can then be read and output on either the next falling or rising edge. Subsequent bits are transmitted on subsequent rising edges of the clock signal. After the last bit of the clock signal is transmitted, the data output goes low, maintaining the reading termination time for t. M When t M When the time is up, the data output goes high again; and before the next data read, this high level must be maintained for at least t. P When reading data, the clock cycle t CL It must not exceed twice the amount of t. M .

[0043] The beneficial effects of the present invention are as follows: (1) SPI is usually a four-wire system, namely clock line SCK, master input / slave input line MOSI, master input / slave output line MISO and chip select line NSS; while in the present invention, only clock line SCK and master input / slave output line MISO are used to complete the corresponding functions, and the wiring is simpler; (2) RS422 differential signal transmission is used, which enhances the anti-interference capability of the signal and allows data transmission over a longer distance; (3) High-resolution applications can be achieved by configuring the MCU processor and the main controller, which can reach 24-bit, 25-bit, 30-bit or 32-bit, suitable for application scenarios that require high-precision position measurement; (4) Data synchronous reading is performed according to the clock frequency given by the SSI counting part, which improves the consistency and accuracy of data transmission.

[0044] The foregoing has provided a very detailed description of one and more embodiments of the present invention. However, the description is merely a specific example of the present invention and should not be considered as limiting the scope of application of the present invention. All other methods and modifications proposed based on the content of this invention should fall within the scope of patent protection of this invention.

Claims

1. An ARM-based SSI absolute encoder, characterized in that, Includes at least one MCU processor; The MCU processor and the main controller are electrically connected via an RS422 signal converter, and the MCU processor and the main controller communicate using SSI communication software. The SSI communication software is initialized as follows: the MISO pin of the MCU processor is set to output the data signal on the second edge of the clock, the clock phase and clock polarity are set to CPHA=0 and CPOL=1 respectively, the transmission bit between the clock and the main controller is configured to 8 bits, the data mode is set to MSB, and the SPI interrupt is enabled. Next, the MCU processor and the main controller are configured to transmit 12-bit multi-turn and 16-bit single-turn data. Four 8-bit buffers are created, and packets are grouped and transmitted according to the actual required number of data bits. The SPI_DATA register is assigned a value within the SPI interrupt. Simultaneously, after the last transmission, SPI is turned off, and a timer is turned on to pull the MISO pin of the MCU processor low. When the count reaches the timeout period Tm, MISO is pulled high to turn on SPI and the timer is turned off. This process of assigning values ​​to the SPI_DATA register is repeated to achieve SSI communication. The MCU processor receives a pulse sequence from the main controller, which sends a request for the encoder's position and status data via a clock input. In the MCU processor, the clock signal always starts from a high level. The first falling edge of the clock signal latches the last available position data. On the first rising edge of the clock signal, the most significant bit of the position data is output to the data output. Then, data can be read and output on the next falling or rising edge. Subsequent bits are transmitted on subsequent rising edges of the clock signal. After the last clock signal is transmitted, the data output goes low, and the reading termination time is maintained. ,when When the time is up, the data output goes high again; and before the next data read, the high level must be maintained for at least [time missing]. ; When reading data, the clock cycle No more than twice .

2. The ARM-based SSI absolute encoder according to claim 1, characterized in that, The peripherals of the MCU processor are configured in SPI_SLAVE mode; The SCK pin of the MCU processor receives the clock signal from the main controller through an RS422 signal converter; the MISO pin of the MCU processor outputs the data signal and sends it to the main controller through an RS422 signal converter.

3. The ARM-based SSI absolute encoder according to claim 1, characterized in that, The purpose of activating the timer is to prevent accidental external operation, and the specific method is as follows: The MCU interrupt program is triggered by the I / O level signal. That is, after the MCU triggers the falling edge interrupt, it starts the timer. When the timer reaches the timeout period Tm, Tm=3s, the timer interrupt is triggered. The level signal is obtained within the timer interrupt, and the encoder control is performed accordingly.

4. The ARM-based SSI absolute encoder according to claim 3, characterized in that, The encoder control rule is as follows: if the level signal obtained within the timer interrupt is still a low level signal, a zeroing operation or an inversion operation needs to be performed, specifically: When the I / O level signal is introduced by the interrupt source CTL, a zero-reset operation is performed. When the I / O level signal is introduced by the interrupt source DIR, the operation is reversed.

5. The ARM-based SSI absolute encoder according to claim 1, characterized in that, The MCU processor is a Cortex-M series MCU processor, which performs AD sampling, magnetic signal acquisition communication, high-speed rotation count calculation, SSI communication processing, zeroing, and rotation direction control functions.

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