Signal acquisition and transmission method and device based on main control unit, equipment and medium

Abstract

The invention relates to the technical field of earthquake and acoustic exploration, and discloses a signal acquisition and transmission method, device, equipment and medium based on a main control unit, and the method comprises the steps: generating a sampling clock signal and a time counting signal, driving an analog-to-digital conversion unit to obtain a digital acquisition signal, and reading equipment state parameters; after the timestamp is added, the digital signal is stored in the first cache unit, the state data after the timestamp is added is stored in the second cache unit, the data signal cache unit is written into a first FLASH partition after being full, and the state data cache unit is written into a second FLASH partition after being full. And after data is read from the FLASH, differential signals are output through the multi-wire parallel interface, the logic processing unit and the serialization unit. According to the invention, power consumption is reduced through unified power management and optimization of clock control and a dormancy mechanism, and transmission bandwidth is improved in combination with high-speed differential output, so that both low power consumption and high efficiency are realized.

Description

Technical Field

[0001] This invention relates to the field of seismic and acoustic exploration technology, and in particular to a signal acquisition and transmission method, device, equipment and medium based on a master control unit. Background Technology

[0002] In the field of underwater signal acquisition, the ability to operate independently for extended periods is a crucial metric for equipment performance; however, existing devices are generally limited by power consumption. Since the underwater environment cannot provide external power for extended periods, equipment primarily relies on battery power for signal acquisition, processing, and storage. Therefore, any additional energy consumption in the acquisition and transmission links directly reduces the equipment's operating time. Currently, most underwater signal acquisition devices still fall short in terms of systematic low-power design. Their internal clock control, data processing, and storage scheduling often involve multiple levels of circuitry operating in coordination, making it difficult to effectively reduce overall power consumption and thus limiting the equipment's continuous operation in tasks such as ocean exploration.

[0003] On the other hand, underwater signal acquisition devices need to complete the acquisition and transmission of large amounts of sensor data under limited energy consumption. Traditional devices generally rely on conventional communication interfaces such as SPI and I2C for data readout. Although these interfaces have the characteristics of low power consumption, their transmission bandwidth is usually low, making it difficult to meet the data throughput requirements of high-density, multi-channel signal acquisition tasks. When the amount of data to be acquired is large, the transmission time increases significantly, affecting data processing efficiency. Increasing the transmission rate often requires higher-performance interface circuits, which in turn leads to higher energy consumption, creating a significant contradiction between transmission bandwidth and power consumption.

[0004] Furthermore, existing devices generally rely on external dedicated chips or complex logic circuits to implement functions such as clock division, timestamp generation, and data synchronization control. This not only increases the hardware size but also generates additional static and dynamic power consumption when performing these operations. Some structures also need to keep multiple modules in operation simultaneously, further increasing overall energy consumption and reducing battery life. Summary of the Invention

[0005] The main objective of this invention is to provide a signal acquisition and transmission method, device, equipment, and storage medium based on a main control unit, aiming to solve the technical problem that existing technologies cannot simultaneously achieve clock control, data acquisition, time synchronization, storage management, and high-speed data transmission of multiple stages under low power consumption constraints, resulting in insufficient battery life and low data processing efficiency.

[0006] To achieve the above objectives, the present invention provides a signal acquisition and transmission method based on a main control unit, comprising: The main control unit performs frequency division processing on the received reference frequency source signal to generate a sampling clock signal and a time count signal. The sampling clock signal is output to the analog-to-digital conversion unit, and the time count signal is output to the timestamp unit inside the main control unit. The analog-to-digital conversion unit converts the analog electrical signal output by the sensor into a digital acquisition signal under the drive of the sampling clock signal; The main control unit acquires device status parameters; The main control unit uses the timestamp unit to add timestamps to the digital acquisition signal and the device status parameters based on the time counting signal, and classifies the data after adding timestamps and stores it in the first storage unit of the main control unit. When the main control unit detects that the amount of data in the first storage unit has reached a preset capacity threshold, it wakes up the second storage unit to write data, and after the writing is completed, it controls the second storage unit to enter a sleep state. The main control unit responds to the data read command, reads the stored data from the second storage unit and sends it to the logic processing unit connected to the main control unit through the multi-line serial interface. The logic processing unit performs bit-width encoding conversion on the received data and sends it to the serialization unit connected to the logic processing unit. The serialization unit converts the data into a differential signal and outputs it.

[0007] Furthermore, to achieve the above objectives, the present invention provides a signal acquisition and transmission device based on a main control unit, comprising: The frequency division control module is used by the main control unit to perform frequency division processing on the received reference frequency source signal, generate a sampling clock signal and a time count signal, and output the sampling clock signal to the analog-to-digital conversion unit and the time count signal to the timestamp unit inside the main control unit. An analog-to-digital conversion module is used by the analog-to-digital conversion unit to convert the analog electrical signal output by the sensor into a digital acquisition signal under the drive of the sampling clock signal; The device status acquisition module is used by the main control unit to acquire device status parameters; The timestamp and classification storage module is used by the main control unit to add timestamps to the digital acquisition signal and the device status parameters based on the time counting signal, classify the data after adding timestamps, and store them in the first storage unit of the main control unit. The hierarchical storage management module is used by the main control unit to wake up the second storage unit to write data when it detects that the data volume of the first storage unit has reached a preset capacity threshold, and to control the second storage unit to enter a sleep state after the writing is completed. A serial transmission processing module is used by the main control unit to respond to a data read command, read the stored data from the second storage unit and send it to the logic processing unit connected to the main control unit through a multi-line serial interface. The logic processing unit performs bit-width encoding conversion on the received data and sends it to the serialization unit connected to the logic processing unit. The serialization unit converts the data into a differential signal and outputs it.

[0008] Furthermore, to achieve the above objectives, the present invention also provides a computer device, the computer device including a memory, a processor, and a signal acquisition and transmission program based on a main control unit stored in the memory and executable on the processor, wherein when the signal acquisition and transmission program based on the main control unit is executed by the processor, it implements the steps of the signal acquisition and transmission method based on the main control unit as described above.

[0009] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a signal acquisition and transmission program based on a main control unit, wherein when the signal acquisition and transmission program based on the main control unit is executed by a processor, it implements the steps of the signal acquisition and transmission method based on the main control unit as described above.

[0010] Beneficial Effects: This invention relates to the field of seismic and acoustic exploration technology, and discloses a signal acquisition and transmission method, device, equipment, and medium based on a main control unit, including: receiving a reference frequency source signal and performing frequency division processing to generate a sampling clock signal and a time counting signal; driving an analog-to-digital conversion unit to convert the analog electrical signal output by the sensor into a digital acquisition signal; reading device status parameters; adding timestamps to the digital acquisition signal and device status parameters using the time counting signal; classifying the data with added timestamps and writing it into a first storage unit; when the data volume in the first storage unit reaches a preset capacity threshold, waking up and writing data to the second storage unit; controlling the second storage unit to enter sleep mode after the writing is completed; receiving a data reading instruction and reading data from the second storage unit; sending the data to a logic processing unit connected to the main control unit through a multi-line serial interface; sending the data to a serialization unit after bit-width encoding conversion and outputting a differential signal. This invention achieves high-speed differential data transmission by completing frequency division control, timestamp generation, data classification management, storage space monitoring and sleep control within the main control unit, and by using a multi-line serial interface and serialized output structure. This allows both the data acquisition link and the transmission link to operate under low power conditions, thereby achieving compatibility between long-term independent operation capability and high-bandwidth data output, and improving system endurance and data processing efficiency. Attached Figure Description

[0011] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1This is a schematic diagram of an application environment for a signal acquisition and transmission method based on a main control unit according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating an embodiment of the signal acquisition and transmission method based on a main control unit according to the present invention; Figure 3 This is a schematic diagram of the working process of a signal acquisition and transmission device based on a main control unit in one embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware architecture of a preferred embodiment of the signal acquisition and transmission device based on the main control unit of the present invention; Figure 5 This is a schematic diagram of the low-power management algorithm logic in an embodiment of the signal acquisition and transmission device based on the main control unit of the present invention. Figure 6 This is a schematic diagram of the data transmission process in one embodiment of the signal acquisition and transmission device based on the main control unit of the present invention. Detailed Implementation

[0012] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0013] The signal acquisition and transmission method based on the main control unit provided in this embodiment of the invention can be applied to, for example... Figure 1In this application environment, the client communicates with the server via a network. The server can receive a reference frequency source signal from the client and perform frequency division processing to generate a sampling clock signal and a time count signal. It drives the analog-to-digital conversion unit to convert the analog electrical signal output by the sensor into a digital acquisition signal, reads the device status parameters, adds timestamps to the digital acquisition signal and device status parameters using the time count signal, classifies the timestamped data and writes it to the first storage unit. When the data volume in the first storage unit reaches a preset capacity threshold, it wakes up and writes data to the second storage unit. After the writing is completed, it controls the second storage unit to enter sleep mode, receives data read commands and reads data from the second storage unit, sends it to the logic processing unit connected to the main control unit through a multi-line serial interface, and sends it to the serialization unit after bit-width encoding conversion and outputs a differential signal. This invention achieves high-speed differential data transmission by completing frequency division control, timestamp generation, data classification management, storage space monitoring, and sleep control within the main control unit, and employing a multi-line serial interface and serialized output structure. This allows both the data acquisition and transmission links to operate under low power consumption conditions, thereby achieving compatibility between long-term independent operation and high-bandwidth data output, improving system endurance and data processing efficiency. The client can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. The server can be implemented using a standalone server or a server cluster consisting of multiple servers. The invention will be described in detail below through specific embodiments.

[0014] Please see Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the signal acquisition and transmission method based on a main control unit provided by the present invention. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0015] like Figure 2 As shown, the signal acquisition and transmission method based on the main control unit proposed in this invention includes the following steps: S10, the main control unit performs frequency division processing on the received reference frequency source signal to generate a sampling clock signal and a time counting signal, and outputs the sampling clock signal to the analog-to-digital conversion unit, and outputs the time counting signal to the timestamp unit inside the main control unit; In this embodiment, the main control unit performs frequency division processing on the received reference frequency source signal to derive multiple timing control signals from the input reference frequency source signal. The reference frequency source signal is typically provided by a crystal oscillator, a temperature-compensated oscillator, or a voltage-controlled oscillator, whose output frequency features long-term stability and low short-term jitter. The clock management module inside the main control unit analyzes the reference frequency source signal, identifies its edge variation characteristics and periodic distribution, and configures the frequency division parameters through internal registers to generate a new time series. The frequency division process is implemented through digital counting accumulation, that is, the reference frequency pulses are incremented, and when the count value reaches a set threshold, an output pulse is triggered and the counter is cleared, thereby obtaining a sampling clock signal and a time count signal. The sampling clock signal is used to drive the analog-to-digital conversion unit to complete the sampling of the analog electrical signal and has strict periodic control characteristics. The time count signal is used to provide a monotonically increasing counting reference in the digital domain, providing a unified timing reference for subsequent timestamp generation.

[0016] After the sampling clock signal is generated internally in the main control unit, it is output to the analog-to-digital converter (ADC) via a dedicated pin. This output process relies on the clock drive circuit to ensure level stability, clock edge integrity, and drive capability matching, guaranteeing that the waveform quality reaching the ADC meets its setup and hold time requirements. The time count signal is received by the time base register inside the main control unit, which stores time information in an incrementing count. During the transmission of the time count signal to the timestamp unit, the internal bus uses synchronization control logic to avoid read / write contention during count acquisition, and handshake control ensures that each count value read by the timestamp unit corresponds to the same reference time.

[0017] Frequency division not only generates necessary timing control signals but also affects the overall power consumption and accuracy of the acquisition system. Lower sampling clocks reduce power consumption but may decrease the sampling frequency coverage; higher sampling clocks improve sampling capability but increase energy consumption. Therefore, the selection of frequency division parameters needs to be balanced by considering the sensor's frequency response bandwidth, circuit power supply capability, and long-term underwater operation requirements. After the frequency division result stabilizes, the sampling clock signal and the time count signal are transmitted to the analog-to-digital conversion unit and the timestamp unit through different output paths, respectively, so that the entire acquisition link obtains a unified time driving reference.

[0018] This embodiment generates sampling clock and time counting signals based on a unified clock division mechanism, enabling stable timing drive for the acquisition stage. This avoids the need for additional external frequency divider chips, reducing structural complexity and power consumption. The sampling clock and time counting signals are derived from the same reference frequency source signal, ensuring consistency between the sampling link and the time marker link in the time dimension, thus improving the time reliability of the digital acquisition signal and the time synchronization quality of subsequent data processing.

[0019] S20, the analog-to-digital conversion unit converts the analog electrical signal output by the sensor into a digital acquisition signal under the drive of the sampling clock signal; In this embodiment, the analog-to-digital converter (ADC) converts the analog electrical signal output by the sensor into a digital acquisition signal under the drive of the sampling clock signal, requiring the completion of multiple consecutive signal processing actions. The sampling clock signal provides uniformly distributed timing triggering, enabling the ADC to acquire the amplitude of the analog electrical signal at fixed time intervals. The sampling behavior is triggered based on the rising or falling edge of the clock to ensure consistent time intervals between different sampling periods, allowing the sampling results to maintain accurate time positioning in the subsequent digital domain.

[0020] The analog electrical signals output by the sensors may originate from vibration sensors, underwater acoustic sensors, electromagnetic transducers, or other underwater detection units. These analog signals have different spectral structures, noise characteristics, and dynamic ranges. Therefore, the analog-to-digital converter (ADC) is equipped with an anti-aliasing filter at the input to limit the highest frequency of the input signal, preventing high-frequency components from folding to the low-frequency end during sampling. The cutoff frequency of the anti-aliasing filter is related to the frequency of the sampling clock signal, and the input bandwidth is controlled through hardware design under the constraints of Nyquist theory.

[0021] The sampling process extracts discrete amplitude values ​​from analog voltage or current signals at fixed time intervals. These sampled analog amplitude values ​​are then mapped to a finite set of digital levels using quantization logic. The quantization precision is determined by the number of bits in the analog-to-digital converter (ADC), typically using 12-bit, 16-bit, or higher resolution to ensure that details in weak underwater signals are not lost during digitization. The quantization process is implemented using a comparator array or a successive approximation register structure. The successive approximation structure approximates the analog input by progressively adjusting the digital codeword, ultimately obtaining a digital code representing the analog amplitude.

[0022] After quantization, the digitally acquired signal forms a digital sequence of fixed word length, which is then sent to the output register to await reading by the main control unit. The trigger timing during the sampling process is entirely determined by the sampling clock signal, avoiding sampling point offsets caused by time drift, thus ensuring that the digitally acquired signal accurately reflects the sensor's instantaneous output. The entire sampling link achieves cross-domain conversion between the analog and digital domains at the circuit level, enabling underwater signals to enter the digital processing flow for subsequent storage, labeling, transmission, and analysis.

[0023] This embodiment drives the analog-to-digital conversion unit through a sampling clock signal, ensuring time consistency in the sampling process and improving the timing accuracy of subsequent signal processing. The analog electrical signal is quantized to generate a digital acquisition signal, enabling the underwater sensor output to be stored, played back, and transmitted remotely. The sampling link eliminates the need for an external clock or additional processing unit, reducing overall power consumption and enhancing the system's long-term stable operation.

[0024] S30, the main control unit acquires device status parameters; In this embodiment, acquiring device status parameters involves reading data from multiple independent sources. These sources reflect the device's energy status, spatial attitude, and environmental conditions during long-term underwater operation. The device status parameters include battery power information, angle data, and temperature, humidity, and air pressure data, sourced from the battery management chip, digital compass, and environmental sensors. These sensors are connected to the main control unit via different bus interfaces. Different interfaces use different physical layer protocols, and the main control unit uses a unified access mechanism to periodically or event-triggeredly query these sources.

[0025] Battery power information is read through the battery management chip interface. The battery management chip typically has voltage sampling, current integration, and remaining capacity estimation functions. Its output may be a voltage value, remaining power percentage, or a capacity prediction value calculated by a battery model. When reading the data, the main control unit triggers an update to its internal sampling register, and then obtains the power data from the status register to determine if the device can support the next data acquisition task.

[0026] Angle information is read through a digital compass interface. The digital compass outputs angle information based on three-axis magnetic field data generated by a magnetic sensing element or by attitude fusion results obtained by combining accelerometers and gyroscopes. The main control unit reads the angle data through register mapping or data-triggered interrupts to identify changes in device attitude and ensure that no data quality issues are caused by device position shifts during the acquisition process.

[0027] Temperature, humidity, and air pressure data are acquired through an environmental sensor interface. These sensors sample temperature, humidity, and air pressure using built-in measurement units and store the results in a data register. When querying, the main control unit sends a read command via the bus protocol, subsequently acquiring the environmental data to determine whether the equipment is operating normally, such as whether there is water leakage from the equipment casing or whether the temperature exceeds the allowable range.

[0028] To ensure the reliability of status parameters, the main control unit performs a format standardization operation after reading each type of parameter, converting power, angle, temperature, humidity, and air pressure into a consistent data structure for subsequent timestamp addition and categorized storage. Low-power access mechanisms are employed during the reading process, such as delayed sensor wake-up and batch register reading, ensuring that the entire status parameter acquisition process does not significantly impact the device's overall energy budget.

[0029] This embodiment acquires device status parameters, enabling the underwater data acquisition device to continuously monitor energy status, attitude changes, and environmental conditions during long-term operation. It maintains the stability of the device under low-power operation through multi-source status monitoring and provides the necessary operating conditions support for timestamp addition and data classification storage.

[0030] S40, the main control unit uses the timestamp unit to add timestamps to the digital acquisition signal and the device status parameters based on the time counting signal, and classifies the data after adding timestamps and stores it in the first storage unit of the main control unit; In this embodiment, the process of adding timestamps to the digital acquisition signals and device status parameters based on the time counting signal by the main control unit includes three consecutive operating stages. The first stage is the establishment of the timestamp generation mechanism. The main control unit uses the time counting signal obtained in the previous steps as a unified timing reference. The time counting signal is generally generated by an internal counter incrementing under the drive of a frequency-divided clock. Its value increases steadily over time, used to construct a monotonic and traceable timing sequence. The timestamp unit reads the current count value of the counter and uses it as the source of the timestamp. This count value has the characteristic of being synchronized with the sampling clock, enabling the digital acquisition signals and device status parameters to be aligned under the same time base.

[0031] The second stage involves the main control unit adding timestamps to the digital acquisition signals and device status parameters. The digital acquisition signals originate from the quantization results of the analog-to-digital converter and exhibit continuous sampling characteristics; device status parameters are read from different sensor interfaces and have different update cycles. After acquiring each type of data, the main control unit combines the count value output by the timestamp unit with the data content to form a unified data structure, ensuring that data from different sources possess strict time-series characteristics. The timestamp addition is typically achieved through data structure expansion, field insertion, or header field writing, ensuring that the time correlation of various data types is preserved during storage and subsequent transmission.

[0032] The third stage involves classifying the timestamped data and writing it into the first storage unit. The purpose of this classification is to distinguish the data source and purpose. The main control unit typically categorizes digital acquisition signals as continuously sampled data and device status parameters as system operation information. Classification rules can be based on data type identifiers, data length formats, or source port numbers. After classification, the main control unit organizes the data into a cache structure that facilitates subsequent access, such as building independent storage blocks by category or constructing a linear cache according to time order, and finally writing it into the first storage unit. The first storage unit is generally a low-power on-chip memory, characterized by low access power consumption and fast write speed, making it suitable as a short-term cache area.

[0033] There is a strict logical relationship between timestamp addition, classification, and writing. Timestamp addition ensures the foundation of data serialization, classification ensures structured data management, and writing ensures the secure storage of data in a low-power environment. These three stages form a continuous data processing chain, ensuring that digital acquisition signals and device status parameters have complete time and category information before entering the subsequent storage system.

[0034] This embodiment adds timestamps to digital acquisition signals and device status parameters based on a unified time counting signal using a timestamp unit, and completes classification before writing. This can maintain the temporal order, source differentiation, and structured organization of data under low power conditions, enabling subsequent storage, transmission, and analysis to maintain high reliability and efficiency in energy-constrained environments.

[0035] S50, when the main control unit detects that the amount of data in the first storage unit has reached a preset capacity threshold, it wakes up the second storage unit to write data, and after the writing is completed, it controls the second storage unit to enter a sleep state. In this embodiment, data volume monitoring is a real-time assessment of cache space occupancy within the main control unit. The first storage unit is typically on-chip storage, with limited capacity but low access power consumption. The main control unit obtains the current data volume by reading the internal address pointer, write pointer, or space counter register. The data volume represents the length of data written to the cache or the space occupied. Monitoring methods can be based on incremental count values, periodic scanning mechanisms, or interrupt triggering mechanisms to achieve efficient space usage assessment. The preset capacity threshold is a reference limit set based on cache capacity, write speed, power budget, and external storage characteristics, used to determine when to trigger data write operations to external memory. The threshold can be expressed as a percentage or as a fixed capacity, derived from the balance between steady-state power consumption and transmission latency during the system design phase.

[0036] When the data volume reaches a threshold, the main control unit wakes up the second memory unit. The second memory unit is typically an external non-volatile memory, which consumes very little power in its sleep state but has write capability after waking up. The second memory unit can also be a non-volatile memory area integrated within the main control unit. When using an external non-volatile memory chip, the second memory unit connects to the main control unit via an SDMMC interface, OCTOSPI interface, or other parallel or serial memory interfaces. Its power supply pins and chip select control pins are jointly controlled by the power management circuit and the main control unit's control pins. When data needs to be written, the main control unit turns on the power supply to the second memory unit and pulls the chip select signal low, switching the second memory unit from sleep state to writable state. After completing the data block writing, it turns off the power supply or pulls the chip select signal high, returning the second memory unit to sleep state. When using a non-volatile memory region integrated within the main control unit, the second memory unit is directly connected to the main control core via an on-chip bus. Sleep and wake-up are implemented through an internal power domain control unit and clock gating logic. When the data volume reaches a preset capacity threshold, the main control unit restarts the corresponding storage power domain and operating clock, moves the data block from the first memory unit to the internal non-volatile memory region, and then shuts down the operating clock of that memory region and switches to a low-leakage retention mode to reduce static power consumption. This optional configuration of external non-volatile memory chips and internally integrated non-volatile memory regions allows for flexible selection of the second memory unit implementation under different capacity requirements, package sizes, and power consumption constraints, while maintaining a unified wake-up, write, and sleep control process.

[0037] After waking up, the master control unit sequentially transfers the cached data from the first storage unit to the second storage unit. Writing can be based on page writing, block writing, or streaming writing mechanisms. Digital content is written to external storage according to a predetermined data layout after classification, ensuring that the timestamp data maintains consistency with the classification results. During the data writing phase, the master control unit typically uses write completion flags, busy / idle status indicators, or verification mechanisms to ensure complete data persistence to disk. The internal state machine of the second storage unit performs erase, programming, and verification operations based on the write commands, maintaining data stability in non-volatile storage media.

[0038] Once the write operation is complete, the main control unit controls the second storage unit to re-enter sleep mode to reduce continuous power consumption. Sleep control is typically implemented through low-power mode commands, clock shutdown, or power switching. In sleep mode, the stored content is preserved without loss while reducing continuous power consumption. Before entering sleep mode, the main control unit can perform a storage integrity check to ensure that the data has been written and the retention time requirement has been met.

[0039] This embodiment triggers external writing through a data volume monitoring mechanism and puts the second storage unit into hibernation after the writing is completed. This can effectively reduce the high power consumption of external memory while maintaining reliable data persistence capabilities, enabling long-running devices to achieve stable data recording under limited power conditions.

[0040] S60, the main control unit responds to the data read command, reads the stored data from the second storage unit and sends it to the logic processing unit connected to the main control unit through the multi-line serial interface. The logic processing unit performs bit-width encoding conversion on the received data and sends it to the serialization unit connected to the logic processing unit. The serialization unit converts the data into a differential signal and outputs it.

[0041] In this embodiment, the main control unit's response to a data read command initiates the read process based on external triggering, a scheduling mechanism, or a data query requirement. The data read command can originate from a host computer control, periodic data synchronization, or an internal time scheduling mechanism, used to notify the main control unit to read the stored content in the second storage unit. The response process includes parsing the command format, determining the target address range, and preparing the timing for the read process, enabling the main control unit to accurately locate the data that needs to be returned.

[0042] The data stored in the second storage unit consists of previously written digital acquisition data, status data, and timestamp information. Read operations are implemented through bus access, address positioning, and sequential read mechanisms, enabling data to be retrieved sequentially from the non-volatile storage medium. The main control unit uses internal read pointers, address counters, or page access commands to extract data blocks, achieving reliable acquisition of historical data.

[0043] Multi-line serial interfaces are used to increase data transmission bandwidth by transmitting multiple bits simultaneously through parallel data lines to reduce transmission latency. These interfaces typically include multiple data lines, synchronization signal lines, and direction control lines. Link initialization, frame encapsulation, verification, and transmission are completed by the transmission control module of the main control unit. During data transmission, preset transmission formats, frame structures, and synchronization mechanisms enable the logic processing unit to accurately recover the original data blocks.

[0044] After receiving data from the multi-wire serial interface, the logic processing unit performs bit-width encoding conversion. Bit-width encoding conversion maps data from a source bit-width to a new target bit-width, adapting it to the requirements of subsequent serialization modules. The source data may be processed in units of byte, word, or bits, while the target bit-width is the bit granularity required by the serial propagation link. Bit-width conversion includes operations such as splitting, combining, padding, aligning, or compressing to ensure that the data has clear boundaries and a uniform structure before entering the serialization unit.

[0045] After receiving a data block in the target bit-width format, the serialization unit performs serialization processing, converting the parallel wide data into a sequentially output transmission bit stream. Serialization enables high-bit-width data to be transmitted across fewer physical output lines, improving reliability and reducing the number of interface connections. The serialization process includes shift control, transmit clock generation, and output buffer management.

[0046] Differential signal output refers to encoding a serially transmitted bit stream into two opposing-phase level signals using a differential output driver structure. Differential structures can suppress electromagnetic interference, improve noise immunity, and ensure stable data transmission even in environments with long cables or strong underwater interference. Differential drivers are typically based on current-mode or voltage-mode differential circuits, and signal quality is ensured through impedance matching and output calibration.

[0047] This embodiment forms a unified link by reading data from the second storage unit, converting the bit width of the data into encoding, and outputting differential signals. This enables static data to be output in a high-bandwidth form under low power consumption constraints, ensuring that underwater equipment operating for extended periods still has efficient data transmission capabilities under limited energy consumption conditions.

[0048] In one embodiment, step S10 includes: S101, the main control unit detects the frequency accuracy and stability of the received reference frequency source signal and generates the detection result; S102, if the detection result indicates that the signal is normal, then initialize the internal frequency division module and load the frequency division parameters from the non-volatile memory; S103, set the frequency division ratio based on the frequency division parameters, and perform frequency division processing on the reference frequency source signal based on the frequency division ratio to generate a sampling clock signal and a time counting signal; S104, verify the frequency stability of the sampling clock signal and the time counting signal and calibrate the phase deviation; S105 outputs the verified and calibrated sampling clock signal to the clock input pin of the analog-to-digital converter unit; S106 outputs the verified and calibrated time count signal to the counter register of the timestamp unit; S107, if the detection result indicates an abnormal signal, the frequency division process is stopped and an error handling procedure is executed.

[0049] In this embodiment, when the main control unit performs frequency division processing on the received reference frequency source signal, it needs to first establish a reliable connection with the reference frequency source signal. The reference frequency source signal is typically provided by a crystal oscillator circuit, an external temperature-controlled oscillator, or a high-stability clock module, and is input to the clock management module inside the main control unit in the form of continuous periodic pulses. The main control unit measures the period and frequency of this input pulse through an internal counting circuit or timer channel, counts the number of pulses per unit time within multiple consecutive observation windows, and calculates the deviation relative to the target frequency to simultaneously reflect frequency accuracy and long-term stability. Frequency accuracy can be judged by comparing whether the measured average period and the target period fall within a preset error range, and frequency stability can be evaluated by measuring the frequency fluctuation, jitter, or maximum deviation between different observation windows. The detection results are registered inside the main control unit in the form of status flags, numerical indicators, or error codes for use by subsequent logic branches.

[0050] When the detection result indicates a normal signal, the main control unit initiates the initialization process of the frequency divider module within the clock management module. The frequency divider module can be an integer divider, a fractional divider, or a clock generation unit with adjustable phase integrated into the microcontroller. The main control unit resets, clears, and sets the operating mode of the frequency divider module through the register configuration interface, ensuring that the frequency divider logic is in a predictable initial state. To obtain an output that meets specific sampling frequency and time counting accuracy requirements, the main control unit reads pre-stored frequency divider parameters from non-volatile memory. These parameters may include the division factor, multiplication factor, fractional accumulation factor, phase compensation amount, and configuration tables corresponding to different operating modes. The non-volatile memory can be on-chip flash memory, external serial flash memory, or electrically erasable memory, providing a stable and consistent parameter source for the frequency divider module during power-on configuration or mode switching.

[0051] After acquiring the frequency division parameters, the main control unit sets the division ratio based on these parameters, binds the input of the frequency division module to the reference frequency source signal, and performs frequency division processing on the reference frequency source signal according to the specified division ratio. Internally, the frequency division process uses a counter to periodically count the input clock. When the counter reaches a preset value, it flips the output clock level, or generates the target frequency output through phase accumulation and comparison logic. This allows for the simultaneous generation of a sampling clock signal and a time count signal without altering the hardware conditions of the reference oscillator. The sampling clock signal is optimized for the sampling requirements of the analog-to-digital converter, with its frequency matching the analog signal bandwidth, desired resolution, and signal chain performance. The time count signal is configured for the counting accuracy of the timestamp unit, providing a fine-grained time reference through a higher or more easily integer-divided frequency. Both signals can be derived from the same reference frequency using different division coefficients, or generated under the same integer multiple relationship, to achieve integer-ratio mapping when subsequently associating sampling points with timestamps.

[0052] After the frequency divider module generates the sampling clock signal and the time count signal, the main control unit needs to re-verify the frequency stability and phase relationship of these two signals. The verification process can restart the internal measurement logic, count the number of pulses in the sampling clock signal and the time count signal within a given reference time window, calculate the frequency error against the expected value, and observe jitter and drift within multiple consecutive windows. If the frequency error is still within the preset limit, the frequency stability is considered to meet the operating requirements; if the error is too large, the frequency division coefficient can be adjusted or the frequency division parameters can be reloaded. Regarding phase deviation calibration, the main control unit can set a phase adjustment register to introduce a controllable delay into the sampling clock path or the time count path. By repeatedly measuring the offset between the sampling clock edge and the time count signal edge, the phase relationship is adjusted within the allowable range until a predetermined alignment strategy is achieved, such as fixing the offset or fixing the position of the sampling point relative to the time count edge. This calibration process ensures a reconstructable and consistent mapping between the sampling time of the analog-to-digital conversion unit and the accumulated count value of the timestamp unit, so that subsequent data timestamps do not depend on additional synchronization lines.

[0053] After frequency verification and phase calibration are completed, the main control unit connects the verified and calibrated sampling clock signal to the clock input pin of the analog-to-digital converter (ADC) unit via its internal clock routing network. During this process, the fan-out capability, trace delay, and signal integrity of the clock line need to be considered. The main control unit can configure drive strength, rising edge control, and buffer structures to reduce distortion and jitter introduced by the transmission path, ensuring the ADC unit operates under a stable sampling clock with a reasonable duty cycle. The sampling clock input pin directly uses this signal as a sampling control pulse, ensuring that each analog-to-digital conversion is triggered at a precisely defined time point, thereby guaranteeing the consistency of the digital acquisition signal on the time axis.

[0054] After calibration, the time count signal is distributed by the main control unit to the counter register inside the timestamp unit. The counter register uses this time count signal as its input clock source, incrementing the count value by one with each signal edge, resulting in a count proportional to the actual time. The main control unit can control the timestamp range and cycle period by setting the initial value, maximum value, and overflow strategy of the counter. For example, it can extend the non-repeating time window by expanding the count bit width, or divide a long running process into multiple consecutive intervals by segmented recording. The timestamp unit uses this count value as a time stamp in the data acquisition link, providing a unified time reference when adding time tags to digital acquisition signals and device status parameters, thus achieving internal system time correlation without relying on an external synchronization bus.

[0055] When the detection result indicates an abnormality in the reference frequency source signal, the main control unit ceases the aforementioned frequency division processing and immediately terminates operations related to the frequency division module. Termination actions may include disabling the frequency division clock input, placing the frequency division module in shutdown mode, and disabling the output updates of the sampling clock and time count signals to avoid generating invalid data under erroneous time base conditions. Simultaneously, the main control unit enters an error handling program, records the current error type, error occurrence time, and relevant environmental parameters, stores the error information in internal storage or a secondary storage unit, and selects subsequent actions based on the system design. Subsequent actions may include switching to a backup reference frequency source signal to re-execute the detection and frequency division configuration, sending an error alarm message to the upper-level system, entering a low-power protection mode to await manual intervention, or, in certain scenarios, operating under a low-precision backup clock with a safety degradation configuration to maintain limited functionality. The existence of the error handling program enables the entire time base link to be fault-tolerant, preventing frequency anomalies from spreading in the signal acquisition and data time stamping links and preventing incorrect judgments based on erroneous time information during post-processing.

[0056] This embodiment performs detection, frequency division, stability verification, and phase calibration on the reference frequency source signal within the main control unit. This allows for the simultaneous construction of two time base links—the sampling clock signal and the time counting signal—within the same controller. On one hand, this reduces the additional power consumption and hardware complexity caused by external dedicated frequency division chips and timestamp controllers. On the other hand, it establishes a precisely reconstructable correspondence between the sampling trigger moment and the time counting field, thereby improving the matching accuracy of acquired data and time stamps in long-term underwater operation scenarios and enhancing the reliability of subsequent multi-source data fusion and time series analysis.

[0057] In one embodiment, step S20 above includes: S201, the analog-to-digital conversion unit samples the analog electrical signals output by the vibration sensor and the underwater acoustic sensor under the drive of the sampling clock signal to obtain the sampled analog electrical signals; S202, the analog-to-digital conversion unit quantizes the sampled analog electrical signal into a digital acquisition signal through a successive approximation register; S203, the analog-to-digital conversion unit outputs the digital acquisition signal to the main control unit.

[0058] In this embodiment, when the vibration sensor converts the seismic wave signal into an analog electrical signal, a stable mechanical transmission path must first be established between the mechanical structure and the sensitive element. Seismic wave signals propagate through seabed strata or structures as low- to mid-frequency vibrations, which can be detected by piezoelectric accelerometers, velocities, or strain gauges. The vibration sensor typically contains a sensitive mass, elastic supports, and an electrical conversion unit. The acceleration changes induced by the external seismic wave on the structural surface are converted into relative displacement or strain by the mass and elastic supports, and then converted into electrical changes proportional to the vibration intensity by piezoelectric ceramics, resistance strain gauges, or capacitor structures. This electrical change passes through a preamplifier circuit, a bias network, and a filter network to form an analog electrical signal that is continuous in time and whose voltage or current value varies with the seismic wave signal. To improve the separation capability of seismic wave signals from background noise, a bandpass filter structure can be added to the front end of the vibration sensor to match the frequency band of the target seismic wave. At the same time, the amplification range and noise figure can be adjusted in the circuit parameters to take into account both weak vibration response and unsaturated output of strong vibration, thereby providing an analog electrical signal with controlled amplitude and frequency range for subsequent sampling.

[0059] When underwater acoustic sensors convert underwater acoustic signals into analog electrical signals, the acoustic impedance matching between the underwater sound field and the sensor's sensitive surface must be considered. Underwater acoustic signals can be the re-radiation of seabed seismic waves in the water, or they can be artificial excitation sources or environmental noise, typically received by hydrophones or piezoelectric underwater acoustic probes. Internally, underwater acoustic sensors often employ piezoelectric crystals or piezoelectric ceramic ring structures to convert incident sound pressure into a voltage signal. Externally, an acoustic matching layer and waterproof encapsulation ensure efficient coupling of acoustic energy at the sensitive element. The sensor output is connected to a low-noise preamplifier and a DC isolation network to filter out low-frequency drift and limit high-frequency interference, forming an analog electrical signal that varies with the sound pressure of the underwater acoustic signal. To maintain a usable dynamic range under different water depths and background noise conditions, a configurable gain stage or automatic gain control logic can be introduced into the underwater acoustic sensor path. The amplification factor can be adjusted by configuration parameters issued by the main control unit, allowing the underwater acoustic signal to occupy as much of the effective range as possible within the input range allowed by the analog-to-digital conversion unit, thus improving the resolution of weak echoes and long-distance reflections.

[0060] When the analog-to-digital converter (ADC) samples the analog electrical signals output by the vibration sensor and the underwater acoustic sensor under the drive of the sampling clock signal, it connects the analog inputs of the two paths to the input multiplexing network and the sample-and-hold circuit, respectively. The sampling clock signal provides the ADC with a specific sampling time point. When the rising or falling edge of the sampling clock arrives, the sample-and-hold circuit briefly turns on via a high-speed switch, storing the instantaneous voltage of the current analog electrical signal on the sampling capacitor, and holding this voltage after the switch is turned off until a quantization process is completed. For the two paths of the vibration sensor and the underwater acoustic sensor, alternating sampling, parallel dual-channel sampling, or multiplexed sampling can be used. The internal channel selection control logic selects the analog signal to be acquired in each sampling cycle. The sampling frequency is related to the bandwidth of the sensor output signal. By making the sampling frequency higher than twice the highest effective frequency of the two sensors and adding an anti-aliasing filter at the front end, high-frequency noise can be prevented from folding into the effective bandwidth, maintaining the frequency domain distinguishability of the seismic wave signal and the underwater acoustic signal.

[0061] The sampled analog electrical signal remains relatively stable across the sampling capacitor, providing input for quantization by the successive approximation register. Inside the analog-to-digital converter (ADC), the successive approximation register, combined with comparators and digital control logic, compares the sampled analog electrical signal multiple times with a reference voltage generated by the internal ADC. Each comparison determines whether the ADC output increases or decreases based on the assumed value of the current bit. Within one conversion cycle, adjustments are made bit by bit, starting from the most significant bit, gradually reducing the difference between the reference voltage and the sampled analog electrical signal. Through this sequential comparison process, a binary value is obtained after a finite number of comparisons. This value approximates the voltage or current corresponding to the sampled analog electrical signal in amplitude, forming a digital acquisition signal with a fixed bit width. The bit width of the successive approximation register determines the quantization accuracy; different bit configurations can be used to adapt to target resolution requirements. The combination of the internal reference voltage and front-end gain determines the full-scale range of the digital acquisition signal, enabling quantization of both vibration and underwater acoustic pathways under a unified reference condition.

[0062] The digital acquisition signals can be organized into a data sequence according to channel number and time order within the analog-to-digital converter (ADC). After each quantization, the ADC writes the digital acquisition signal of the current channel into the output register or internal buffer and transmits it through a parallel bus, serial bus, or dedicated interface with the main control unit. The main control unit, on the interface side, reads these digital acquisition signals sequentially through timing control circuitry, distinguishing and buffering the quantization results from the vibration sensor and underwater acoustic sensor according to channel identifiers. To reduce the number of interface switching operations and bus switching losses, the ADC can support batch output, organizing digital acquisition signals from multiple sampling periods into data frames for interaction with the main control unit. It can also notify the main control unit of the read window through interrupt requests or data ready flags. When reading the digital acquisition signals, the main control unit can deduce the sampling time order by combining the sampling clock information generated in the previous part, providing a consistent data basis for subsequent timestamp addition and multi-source data fusion.

[0063] This embodiment constructs a unified conversion link from analog signals to digital acquisition signals in the vibration sensor and underwater acoustic sensor paths, and uses a successive approximation register to complete quantization within the analog-to-digital conversion unit. This reduces the power consumption and hardware complexity of the conversion circuit while ensuring the complete preservation of the waveform characteristics of the seismic wave signal and the underwater acoustic signal. At the same time, it uses the same sampling clock signal to coordinate the sampling timing of the two sensing paths, making underwater signals from different physical sources comparable and synchronized on the time axis. This provides a stable and reliable digital input source for subsequent timestamp marking, state parameter fusion, and high-bandwidth differential transmission, thus balancing energy consumption control and signal quality in long-term underwater independent operation scenarios.

[0064] In one embodiment, step S30 above includes: S301, the main control unit reads battery power information through the battery management chip interface; S302 reads three-axis angle information via a digital compass interface; S303 reads temperature, humidity and air pressure data through the environmental sensor interface; S304, integrate the battery power information, the three-axis angle information, and the temperature, humidity, and air pressure data into device status parameters.

[0065] In this embodiment, obtaining device status parameters primarily relies on the communication link between the main control unit and the battery management chip. The battery management chip interface can be a serial peripheral interface, an I²C bus, or a dedicated single-wire interface. During the power-on initialization phase, the main control unit configures the clock frequency, address, verification method, and interrupt behavior of this interface, and initiates read commands according to a fixed period or event-triggered method during operation. Internally, the battery management chip calculates the current remaining power, state of charge, and health status by sampling physical quantities such as battery terminal voltage, battery terminal current, and internal temperature. The main control unit obtains battery power information by reading power-related registers in the register group. Battery power information can include remaining power values ​​in percentage form, ampere-hour (Ah) values, predicted available time, etc., with multiple fields combined to form a complete power record. After reading, the main control unit converts the original register values ​​into a unified numerical unit, such as milliampere-hours (mAh) and percentage, and adds a timestamp and acquisition sequence number, forming a battery power information data unit that can directly participate in subsequent judgments.

[0066] The digital compass interface is used to communicate with triaxial magnetometers or integrated inertial devices. During interface initialization, the main control unit configures the measurement range, output data rate, and low-power operating mode, enabling triaxial magnetic field measurements to reduce internal power consumption while maintaining attitude resolution accuracy. The acquisition of triaxial angle information involves reading raw magnetic field strength data from the magnetometer in three orthogonal directions, combining this data with a preset geomagnetic reference model and sensor installation orientation parameters, and then calculating the azimuth, pitch, and roll angles of the device relative to geomagnetic north and the gravitational direction using algorithms. The main control unit can perform numerical filtering and attitude calculation locally, or it can simply read the angle register values ​​already processed by the sensor's internal digital core. The triaxial angle information is ultimately represented by three bounded values, each corresponding to a spatial attitude dimension, along with sampling time and data quality markers to support subsequent analysis of attitude change trends.

[0067] The environmental sensor interface connects to an integrated temperature, humidity, and pressure sensor or multiple independent sensors. The main control unit periodically triggers the environmental sensors to perform measurements and reads the converted temperature, humidity, and pressure data through the digital interface. Temperature data can be used to assess battery performance degradation, sensor drift, and electronic component reliability; humidity data reflects the internal sealing condition of the housing and the risk of condensation; and pressure data is related to underwater depth or changes in external pressure. The main control unit performs linear correction and calibration compensation on the raw environmental data, superimposing the sensor's factory calibration parameters and field calibration parameters to ensure the comparability of environmental data under different environmental conditions. The corrected temperature, humidity, and pressure data are organized into structured records, where each record contains temperature, relative humidity, and pressure values, and optional additional fields such as sensor operating mode and error status can be added for diagnosis in case of environmental anomalies.

[0068] Battery power information, triaxial angle information, and temperature, humidity, and air pressure data are integrated into device status parameters within the main control unit. This integration process is not merely a simple field concatenation; rather, it aligns data from different sources into a single state snapshot within the same acquisition cycle using a unified time base, device identifier, and data format. The main control unit first divides the state acquisition cycle based on internal time counting information or external synchronization signals. Within a cycle, it polls and reads data from the battery management chip, digital compass, and environmental sensors. Then, it correlates multiple sets of data obtained within that cycle using an index. For situations where different sensors have varying response delays, the main control unit can configure different trigger advances for each data path to ensure that the data ultimately written to the status buffer is as synchronized as possible in time. The integrated device status parameters can be represented as structures, field arrays, or tag key-value pairs. Each status parameter instance corresponds to an acquisition cycle and includes a power field, attitude field, and environmental field, carrying a unified status number used to establish a mapping relationship with the timestamp of the digital acquisition signal. The resulting device status parameters not only describe the current energy reserve and spatial attitude but also reflect the surrounding environmental conditions, providing fundamental information for acquisition strategy adjustments and data interpretation.

[0069] This embodiment acquires battery power information, three-axis angle information, and temperature, humidity, and air pressure data uniformly within a single acquisition cycle by the main control unit. This data is then integrated into structured device status parameters. This allows for the construction of a joint monitoring capability for energy status, attitude status, and environmental status without significantly increasing additional power consumption. Subsequent digital acquisition signals can be precisely correlated with the corresponding device status in the time dimension. This enables dynamic adjustment of sampling frequency, storage strategy, and transmission strategy based on device status parameters to extend the duration of independent underwater operation. Furthermore, during offline analysis, the acquired vibration and underwater acoustic signals can be interpreted and corrected in conjunction with device attitude and environmental conditions, improving the reliability and usability of the data.

[0070] In one embodiment, step S40 above includes: S401, the main control unit obtains the timestamp value from the timestamp unit based on the time counting signal; S402, use the timestamp value to add a timestamp to the digital acquisition signal and the device status parameter; S403 classifies the digital acquisition signals after adding timestamps and the device status parameters after adding timestamps into analog data and status data. S404, format the classified simulation data class and status data class into a fixed storage format; S405, the formatted simulation data class and status data class are stored in the first storage unit of the main control unit.

[0071] In this embodiment, when the main control unit adds timestamps to digital acquisition signals and device status parameters based on time counting signals using the timestamp unit, it first needs to establish an internal register access relationship with the timestamp unit. The timestamp unit internally maintains a counter driven by the time counting signal. This counter can be a fixed-width binary counting register or a time stamp register that accumulates according to a preset scale. The time counting signal originates from a time base generated by the previous stage frequency division processing; its frequency and duty cycle have already been calibrated in the previous stage. The timestamp unit updates the count value each time a time counting signal arrives. The main control unit periodically, or when a data ingress event is triggered, reads the contents of the counting register in the timestamp unit through the bus access interface and parses the register contents into a timestamp value. The timestamp value can be a time offset relative to system startup, a count value recording the acquisition time, or a converted absolute time code. The main control unit can configure the conversion relationship at the software level to reuse the same timestamp unit in different task cycles.

[0072] After acquiring the timestamp value, the main control unit associates the timestamp value with the currently cached digital acquisition signals and device status parameters. Digital acquisition signals are typically stored in an internal buffer as a sequence of continuous sampling points or grouped data blocks, with each group of data indicating the acquisition order via a sampling sequence number or sampling time index. Device status parameters are composed of battery power information, three-axis angle information, and temperature, humidity, and air pressure data, and are also temporarily cached within the main control unit. During processing, the main control unit binds the digital acquisition signals and device status parameters to the timestamp value according to a preset alignment strategy. For example, it adds a timestamp field to each group of sampled data and its corresponding status parameter, writing the timestamp value into this field. For cases where a time slice contains multiple groups of digital acquisition signals, the main control unit can record the timestamp value at the beginning of the time slice and then describe the accurate time of each group of data using a relative offset. Alternatively, it can write an independent timestamp value for each group of data to improve the accuracy of subsequent analysis. The process of adding timestamps is reflected in the storage structure by inserting a timestamp field into the existing data structure or expanding the header information area, ensuring a one-to-one correspondence between the timestamp value and the corresponding data content through field offsets or tag indexes.

[0073] After timestamps are appended to the digital acquisition signals and device status parameters, the main control unit classifies the two types of data into analog data and status data according to preset classification rules. Analog data corresponds to digital acquisition signals from vibration and underwater acoustic sensors, typically characterized by high sampling rates, continuous sequences, and large data volumes. Status data corresponds to device status parameters, with smaller data volumes but more field types, and an update frequency typically lower than that of analog data. During classification, the main control unit can add a type identifier field to each data record or map data to different classification queues based on the data source buffer. For example, data from the analog-to-digital conversion unit path is assigned to the analog data buffer by default, while device status parameters from the battery management chip interface, digital compass interface, and environmental sensor interface (fused together) are assigned to the status data buffer. The classification process not only clearly distinguishes between the two types of data but also internally assigns different priorities, cache depths, and subsequent processing strategies to different data types, providing a basis for subsequent threshold judgments and external storage writes.

[0074] After classification, the master control unit formats the simulated data and status data classes into a fixed storage format. A fixed storage format means using a uniformly defined field layout, length encoding method, and alignment method in the first storage unit to ensure data structure consistency across different batches of writes. The master control unit can construct a record header for each record, containing a data type identifier, timestamp value, data length, data payload, and optional check fields. Then, it writes the corresponding data payload based on the length field in the record header. For example, simulated data records can use a continuous sample array as the data payload, while status data records can use a multi-field structure. Both maintain a unified header format for easy processing by the same parsing logic. To improve the space utilization of the first storage unit, the master control unit can employ a compact alignment strategy, aligning records by byte or word, and maintaining pointers to free and used areas through an internal management structure to reduce fragmentation. For scenarios requiring verification, the master control unit can also add a checksum field to the fixed storage format, calculating a checksum based on the record content and writing it to this field to support subsequent data integrity verification.

[0075] After the fixed storage format is generated, the main control unit writes the formatted analog data class and status data class into the first storage unit. The first storage unit is usually a random access memory located inside the main control unit, which is directly addressed and accessed by the main control unit. Before writing, the main control unit determines whether the remaining available space meets the writing requirements based on the current write pointer position and record length. If it does, the main control unit continuously writes the record header and data payload into the storage area and updates the write pointer position and related management information, such as the record count counter and data volume counter. If the first storage unit has independent areas to store the analog data class and status data class respectively, the main control unit maintains two or more write pointers respectively and performs independent write management for different areas. After writing is completed, a record sequence organized according to the fixed storage format is formed in the first storage unit. Each record carries timestamp information and data type identifier, providing a structural basis for subsequent writing to the second storage unit triggered according to a preset capacity threshold and for classified transmission during the data reading stage.

[0076] In this embodiment, the main control unit obtains the timestamp value from the timestamp unit based on the time counting signal, and adds timestamps to the digital acquisition signal and device status parameters. Then, the data with added timestamps is classified into analog data type and status data type and written into the first storage unit in a fixed storage format. The three key processes of time stamping, category differentiation and structured caching can be completed within a single main control chip. On the one hand, it establishes an accurate time correlation between the digital acquisition signal and the device status parameters without adding additional peripheral devices, providing a reliable foundation for subsequent status-based acquisition quality analysis and anomaly judgment. On the other hand, the classification and fixed storage format design makes the data in the first storage unit compact and easy to migrate in batches by type. When the data volume reaches the preset capacity threshold, it can be efficiently written to the second storage unit in units of records, reducing the number of writes and control overhead, which helps to reduce overall power consumption and improve the data processing efficiency in the subsequent reading and transmission stages.

[0077] In one embodiment, step S50 above includes: S501, the main control unit monitors the current data volume of the first storage unit; S502, compare the current data volume with the preset capacity threshold; S503, if the current data volume reaches the preset capacity threshold, a wake-up signal is sent to the second storage unit, and the data block in the first storage unit is transferred to the second storage unit for data writing; S504: After the data writing is completed, a hibernation command is sent to the second storage unit.

[0078] In this embodiment, when the main control unit monitors the data volume of the first storage unit, it first needs to maintain data volume count information related to the first storage unit internally. The first storage unit is generally a random access storage space inside the main control unit, used to cache simulated data and status data records after timestamp processing and formatting. Each time the main control unit writes a record to the first storage unit, it can accumulate the byte count according to the record length or count according to the number of records; at the same time, when clearing or migrating cached data to the second storage unit, it correspondingly decrements or resets the count. The current data volume can be implemented using different measurement methods such as the number of bytes, the number of records, and the number of sampling frames. During the initialization phase, the main control unit writes the selected measurement method and initial value into an internal register or static variable, and continuously updates it during subsequent data writing and clearing processes to reflect the current occupancy of the first storage unit.

[0079] A preset capacity threshold is used to define the boundary conditions for triggering external write operations on the first storage unit. This threshold is directly related to the physical capacity of the first storage unit, the write granularity of the second storage unit, and the overall power consumption budget. During power-on or configuration, the main control unit reads the capacity threshold parameter from non-volatile memory or the configuration area and stores it in the internal configuration register. For example, it may represent the maximum cache space allowed for the first storage unit in bytes, or the number of records required for one write cycle in records. The capacity threshold can be set according to the duration of the marine exploration mission, the sampling frequency, and the page write scale of the external storage chip to balance the number of writes and cache utilization. During monitoring, the main control unit periodically compares the current data volume with the preset capacity threshold, or after each write operation. The comparison can be achieved through simple numerical judgment or by combining safety margins for multi-level judgment. For example, when the current data volume is close to the threshold, a write operation can be triggered in advance to avoid overflow during subsequent data writes.

[0080] When the comparison result indicates that the current data volume has reached the preset capacity threshold, the main control unit initiates the write process related to the second storage unit. The second storage unit is typically an external non-volatile device, such as a serial flash memory chip or other low-power, high-capacity storage device, which maintains a low-power sleep state during non-operational periods. To reduce static power consumption, the main control unit keeps the second storage unit in deep sleep mode by controlling the chip select pin, power control pin, or a dedicated power management interface when no data is being written. The wake-up signal can be manifested by pulling the effective level of the chip select pin low and sending a specific wake-up command code, or it can be controlled by the power management module to enable the power supply to the second storage unit, guiding it to switch from shutdown or standby mode to operating mode. After sending the wake-up signal, the main control unit can confirm that the second storage unit has entered a writable state by reading the status register, monitoring the busy / idle flag, or waiting for a fixed wake-up time.

[0081] After the second storage unit enters the working state, the main control unit retrieves the data blocks to be written from the first storage unit. Data blocks can be divided into fixed-length segments or packaged into complete record sequences to ensure that a single write operation in the second storage unit can cover the entire data record without generating page fragmentation. The main control unit internally generates the start address and length information of the data blocks, moves the data block content to the transmission buffer, and then executes the data writing through the bus interface connected to the second storage unit. The bus interface can be a multi-wire serial interface, SPI interface, QSPI interface, or other adapted physical links. The main control unit can enable a direct memory access controller to reduce the central processing core's workload during data transfer. The data write instruction sequence generally includes a write command, a target address byte, and consecutive data bytes. After sending the data, the main control unit can also read status information to confirm whether the write operation is complete and whether any write errors have occurred.

[0082] To ensure effective power control after the write operation is complete, the main control unit sends a sleep command to the second memory unit after the data write is finished. The sleep command corresponds to the low-power mode switching instructions supported by the second memory unit, such as deep power-down commands or standby commands. Before sending the sleep command, the main control unit can check the busy / idle status of the second memory unit to ensure that all write cycles have ended and no page programming or block erase operations are in progress, preventing data corruption caused by entering sleep mode before the write operation is complete. After sending the sleep command, the main control unit can isolate the second memory unit from the bus logic by pulling the chip select pin high, disabling the clock input, or disabling the power management module output, further reducing leakage current and dynamic power consumption. Simultaneously, the main control unit updates the data volume count of the first memory unit, deducting or resetting the count of data already migrated to the second memory unit, freeing up space for subsequent cache cycles and implementing a multi-round data migration cycle.

[0083] This embodiment, through the above steps, can limit the operation of high-power external storage devices to the necessary write window, reduce the number of external writes and the length of time to maintain activation by migrating cached data in batches, and achieve fine power control of the external storage link while ensuring the safe storage of large amounts of data to disk. This improves the continuous working time of underwater signal acquisition equipment under battery power conditions, while taking into account both cache space utilization efficiency and data storage reliability.

[0084] In one embodiment, step S60 above includes: S601, the main control unit parses the data reading instruction to determine the starting address and reading length of the target data segment, and sequentially reads the corresponding data content from the second storage unit based on the starting address; S602, the main control unit encapsulates the data content into a multi-line serial transmission data frame according to a preset transmission format, and sends the multi-line serial transmission data frame to the logic processing unit connected to the main control unit through the multi-line serial interface. S603, the logic processing unit performs integrity verification on the multi-line serial transmission data frame, and after the integrity verification is passed, performs bit width encoding conversion on the multi-line serial transmission data frame based on the preset bit width mapping table to obtain a data block in the target bit width format. S604, the logic processing unit sends the target bit-width format data block to the serialization unit connected to the logic processing unit, and the serialization unit performs serialization processing on the target bit-width format data block to generate a serial transmission bit stream; S605, the serialization unit converts the serial transmission bit stream into a differential signal and outputs it based on the differential output driving structure.

[0085] In this embodiment, during the data reading process, the main control unit first needs to understand the data reading instructions from the host device or task scheduling module. Data reading instructions are typically encoded in a fixed format, including an operation type marker, a target data segment identifier, a start address field, and a read length field. Upon receiving the instruction, the main control unit uses internal parsing logic to break down the instruction bytes field by field, matching the operation type with the current state machine to confirm that the operation to be performed is reading data from the second storage unit. Then, it parses the start address and read length of the target data segment from the instruction. The start address can be a physical or logical address within the second storage unit, and the read length can be in bytes, words, or pages, indicating the range of data covered by this read. After parsing, the main control unit saves the start address and read length in internal registers or local variables and generates a read access command sequence for the second storage unit accordingly.

[0086] The second storage unit is typically a non-volatile memory chip, such as a serial flash memory device or a low-power, high-capacity storage component. After completing the data write and entering sleep mode, it needs to be accessible before read access. During the read access phase, the main control unit can either have already put the second storage unit into working mode during the previous write phase, or it can perform a wake-up process when the data read command arrives. Then, based on the starting address and read length, it sequentially reads the corresponding data content through the physical bus connected to the second storage unit. The read process usually includes sending a read command, specifying the target address, and receiving consecutive data bytes. The main control unit can use direct access to read the data content into the internal buffer sequentially, or it can use a direct memory access controller to complete the data transfer without consuming too much processing kernel time. The data content here corresponds one-to-one with the data blocks previously written to the second storage unit and is usually a set of records organized according to timestamps and a fixed storage format.

[0087] The second storage unit can be configured as an external non-volatile memory connected to the main control unit via a storage interface, or a large-capacity non-volatile memory array can be integrated inside the main control unit chip. The first storage unit is used for on-chip caching, and the second storage unit is used for long-term data storage.

[0088] After the main control unit completes the sequential reading from the second storage unit, it needs to convert this data content into a transmission structure adapted to the multi-line serial interface. The multi-line serial interface is an interface form that groups and encodes data on a parallel basis and transmits it in parallel through multiple physical lines. Compared to a single-line serial link, it can significantly improve throughput while not requiring as many pins as a wide parallel bus. To ensure that the receiving end of the multi-line serial interface can correctly parse each piece of data, the main control unit encapsulates the data content into a multi-line serial transmission data frame according to a preset transmission format. The preset transmission format may include a frame header field, frame length field, payload field, check field, and alignment padding field, used to identify frame boundaries, describe data length, and provide error detection capabilities. The main control unit constructs a complete data frame in its internal buffer according to this format, fills the read data content into the payload area, calculates the check value after filling, writes it into the check field, and then sends the multi-line serial transmission data frame to the logic processing unit through several data lines and a synchronization clock line of the multi-line serial interface.

[0089] In one implementation, the logic processing unit is located outside the main control unit and is electrically connected to the main control unit through a multi-wire serial interface. The logic processing unit and the main control unit can be arranged on the same circuit board or integrated inside the same system-on-a-chip and interact with each other through the on-chip bus.

[0090] After receiving multi-line serial transmission data frames, the logic processing unit needs to parse the frame structure and perform integrity checks on the content. Integrity checks can be based on frame header markers, frame length information, and check fields, using mechanisms such as cyclic redundancy check (CRC), polynomial check, or other error detection mechanisms. The logic processing unit first performs word alignment and frame boundary detection on the received data stream, determines the start position of each data frame based on the frame header identifier, and then extracts the payload and check field based on the frame length field. Subsequently, it performs check calculations on the extracted data using a preset check algorithm and compares the calculation result with the check value encoded in the frame. If the comparison result indicates that no bit errors occurred during the data frame transmission, the logic processing unit marks the frame as valid data and proceeds to the next stage; if an error is detected, the frame can be discarded, and the error status can be reported back to the main control unit or the upper-level system, triggering a retransmission mechanism if necessary. Integrity checks ensure that subsequent bit-width encoding conversion and serialization processing are based on reliable data, preventing errors from further propagating to the physical link.

[0091] After integrity verification, the logic processing unit needs to perform bit-width encoding conversion on the data content according to the data bit-width requirements of the downstream interface. Bit-width encoding conversion refers to mapping the bit width of each unit of data in the current data format to the target bit width to adapt to the parallel input bus width within the serialization unit or the logic encoding scheme of subsequent links. To achieve this process, the logic processing unit maintains a preset bit-width mapping table to describe the mapping relationship between the original data bit width and the target bit width, as well as the possible encoding methods. For example, the original data may be aligned to 16 bits or 24 bits, while the serialization unit needs to perform parallel sampling with 10 bits, 12 bits, or other widths. In this case, the logic processing unit can determine the specific segmentation method and padding strategy by looking up the table, and perform grouping, rearrangement, compression, or expansion processing on the data to generate data blocks in the target bit-width format. The data blocks in the target bit-width format are the re-encoded data sets, which are logically matched to the input width of the serialization unit and can be directly sent to the subsequent serialization stage.

[0092] After receiving the data block in the target bit-width format, the logic processing unit transmits it to the serialization unit via an internal bus or inter-module interface. The main task of the serialization unit is to convert the parallel target bit-width data into a single-bit or low-bit-width serial transmission bit stream. To accomplish this conversion, the serialization unit typically includes shift registers, parallel loading logic, and clock control logic synchronized with the upstream data blocks. In each transmission cycle, the serialization unit receives a set of data blocks in the target bit-width format from the logic processing unit, loads these data blocks in parallel into shift registers, and then shifts them out bit by bit in subsequent clock cycles, forming a continuous serial transmission bit stream. The bit rate of the serial transmission bit stream is related to the width of the upstream parallel data and the loading cycle. The serialization unit can adjust the internal clock multiplication, division, or phase correction mechanisms to match the bit stream rate with the bandwidth requirements of the external physical link, thereby achieving high throughput transmission capability with a limited number of pins.

[0093] In one implementation, the serialization unit is located downstream of the logic processing unit, electrically connected to the logic processing unit via a parallel data bus, and connected to an external data receiving device via a differential signal output port. The serialization unit can be implemented as an independent serializer chip or as a serial transceiver module integrated within a programmable logic device.

[0094] After generating the serial transmission bitstream, the serialization unit needs to convert the bitstream into a differential signal and output it to an external physical interface. The differential output driver structure typically consists of two complementary output terminals, expressing the digital bit state by outputting voltage or current signals of opposite amplitudes on two wires. Compared to single-ended signals, differential signals have stronger anti-interference capabilities and lower bit error rates in long-distance transmission and electromagnetic interference environments. The differential output driver structure inside the serialization unit receives the serial transmission bitstream, converts the logic high and low levels into a pair of inverted outputs, and controls the output swing, rise time, and fall time according to predetermined electrical standards. For example, the output bias and termination matching can be controlled according to low-voltage differential signal standards to reduce reflections and crosstalk. In this way, the serialization unit accurately maps the bitstream in the logic domain to differential electrical signals in the physical domain, outputting them to the host acquisition system or shore-based receiving equipment via underwater cables or connectors, providing stable physical layer support for high-bandwidth, low-noise data links.

[0095] Example Description: In a long-term seabed monitoring mission, after the user arrives at the deployment location with a signal acquisition and transmission device based on the main control unit, they send acquisition commands to the device via an external control terminal. The main control unit inside the device immediately initiates the system initialization process and dynamically sets the power configuration, module sleep strategy, and MCU main frequency according to a low-power management algorithm, so that each hardware component enters the most suitable energy consumption state before entering the continuous acquisition phase. Subsequently, the main control unit loads the clock signal of a high-precision crystal oscillator and generates an ADC sampling clock and a reference frequency for timestamp counting through an internal clock divider module. After the clock stabilizes, the vibration sensor and the underwater acoustic sensor begin to sense weak seismic waves and underwater acoustic signals from the surrounding environment in real time. These analog signals are input to a high-resolution ADC converter and, driven by the counting of the high-precision timestamp module, obtain corresponding timestamps, which are then converted into digital sampled data one by one.

[0096] During the data acquisition process, the main control unit simultaneously reads the battery level information returned by the battery management chip at predetermined intervals. Under intermittent power supply, it sequentially activates the three-axis digital compass and temperature, humidity, and barometric pressure sensors to collect status data such as device attitude changes, temperature and humidity conditions, and atmospheric pressure changes. The main control unit distinguishes between analog data from the ADC and device status data based on the type of data acquired, writing them to the on-chip RAM using a fixed-structure buffer format to ensure data structure consistency and ease of processing when subsequently writing to storage media.

[0097] As data acquisition continues, the on-chip RAM will gradually become full. At this point, the main control unit detects that the storage capacity has reached a preset threshold and automatically wakes up the large-capacity FLASH unit that is in sleep mode, putting it into a writable state. The categorized cache data in RAM is then written to the designated partition of the FLASH. After the writing is completed, the main control unit re-executes low-power settings on the FLASH, causing it to return to sleep mode, thereby extending the overall battery life of the device and ensuring continuous data acquisition and storage capabilities for hundreds of days.

[0098] Throughout this process, the low-power management algorithm remains running, adjusting the power supply path, main control frequency, sensor power-on duration, and peripheral duty cycle as needed based on the device's state of acquisition, idle, low power consumption, or low battery. This ensures the entire system automatically maintains the lowest possible energy consumption level under different operating conditions. For example, when low battery levels are detected, the algorithm reduces the sampling frequency and shortens the peripheral's duty cycle; when the device is idle and waiting for new instructions, non-essential modules are immediately disconnected from power or enter deep sleep mode, minimizing device power consumption.

[0099] When the external control terminal issues a stop acquisition command, the main control unit writes the remaining cached data in RAM to the corresponding area of ​​FLASH, and ends the acquisition mode after the write is complete. If a data read command is subsequently received, the main control unit will prioritize reading the analog data in FLASH according to the data type, and send the data to the FPGA via the OSPI interface. The FPGA is responsible for performing 8b / 10b encoding on the received data and transmitting it to the serializer chip through the parallel interface. The serializer chip then converts the parallel LVTTL signal into a serial LVDS signal, realizing high-speed, low-interference long-distance data transmission. After the analog data reading and transmission are completed, the main control unit continues to read the status data stored in FLASH and outputs it in the same process to ensure that the external system can completely analyze the environmental changes and device status throughout the entire acquisition cycle.

[0100] During data transmission, the high bandwidth of the OCTOSPI interface enables the entire link to stably reach a maximum data transmission rate of 50MB / s, making it suitable for large-scale device deployments and centralized data retrieval scenarios. If the control terminal issues an interface call related to clock synchronization, the FPGA can use its internal PLL to shape the high-precision crystal oscillator signal into a specified output frequency, and then pass it to the LVDS transmitter to convert it into a differential signal to achieve external clock synchronization, providing a stable and reliable reference clock source for multi-device collaborative acquisition scenarios.

[0101] Throughout the deployment cycle, based on the above-mentioned working mode and hardware co-design, the device can operate continuously under low power consumption constraints, capture high-precision seismic waves and underwater acoustic signals in real time, maintain stable data acquisition quality in ultra-long-term mission environments, and achieve rapid data retrieval by relying on high-speed transmission links, providing a continuous and reliable data source for underwater monitoring, geological exploration and marine scientific research.

[0102] Through the above steps, this embodiment can achieve a high-throughput data readout link while maintaining a low number of pins and controlled power consumption. At the same time, it improves the anti-interference capability and data integrity during long-distance underwater transmission, enabling the digital acquisition signals and device status parameters accumulated at the front end to be transmitted quickly and stably to the upper system within a limited uplink window. This reduces the pressure on the overall power consumption budget during the data backhaul stage, thereby further enhancing the continuous working capability and data reliability of the underwater signal acquisition device in high-bandwidth demand scenarios.

[0103] In one embodiment, a signal acquisition and transmission device based on a master control unit is provided, which corresponds one-to-one with the signal acquisition and transmission method based on a master control unit in the above embodiments.

[0104] In one embodiment, a computer device is provided, which may be a server. The computer device includes a processor, memory, a network interface, and a database connected via a system bus.

[0105] In one embodiment, a computer device is provided, which may be a client. The computer device includes a processor, memory, network interface, display screen, and input device connected via a system bus.

[0106] In one embodiment, a workflow of a signal acquisition and transmission device based on a main control unit is provided. A schematic diagram of the workflow is shown below. Figure 3 As shown. Reference Figure 3 , Figure 3 This illustrates the overall process from "MCU Operation" to the completion of a single data acquisition and write operation, as well as data reading and transmission. After the MCU powers on and enters the running state, it first determines whether to enter the acquisition process at the "Start Acquisition" checkpoint based on external control instructions or internal task configuration. If the checkpoint is yes, the process enters the "Power Management" stage, where the MCU configures the power supply to the signal acquisition link, memory, and related peripherals, ensuring the system operates at a power consumption suitable for continuous acquisition. After power management, the process enters the "Data Acquisition" stage. The MCU controls the analog-to-digital converter to output sampled data according to preset sampling parameters and writes the acquired digital data into the on-chip RAM for buffering. At the "RAM Full" checkpoint, the MCU determines whether to trigger a non-volatile memory write based on RAM occupancy. If the checkpoint is yes, the process enters the "FLASH Data Write" stage, waking up the connected large-capacity FLASH memory and writing the data block from the RAM into the FLASH. After writing is complete, the process enters the "Stop Acquisition" checkpoint, where it determines whether to return to the "Data Acquisition" checkpoint to continue the loop of acquisition and writing, or to terminate the current acquisition task, depending on whether a stop acquisition command has been received. When the conditions for stopping data acquisition are met, the MCU, after writing the remaining buffered data, proceeds to the "Start Data Reading" judgment node. If there is a data reading requirement, it enters the "FLASH Data Reading" stage, reading the stored data from the FLASH memory in address order. At the "Data Sending" node, the read data is then sent via the external communication link. Finally, at the "Data Reading Complete" judgment node, depending on whether there is still data to be exported, it decides whether to continue looping between "FLASH Data Reading" and "Data Sending," or to end the data reading process and return to the non-acquisition running state.

[0107] In one embodiment, a signal acquisition and transmission device based on a main control unit is provided, the hardware architecture of which can be illustrated as follows: Figure 4 As shown. Reference Figure 4 , Figure 4This demonstrates the interconnections of the various modules within the low-power underwater signal acquisition device. A centrally located ultra-low-power MCU runs a "data acquisition and processing unit" and a "low-power management algorithm." It connects to multiple vibration and underwater acoustic sensors on the left side via a multi-channel analog front-end. The analog signals output from these sensors are fed into a "high-resolution ADC circuit," where analog-to-digital conversion is performed. The digital data output from the ADC is then transmitted back to the MCU via a data line. Above the MCU are a "high-precision time source" and a "clock divider" module. The high-precision time source provides a reference clock, and the divided clock signal is sent to the ADC for sampling and also input to the MCU's internal timestamp unit for data acquisition time stamping. In the status monitoring path, the MCU connects to a "battery management," "three-axis digital compass," and "temperature, humidity, and barometric pressure" sensor via interface circuits. These devices form the device status monitoring link, providing the MCU with power, attitude, and environmental parameters. On the right side is a "large-capacity FLASH," connected to the MCU via the "SDMMC bus," used to store long-term acquired data. Simultaneously, an "external communication unit" is located at the lower right, containing an "FPGA," a serializer, an "LVDS transmitter," an "LVDS receiver," and a "PLL." The MCU communicates with the FPGA via the "OCTOSPI bus" and "UART interface." In the data transmission direction, the MCU outputs packaged sampled data to the FPGA via the OCTOSPI bus. The FPGA internally performs "8b / 10b conversion" and I / O data organization, then sends the parallel LVTTL data to the serializer, which outputs an "LVDS" differential signal, enabling long-distance, high-speed transmission. In the command reception direction, the external "LVDS" link is input to the "LVDS receiver," converted to LVTTL level, and then enters the FPGA. The FPGA forwards control commands to the MCU via the UART interface, thereby completing data acquisition control and parameter configuration.

[0108] In one embodiment, a low-power management algorithm suitable for a signal acquisition and transmission device based on a main control unit is provided, and its state machine logic diagram can be as follows: Figure 5 As shown. Reference Figure 5 , Figure 5The "state machine" in the system switches between different states such as "power off," "low power," "idle," and "acquisition" based on the current operating state of the device. It also performs combined control of the MCU main frequency, power supply to the signal acquisition unit, power supply to the status monitoring unit, and the high-capacity FLASH power supply. In the "power off" and "low power" states, the control strategy employs "MCU-only power supply" and "reduced MCU main frequency," shutting down or putting most peripherals into sleep mode, leaving only the MCU running at a low frequency to handle long standby times or extremely low battery scenarios. In the "idle" state, the state machine restores the MCU main frequency to a frequency suitable for responding to external commands according to the task schedule. Simultaneously, it activates the "signal acquisition unit power supply" and uses "intermittent power supply" for the status monitoring unit, periodically activating sensors such as the "three-axis digital compass" and "temperature, humidity, and air pressure" to acquire environmental and attitude data within a limited duty cycle, allowing the device to maintain its operating status even when not continuously acquiring data. During this time, the "high-capacity FLASH power supply" remains on to receive data written by the MCU or participate in data management. In the "acquisition" state, the state machine maintains or restores the MCU main frequency so that the data processing capability meets the continuous sampling requirements. The vibration sensor, underwater acoustic sensor and high-resolution ADC circuit are kept working continuously through the "signal acquisition unit power supply". The status monitoring unit still periodically powers on to acquire the operating status according to the "intermittent power supply" strategy. The "large capacity FLASH hibernation / shutdown" keeps the non-volatile memory at low power when no write operation is performed, and is woken up by the acquisition process when a write operation is required. Figure 5 Multiple arrows indicate the transition direction between different states. The state machine switches back and forth between power off, low power, idle and acquisition states based on conditions such as battery level, acquisition task, and external control commands. By combining the power supply of each module and the MCU main frequency, the overall energy consumption of long-term underwater operation is reduced.

[0109] In one embodiment, a data transmission process is provided in a signal acquisition and transmission device based on a main control unit, in which the main control unit cooperates with an external communication unit. A schematic diagram of this process is shown below. Figure 6 As shown. Reference Figure 6 , Figure 6The demonstration showcased the signal transmission paths between the "large-capacity FLASH," the MCU's internal "SDMMC read / write" and "data encapsulation" modules, the "OCTOSPI transmit" module, and the FPGA's internal "8-channel receive," "8b / 10b conversion," "IO data transmission," and "serializer." In the data export phase, the MCU first reads stored data from the large-capacity FLASH sequentially by sector or data block via the SDMMC bus through the "SDMMC read / write" module. The read data enters the MCU's internal "data encapsulation" module, where it is organized according to a predetermined frame structure. The sampled data is combined with necessary identification information to form a data format suitable for OCTOSPI bus transmission. The encapsulated data is then output through the "OCTOSPI transmit" module to the FPGA's "8-channel receive" unit. This unit receives multiple data line signals from the OCTOSPI bus in parallel and performs data alignment. The aligned data is then sent to the "8b / 10b conversion" module to perform 8b / 10b encoding, generating an encoded sequence with DC balance and clock recovery characteristics. The encoded data is transferred from the "IO data transmission" unit to the "serializer." The serializer converts the parallel LVTTL data into a high-speed serial bit stream and sends it to the external physical link at the output in the form of "LVDS" differential signals. Figure 6 The data transmission flow shown illustrates the cascading order of functional modules from the large-capacity FLASH to the LVDS physical interface, as well as the collaborative relationship between SDMMC read / write, data encapsulation, OCTOSPI transmission, 8-channel reception, 8b / 10b conversion, IO data transmission, and serializer output. The entire process ensures high bandwidth export while also taking into account link reliability and interface compatibility.

Claims

1. A signal acquisition and transmission method based on a main control unit, characterized in that, Includes the following steps: The main control unit performs frequency division processing on the received reference frequency source signal to generate a sampling clock signal and a time count signal. The sampling clock signal is output to the analog-to-digital conversion unit, and the time count signal is output to the timestamp unit inside the main control unit. The analog-to-digital conversion unit converts the analog electrical signal output by the sensor into a digital acquisition signal under the drive of the sampling clock signal; The main control unit acquires device status parameters; The main control unit uses the timestamp unit to add timestamps to the digital acquisition signal and the device status parameters based on the time counting signal, and classifies the data after adding timestamps and stores it in the first storage unit of the main control unit. When the main control unit detects that the amount of data in the first storage unit has reached a preset capacity threshold, it wakes up the second storage unit to write data, and after the writing is completed, it controls the second storage unit to enter a sleep state. The main control unit responds to the data read command, reads the stored data from the second storage unit and sends it to the logic processing unit connected to the main control unit through the multi-line serial interface. The logic processing unit performs bit-width encoding conversion on the received data and sends it to the serialization unit connected to the logic processing unit. The serialization unit converts the data into a differential signal and outputs it.

2. The signal acquisition and transmission method based on the main control unit as described in claim 1, characterized in that, The main control unit performs frequency division processing on the received reference frequency source signal to generate a sampling clock signal and a time count signal. The sampling clock signal is output to the analog-to-digital conversion unit, and the time count signal is output to the timestamp unit within the main control unit. This includes: The main control unit detects the frequency accuracy and stability of the received reference frequency source signal and generates the detection result; If the detection result indicates that the signal is normal, the internal frequency division module is initialized and the frequency division parameters are loaded from the non-volatile memory; The frequency division ratio is set based on the frequency division parameters, and the reference frequency source signal is divided based on the frequency division ratio to generate a sampling clock signal and a time counting signal. Verify the frequency stability of the sampling clock signal and the time counting signal and calibrate the phase deviation; The verified and calibrated sampling clock signal is output to the clock input pin of the analog-to-digital converter unit; The verified and calibrated time count signal is output to the counter register of the timestamp unit; If the detection result indicates an abnormal signal, the frequency division process is stopped and an error handling procedure is executed.

3. The signal acquisition and transmission method based on the main control unit as described in claim 1, characterized in that, The analog-to-digital conversion unit, driven by the sampling clock signal, converts the analog electrical signal output by the sensor into a digital acquisition signal, including: The analog-to-digital conversion unit samples the analog electrical signals output by the vibration sensor and the underwater acoustic sensor under the drive of the sampling clock signal to obtain the sampled analog electrical signals. The analog-to-digital conversion unit quantizes the sampled analog electrical signal into a digital acquisition signal through a successive approximation register; The analog-to-digital conversion unit outputs the digital acquisition signal to the main control unit.

4. The signal acquisition and transmission method based on the main control unit as described in claim 1, characterized in that, The main control unit acquires device status parameters, including: The main control unit reads battery power information through the battery management chip interface; Read the three-axis angle information through the digital compass interface; Read temperature, humidity, and air pressure data through the environmental sensor interface; The battery power information, the three-axis angle information, and the temperature, humidity, and air pressure data are integrated into the device status parameters.

5. The signal acquisition and transmission method based on the main control unit as described in claim 1, characterized in that, The main control unit uses the timestamp unit to add timestamps to the digital acquisition signal and the device status parameters based on the time counting signal, and classifies and stores the timestamped data into the first storage unit of the main control unit, including: The main control unit obtains the timestamp value from the timestamp unit based on the time counting signal; Use the timestamp value to add timestamps to the digital acquisition signal and the device status parameters; The digital acquisition signals with added timestamps and the device status parameters with added timestamps are classified into analog data and status data. The categorized simulation data classes and status data classes are formatted into a fixed storage format; The formatted simulation data class and status data class are stored in the first storage unit of the main control unit.

6. The signal acquisition and transmission method based on the main control unit as described in claim 1, characterized in that, When the main control unit detects that the data volume of the first storage unit has reached a preset capacity threshold, it wakes up the second storage unit to write data, and after the writing is completed, it controls the second storage unit to enter a sleep state, including: The main control unit monitors the current data volume of the first storage unit; Compare the current data volume with the preset capacity threshold; If the current data volume reaches the preset capacity threshold, a wake-up signal is sent to the second storage unit, and the data block in the first storage unit is transferred to the second storage unit for data writing; After the data writing is complete, a hibernation command is sent to the second storage unit.

7. The signal acquisition and transmission method based on the main control unit as described in claim 1, characterized in that, The main control unit responds to a data read command, reads the stored data from the second storage unit, and sends it to the logic processing unit connected to the main control unit via a multi-line serial interface. The logic processing unit performs bit-width encoding conversion on the received data and then sends it to the serialization unit connected to the logic processing unit. The serialization unit converts the data into a differential signal and outputs it, including: The main control unit parses the data reading instruction to determine the starting address and reading length of the target data segment, and sequentially reads the corresponding data content from the second storage unit based on the starting address; The main control unit encapsulates the data content into a multi-line serial transmission data frame according to a preset transmission format, and sends the multi-line serial transmission data frame to the logic processing unit connected to the main control unit through the multi-line serial interface. The logic processing unit performs integrity verification on the multi-line serial transmission data frame, and after the integrity verification is passed, performs bit width encoding conversion on the multi-line serial transmission data frame based on the preset bit width mapping table to obtain a data block in the target bit width format. The logic processing unit sends the target bit-width format data block to the serialization unit connected to the logic processing unit, and the serialization unit performs serialization processing on the target bit-width format data block to generate a serial transmission bit stream; The serialization unit converts the serial transmission bit stream into a differential signal and outputs it based on a differential output driving structure.

8. A signal acquisition and transmission device based on a main control unit, characterized in that, The signal acquisition and transmission device based on the main control unit includes: The frequency division control module is used by the main control unit to perform frequency division processing on the received reference frequency source signal, generate a sampling clock signal and a time count signal, and output the sampling clock signal to the analog-to-digital conversion unit and the time count signal to the timestamp unit inside the main control unit. An analog-to-digital conversion module is used by the analog-to-digital conversion unit to convert the analog electrical signal output by the sensor into a digital acquisition signal under the drive of the sampling clock signal; The device status acquisition module is used by the main control unit to acquire device status parameters; The timestamp and classification storage module is used by the main control unit to add timestamps to the digital acquisition signal and the device status parameters based on the time counting signal, classify the data after adding timestamps, and store them in the first storage unit of the main control unit. The hierarchical storage management module is used by the main control unit to wake up the second storage unit to write data when it detects that the data volume of the first storage unit has reached a preset capacity threshold, and to control the second storage unit to enter a sleep state after the writing is completed. A serial transmission processing module is used by the main control unit to respond to a data read command, read the stored data from the second storage unit and send it to the logic processing unit connected to the main control unit through a multi-line serial interface. The logic processing unit performs bit-width encoding conversion on the received data and sends it to the serialization unit connected to the logic processing unit. The serialization unit converts the data into a differential signal and outputs it.

9. A computer device, characterized in that, The computer device includes a memory, a processor, and a signal acquisition and transmission program based on a main control unit stored in the memory and executable on the processor. When the main control unit-based signal acquisition and transmission program is executed by the processor, it implements the steps of the signal acquisition and transmission method based on a main control unit as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a signal acquisition and transmission program based on a main control unit. When the main control unit-based signal acquisition and transmission program is executed by the processor, it implements the steps of the signal acquisition and transmission method based on a main control unit as described in any one of claims 1-7.

Images