Method, device, electronic device and readable storage medium for out-of-order scheduling of memory access instructions

Abstract

The present application provides a method, device, electronic device and readable storage medium for out-of-order scheduling of memory access instructions, and relates to the field of computer technology. The method includes: receiving a first memory access instruction and obtaining a first address of the first memory access instruction; obtaining a second address of a second memory access instruction from a missing state processing register; the second memory access instruction is a memory access instruction of a cache miss; if the first address and the second address are the same, the first memory access instruction is suspended in a conflict processing transmission table, and when the data accessed by the second memory access instruction is written to the second address in the missing state processing register, the first memory access instruction is awakened by the wake-up information provided by the corresponding item in the cache; if the first address and the second address are not the same, the first memory access instruction is stored in a regular memory access transmission queue, and the first memory access instruction is emitted according to the emission order of the regular memory access transmission queue. The method of the present application can avoid conflicting memory access instructions blocking other memory access instructions from entering the queue.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, electronic device and readable storage medium for out-of-order scheduling of memory access instructions. Background Art

[0002] As data processing applications have an increasing demand for memory-level parallelism, a trend in high-performance processor design is to increase the total amount of key hardware resources for maintaining concurrent memory access requests. For example, the Miss Status Handling Register (MSHR) is expanded to a larger number of items to improve the processor's concurrent memory access capability. Typical MSHR expansion methods include hierarchical grouping structures, hash search methods, etc. However, these methods only expand the upper limit of concurrent memory access requests. Whether the processor can fully utilize the expanded capacity of the MSHR to generate enough memory access requests still depends on the processor's memory access instruction scheduling capability.

[0003] In the related art, a first-in-first-out (FIFO) queue is used to store and record memory access instructions. If a memory access instruction conflict is detected, the queue is blocked until the conflicting memory access instruction is processed, and the memory access instruction will continue to be scheduled. In addition, the detection of memory access instruction conflicts in the related art includes detection in the issue queue (IQ) and detection in the MSHR. This conflict blocking queue design greatly limits the concurrency of memory access requests and cannot fully utilize the MSHR with expanded capacity. In order to reduce blocking, the memory access issue queue is split in the related art to obtain multiple memory access issue queues. Therefore, when a transmission queue is blocked due to a conflict and cannot continue to send memory access requests, one or more other transmission queues can still continue to schedule memory access instructions. Specifically, the splitting can be performed according to different functions of loading and storage, and can also be split according to priority. This method of expanding multiple transmission queues will introduce complex queue management logic, and when detecting conflicts, it is also necessary to perform full-associative searches on multiple transmission queues, which makes the capacity of each transmission queue very limited and difficult to meet the memory-level parallel requirements. In order to reduce congestion, memory access violation prediction can also be performed in the related art to detect memory access instructions that may cause violations in advance. However, since instructions predicted to violate the rules need to wait until all previous memory access instructions are executed, the effect of alleviating congestion is limited. In addition, congestion can also be reduced by speculating the design of launch and rollback in the related art, but once the speculation is wrong, the cost of rollback is often high, and the performance loss is large.

[0004] In designs where the MSHR capacity is expanded many times, for example, in designs where the MSHR is expanded to hundreds of items to support memory-level concurrency of remote memory access, in order to prevent memory access instruction scheduling from becoming a bottleneck for system performance optimization, it is necessary to design a non-blocking queue mechanism for out-of-order memory access scheduling to implement a non-blocking instruction scheduling method. Summary of the invention

[0005] The embodiments of the present application provide a method, device, electronic device and readable storage medium for out-of-order scheduling of memory access instructions to solve the problem in the prior art that, under the general trend of current high-performance processor designs to significantly increase the total amount of key hardware resources for maintaining concurrent memory access requests, there is a lack of a non-blocking queue mechanism for out-of-order scheduling of memory accesses that can fully enhance the memory access instruction scheduling capability of the processor.

[0006] In a first aspect, an embodiment of the present application provides a method for out-of-order scheduling of memory access instructions, comprising:

[0007] receiving a first memory access instruction and obtaining a first address of the first memory access instruction;

[0008] Obtaining a second address of a second memory access instruction from the miss status processing register; the second memory access instruction is a memory access instruction that is a cache miss;

[0009] If the first address and the second address are the same, suspending the first memory access instruction in the conflict processing transmission table, and waking up the first memory access instruction through the wake-up information provided by the corresponding item in the cache when the missing state processing register writes the data accessed by the second memory access instruction to the second address;

[0010] If the first address and the second address are different, the first memory access instruction is stored in a regular memory access transmission queue, and the first memory access instruction is transmitted according to the transmission order of the regular memory access transmission queue.

[0011] In a second aspect, an embodiment of the present application provides a device for out-of-order scheduling of memory access instructions, the device comprising:

[0012] A first acquisition module, used for receiving a first memory access instruction and acquiring a first address of the first memory access instruction;

[0013] A second acquisition module acquires a second address of a second memory access instruction from the missing state processing register; the second memory access instruction is a memory access instruction of a cache miss;

[0014] a wake-up module, configured to suspend the first memory access instruction in a conflict processing transmission table if the first address and the second address are the same, and wake up the first memory access instruction when the missing state processing register writes the data accessed by the second memory access instruction into the second address;

[0015] The first storage module is used for storing the first memory access instruction into a regular memory access transmission queue if the first address is different from the second address, and transmitting the first memory access instruction according to the transmission order of the regular memory access transmission queue.

[0016] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor;

[0017] a memory for storing processor-executable instructions;

[0018] The processor is configured to execute instructions to implement the method of the first aspect.

[0019] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0020] In the embodiment of the present application, if it is detected that the first memory access instruction has a conflict, it will be hung in the conflict processing emission table, and will be awakened after the request data is ready; if it is detected that the first address and the second address are not the same, it means that there is no conflict in the first memory access instruction, and it will be stored in the conventional memory access emission queue, and will be emitted according to the emission order of the conventional emission queue. Based on the method of this embodiment, even if the memory access instruction is a memory access instruction with a conflict, it will not block other memory access instructions from entering the queue, so that subsequent memory access requests that are not related to the conflicting memory access instruction can continue to be sent without being affected by the conflicting memory access instruction. In addition, the conflict processing does not need to search the conventional memory access emission queue, so that the conventional memory access emission queue can be expanded to a large number of items, and then cooperate with the large-capacity MSHR to support memory-level concurrency. This embodiment can greatly reduce the blocking of memory access requests, solves the design of conflict blocking queuing in the relevant technology, the problem that the conflicting memory access instruction will block other memory access instructions from entering the queue, and the problem that it is difficult to expand the emission queue capacity by searching the emission queue, thereby limiting the scheduling ability of the memory access instruction.

[0021] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 This is a schematic diagram of an application scenario of a method for out-of-order scheduling of memory access instructions provided in an embodiment of the present application;

[0024] Figure 2 It is a flowchart of the steps of a method for out-of-order scheduling of memory access instructions provided by an embodiment of the present application;

[0025] Figure 3 It is a flowchart of another method for out-of-order scheduling of memory access instructions provided by an embodiment of the present application;

[0026] Figure 4 This is a flowchart of the steps of another out-of-order scheduling method for memory access instructions provided by an embodiment of the present application;

[0027] Figure 5 It is a structural diagram of a memory access instruction out-of-order scheduling system provided by an embodiment of the present application;

[0028] Figure 6 It is a block diagram of a memory access instruction out-of-order scheduling device provided by an embodiment of the present invention;

[0029] Figure 7 is a block diagram of an electronic device provided by an embodiment of the present invention;

[0030] Figure 8 is a block diagram of another electronic device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0033] Figure 1 This is a schematic diagram of an application scenario of a method for out-of-order scheduling of memory access instructions provided in an embodiment of the present application, referring to Figure 1 The application scenario includes at least a non-blocking memory access scheduling queue and a cache, wherein the non-blocking memory access scheduling queue includes at least a regular memory access transmission queue and a conflict handling transmission table; the cache includes at least MSHR.

[0034] When a memory access instruction is received, the memory access instruction is stored in a non-blocking memory access scheduling queue, and then the memory access instruction in the non-blocking memory access scheduling queue is transmitted to the cache.

[0035] The present embodiment provides a method for out-of-order scheduling of memory access instructions, receiving a first memory access instruction and obtaining a first address of the first memory access instruction; obtaining a second address of a second memory access instruction from a missing status processing register; the second memory access instruction is a memory access instruction that does not hit the cache; if the first address and the second address are the same, the first memory access instruction is suspended in a conflict processing transmission table, and when the missing status processing register writes the data accessed by the second memory access instruction to the second address, the first memory access instruction is awakened by the wake-up information provided by the corresponding item in the cache; if the first address and the second address are not the same, the first memory access instruction is stored in a regular memory access transmission queue, and the first memory access instruction is transmitted according to the transmission order of the regular memory access transmission queue. By storing conflicting memory access instructions and non-conflicting memory access instructions into different emission queues, even if the memory access instruction is a conflicting memory access instruction, it will not block other memory access instructions from entering the queue. Therefore, subsequent memory access requests that are not related to the conflicting memory access instruction can continue to be sent without being affected by the conflicting memory access instruction, thereby greatly reducing the blocking of memory access requests, solving the problem of conflict blocking queuing in the related technology, and the conflicting memory access instruction will block other memory access instructions from entering the queue. In addition, for each item in the conflict processing emission table, the corresponding item in the cache is used to provide wake-up information when waking up, and there is no need to search in the emission table, so that the capacity of the emission table can be designed to be very large; finally, conflict detection does not need to search the regular memory access request emission queue, so the capacity of the regular memory access request emission queue can be designed to be very large, so as to make full use of the extended capacity MSHR to generate enough memory access requests, support memory-level concurrency, and improve the processor's out-of-order scheduling capability of memory access instructions.

[0036] The instruction scheduling method provided in the embodiment of the present application is described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0037] Figure 2 is a flowchart of a method for out-of-order scheduling of memory access instructions provided by an embodiment of the present application, such as Figure 2 As shown, the method may include:

[0038] Step 101: Receive a first memory access instruction and obtain a first address of the first memory access instruction.

[0039] Specifically, the first address of the first memory access instruction is an address of a cache that the first memory access instruction needs to access.

[0040] The first memory access instruction may be a read instruction or a write instruction.

[0041] Step 102: Obtain a second address of a second memory access instruction from a missing status processing register.

[0042] Specifically, the second memory access instruction is a memory access instruction that is a cache miss;

[0043] In high-performance processor design, in order to prevent cache misses from blocking the processor's instruction execution, a miss status handling register can be introduced to implement non-blocking cache. Furthermore, the MSHR is used to track and record the information of the missing buffer blocks, thereby allowing the processor to issue new memory access requests even when the cache misses.

[0044] The MSHR records the second address of the second memory access instruction, wherein the second address may be one or more.

[0045] Step 103, if the first address and the second address are the same, the first memory access instruction is suspended in the conflict processing transmission table, and when the missing status processing register writes the data accessed by the second memory access instruction to the second address, the first memory access instruction is awakened through the wake-up information provided by the corresponding item in the cache.

[0046] If the first address and the second address are the same, it is determined that there is a conflict between the first memory access instruction and the second memory access instruction. Furthermore, there may be multiple second addresses recorded in the MSHR. When there are multiple second addresses, if the first address is the same as any of the second addresses, it is determined that the first address and the second address are the same, and there is a conflict between the first memory access instruction and the second memory access instruction corresponding to the second address.

[0047] For example, the conflict handling emission table is designed to be out-of-order scheduling, which greatly reduces the blocking of memory access requests. Specifically, when multiple conflicting memory access instructions are suspended in the conflict handling emission table, the memory access instructions are not awakened according to the order in which the memory access instructions are suspended in the conflict handling emission table, but when the data in the MSHR item corresponding to the memory access instruction is ready, the memory access instruction is awakened.

[0048] The first memory access instruction has a first index number, and the cache stores the first index number of the first memory access instruction. The corresponding wake-up information provided in the cache includes the first index number of the first memory access instruction stored in the cache. The first memory access instruction is awakened by the first index number of the first memory access instruction in the cache.

[0049] Step 104: if the first address and the second address are not the same, the first memory access instruction is stored in a regular memory access transmit queue, and the first memory access instruction is transmitted according to the transmission order of the regular memory access transmit queue.

[0050] If the first address and the second address are not the same, it is determined that there is no conflict between the first instruction and the second instruction. Further, there may be multiple second addresses recorded in the MSHR. When there are multiple second addresses, if the first address and all the second addresses are different, it is determined that the first address and the second address are different, and there is no conflict between the first memory access instruction and the second memory access instruction.

[0051] For example, the conventional memory access transmission queue is implemented using a first-in-first-out (FIFO) queue to achieve order preservation of the conventional memory access transmission queue. Specifically, when multiple memory access instructions are recorded in the conventional memory access transmission queue, each memory access instruction is transmitted in the order in which the memory access instructions are written. Further, in the conventional memory access transmission queue, the memory access instruction written first is transmitted first, and the memory access instruction written later is transmitted later.

[0052] After the first memory access instruction is stored in the regular memory access issue queue, the first memory access instruction is issued to the cache after the memory access instruction stored in the regular memory access issue queue before the first memory access instruction is issued.

[0053] The conventional memory access transmission queue is implemented using FIFO, which can be expanded to multiple items with large capacity, and then combined with large-capacity MSHR to support memory-level concurrency.

[0054] In summary, in the embodiment of the present application, the second address of the second memory access instruction with a cache miss is recorded in the MSHR. When the first memory access instruction is received, if the first address of the first memory access instruction is detected to be the same as the second address of the second memory access instruction recorded in the MSHR, it indicates that the first memory access instruction is a conflicting memory access instruction with a conflict, and it is hung in the conflict processing transmission table, and waits for the MSHR to write the data accessed by the second memory access instruction to the second address before waking up. That is, if it is detected that the first memory access instruction has a conflict, it is hung in the conflict processing transmission table, and wakes up again after the request data is ready. If it is detected that the first address and the second address are not the same, it indicates that the first memory access instruction is a non-conflicting memory access instruction without a conflict, and it is stored in a regular memory access transmission queue and transmitted according to the transmission order of the regular transmission queue. In this embodiment, the memory access instructions with conflicts and those without conflicts are recorded separately. Even if the memory access instruction is a memory access instruction with conflicts, it will not block other memory access instructions from entering the queue. Therefore, subsequent memory access requests that are not related to the conflicting memory access instruction can continue to be sent without being affected by the conflicting memory access instruction. In addition, in the related art, when there is a conflicting memory access request, it is necessary to search each conventional memory access transmission queue, while in the present embodiment, the conflict handling does not need to search the conventional memory access transmission queue, so that the conventional memory access transmission queue can be expanded to a large number of items, and then cooperate with the large-capacity MSHR to support memory-level concurrency; the first memory access instruction is awakened by the wake-up information provided by the corresponding item in the cache, which can avoid searching the conflict handling transmission table when waking up the first memory access instruction, thereby, the capacity of the conflict handling transmission table can be set very large. That is, based on the method of the present embodiment, the capacity of the conventional memory access transmission queue and the conflict handling transmission table can be set very large, which improves the scheduling ability of the memory access instruction. The present embodiment can greatly reduce the blocking of the memory access request, solves the memory access instruction scheduling method in the related art, the conflicting memory access instruction will block other memory access instructions from entering the queue, and needs to search the transmission queue, resulting in difficulty in expanding the transmission queue capacity, thereby limiting the scheduling ability of the memory access instruction.

[0055] Figure 3 is a flowchart of the specific steps of an instruction scheduling method provided in an embodiment of the present application, such as Figure 3 The method may include:

[0056] Step 201: Receive a first memory access instruction and obtain a first address of the first memory access instruction.

[0057] The method of this step has been described in the aforementioned step 101 and will not be repeated here.

[0058] Step 202: If the first address and the second address are the same, a first index number is assigned to the first memory access instruction, and the first index number is stored in the cache.

[0059] The first address and the second address are the same, indicating that the first memory access instruction is a conflicting memory access instruction with a conflict, and the free item index number can be obtained from the first-in-first-out free item index queue and assigned to the first memory access instruction as the first index number. The conflict handling emission table includes at least one instruction item, and the free item index number is the index number corresponding to the instruction item that has not yet stored the conflicting memory access instruction.

[0060] Furthermore, the first memory access instruction is suspended in the instruction item corresponding to the first index number in the conflict handling emission table, and the first index number is stored in the cache.

[0061] For example, storing the first index number in the cache in step 202 may include the following sub-steps:

[0062] Sub-step 2021, obtaining the dependency relationship between the first memory access instructions.

[0063] The dependency relationship includes strong dependency or weak dependency, that is, the dependency relationship includes strong dependency between first memory access instructions or weak dependency between first memory access instructions.

[0064] Furthermore, when the dependency relationship between the first memory access instructions is weak, it means that there are fewer conflicting first memory access instructions; when the dependency relationship between the first memory access instructions is strong, it means that there are more conflicting first memory access instructions.

[0065] Sub-step 2022, according to the dependency relationship between the first memory access instructions and the correspondence between the preset dependency relationship and the index number storage strategy, obtain the target index number storage strategy corresponding to the dependency relationship.

[0066] For example, the MSHR may include multiple pending items, where the pending items are used to record the second addresses of the memory access instructions that miss the cache, and may also record the index numbers of the conflicting memory access instructions.

[0067] For example, when the dependency between the first memory access instructions is a weak dependency, the target index number storage strategy is: store the first index numbers of all first memory access instructions at the same address into the pending items recorded in the MSHR with the same second address and first address.

[0068] For example, when the dependency between the first memory access instructions is a strong dependency, that is, when multiple conflicting items may be suspended in the conflict handling transmission table in a short period of time, the target index number storage strategy is: the first index numbers of multiple first memory access instructions with the same address are stored in the index space maintained in the form of a linked list in the cache.

[0069] Sub-step 2023, storing the first index number in the cache according to the target index number storage strategy.

[0070] The first index number is stored in MSHR. Later, after the cache is ready to access the memory data, the first memory access instruction can be directly determined from the conflict handling transmission table based on the first index number in MSHR, without the need to perform a full associative search on the conflict handling transmission table, thereby supporting large-capacity and multiple expansions of the conflict handling transmission table.

[0071] Step 203: Suspend the first memory access instruction in the conflict handling transmission table.

[0072] The method of this step has been described in the aforementioned step 103 and will not be repeated here.

[0073] Step 204: determine and wake up a first memory access instruction from at least one conflicting memory access instruction in the conflict handling transmission table according to the first index number stored in the cache.

[0074] The address of the conflicting memory access instruction is the same as the second address, and each conflicting memory access instruction has a corresponding index number.

[0075] According to the method of step 202 to step 204, when a conflicting memory access occurs, the first memory access instruction can enter the conflict processing transmission table and suspend, waiting to be awakened after the requested data is ready. Thus, the conflict will not block the queuing. In the subsequent processing process, memory access requests that are not related to the first memory access instruction can continue to be sent without being affected by the conflict.

[0076] When the first memory access instruction with a conflict is suspended, the cache provides an index number when it is awakened. This process does not require searching the conflict transmission table, thereby allowing the number of entries in the conflict transmission table to be greatly expanded.

[0077] Based on the method of this embodiment, the regular memory access queue can be made very large, because in this embodiment, based on the sub-queues (including the regular memory access transmission queue and the conflict handling transmission table) and the conflict suspension wake-up mechanism, it is not necessary to fully associatively search the regular memory access transmission queue. Therefore, enough memory access requests can be sent from the regular transmission queue to the cache, thereby making full use of the blank items of the large-capacity MSHR.

[0078] Step 205: If the first address and the second address are not the same, the first memory access instruction is stored in a regular memory access transmission queue, and the first memory access instruction is transmitted according to the transmission order of the regular memory access transmission queue.

[0079] The method of this step has been described in the aforementioned step 104 and will not be repeated here.

[0080] In this embodiment, if the first memory access instruction is a conflicting memory access instruction whose address is the same as the second address in the MSHR, the first memory access instruction is suspended in the conflict handling transmission table, and after the subsequent MSHR is ready for memory access data, the first memory access instruction is directly determined and awakened from the conflict handling transmission table according to the first index number provided by the cache. That is, the suspended first memory access instruction is awakened by the first index number provided by the cache, and there is no need to search the conflict handling transmission table, thereby, the number of items in the conflict handling transmission table can be expanded to a large extent. In addition, this embodiment records the memory access instructions with and without conflicts in the conflict handling transmission table and the conventional memory access transmission queue respectively, even if the memory access instruction is a memory access instruction with conflicts, it will not block other memory access instructions from entering the queue, and can greatly reduce the blocking of memory access requests, solving the design of conflict blocking entry into the queue in the related art, and the problem that the conflicting memory access instruction will block other memory access instructions from entering the queue.

[0081] In one embodiment, the conflict handling emission table has at least one instruction item, the instruction item includes at least one free item in which the conflicting memory access instruction is not stored, and each free item has a corresponding index number. In addition, the instruction item also includes an instruction item in which the conflicting memory access instruction is stored. Correspondingly, assigning the first index number to the first memory access instruction in step 202 may include the following sub-steps:

[0082] Sub-step 2024, obtaining the idle item index queue.

[0083] The free item index queue is used to record the index number of the free item.

[0084] For example, the idle item index queue may be a first-in-first-out queue, and when the idle item index queue is initialized, all idle index numbers of the conflict handling transmission table are filled in the idle item index queue. Furthermore, the idle item index queue may also record the count value of the idle item index number.

[0085] For example, the conflict handling transmission table has 16 items, each item has a corresponding index number, and the index numbers are 0, 1, 2...15 in sequence. When initializing the available item index queue, the 16 available item index numbers 0 to 15 are filled in it; among them, the count value of the free item index number is 16.

[0086] Sub-step 2025, obtaining a first index number from the index numbers of the free item index queue, and assigning the first index number to a first memory access instruction.

[0087] For example, the free item index queue allocates index numbers to memory access instructions in a first-in-first-out manner. When a first memory access instruction is received, the index number at the head of the free item index queue is used as the first index number and allocated to the first memory access instruction.

[0088] In this embodiment, the first index number is obtained from the free item index queue for recording the free item index number, and the first index number is assigned to the first memory access instruction. Based on this embodiment, it is not necessary to search the index number of the free item from the conflict handling transmission table by a fully associative search method, and assign it as the first index number to the first memory access instruction. This embodiment avoids the fully associative search of the conflict handling transmission table, and thus can support large-capacity and multiple extensions of the conflict handling transmission table. At the same time, conflict handling is separated from the conventional memory access request transmission queue, and also avoids the fully associative search of the conventional memory access request transmission queue by conflict detection, and thus can support large-capacity and multiple extensions of the conventional memory access request transmission queue.

[0089] In one embodiment, step 2022 may include the following sub-steps:

[0090] Sub-step A1, according to the order in which the index numbers of the free items are stored in the free item index queue, obtain the first index number from the index numbers recorded in the free item index queue.

[0091] Specifically, the first index number is obtained from the index numbers recorded in the free item index queue in a first-in-first-out manner.

[0092] For example, during the processing, the index numbers of the current records in the free item index queue are 1, 3, 2, 5, 15, and the count value of the free item index number is 5. The head index number is 1, and after receiving a first memory access instruction, the head index number 1 is assigned to the first memory access instruction.

[0093] Further, after the head index number 1 is assigned to the first memory access instruction, the index number of the current record in the free item index queue is updated to 3, 2, 5, 15, and the count value of the free item index number is 4. At this time, the head index number is 3, and after receiving a new first memory access instruction, the head index number 3 is assigned to the first memory access instruction.

[0094] Correspondingly, after the first memory access instruction is awakened in step 204, the following further includes:

[0095] Step 206, issuing a first memory access instruction.

[0096] Specifically, the first memory access instruction is sent to the cache, and a read operation or a write operation is performed on the first address.

[0097] After the first memory access instruction is issued, the first memory access instruction is deleted from the conflict processing issuance list, and the instruction item previously occupied by the first memory access instruction in the conflict instruction issuance table becomes an idle item in which no conflicting memory access instruction is stored.

[0098] Step 207: store the first index number of the first memory access instruction into the free item index queue.

[0099] After the first memory access instruction is issued, the instruction item previously occupied by the first memory access instruction in the conflicting instruction issuance table becomes an idle item in which no conflicting memory access instructions are stored. Correspondingly, the first index number of the first memory access instruction becomes the index number of the idle item.

[0100] For example, the free item index queue adopts a first-in first-out mechanism to record the index number of the free item released by the conflict handling transmission table. In addition, the free item index queue records the count value of the free item index number.

[0101] Furthermore, when the conflict handling transmission table transmits a conflicting memory access instruction, the index number of the conflicting memory access instruction is stored in the free item index queue according to the first-in first-out method, and the count value of the free item index number is increased by one.

[0102] For example, the index numbers of the current records in the free item index queue are 3, 2, 5, 15, and the count value of the free item index number is 4; the first index number of the first memory access instruction is 8. After the first memory access instruction is dequeued, the first index number 8 is stored in the free item index queue, and the index numbers of the current records in the free item index queue are updated to 3, 2, 5, 15, 8; the count value of the free item index number is updated to 5.

[0103] The free item index queue can be used to quickly allocate empty items in the conflict handling transmission table. Specifically, by maintaining a free item index queue, the allocation circuit for allocating index numbers can quickly find empty items in the conflict handling transmission table to support capacity expansion of the conflict transmission table.

[0104] In one embodiment, if the dependency between memory access requests is weak, the conflicts between data are relatively few. In this case, the missing state processing register includes multiple items to be processed, and each item to be processed corresponds to one address; when there are multiple first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency between the first memory access instructions is weak, storing the first index number in the cache in step 202 may include the following sub-steps:

[0105] Sub-step 2026, recording the multiple first index numbers in the first item to be processed.

[0106] The address corresponding to the first item to be processed is the same as the first address, and the first index number and the first memory access instruction correspond one to one.

[0107] Specifically, the first index numbers of the first memory access addresses with the same first addresses are recorded in the same first item to be processed.

[0108] In step 204, waking up the first memory access instruction through the wake-up information provided by the corresponding item in the cache includes the following sub-steps:

[0109] Sub-step 2041, simultaneously waking up multiple first memory access instructions corresponding to multiple first index numbers.

[0110] Specifically, according to the multiple first index numbers, multiple first memory access instructions are determined from at least one conflicting memory access instruction in the conflict processing transmission table, and the multiple first memory access instructions are awakened simultaneously.

[0111] For example, after waking up a plurality of first memory access instructions at the same time, the plurality of first memory access instructions are transmitted to the cache in a strictly order-preserving manner.

[0112] For example, when there are multiple first memory access instructions and the first addresses of the multiple first memory access instructions are the same, waking up the first memory access instruction through the wake-up information provided by the corresponding item in the cache in step 204 may further include the following sub-steps:

[0113] Sub-step 2042, waking up the multiple first memory access instructions in sequence according to the order in which the multiple first memory access instructions are suspended in the conflict handling transmission table.

[0114] Based on the method of this step, multiple awakened first memory access instructions can be transmitted to the cache in a strictly order-preserving manner.

[0115] In one embodiment, MSHR includes multiple pending items, one pending item corresponds to one address, and each pending item records the total number of same-address conflicting memory access instructions and the index number of the last same-address conflicting memory access instruction.

[0116] The same-address conflicting memory access instruction is a conflicting memory access instruction in the conflict processing emission table, whose address is the same as the address corresponding to the item to be processed;

[0117] In the case where there are multiple first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency relationship between the first memory access instructions is a strong dependency, storing the first index number into the cache in step 202 may include the following sub-steps:

[0118] Sub-step 2027, adding one to the total number of items to obtain a new total number of items.

[0119] Specifically, after receiving a first memory access instruction, the total number of items is incremented by one to obtain a new total number of items.

[0120] For example, one pending item corresponds to one address, and one pending item may include multiple memory access instructions with the same address. The total number of items with index numbers in the pending items corresponding to the first address is incremented by one to obtain an updated total number of items.

[0121] Sub-step 2028, write the first index number of the currently received first memory access instruction into the address corresponding to the index number of the last memory access instruction with the same address conflict in the second to-be-processed item record.

[0122] The address corresponding to the second item to be processed is the same as the first address.

[0123] Specifically, the last same-address conflicting memory access instruction is the last memory access instruction suspended in the conflict handling emission table among multiple same-address conflicting memory access instructions in the conflict handling emission table.

[0124] Each to-be-processed item is also used to record the index number of the first memory access instruction with the same address conflict; when there are multiple first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency relationship between the first memory access instructions is a strong dependency, waking up the first memory access instruction in step 204 may include the following sub-steps:

[0125] Sub-step 2042, obtaining the first index number from the address corresponding to the index number of the first same-address conflicting memory access instruction recorded in the second item to be processed.

[0126] Specifically, the first same-address conflicting memory access instruction is the first memory access instruction suspended in the conflict handling emission table among multiple same-address conflicting memory access instructions in the conflict handling emission table.

[0127] Sub-step 2043, according to the first index number, determine and wake up the first memory access instruction corresponding to the first index number from at least one conflicting memory access instruction in the conflict handling transmission table.

[0128] The method of this step can refer to the description of the aforementioned step 204, which will not be repeated here.

[0129] Sub-step 2044, subtract one from the total number of items to obtain a new total number of items.

[0130] After a first memory access instruction is awakened, the number of memory access instructions in the conflict handling transmission table suspended in the MSHR is reduced by one, so the total number of entries needs to be reduced by one to update the total number of entries.

[0131] Sub-step 2045, when the new total number of entries is equal to zero, the index numbers of the first and last conflicting memory access instructions recorded in the missing status processing register are set to zero.

[0132] When the new total number of entries is equal to zero, it means that all the first memory access instructions in the conflict handling emission table are awakened. At this time, the index numbers of the first and last conflicting memory access instructions need to be set to zero.

[0133] Furthermore, when the new total number of entries is not equal to zero, it indicates that the memory access instruction in the conflict handling emission table suspended by MSHR has not been fully awakened, and sub-steps 2042 to 2044 can be executed in a loop until the new total number of entries is equal to zero.

[0134] When there are multiple conflicting memory access instructions recorded in the conflict handling transmission table, the selection circuit can support reorder transmission. Furthermore, when the same MSHR is suspended in the conflict handling transmission table for multiple items, these memory access requests need to be transmitted in a strict order-preserving manner after being awakened; conflicting memory access instructions corresponding to different MSHR items can be transmitted in a disorderly manner. Using different transmission methods in different situations can make the design of the selection circuit more flexible.

[0135] Furthermore, the conflict handling transmission table in the present application supports out-of-order transmission, so the wake-up circuit used to wake up the conflicting memory access instructions needs to add an order-preserving mechanism to ensure that the memory access requests suspended by the same MSHR are strictly transmitted in order.

[0136] For example, the cache can record and provide the wake-up sequence. This method is simple to implement, but it is only suitable for application scenarios with relatively few memory access conflicts.

[0137] For another example, an index space can be maintained in the form of a linked list. Based on the sequential nature of the linked list itself, strict order preservation can be achieved for memory access requests pending on the same MSHR. This method will not result in insufficient index numbers recorded in the MSHR, leading to blocking the issuance of memory access instructions. Based on this method, the large capacity expanded by the conflict handling issuance table can be fully utilized.

[0138] Corresponding, refer to Figure 4 , after the first memory access instruction is awakened in step 204, the following steps are also included:

[0139] Step 208, when there are non-conflicting memory access instructions to be issued in the regular memory access issue queue, the first memory access instruction after wake-up is issued first, and then the non-conflicting memory access instruction to be issued is issued.

[0140] For example, the priority of the conflict handling transmission table is higher than that of the regular memory access transmission queue, because the memory access request of the conflict handling transmission table is waiting for the request data of MSHR to be prepared and has been suspended in the conflict handling transmission table for a period of time. When there are non-conflicting memory access instructions to be transmitted in the regular memory access transmission queue, the first memory access instruction after awakening is first transmitted to the cache, and then the non-conflicting memory access instructions to be transmitted are transmitted to the cache, so that the conflicting memory access instructions in the conflict handling transmission table can be transmitted as early as possible to reduce the probability of conflict blocking.

[0141] This embodiment also provides a memory access instruction out-of-order scheduling system that can implement the above instruction scheduling method, referring to Figure 5 , the system includes a non-blocking memory access scheduling queue and a cache.

[0142] The non-blocking memory access scheduling queue includes a regular memory access transmission queue, a conflict handling transmission table, an allocation circuit, a selection circuit, a wake-up circuit, and a multiplexer (MUX); the cache includes a data array, a flag array, and a missing status processing register. Figure 5 The memory access instruction in is the first memory access instruction in the aforementioned embodiment.

[0143] When receiving a memory access instruction, if a conflict is detected, the entry into the queue is not blocked, but the memory access instruction is suspended in the conflict handling transmission table. When the wake-up condition is met, the corresponding item in the cache provides wake-up information, and the suspended memory access instruction is awakened according to the wake-up information. The memory access instruction with a conflict is suspended in the conflict handling transmission table. Therefore, based on the method of this embodiment, it is not necessary to search for the conflicting memory access instruction in the regular memory access transmission queue. Therefore, the capacity of the regular memory access transmission queue can be set very large, and the MSHR with an extended capacity can be fully utilized to generate sufficient memory access requests to support memory-level concurrency.

[0144] Specifically, refer to Figure 5 The conflict detection module obtains the first address of the memory access instruction, and performs conflict detection on the memory access instruction according to the first address of the memory access instruction and the second address recorded in the MSHR, wherein the second address is the address of the memory access instruction that is not cached.

[0145] If there is no memory access conflict, the memory access instruction is sent to the regular memory access transmission queue; if there is a memory access conflict, the memory access instruction is sent to the conflict handling transmission table and suspended. In the related art, if there is a conflicting memory access instruction in the transmission queue, the transmission of the memory access instruction will be blocked regardless of whether the transmission queue is filled with data. However, based on the memory access instruction scheduling mechanism of this embodiment, the transmission of the memory access instruction will be blocked only when the regular memory access transmission queue and the conflict handling transmission table are full of data. Therefore, based on the memory access instruction scheduling mechanism of this embodiment, the blocking of memory access requests can be greatly reduced.

[0146] For example, the conventional memory access transmission queue is implemented using a simple first-in-first-out queue, and the conflict handling transmission surface is designed for out-of-order scheduling.

[0147] When a memory access conflict is detected and a memory access instruction is queued, the dispatch circuit supports finding an empty entry. The memory access request in the conflict handling transmit table is awakened only when the missing data recorded in the MSHR of the cache is ready.

[0148] Further, in this embodiment, the memory access request in the conflict processing transmission table is awakened by the wake-up information provided by the cache, without searching the conflict processing transmission table and the regular memory access request transmission queue in a fully associative manner. When the memory access queue is dequeued, the selection circuit supports reordering transmission. The multiplexer selects the memory access instruction from the non-conflicting memory access instructions in the regular memory access transmission queue and the conflicting memory access instructions in the conflict processing transmission table, and transmits it to the cache.

[0149] The selection circuit does not strictly require order preservation, but only requires strict order preservation for the memory access requests pending by the same MSHR, so that the design of the selection circuit can be more flexible. Among them, the addresses of the memory access requests pending by the same MSHR are the same.

[0150] The regular memory access transmission queue is implemented with a simple first-in-first-out queue, which can achieve the order preservation of the regular memory access transmission queue. When performing conflict detection on memory access instructions, it is only necessary to check in the MSHR, and the regular memory access transmission queue is not checked. Therefore, the capacity of the regular memory access transmission queue can be greatly expanded, thereby meeting the need to provide sufficient memory access requests for the MSHR with expanded capacity.

[0151] based on Figure 5 In the instruction scheduling mechanism shown, a conventional memory access issue queue may send a memory access instruction with the same address as an outstanding request recorded in the MSHR to the cache, and the cache needs to be designed to support merging and eliminating memory access requests with the same address.

[0152] The conflict handling emission table only stores memory access instructions that conflict with the incomplete memory access request recorded in MSHR. The conflicting memory access instruction enters the conflict handling emission table and is suspended, and wakes up again after waiting for the incomplete memory access request recorded in MSHR to obtain valid data.

[0153] For memory-intensive data processing applications, the dependencies between memory requests are usually weak, and conflicts between data are usually rare. Therefore, the number of entries in the conflict handling transmission table does not need to be greatly expanded to be sufficient to support the expanded capacity MSHR.

[0154] For memory-intensive or non-memory-intensive data processing applications, when there are many data conflicts, it is necessary to support the capacity expansion of the conflict handling emission table. To support the capacity expansion of the conflict handling emission table, it is necessary to allocate circuits that can quickly find empty items in the conflict handling emission table.

[0155] For example, a first-in-first-out available item index queue can be maintained, and when the available item index queue is initialized, all available item index numbers of the conflict handling transmission table are automatically filled, and the available index number count value is loaded. The available item index queue is the idle item index queue in the aforementioned embodiment, and the available item index number is the index number of the idle item in the instruction item of the conflict handling transmission table that has not yet stored the conflicting memory access instruction.

[0156] When a memory access request is queued in the conflict handling transmission table, the index number at the head of the available item index queue is assigned to the queued memory access request, and the count value of the available item index queue is reduced by 1. When a memory access request is dequeued from the conflict handling transmission table, the index number of the dequeued memory access request is recorded in the available item index queue, and the count value of the available item index queue is increased by 1.

[0157] Based on the available item index queue, the allocation circuit can quickly find empty items. By introducing the available item index queue, the allocation circuit avoids the full associative search of the conflict handling emission table, thereby supporting the large-capacity multi-item expansion of the conflict handling emission table.

[0158] Furthermore, in order to support the capacity expansion of the conflict handling transmission table, the wake-up circuit is required to support a wake-up mechanism without searching the conflict handling transmission table. For example, each time the second address in the MSHR is searched, when a conflict in the memory access instruction is detected according to the second address, an index information table is maintained by the cache to record the index number assigned by the allocation circuit to the current conflicting instruction, so that after the MSHR obtains valid data, the index number can be directly passed to the wake-up circuit to wake up the corresponding item suspended in the conflict handling transmission table.

[0159] Since the same MSHR may have multiple items suspended in the conflict handling transmission table, it is necessary to design the index information table according to the memory access characteristics of the data processing application to avoid queue blocking as much as possible. Specifically, the index information table is designed according to the correlation between the memory access requests of the data processing application, and the correlation between the memory access requests includes strong correlation or weak correlation.

[0160] In this embodiment, the conflict handling transmission surface is designed for out-of-order scheduling of memory access. Since the conflict handling transmission surface is designed for out-of-order scheduling of memory access, it is necessary to select a circuit to support reorder transmission. There are many designs of reorder buffer (ROB), which are not limited here. For example, the order in which the memory access requests are queued can be reordered.

[0161] Among them, the addresses of the memory access requests suspended by different MSHR items are different. There is no correlation between these memory access requests, and they can be processed out of order when reordered. However, due to the same MSHR, multiple memory access requests may be suspended in the conflict handling transmission table. These memory access requests need to be strictly sequenced when they are transmitted after being awakened.

[0162] The multiplexer (MUX) selects memory access instructions from the regular memory access transmission queue and the conflict handling transmission table and transmits them to the cache. For example, the conflict handling transmission table can be set to a high priority, the regular memory access transmission queue can be set to a low priority, and the MUX preferentially transmits the memory access instructions in the conflict handling transmission table. Because the memory access request in the conflict handling transmission table is waiting for the request data of the MSHR to be ready, it has been suspended in the conflict handling transmission table for a period of time, and transmitting it as soon as possible can reduce the probability of conflict blocking.

[0163] Furthermore, an anti-starvation mechanism can be added to prevent the regular memory access transmission queue from being blocked for a long time.

[0164] Aiming at improving the memory access instruction scheduling capability to support application scenarios of memory-level concurrency, the non-blocking memory access scheduling queue includes a regular memory access emission queue, a conflict handling emission table, an allocation circuit, a selection circuit and a multiplexer.

[0165] Reference Figure 5 , the cache needs to maintain the wake-up information, and the wake-up circuit processes the memory access instruction in the transmission table according to the wake-up information. The following is a further exemplary description of the method of telling the cache to maintain the wake-up information in combination with two specific embodiments.

[0166] In one embodiment, the index number of the pending item in the conflict handling transmission table can be recorded in the MSHR of the cache. If the conflict handling transmission table is large, for example, the conflict handling transmission table has 64 items, then 6 bits are required to record an index number. The number of items in the MSHR is usually large, so the number of pending items that can be recorded in the MSHR will be small. Because if the number of MSHR items is large and the number of pending items recorded in the MSHR is also large, the hardware requirements for the MSHR are relatively high, resulting in a large cache overhead. For example, the index number that can be recorded in the MSHR is 2 to 3 items.

[0167] However, if the same address is accessed more than three times within the request window, there will be no recordable index number location in the MSHR, which will block the entire memory access instruction sending, which will waste the large capacity expanded by the conflict handling transmission table.

[0168] Therefore, the method of this embodiment is suitable for scenarios where conflicts between memory access request data of data processing applications are relatively rare.

[0169] Based on the method of this embodiment, each MSHR records the index numbers of all the conflict handling transmission tables that are suspended, for example, the index numbers are 2 to 3. The memory access requests corresponding to the 2 to 3 index numbers can be woken up at the same time. The wake-up circuit design based on this wake-up mechanism is simple. For example, the wake-up circuit design can be implemented through a hardware bitmap.

[0170] In another embodiment, there is an application scenario where some memory access addresses are frequently accessed. When the capacity of the expanded MSHR is large, only the total number of memory access instructions a in the pending conflict handling emission table and the index numbers of the first memory access instruction b and the last memory access instruction c in the conflict handling emission table can be recorded in the MSHR.

[0171] For example, the conflict handling emission table has 64 items, 7 bits are required to record the total number of items a, and 6×2=12 bits are required to record the index numbers of the memory access instructions of the first and last items.

[0172] Furthermore, after the above parameters are recorded in the MSHR, an index space is maintained in the form of a linked list, and the number of its entries is the same as the number of entries in the conflict handling transmission table.

[0173] Specifically, when detecting a memory access instruction conflict, if the current MSHR item detects a conflict, the total number of memory access instruction items a in the MSHR is increased by 1, and the index space is addressed according to the last memory access instruction c, and the index number d of the conflict processing emission table generated by the allocation circuit is written at the address, and then the parameter d is filled in the position of the last memory access instruction c in the MSHR to update the index number of the last item.

[0174] When MSHR obtains valid data and prepares to wake up the suspended memory access requests, it first records the total number of memory access instructions a and uses it as the initial value of the counter for the number of wake-up items. It then addresses the index space according to the first memory access instruction b. Each time a new index number is obtained, the count value is reduced by 1, and the corresponding item in the conflict processing emission table is awakened with the index number. The index number is then used to address the index space, and so on, until the count value reaches 0, indicating that all suspended instructions corresponding to the MSHR item have been awakened. Then the total number of memory access instructions a, the index number b of the first item, and the index number c of the last item recorded in the MSHR are all set to 0.

[0175] Based on the method of this embodiment, the situation that insufficient index numbers are recorded in MSHR will not block the transmission of memory access instructions, and the large capacity expanded by the conflict handling transmission table can be fully utilized. However, compared with the mechanism that each MSHR records the index numbers of all the suspended conflict handling transmission tables, the wake-up circuit design in this embodiment is relatively complicated.

[0176] Based on the wake-up mechanism of the present application, it can be ensured that there is no need to search the conflict handling transmission table during wake-up, thereby supporting large-capacity and multiple expansions of the conflict handling transmission table.

[0177] refer to Figure 6 , which shows an instruction scheduling device provided in an embodiment of the present application, the device 30 includes:

[0178] A first acquisition module 301, configured to receive a first memory access instruction and acquire a first address of the first memory access instruction;

[0179] A second acquisition module 302 acquires a second address of a second memory access instruction from the missing state processing register; the second memory access instruction is a memory access instruction that is a cache miss;

[0180] A wake-up module 303 is used to suspend the first memory access instruction in the conflict processing transmission table if the first address and the second address are the same, and wake up the first memory access instruction through the wake-up information provided by the corresponding item in the cache when the missing state processing register writes the data accessed by the second memory access instruction to the second address;

[0181] The first storage module 304 is used for storing the first memory access instruction into the regular memory access transmission queue if the first address and the second address are not the same, and transmitting the first memory access instruction according to the transmission order of the regular memory access transmission queue.

[0182] For example, the device 30 further includes:

[0183] A second storage module, configured to assign a first index number to the first memory access instruction and store the first index number in the cache if the first address and the second address are the same;

[0184] The wake-up module 303 includes:

[0185] The first wake-up submodule is used to determine and wake up the first memory access instruction from at least one conflicting memory access instruction in the conflict processing transmission table according to the first index number stored in the cache; wherein the address of the conflicting memory access instruction is the same as the second address, and each conflicting memory access instruction has a corresponding index number.

[0186] For example, the conflict handling emission table has at least one instruction item, the instruction item includes at least one free item in which the conflicting memory access instruction is not stored, and one free item has a corresponding index number; the second storage module includes:

[0187] The first acquisition submodule is used to acquire a free item index queue; the free item index queue is used to record the index number of the free item;

[0188] The first allocation submodule is used to obtain a first index number from the index numbers of the free item index queue and allocate the first index number to a first memory access instruction.

[0189] For example, the device 30 further includes:

[0190] A transmitting module, used for transmitting the first memory access instruction after waking up the first memory access instruction;

[0191] The third storage module is used to store the first index number of the first memory access instruction into the free item index queue.

[0192] For example, the first allocation submodule includes:

[0193] The first acquisition unit is used to acquire a first index number from the index numbers recorded in the free item index queue according to the order in which the index numbers of the free items are stored in the free item index queue.

[0194] For example, the second storage module may include:

[0195] A second acquisition submodule is used to acquire the dependency relationship between the first memory access instructions; the dependency relationship includes a strong dependency or a weak dependency;

[0196] A third acquisition submodule, configured to acquire a target index number storage strategy corresponding to the dependency relationship according to the dependency relationship between the first memory access instructions and the correspondence between the preset dependency relationship and the index number storage strategy;

[0197] The first storage submodule is used to store the first index number into the cache according to the target index number storage strategy.

[0198] For example, the missing state processing register includes multiple items to be processed, and one item to be processed corresponds to one address; when there are multiple first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency relationship between the first memory access instructions is weak dependency, the second storage module includes:

[0199] A first recording submodule is used to record a plurality of first index numbers in a first to-be-processed item; the first to-be-processed item is an to-be-processed item with the same address as the first address, and the first index number corresponds to the first memory access instruction one by one;

[0200] The wake-up module includes:

[0201] The wake-up submodule is used to determine multiple first memory access instructions from at least one conflicting memory access instruction in the conflict processing transmission table according to multiple first index numbers, and to wake up the multiple first memory access instructions at the same time.

[0202] For example, the missing state processing register includes multiple items to be processed, one item to be processed corresponds to one address, and when there are multiple first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency relationship between the first memory access instructions is a strong dependency, the second storage module includes:

[0203] The fourth acquisition submodule is used to add one to the total number of items to obtain a new total number of items;

[0204] The first writing submodule is used to write the first index number of a currently received first memory access instruction into the address corresponding to the index number of the last memory access instruction with the same address conflict recorded in the second pending item; the second pending item is an pending item with the same address as the first address.

[0205] For example, each item to be processed is also used to record the index number of the first memory access instruction with the same address conflict; when there are multiple first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency relationship between the first memory access instructions is a strong dependency, the wake-up module 303 includes:

[0206] A fifth acquisition submodule, configured to acquire a first index number from an address corresponding to the index number of the first same-address conflicting memory access instruction recorded in the second item to be processed;

[0207] A first determination submodule is used to determine and wake up a first memory access instruction corresponding to the first index number from at least one conflicting memory access instruction in the conflict processing transmission table according to the first index number;

[0208] The sixth acquisition submodule is used to reduce the total number of items by one to obtain a new total number of items;

[0209] The zeroing submodule is used to set the index numbers of the first and last conflicting memory access instructions recorded in the missing status processing register to zero when the new total number of entries is equal to zero.

[0210] For example, the device 30 further includes:

[0211] The transmitting submodule is used to transmit the first memory access instruction after waking up, and then transmit the non-conflicting memory access instruction to be transmitted if there is a non-conflicting memory access instruction to be transmitted in the regular memory access transmission queue.

[0212] In the embodiment of the present application, even if the memory access instruction is a memory access instruction with a conflict, it will not block other memory access instructions from entering the queue, so the subsequent memory access request that has no correlation with the conflicting memory access instruction can continue to be sent, and is not affected by the conflicting memory access instruction. In addition, the conflict handling does not need to search for a conventional memory access transmission queue, so that the conventional memory access transmission queue can be expanded to a large number of items, and then cooperate with the large-capacity MSHR to support the concurrency of the memory level. The present embodiment can greatly reduce the blocking of memory access requests, solves the design of conflict blocking entry in the related art, greatly limits the concurrency of memory access requests, cannot fully utilize the problem of the MSHR with expanded capacity, and is difficult to expand the transmission queue capacity when searching for the transmission queue, thereby limiting the problem of the scheduling ability of the memory access instruction.

[0213] Figure 74 is a block diagram of an electronic device 400 according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0214] Reference Figure 7 , the electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output (I / O) interface 412 , a sensor component 414 , and a communication component 416 .

[0215] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 402 may include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402.

[0216] The memory 404 is used to store various types of data to support the operation of the electronic device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, multimedia, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0217] The power supply component 406 provides power to the various components of the electronic device 400. The power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 400.

[0218] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the demarcation of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0219] The audio component 410 is used to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), and when the electronic device 400 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 404 or sent via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0220] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0221] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the electronic device 400, the relative positioning of components, such as the display and keypad of the electronic device 400, and the sensor assembly 414 can also detect the position change of the electronic device 400 or a component of the electronic device 400, the presence or absence of user contact with the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and the temperature change of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0222] The communication component 416 is used to facilitate wired or wireless communication between the electronic device 400 and other devices. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0223] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement a method for out-of-order scheduling of memory access instructions provided in an embodiment of the present application.

[0224] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, and the above instructions can be executed by a processor 420 of an electronic device 400 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0225] Figure 8 is a block diagram of an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be provided as a server. Figure 8 , the electronic device 500 includes a processing component 522, which further includes one or more processors, and a memory resource represented by a memory 532, for storing instructions that can be executed by the processing component 522, such as an application. The application stored in the memory 532 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute instructions to perform an instruction scheduling method provided in an embodiment of the present application.

[0226] The electronic device 500 may also include a power supply component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input / output (I / O) interface 558. The electronic device 500 may operate based on an operating system stored in the memory 532, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0227] An embodiment of the present application also provides a computer program product, including a computer program and an instruction scheduling method implemented when the computer program is executed by a processor.

[0228] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0229] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

[0230] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

[0231] The above is a detailed introduction to an instruction scheduling method, device, electronic device and computer-readable storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A memory access instruction scheduling method, characterized in that: include: receiving a first memory access instruction and obtaining a first address of the first memory access instruction; Obtaining a second address of a second memory access instruction from the miss status processing register; the second memory access instruction is a memory access instruction of a cache miss; If the first address and the second address are the same, suspending the first memory access instruction in the conflict processing transmission table, and waking up the first memory access instruction through the wake-up information provided by the corresponding item in the cache when the missing state processing register writes the data accessed by the second memory access instruction to the second address; If the first address and the second address are not the same, storing the first memory access instruction in a regular memory access transmission queue, and transmitting the first memory access instruction according to the transmission order of the regular memory access transmission queue; The conflict handling transmission table has at least one instruction item, and the instruction item includes at least one free item in which the conflicting memory access instruction is not stored, and each free item has a corresponding index number; if the first address and the second address are the same, a first index number is assigned to the first memory access instruction, and the first index number is stored in the cache.

2. The method according to claim 1, characterized in that The method further includes: waking up the first memory access instruction through the wake-up information provided by the corresponding item in the cache, including: According to the first index number stored in the cache, determining and waking up a first memory access instruction from at least one conflicting memory access instruction in the conflict handling emission table; The address of the conflicting memory access instruction is the same as the second address, and each conflicting memory access instruction has a corresponding index number.

3. The method according to claim 2, characterized in that Allocating a first index number to the first memory access instruction includes: Obtaining a free item index queue; the free item index queue is used to record the index number of the free item; The first index number is obtained from the index numbers of the free item index queue, and the first index number is assigned to the first memory access instruction.

4. The method according to claim 3, characterized in that Acquiring the first index number from the index number of the free item index queue includes: According to the order in which the index numbers of the free items are stored in the free item index queue, the first index number is obtained from the index numbers recorded in the free item index queue.

5. The method according to claim 2, characterized in that Storing the first index number in the cache includes: Obtaining a dependency relationship between the first memory access instructions; the dependency relationship includes a strong dependency or a weak dependency; According to the dependency relationship between the first memory access instructions and the correspondence between the preset dependency relationship and the index number storage strategy, acquiring the target index number storage strategy corresponding to the dependency relationship; According to the target index number storage strategy, the first index number is stored in the missing state processing register.

6. The method according to claim 2, characterized in that The missing state processing register includes a plurality of items to be processed, each item to be processed corresponds to an address; when there are a plurality of first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency relationship between the first memory access instructions is a weak dependency, storing the first index number in the cache includes: Recording a plurality of first index numbers in a first item to be processed; the address corresponding to the first item to be processed is the same as the first address, and the first index number corresponds to the first memory access instruction one by one; Waking up the first memory access instruction through the wake-up information provided by the corresponding item in the cache, including: Simultaneously wake up multiple first memory access instructions corresponding to multiple first index numbers.

7. The method according to claim 2, characterized in that The missing state processing register includes a plurality of pending items, one pending item corresponds to one address, and when there are a plurality of first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency relationship between the first memory access instructions is a strong dependency, the first index number is stored in the cache, including: Add one to the total number of items to obtain a new total number of items; The first index number of a currently received first memory access instruction is written into the address corresponding to the index number of the last memory access instruction with the same address conflict recorded in the second item to be processed; the address corresponding to the second item to be processed is the same as the first address.

8. The method according to claim 7, characterized in that Each of the items to be processed is used to record the index number of the first memory access instruction with the same address conflict; when there are multiple first memory access instructions, the first addresses of the first memory access instructions are the same, and the dependency relationship between the first memory access instructions is strong, the first memory access instruction is awakened by the wake-up information provided by the corresponding item in the cache, including: Obtaining the first index number from the address corresponding to the index number of the first item of the second item to be processed record that has the same address conflict with the memory access instruction; According to the first index number, determining and waking up a first memory access instruction corresponding to the first index number from at least one conflicting memory access instruction in the conflict handling emission table; Subtract one from the total number of items to obtain a new total number of items; When the new total number of entries is equal to zero, the index numbers of the first and last conflicting memory access instructions recorded in the miss status processing register are set to zero.

9. The method according to claim 1, characterized in that: In the case that there are multiple first memory access instructions and the first addresses of the multiple first memory access instructions are the same, waking up the first memory access instruction through wake-up information provided by a corresponding item in the cache, further comprising: The plurality of first memory access instructions are awakened in sequence according to the order in which the plurality of first memory access instructions are suspended in the conflict handling transmission table.

10. A memory access instruction out-of-order scheduling device, characterized in that: The device includes: A first acquisition module, used for receiving a first memory access instruction and acquiring a first address of the first memory access instruction; A second acquisition module acquires a second address of a second memory access instruction from the missing state processing register; the second memory access instruction is a memory access instruction of a cache miss; a wake-up module, configured to suspend the first memory access instruction in a conflict processing transmission table if the first address and the second address are the same, and wake up the first memory access instruction through wake-up information provided by a corresponding item in a cache when the missing state processing register writes the data accessed by the second memory access instruction to the second address; a first storage module, configured to store the first memory access instruction into a regular memory access transmission queue if the first address and the second address are different, and transmit the first memory access instruction according to the transmission order of the regular memory access transmission queue; The conflict handling emission table has at least one instruction item, the instruction item includes at least one idle item in which no conflicting memory access instruction is stored, and one of the idle items has a corresponding index number; The second storage module is used to assign a first index number to the first memory access instruction if the first address and the second address are the same, and store the first index number in the cache.

11. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to execute instructions to implement the method as claimed in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of claims 1 to 9.

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