A low-latency and small-area read data path for DDR hosts

Abstract

The present invention discloses a DDR host low-latency small-area read data path, belonging to the technical field of DDR host read data paths. The read data path first expands DQ to 4 times UI in the DQS clock domain by calculating the phase relationship between DQS and PHY_CLK at the actual sampling point, selects a suitable rising edge of PHY_CLK by using the calculated DQS delay information of the actual sampling point, samples the DQ expanded to 4 times UI, and directly generates dfi_rddata and dfi_rddata_valid signals, thereby minimizing the cross-clock domain delay between DQS and PHY_CLK, and completing serial-to-parallel conversion in the DQS clock domain without using FIFO, thereby finally achieving minimum delay and area occupancy.

Description

Technical Field

[0001] The present invention belongs to the technical field of DDR host read data path, and in particular relates to a DDR host low-latency small-area read data path. Background Art

[0002] Contemporary SoC (System-On-Chip) has an increasing demand for memory bandwidth. The single-bit rates of DDRn and LPDDRn are constantly increasing, while HBM is expanding the data bit width and also increasing the single-bit rate, so the clock frequency is also increasing. In high-speed bidirectional source synchronous systems such as DDR, LPDDRn, and HBM, the memory (Memory) returns data (DQ) and its accompanying clock DQS. DQS is a clock with the same frequency as the internal PHY_CLK, but due to the host IO delay and the unknown board-level routing delay, only an approximate range can be known, and the parameter tDQSCK of the memory (Memory) also specifies only a range. Therefore, the arrival time of the first real DQS rising edge at the SoC is unknown, that is, the round-trip time (Round-Trip Delay) is unknown.

[0003] As the frequency continues to increase, the round-trip delay can be as long as several cycles. The unknown round-trip delay is the first problem that the DDR host system needs to solve. SoC uses asynchronous FIFO to handle the cross-clock domain processing of DQS and PHY_CLK. Each DQ bit introduces an asynchronous FIFO of a certain depth. The DQS clock is used to write data to the FIFO, and PHY_CLK is used to read data from the FIFO. The start time of reading data needs to be later than the start time of writing data. When to start reading data from the FIFO, if the round-trip delay is unknown, you can only start reading as late as possible to ensure that the data has entered the FIFO before reading. And the round-trip delay is dynamically changing. When it becomes larger, the start time of reading data needs to be later than before, but there is still no information for reference on how late it needs to be. In order to avoid this dynamic adjustment or there is no appropriate method to adjust it, the SoC has to further increase the depth of the FIFO and continuously delay the start time of PHY_CLK reading data. An increase in FIFO depth means an increase in area, and a later start time of PHY_CLK reading data means an increase in latency.

[0004] If the SoC knows when DQS starts writing data to the FIFO, it will help solve this problem. At least it can reduce the depth of the FIFO and read out the data as early as possible to reduce latency. In order to get the correct gate logic opening time, the SoC measures the first real DQS arrival time. At this time, it has a rough understanding of the round-trip delay. However, DQS needs to sample the DQ with a nominal 1 / 4 cycle delay, and DQS needs to be routed to each DQ module in a clock-balanced tree. Therefore, at the actual sampling point, its phase is still unknown. With static timing analysis or other methods during physical implementation, it is possible to estimate its range and control the start time of reading data. But this still does not fundamentally solve the problem. Summary of the invention

[0005] The purpose of the present invention is to provide a DDR host low-latency and small-area read data path, by accurately calculating the phase relationship (integer plus fractional period) between the DQS and PHY_CLK clocks at the actual sampling point, for the DQ expanded to 4 times the UI (symbol interval), selecting the appropriate rising edge of PHY_CLK for sampling, so as to achieve the minimum delay and area occupancy, so as to solve the problems raised in the above background technology.

[0006] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a DDR host low-latency and small-area read data path, which calculates the phase relationship between DQS and PHY_CLK at the actual sampling point, first expands DQ to 4 times UI in the DQS clock domain, uses the calculated DQS delay information of the actual sampling point, selects a suitable rising edge of PHY_CLK, samples the DQ expanded to 4 times UI, and directly generates dfi_rddata and dfi_rddata_valid signals, thereby minimizing the cross-clock domain delay between DQS and PHY_CLK, and completing the serial-to-parallel conversion in the DQS clock domain, ultimately achieving the minimum delay and area occupancy.

[0007] Preferably, the DQS is sent to DQS_DLL through the IO module, and then sent to the gate through the delayed DQS. The DQS signal Gated_DQS_o after passing through the gate and the input signal Gated_DQS_i enter the measurement state machine through the multiplexer; at the same time, in the physical implementation stage, the DQS signal Gated_DQS_o is used as the output signal, and the clock tree balancing method is adopted to insert the even-numbered inverter winding to each DQ / DM module, and at the same time return to the DQS module itself;

[0008] Among them, DQS_DLL includes two stages. In the measurement stage, the measurement state machine changes the DQS_DLL delay setting to align the measured signal with the clock signal of PHY_CLK, thereby calculating the phase relationship of the measured signal relative to PHY_CLK; in the functional stage, DQS_DLL is switched to be controlled by the functional delay control and is set to 1 / 4 cycle for sampling DQ;

[0009] Gate control also includes two stages: the measurement stage, in which the gate is normally open; and the functional stage, in which it is controlled by the FUNC Gate module;

[0010] The control process of the FUNC Gate module is as follows: dfi_rddata_en generates an integer cycle delay through the shift register, and the number of delay cycles is controlled by rd_coarse_delay[3:0]; the fractional cycle delay is controlled by rd_fine_delay[7:0], and its highest bit rd_fine_delay[7] controls whether to select the DFF triggered by the falling edge of the clock to delay the signal for another half cycle. The remaining half cycle is controlled by rd_fine_delay[6:0] to control the Gate DLL of the half cycle length, and gate_close_extend controls whether the positive level of the gate is extended by 1 / 2 cycle.

[0011] Preferably, the DQ is sampled by Gated_DQS_i after passing through two-stage delay lines to measure the phase of Gated_DQS_i at the actual sampling point of DQ, thereby being converted into the phase of Gated_DQS_i in the DQS module. After being sampled by Gated_DQS_i, DQ is expanded to 4 times UI, which is convenient for selecting a rising edge of PHY_CLK for sampling;

[0012] The first-stage delay line DQS_Tree_DLL is used to compensate for the delay of the DQS clock tree, or the delay of the DQS clock tree can be compensated by directly using an even-numbered-stage inverter as a clock tree; and the second-stage delay line DQ_DLL is used to eliminate bit deviation.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] The present invention generates gate opening logic by accurately calculating the phase relationship (integer cycle plus fractional cycle) between DQS and PHY_CLK at the gate and the actual sampling point, selects a suitable positive edge of PHY_CLK to sample the DQ expanded to 4 times UI, does not use FIFO, and does not need to generate a clock between DQS and PHY_CLK for conversion, thereby minimizing the delay and area of ​​the read data path. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the DQS module of the present invention.

[0016] Figure 2 Specific circuit diagram of the Func Gate in the functional stage of the present invention.

[0017] Figure 3 Schematic diagram of the DQS clock tree of the present invention.

[0018] Figure 4 Schematic diagram of the DQ module of the present invention.

[0019] Figure 5 Sampling delay control diagram of the present invention.

[0020] Figure 6 Timing relationship diagram among GO, RT1, RT2 and SS of the present invention.

[0021] Figure 7 Relationship diagram between the SS_F value of the present invention and the setup and hold times of sampling.

[0022] Figure 8 Timing relationship diagram of two sampling points of N < SS_F < 1 - M of the present invention.

[0023] Fig. 9 Flow chart of the round-trip delay fractional period measurement of the present invention.

[0024] Fig.10 Flow chart of the first round-trip delay integer period measurement of the present invention.

[0025] Fig.11 Timing diagram of avoiding the leading gate opening time of the present invention.

[0026] Fig.12 Flow chart of the second round-trip delay integer period measurement of the present invention. Specific implementation manners

[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] The present invention accurately calculates the phase (integer plus fractional period) relationship between DQS and PHY_CLK at the actual sampling point, does not use a FIFO structure, first expands DQ to 4 times UI in the DQS clock domain, uses the calculated DQS delay information (integer plus fractional period) of the actual sampling point, selects a suitable rising edge of PHY_CLK, samples the DQ expanded to 4 times UI, and directly generates dfi_rddata and dfi_rddata_valid signals. With this structure, the cross-clock domain delay between DQS and PHY_CLK is minimized, and the serial-to-parallel conversion has been completed in the DQS clock domain, achieving the minimum delay and area occupancy.

[0029] The present invention, based on the modular concept, divides DQS and DQ into several modules. Among them, the DQS module is as follows: Figure 1 As shown, DQS is sent into the IO module Figure 1-10 0 DQS_DLL (delay line). DQS_DLL has two functions. One is in the measurement phase. Figure 1-10 3. The measurement state machine (Measure FSM) changes the DQS_DLL delay setting to align the measured signal with the PHY_CLK clock signal, thereby calculating the phase relationship of the measured signal relative to PHY_CLK. Second, in the functional stage, the DQS_DLL setting is switched to Figure 1-10 5 Function delay control (Func DLYC) is nominally set to 1 / 4 cycle to sample DQ. The delayed DQS is input Figure 1-10 1 Gate, similarly, gate control is also divided into two stages, the measurement stage, which is normally open, and the functional stage, which is controlled by the FUNC Gate module. The specific circuit of Func Gate is as follows Figure 2 As shown, dfi_rddata_en passes Figure 2-2 00 The shift register generates integer cycle delay, the number of delay cycles is controlled by rd_coarse_delay[3:0], and the fractional cycle delay is controlled by rd_fine_delay[7:0]. The highest bit rd_fine_delay[7] controls whether to select Figure 2-2 03 The DFF triggered by the falling edge of the clock delays the signal for another half cycle, and the remaining half cycle is controlled by rd_fine_delay[6:0] to control the Gate DLL of the half cycle length. Figure 2-2 07 signal gate_close_extend (gce) controls whether the positive level of the gate (Gate) is extended by 1 / 2 cycle. Figure 1-10 6-signal Gated_DQS_o and input signal Figure 1-107 Gated_DQS_i passes Figure 1-10 8 multiplexers enter the measurement state machine (Measure FSM). At the same time, in the physical implementation stage, Gated_DQS_o is used as the output signal, and the clock tree balancing method is used to insert even-level inverters to each DQ / DM module and return to the DQS module itself, such as Figure 3 As shown, in order to reduce the DQS clock tree Figure 3-3 To reduce the jitter caused by 00, the DQS clock tree should be as short as possible. For the convenience of calculation, the length of the DQS clock tree is limited to within 1 cycle of the highest frequency. Since the clock tree is balanced, the delay of Gated_DQS_i to each module, including DQS and DQ / DM, is consistent. Figure 4 In the example, Gated_DQS_i is used to sample DQ, and this place is the actual sampling point. The phase of Gated_DQS_i at this DQ location is converted into the phase of Gated_DQS_i in the DQS module. Fig. 9 Flowchart, in the measurement phase, the Gate is always open. In the preamble phase, the phase relationship between Gated_DQS_o and Gated_DQS_i and PHY_CLK is measured and recorded as a and c respectively. The phase of Gated_DQS_i increases (~c-~a) compared to Gated_DQS_o. In the flowchart, DQS_DLL[7:0] is evaluated from the highest bit (MSB). In order to save time, it is not necessary to end at the lowest bit (LSB). The bit (n) that does not affect the accuracy can be calculated to obtain the lock value of the master DLL (Master DLL) used to lock 1 cycle.

[0030] In the DQ module Figure 4 In the example, DQ passes through two delay lines and is sampled by Gated_DQS_i. The first delay line DQS_Tree_DLL ( Figure 4-4 00) is used to compensate for the delay of the DQS clock tree and is set to (~c-~a). Alternatively, the delay of the DQS clock tree can be compensated by directly using an even-numbered inverter as the clock tree. The second-level delay line DQ_DLL is used to eliminate bit skew. Figure 4-4 03 The comb_en signal flips from 0 to 1 at the odd falling edge of Gated_DQS_i (starting from 1), which is used to indicate the next falling edge (even falling edge) and needs to be combined. Figure 4 After the sampling structure in , DQ is expanded to 4 times UI, which is convenient for selecting a rising edge of PHY_CLK for sampling.

[0031] The abbreviations represent their meanings as follows:

[0032] GO: Gate Open

[0033] RT1: Round trip delay at Gated_DQS_o

[0034] RT2: Round trip delay at Gated_DQS_i

[0035] SS: Symbol Start (4UI DQ Start)

[0036] The delay of GO is divided into two parts: integer delay and fractional delay, which are controlled by rd_coarse_delay[3:0] and rd_fine_delay[7:0] respectively, and concatenated into a 12-bit unsigned number, expressed as:

[0037] GO = {rd_coarse_delay[3:0],rd_fine_delay[7:0]}

[0038] Similarly, by concatenating RT1, RT2, and SS with integer delay (_I) and fractional delay (_F), we can get the following equation:

[0039] RT1 = {RT1_I[3:0],RT1_F[7:0]}

[0040] = GO+(h40< <gce)

[0041] RT2 = {RT2_I[3:0],RT2_F[7:0]}

[0042] = GO+(h40< <gce)+(~c-~a)

[0043] SS= {SS_I[3:0],SS_F[7:0]}

[0044] = GO+(h40< <gce)+(~c-~a)+h180

[0045] The relationship between these four is as follows Figure 6 shown.

[0046] Figure 4-4One condition for the 05 DFF to correctly sample 4UI DQ is that the DFF setup time Tsetup and hold time Thold must be met. The maximum value in the library is selected, jitter is added, deviation (the delay from Gate_DQS_i to DQS / DQ / DM is nominally consistent, but there is still deviation), and a certain margin is added. It is characterized by a cycle, and a score M[7:0](Tsetup) and N[7:0](Thold) can be obtained.

[0047] like Figure 7 and Figure 8 As shown, the value range of SS_F is [0,1), not less than 0 and less than 1. The relationship between the value of SS_F and the values ​​of M and N is as follows:

[0048] If SS_F<=N, there is only one sampling edge, which is the positive edge of SS_I+1.

[0049] If N<=SS_F<1-M, there are two sampling edges, SS_I+1 and SS_I+2, and the positive edge of SS_I+1 with the smaller delay is selected.

[0050] If 1-M<=SS_F<1, there is only one sampling edge, which is the positive edge of SS_I+1.

[0051] Simplify the above description into two cases:

[0052] If (SS_F+M>=1 period) / / SS_F>=~M

[0053] Select the positive edge of SS_I+2

[0054] else / / (SS_F+M<1 cycle),SS_F<~M

[0055] Select the positive edge of SS_I+1

[0056] Figure 4-4 The sample_en signal of the DFF of 05 needs to be set to 1 one cycle before the selected clock edge, and then set to 0 at the selected clock edge, and it is generated once every 2 clock cycles. Figure 5 As shown in the Sample Delay Control module, the control is still performed by Figure 5-5 00 The shift register delays an integer number of cycles. The cycle is determined by Figure 5-5 01 signal sample_delay selection, in the last stage Figure 5-5The 02 register generates a flip signal. According to the above, sample_delay[3:0]=SS_I[3:0]+(SS_F>=~M), and dfi_rddata_valid is the signal with sample_en delayed by 1 cycle.

[0057] According to Fig.10 the flowchart, the DQS module switches from the measurement mode to the function mode, sets rd_fine_delay[7:0]=~a-(h40<<gce)+b, and rd_coars_delay increments from 0 until the value read from the MPR meets the expectation, so that both the correct opening position of the Gate and the correct rising edge of PHY_CLK for sampling can be obtained.

[0058] In addition, there is a more delicate method. First, write the 16-bit data sequence h0000, h0001, h0002,..., h0007 into a row of the memory in sequence. In the function mode, set rd_coarse_delay to a relatively large value S, such as 8, to avoid the preamble. The first half-word (Two Bytes) T read is the difference between the set value S and the correct value. Set rd_coarse_delay back to S-T, as Fig.11 , if the set Gate opening time rd_coarse_delay is 2 cycles later than the value that should be set, then a byte h02 is read. Subtract 2 from the set rd_coarse_delay and set it back to obtain the correct rd_coarse_delay. Its flowchart is as Fig.12 shown.

[0059] Among them, the specific Chinese meanings of some English technical terms in the present invention are as follows:

[0060] dfi_rddata: DDR PHY interface read data signal;

[0061] dfi_rddata_valid: DDR PHY interface read data valid signal;

[0062] dfi_rddata_en: DDR PHY interface read data enable signal;

[0063] Read delay integer cycle value: Read delay integer cycle value;

[0064] rd_fine_delay: Read delay fractional cycle value;

[0065] gate_close_extend: Gate close extension control signal;

[0066] preamble phase leading phase;

[0067] M[7:0](Tsetup) and N[7:0](Thold);

[0068] sample_en: sampling enable signal;

[0069] sample_delay: sampling delay control signal;

[0070] Memory: storage;

[0071] Two Bytes: Two bytes.

[0072] The present invention generates a gate opening logic by accurately calculating the phase relationship (integer cycle plus fractional cycle) between DQS and PHY_CLK at the gate and the actual sampling point, selects a suitable positive edge of PHY_CLK to sample the DQ expanded to 4 times the UI, does not use FIFO, and does not need to generate a clock between DQS and PHY_CLK for conversion, thereby minimizing the delay and area of ​​the read data path.

[0073] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0074] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A DDR host low latency small area read data path, characterized in that: The read data path calculates the phase relationship between DQS and PHY_CLK at the actual sampling point, first expands DQ to 4 times UI in the DQS clock domain, uses the calculated DQS delay information of the actual sampling point, selects a rising edge of PHY_CLK, samples the DQ expanded to 4 times UI, and directly generates dfi_rddata and dfi_rddata_valid signals, thereby minimizing the cross-clock domain delay between DQS and PHY_CLK, and completing the serial-to-parallel conversion in the DQS clock domain, ultimately achieving the minimum delay and area occupancy; The DQS is sent to DQS_DLL through the IO module, and then sent to the gate through the delayed DQS. The DQS signal Gated_DQS_o after passing through the gate and the input signal Gated_DQS_i enter the measurement state machine through the multiplexer; at the same time, in the physical implementation stage, the DQS signal Gated_DQS_o is used as the output signal, and the clock tree balancing method is adopted to insert the even-numbered inverters to each DQ / DM module, and at the same time return to the DQS module itself; Among them, DQS_DLL includes two stages. In the measurement stage, the measurement state machine changes the DQS_DLL delay setting to align the measured signal with the clock signal of PHY_CLK, thereby calculating the phase relationship of the measured signal relative to PHY_CLK; in the functional stage, DQS_DLL is switched to be controlled by the functional delay control and is set to 1 / 4 cycle for sampling DQ; Gate control also includes two stages: the measurement stage, in which the gate is normally open; and the functional stage, in which it is controlled by the FUNC Gate module; The control process of the FUNC Gate module is as follows: dfi_rddata_en generates integer cycle delay through the shift register, and the number of delay cycles is controlled by rd_coarse_delay[3:0]; the fractional cycle delay is controlled by rd_fine_delay[7:0], and its highest bit rd_fine_delay[7] controls whether to select the DFF triggered by the falling edge of the clock to delay the signal for another half cycle, and the remaining half cycle is controlled by rd_fine_delay[6:0] to control the Gate DLL of the half cycle length, and gate_close_extend controls whether the positive level of the gate is extended by 1 / 2 cycle; The DQ is sampled by Gated_DQS_i after passing through two stages of delay lines to measure the phase of Gated_DQS_i at the actual sampling point of DQ, which is then converted into the phase of Gated_DQS_i in the DQS module. After being sampled by Gated_DQS_i, DQ is expanded to 4 times UI, which is convenient for selecting a rising edge of PHY_CLK for sampling; The first-stage delay line DQS_Tree_DLL is used to compensate for the delay of the DQS clock tree, or directly use an even-numbered inverter as a clock tree to compensate for the delay of the DQS clock tree; and the second-stage delay line DQ_DLL is used to eliminate bit deviation.

Images