A bandwidth allocation method, device, equipment, system, medium and program product

Abstract

The present invention discloses a bandwidth allocation method, device, equipment, system, medium and program product, which relates to the field of computer technology, including: controlling the universal input and output interface of a first interface expansion device to output a high level of a preset duration; the first in-place signal pin of each slot is connected to the universal input and output interface of the first interface expansion device; during the period when the universal input and output interface of the first interface expansion device outputs a high level of a preset duration, reading the level of the universal input and output interface of the second interface expansion device corresponding to the root port; the second in-place signal pin of each slot is connected to the universal input and output interface of the second interface expansion device, and the universal input and output interface of the second interface expansion device connected by the second in-place signal pin of the slot is related to the bandwidth of the slot; identifying the bandwidth of the slot to which the root port is connected according to the read level, and performing bandwidth allocation accordingly. The method can improve the efficiency and accuracy of bandwidth allocation.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a bandwidth allocation method, device, equipment, system, medium and computer program product. Background Art

[0002] PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion card standard, mainly used to connect the central processing unit and various expansion cards. The bandwidth of PCIe is closely related to its version and the number of lanes. For example, the theoretical maximum bandwidth of the PCIe x1 slot is 1GB / s, and the theoretical maximum bandwidth of the PCIe x4 slot is 4GB / s. The PCIe slots on the server motherboard generally use PCIe x8 slots and PCIe x16 slots to facilitate the later insertion of different types of expansion cards. In order to reduce the waste of PCIe resources, it is necessary to realize the automatic identification and allocation of PCIe bandwidth. However, the current method of PCIe bandwidth identification and allocation has the problems of low bandwidth allocation efficiency and low accuracy. Therefore, how to improve the efficiency and accuracy of bandwidth allocation has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0003] The purpose of the present invention is to provide a bandwidth allocation method, device, equipment, system, medium and computer program product, which can improve the efficiency and accuracy of bandwidth allocation.

[0004] In order to solve the above technical problems, the present invention provides a bandwidth allocation method, comprising:

[0005] Control the universal input / output interface of the first interface expansion device to output a high level of a preset duration; the first in-position signal pin of each slot is connected to the universal input / output interface of the first interface expansion device;

[0006] During the period when the universal input / output interface of the first interface expansion device outputs a high level for a preset time, the level of the universal input / output interface of the second interface expansion device corresponding to the root port is read; the second in-position signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-position signal pin of the slot is related to the bandwidth of the slot;

[0007] The bandwidth of the slot to which the root port is connected is identified according to the level of the universal input / output interface of the second interface extension device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected.

[0008] In some embodiments, the second presence signal pins of different slots connected to the root port are all connected to the general input and output interface of the same second interface expansion device corresponding to the root port, and the second presence signal pins of each slot connected to the same root port are connected to different general input and output interfaces.

[0009] In some embodiments, the root port includes sixteen channels, and second in-place signal pins of different slots accessed by the sixteen channels are all connected to a universal input / output interface of a same second interface expansion device corresponding to the root port.

[0010] In some embodiments, the second interface expansion device includes sixteen general purpose input and output interfaces, and the general purpose input and output interfaces of the second interface expansion device correspond one-to-one to the channels of the root port.

[0011] In some embodiments, the second in-position signal pin of the slot is connected to the input-output interface corresponding to the channel with the largest sequence number among the channels used by the slot.

[0012] In some embodiments, identifying the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface expansion device includes:

[0013] According to the level of the universal input / output interface of the second interface expansion device corresponding to the root port, a level truth table is queried to identify the bandwidth of the slot to which the root port is connected; the level truth table includes the correspondence between the level of the universal input / output interface of the second interface expansion device and the bandwidth of the slot.

[0014] In some embodiments, the first interface expansion device includes sixteen general purpose input and output interfaces.

[0015] In some embodiments, the level truth table further includes a correspondence between a channel of the root port and a universal input / output interface of the second interface expansion device.

[0016] In some embodiments, controlling the universal input / output interface of the first interface expansion device to output a high level for a preset time period includes:

[0017] The universal input and output interfaces of the first interface expansion device are controlled to sequentially output high levels of a preset duration.

[0018] In some embodiments, before controlling the universal input / output interface of the first interface expansion device to output a high level for a preset time period, the method further includes:

[0019] The first interface expansion device is set to an output mode, and each general input / output interface of the first interface expansion device is set to output a low level.

[0020] In some embodiments, it also includes:

[0021] The second interface expansion device is set to input mode.

[0022] In some embodiments, the second presence signal pin of each slot is further connected to a hot-swap monitoring logic circuit.

[0023] In some embodiments, it also includes:

[0024] If the second on-site signal pin of the slot to which the corresponding first on-site signal pin belongs is continuously at a low level during the period when the universal input / output interface of the first interface expansion device outputs a high level, an exception is reported.

[0025] In some embodiments, it also includes:

[0026] If the second on-site signal pin of the slot to which the corresponding first on-site signal pin belongs is continuously at a low level during the period when the universal input / output interface of the first interface expansion device outputs a high level, the universal input / output interface of the first interface expansion device is controlled to no longer output a high level.

[0027] In some embodiments, controlling the universal input / output interface of the first interface expansion device to output a high level for a preset time period includes:

[0028] The universal input / output interface of the first interface expansion device is controlled via the system management bus to output a high level of a preset duration.

[0029] In some embodiments, reading the level of the general input / output interface of the second interface expansion device corresponding to the root port includes:

[0030] The level of the general input / output interface of the second interface expansion device is read through the system management bus.

[0031] In order to solve the above technical problems, the present invention further provides a bandwidth allocation device, comprising:

[0032] A control module, used for controlling the universal input / output interface of the first interface expansion device to output a high level of a preset duration; the first in-position signal pin of each slot is connected to the universal input / output interface of the first interface expansion device;

[0033] a reading module, configured to read the level of the universal input / output interface of the second interface expansion device corresponding to the root port during the period when the universal input / output interface of the first interface expansion device outputs a high level for a preset time; the second in-position signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-position signal pin of the slot is related to the bandwidth of the slot;

[0034] The allocation module is used to identify the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface extension device, and allocate bandwidth to the root port according to the bandwidth of the slot to which the root port is connected.

[0035] In order to solve the above technical problems, the present invention further provides a bandwidth allocation device, comprising:

[0036] Memory for storing computer programs;

[0037] The processor is used to implement the steps of the bandwidth allocation method as described above when executing the computer program.

[0038] In order to solve the above technical problem, the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the bandwidth allocation method described above when executed by a processor.

[0039] To solve the above technical problem, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the bandwidth allocation method described above are implemented.

[0040] In order to solve the above technical problems, the present invention further provides a bandwidth allocation system, comprising:

[0041] A processor, a first interface expansion device, and a second interface expansion device;

[0042] The processor is used to control the universal input / output interface of the first interface expansion device to output a high level of a preset duration; the first in-place signal pin of each slot is connected to the universal input / output interface of the first interface expansion device; during the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration, the level of the universal input / output interface of the second interface expansion device corresponding to the root port is read; the second in-place signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-place signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot to which the root port is connected is identified according to the level of the universal input / output interface of the second interface expansion device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected.

[0043] The bandwidth allocation method provided by the present invention comprises: controlling the universal input / output interface of a first interface expansion device to output a high level of a preset duration; connecting the first in-place signal pin of each slot to the universal input / output interface of the first interface expansion device; reading the level of the universal input / output interface of a second interface expansion device corresponding to a root port during the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration; connecting the second in-place signal pin of each slot to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-place signal pin of the slot is related to the bandwidth of the slot; identifying the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface expansion device, and allocating bandwidth to the root port according to the bandwidth of the slot to which the root port is connected.

[0044] It can be seen that in the bandwidth allocation method provided by the present invention, the first in-place signal pin of the slot is not directly grounded, but connected to the universal input and output interface of the first interface expansion device, and the second in-place signal pin of the slot is connected to the universal input and output interface of the second interface expansion device. By controlling the universal input and output interface of the first interface expansion device to output a high level, the level of the first in-place signal pin connected to the universal input and output interface of the first interface expansion device can be pulled up. By reading the level of the universal input and output interface of the second interface expansion device, the level of the second in-place signal pin of the slot can be obtained, and then the bandwidth of the slot connected to the root port can be identified according to the level of the second in-place signal pin of the slot, and the corresponding bandwidth allocation is performed on the root port accordingly. The firmware is developed once to form a standard PCIe bandwidth resource adaptive allocation function module. When designing the server motherboard, the first in-place signal pin of the PCIe slot is connected to the universal input and output interface of the first interface expansion device, and the second in-place signal pin of the PCIe slot is connected to the universal input and output interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources of various platforms, various models, and various configurations can be achieved. This method does not need to occupy the general input and output interface resources of the south bridge, nor does it require the participation of the baseboard management controller, and can achieve the allocation of any bandwidth combination. In addition, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe Switch side.

[0045] The bandwidth allocation device, equipment, system, medium and computer program product provided by the present invention all have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A schematic diagram of a flow chart of a bandwidth allocation method provided by an embodiment of the present invention;

[0048] Figure 2 A schematic diagram of a PCIe device and a PCIe slot provided by an embodiment of the present invention;

[0049] Figure 3 A schematic diagram of a first interface extension device provided by an embodiment of the present invention;

[0050] Figure 4 A schematic diagram of a second interface expansion device provided by an embodiment of the present invention;

[0051] Figure 5 A circuit connection diagram provided by an embodiment of the present invention;

[0052] Figure 6 A schematic diagram of a bandwidth allocation device provided by an embodiment of the present invention;

[0053] Figure 7 A schematic diagram of a bandwidth allocation device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The core of the present invention is to provide a bandwidth allocation method, device, equipment, system, medium and computer program product, which can improve the efficiency and accuracy of bandwidth allocation.

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] Please refer to Figure 1 , Figure 1 A schematic diagram of a bandwidth allocation method provided by an embodiment of the present invention, referring to Figure 1 As shown, the method includes:

[0057] S101: Controlling the universal input / output interface of the first interface expansion device to output a high level for a preset time; connecting the first in-position signal pin of each slot to the universal input / output interface of the first interface expansion device;

[0058] S102: while the universal input / output interface of the first interface expansion device outputs a high level for a preset time, reading the level of the universal input / output interface of the second interface expansion device corresponding to the root port; the second in-position signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-position signal pin of the slot is related to the bandwidth of the slot;

[0059] S103: Identify the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface extension device, and allocate bandwidth to the root port according to the bandwidth of the slot to which the root port is connected.

[0060] The first in-position signal pin is the PRSNT1 signal pin, and the second in-position signal pin is the PRSNT2 signal pin. Pin 1 on the A side of the PCIe device is the PRSNT1 signal pin, pin 17 on the B side of the X1 bandwidth device is the PRSNT2 signal pin, pin 31 on the B side of the X4 bandwidth device is the PRSNT2 signal pin, pin 48 on the B side of the X8 bandwidth device is the PRSNT2 signal pin, and pin 81 on the B side of the X16 bandwidth device is the PRSNT2 signal pin. The PRSNT1 signal pin and the PRSNT2 signal pin on the PCIe device side are connected together. Reference Figure 2 As shown, usually the PRSNT1 signal pin of the PCIe slot is grounded, and the PRSNT2 signal pin is pulled high by a pull-up resistor. After the PCIe device is inserted into the PCIe slot, the PRSNT2 signal pin of the PCIe slot is connected to the PRSNT1 signal pin, so the PRSNT2 signal pin is grounded and pulled low, and the level of the PRSNT2 signal pin changes from a high level to a low level, indicating that the PCIe device is inserted.

[0061] In this embodiment, the PRSNT1 signal pin of the PCIe slot (including the system motherboard standard slot and the Riser card standard slot) is not directly grounded, but connected to the GPIO (General-purpose input / output) interface of the first interface expansion device. In some embodiments, the first interface expansion device includes sixteen general-purpose input / output interfaces. If the number of PCIe slots in the server exceeds 16, the number of first interface expansion devices is increased accordingly. For example, the first interface expansion device may be a PCA9555 device. The PCA9555 device includes 16 GPIO interfaces (P00~P07, P10~P17), and the 16 GPIO interfaces are recorded as GPIO1~GPIO16. Figure 3 As shown, the 16 GPIO interfaces of the PCA9555 device are respectively connected to the PRSNT1 signal pins of a slot. Figure 3 Device1_PRSNT1# to Device16_PRSNT1# represent the PRSNT1 signal pins of different slots. If the number of PCIe slots in the server exceeds 16, the number of PCA9555 devices should be increased accordingly.

[0062] The PRSNT2 signal pin of the PCIe slot is connected to the GPIO pin of the second interface expansion device. The GPIO pin of the second interface expansion device to which the PRSNT2 signal pin of the PCIe slot is connected is related to the bandwidth of the PCIe slot, so that the bandwidth of the PCIe slot can be identified according to the level of the GPIO pin of the second interface expansion device to which the PRSNT2 signal pin of the PCIe slot is connected. In some embodiments, the second in-position signal pin of each slot is also connected to a hot-plug monitoring logic circuit. In this way, hot-plug control can be performed by monitoring the second in-position signal pin of the slot. As for the circuit structure of the hot-plug monitoring logic circuit, reference can be made to the prior art, and the present invention will not be repeated here.

[0063] In some embodiments, the second presence signal pins of different slots connected to the root port are all connected to the general input and output interface of the same second interface expansion device corresponding to the root port, and the second presence signal pins of each slot connected to the same root port are connected to different general input and output interfaces.

[0064] In this embodiment, each root port (RootPort) corresponds to a second interface expansion device. The PRSNT2 signal pins of each PCIe slot connected to the same root port are connected to the GPIO interface of the second interface expansion device corresponding to the root port. And the PRSNT2 signal pins of each PCIe slot connected to the same root port are connected to different GPIO interfaces.

[0065] The root port corresponds to a second interface expansion device, and the second in-position signal pins of different slots connected to the root port are all connected to the universal input and output interface of the same second interface expansion device corresponding to the root port, so that the number of second interface expansion devices can be reduced.

[0066] In some embodiments, the root port includes sixteen channels, and second in-place signal pins of different slots accessed by the sixteen channels are all connected to a universal input / output interface of a same second interface expansion device corresponding to the root port.

[0067] The root port includes 16 lanes, and the slot uses part or all of the 16 lanes. For example, if the slot is a x4 slot, the slot uses 4 lanes of the root port. If the slot is a x8 slot, the slot uses 8 lanes of the root port. It can be understood that the lanes used by different slots do not overlap. In addition, it can be agreed that the slots give priority to lanes with smaller serial numbers. For example, there are two slots connected to the same root port, one is a x4 slot and the other is a x8 slot. The x4 slot uses lanes 1 to lane 4, and the x8 slot uses lanes 5 to lane 12. Alternatively, the x8 slot uses lanes 1 to lane 8, and the x4 slot uses lanes 9 to lane 12.

[0068] In some embodiments, the second interface expansion device includes sixteen general purpose input and output interfaces, and the general purpose input and output interfaces of the second interface expansion device correspond one-to-one to the channels of the root port.

[0069] The 16 lanes of the root port correspond one-to-one to the general input and output interfaces of the second interface expansion device corresponding to the root port. The second interface expansion device can be a PCA9555 device. The serial number of the general input and output interface of the second interface expansion device can be the same as the serial number of the corresponding channel. The lane corresponding to GPIO1 is lane1, the lane corresponding to GPIO2 is lane2, and so on. The lane corresponding to GPIO16 is lane16.

[0070] In some embodiments, the second in-position signal pin of the slot is connected to the input-output interface corresponding to the channel with the largest sequence number among the channels used by the slot.

[0071] For example, refer to Figure 4As shown, the x8 slot uses lane1~lane8 (maximum number is 8), and the PRSNT2 signal pin of the x8 slot is connected to GPIO8. The x4 slot uses lane9~lane12 (maximum number is 12), and the PRSNT2 signal pin of the x4 slot is connected to GPIO12. The x4 slot uses lane13~lane16 (maximum number is 16), and the PRSNT2 signal pin of the x4 slot is connected to GPIO16.

[0072] The bandwidth allocation method provided in this embodiment can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe Switch side. The following description is based on the PCIe root port bandwidth allocation on the CPU side as an example. The connection relationship between the CPU, the first interface expansion device, the second interface expansion device, etc. can be referred to in Figure 5 As shown, the CPU is connected to the south bridge, and the south bridge is connected to the first interface expansion device and the second interface expansion device. The PRSNT1 signal pin of the PCIe slot is connected to the universal input and output interface of the first interface expansion device, and the PRSNT2 signal pin of the PCIe slot is connected to the universal input and output interface of the second interface expansion device.

[0073] After the server is powered on, before the PCIe device is enumerated, the BIOS (Basic Input Output System) controls each GPIO interface of the first interface expansion device to output a high level for a preset duration. For example, a high level of 10ms is output. During the period when the GPIO interface of the first interface expansion device outputs a high level for a preset duration, the BIOS reads the level of the GPIO interface of the second interface expansion device and records it in the bandwidth truth value array corresponding to the root port, and then identifies the bandwidth of the slot to which the root port is connected according to the level of the GPIO interface of the second interface expansion device, and allocates the corresponding bandwidth to the root port according to the bandwidth of the slot to which the root port is connected.

[0074] In the case that the first interface expansion device and the second interface expansion device are PCA9555 devices, the BIOS may set the modes of the first interface expansion device and the second interface expansion device by sending control bytes.

[0075] Each PCA9555 device has a corresponding address. When the address is answered correctly, the BIOS sends a control byte, which will be stored in the control register of the PCA9555 device, where the three bits B0, B1, and B2 will define the operation and internal registers (input, output, polarity inversion or configuration).

[0076] There are four internal registers within the PCA9555 device:

[0077] Input Registers: The input port registers (registers 0 and 1) reflect the incoming logic level of the pin, regardless of whether the pin is defined as an input or output by the configuration register. The input registers act only on read operations. Writing to these registers has no effect. Before a read operation, send a write transfer with a control byte to indicate that the I2C device will next access an input port register.

[0078] Output Registers: The output port registers (registers 2 and 3) show the outgoing logic electrical configuration register for pins defined as outputs. The bit values ​​in this register have no effect on pins defined as inputs. Reading the register from here reflects the value in the flip-flop that controls the output selection, not the actual pin value.

[0079] Polarity reversal register: The polarity reversal register (registers 4 and 5) allows the positioning of the input pin polarity reversal configuration register. Writing 1 to a bit in this register indicates that the input polarity of the pin is reversed when it is in the input state. Writing 0 has no effect.

[0080] Configuration Registers: The Configuration registers (Registers 6 and 7) configure the direction of the I / O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high impedance output driver. If this register is cleared to 0 at this point, the corresponding port pin is enabled as an output.

[0081] In some embodiments, identifying the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface expansion device includes:

[0082] According to the level of the universal input / output interface of the second interface expansion device corresponding to the root port, a level truth table is queried to identify the bandwidth of the slot to which the root port is connected; the level truth table includes the correspondence between the level of the universal input / output interface of the second interface expansion device and the bandwidth of the slot.

[0083] A level truth table is pre-built, and the level truth table includes the correspondence between the level of the general input and output interface of the second interface expansion device and the bandwidth of the slot. Based on the level of the GPIO interface of the second interface expansion device corresponding to the root port, the bandwidth of the PCIe slot connected to the root port can be identified by looking up the table, and then the corresponding bandwidth is allocated to the root port accordingly.

[0084] For example, referring to Table 1, when GPIO16 is at a high level, the level true value of GPIO16 is 1; other GPIOs are at a low level, and the level true value of other GPIOs is 0; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO16 are lane1 to lane16, and the bandwidth of the PCIe slot is x16, and the corresponding bandwidth is allocated to the root port accordingly.

[0085] When GPIO8 is high and GPIO16 is high, the true value of GPIO8 and GPIO16 is 1; other GPIOs are low and the true value of other GPIOs is 0; the lanes used by the PCIe slot whose PRSNT2 signal pin is connected to GPIO8 are lane1 to lane8, and the bandwidth of the PCIe slot is x8; the lanes used by the PCIe slot whose PRSNT2 signal pin is connected to GPIO16 are lane9 to lane16, and the bandwidth of the PCIe slot is x8; the corresponding bandwidth is allocated to the root port accordingly.

[0086] When GPIO4 is at a high level, GPIO8 is at a high level, and GPIO16 is at a high level, the true value of the levels of GPIO4, GPIO8, and GPIO16 is 1; other GPIOs are at a low level, and the true value of the levels of other GPIOs is 0; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO4 are lanes 1 to lane 4, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO8 are lanes 5 to lane 8, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO16 are lanes 9 to lane 16, and the bandwidth of the PCIe slot is x8; accordingly, the corresponding bandwidth is allocated to the root port.

[0087] When GPIO8 is high, GPIO12 is high, and GPIO16 is high, the true value of GPIO8, GPIO12, and GPIO16 is 1; other GPIOs are low, and the true value of other GPIOs is 0; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO8 are lanes 1 to lane 8, and the bandwidth of the PCIe slot is x8; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO12 are lanes 9 to lane 12, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO16 are lanes 13 to lane 16, and the bandwidth of the PCIe slot is x4; the corresponding bandwidth is allocated to the root port accordingly.

[0088] When GPIO4 is high, GPIO8 is high, GPIO12 is high, and GPIO16 is high, the true value of GPIO4, GPIO8, GPIO12, and GPIO16 is 1; other GPIOs are low, and the true value of other GPIOs is 0; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO4 are lanes 1 to lane 4, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO8 are lanes 5 to lane 8, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO12 are lanes 9 to lane 12, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO16 are lanes 13 to lane 16, and the bandwidth of the PCIe slot is x4; the corresponding bandwidth is allocated to the root port accordingly.

[0089] When GPIO8 is high, GPIO12 is high, GPIO14 is high, and GPIO16 is high, the true value of GPIO8, GPIO12, GPIO14, and GPIO16 is 1; other GPIOs are low, and the true value of other GPIOs is 0; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO8 are lanes 1 to lane 8, and the bandwidth of the PCIe slot is x8; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO12 are lanes 9 to lane 12, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO14 are lanes 13 to lane 14, and the bandwidth of the PCIe slot is x2; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO16 are lanes 15 to lane 16, and the bandwidth of the PCIe slot is x2; the corresponding bandwidth is allocated to the root port accordingly.

[0090] When GPIO8 is high, GPIO10 is high, GPIO12 is high, and GPIO16 is high, the true value of GPIO8, GPIO10, GPIO12, and GPIO16 is 1; other GPIOs are low, and the true value of other GPIOs is 0; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO8 are lanes 1 to lane 8, and the bandwidth of the PCIe slot is x8; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO10 are lanes 9 to lane 10, and the bandwidth of the PCIe slot is x2; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO12 are lanes 11 to lane 12, and the bandwidth of the PCIe slot is x2; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO16 are lanes 13 to lane 16, and the bandwidth of the PCIe slot is x4; the corresponding bandwidth is allocated to the root port accordingly.

[0091] When GPIO4 is high, GPIO6 is high, GPIO8 is high, and GPIO16 is high, the true value of GPIO4, GPIO6, GPIO8, and GPIO16 is 1; other GPIOs are low, and the true value of other GPIOs is 0; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO4 are lanes 1 to lane 4, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO6 are lanes 5 to lane 6, and the bandwidth of the PCIe slot is x2; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO8 are lanes 7 to lane 8, and the bandwidth of the PCIe slot is x2; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO16 are lanes 9 to lane 16, and the bandwidth of the PCIe slot is x8; accordingly, the corresponding bandwidth is allocated to the root port.

[0092] When GPIO2 is high, GPIO4 is high, GPIO8 is high, and GPIO16 is high, the true value of GPIO2, GPIO4, GPIO8, and GPIO16 is 1; other GPIOs are low, and the true value of other GPIOs is 0; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO2 are lane1 to lane2, and the bandwidth of the PCIe slot is x2; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO4 are lane3 to lane4, and the bandwidth of the PCIe slot is x2; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO8 are lane5 to lane8, and the bandwidth of the PCIe slot is x4; the lanes used by the PCIe slot that represents the PRSNT2 signal pin connected to GPIO16 are lane9 to lane16, and the bandwidth of the PCIe slot is x8; the corresponding bandwidth is allocated to the root port accordingly.

[0093] Table 1

[0094]

[0095] In some embodiments, the level truth table further includes a correspondence between channels and general input and output interfaces.

[0096] As shown in Table 1 above, the level truth table includes not only the correspondence between the level and the bandwidth, but also the correspondence between the channel and the general input and output interface. Lane 1 corresponds to GPIO1, and lane 16 corresponds to GPIO16. By querying the level truth table, not only the bandwidth of the slot can be identified, but also the channel used by the slot can be determined. For example, the level truth value of GPIO8 is 1, the level truth value of GPIO16 is 1, and the level truth value of other GPIOs is 0, indicating that the bandwidth of one slot connected to the root port is x8, and the bandwidth of the other slot is also x8, and one slot uses lane 1~lane 8, and the other slot uses lane 9~lane 16.

[0097] In some embodiments, controlling the universal input / output interface of the first interface expansion device to output a high level for a preset time period includes:

[0098] The universal input and output interfaces of the first interface expansion device are controlled to sequentially output high levels of a preset duration.

[0099] In this embodiment, the universal input / output interfaces of the first interface expansion device sequentially output high levels for a preset time period, and any two universal input / output interfaces do not output high levels at the same time.

[0100] In some embodiments, before controlling the universal input / output interface of the first interface expansion device to output a high level for a preset time period, the method further includes:

[0101] The first interface expansion device is set to an output mode, and each general input / output interface of the first interface expansion device is set to output a low level.

[0102] In some embodiments, it also includes:

[0103] The second interface expansion device is set to input mode.

[0104] After the server is powered on, before the PCIe device is enumerated, the BIOS sets the first interface expansion device to output mode, and sets each general input and output interface of the first interface expansion device to output a low level. The BIOS sets the second interface expansion device to input mode, and configures a pull-down resistor. The BIOS controls each GPIO interface of the first interface expansion device to output a high level for a preset duration. During the period when the GPIO interface of the first interface expansion device outputs a high level for a preset duration, the BIOS reads the level of the GPIO interface of the second interface expansion device.

[0105] In some embodiments, it also includes:

[0106] If the second on-site signal pin of the slot to which the corresponding first on-site signal pin belongs is continuously at a low level during the period when the universal input / output interface of the first interface expansion device outputs a high level, an exception is reported.

[0107] During the period when a certain universal input / output interface of the first interface expansion device outputs a high level, the level of the second in-place signal pin of the slot to which the first in-place signal pin belongs connected by the universal input / output interface should be a high level. If during the period when a certain universal input / output interface of the first interface expansion device outputs a high level, the level of the second in-place signal pin of the slot to which the universal input / output interface belongs connected by the universal input / output interface continues to be a low level, it indicates that there is an abnormality, and the BIOS reports an abnormality.

[0108] In some embodiments, it also includes:

[0109] If the second on-site signal pin of the slot to which the corresponding first on-site signal pin belongs is continuously at a low level during the period when the universal input / output interface of the first interface expansion device outputs a high level, the universal input / output interface of the first interface expansion device is controlled to no longer output a high level.

[0110] During the period when a certain universal input / output interface of the first interface expansion device outputs a high level, the level of the second in-place signal pin of the slot to which the first in-place signal pin belongs connected to the universal input / output interface should be a high level. If during the period when a certain universal input / output interface of the first interface expansion device outputs a high level, the level of the second in-place signal pin of the slot to which the universal input / output interface belongs connected to the first in-place signal pin continues to be a low level, it indicates that there is an abnormality. In addition to reporting the abnormality, at this time, the BIOS can also control the universal input / output interface of the first interface expansion device to no longer output a high level, and the BIOS no longer reads the level of the universal input / output interface of the second interface expansion device.

[0111] In some embodiments, controlling the universal input / output interface of the first interface expansion device to output a high level for a preset time period includes:

[0112] The universal input / output interface of the first interface expansion device is controlled via the system management bus to output a high level of a preset duration.

[0113] In some embodiments, reading the level of the general input / output interface of the second interface expansion device corresponding to the root port includes:

[0114] The level of the general input / output interface of the second interface expansion device corresponding to the root port is read through the system management bus.

[0115] In this embodiment, the first interface expansion device and the second interface expansion device are connected to the SMBUS (System Management Bus). The BIOS controls the universal input / output interface of the first interface expansion device to output a high level of a preset duration through the system management bus, and reads the level of the universal input / output interface of the second interface expansion device corresponding to the root port through the system management bus.

[0116] To save the use of interface expansion devices, when the root port is designed to allocate x16 bandwidth, the second interface expansion device may no longer be used. For a root port without a corresponding second interface expansion device, the BIOS allocates x16 bandwidth to it by default.

[0117] In summary, in the bandwidth allocation method provided by the present invention, the first in-place signal pin of the slot is not directly grounded, but connected to the universal input and output interface of the first interface expansion device, and the second in-place signal pin of the slot is connected to the universal input and output interface of the second interface expansion device. By controlling the universal input and output interface of the first interface expansion device to output a high level, the level of the first in-place signal pin connected to the universal input and output interface of the first interface expansion device can be raised. By reading the level of the universal input and output interface of the second interface expansion device, the level of the second in-place signal pin of the slot can be obtained, and then the bandwidth of the slot connected to the root port can be identified according to the level of the second in-place signal pin of the slot, and the corresponding bandwidth allocation is performed on the root port accordingly. The firmware is developed once to form a standard PCIe bandwidth resource adaptive allocation function module. When designing the server motherboard, the first in-place signal pin of the PCIe slot is connected to the universal input and output interface of the first interface expansion device, and the second in-place signal pin of the PCIe slot is connected to the universal input and output interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources of various platforms, various models, and various configurations can be achieved. This method does not need to occupy the general input and output interface resources of the south bridge, nor does it require the participation of the baseboard management controller, and can achieve the allocation of any bandwidth combination. In addition, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe Switch side.

[0118] The present invention also provides a bandwidth allocation device, and the device described below can be referred to in correspondence with the method described above. Figure 6 , Figure 6 A schematic diagram of a bandwidth allocation device provided by an embodiment of the present invention, combined with Figure 6 As shown, the device comprises:

[0119] The control module 10 is used to control the universal input / output interface of the first interface expansion device to output a high level of a preset duration; the first in-position signal pin of each slot is connected to the universal input / output interface of the first interface expansion device;

[0120] The reading module 20 is used to read the level of the universal input / output interface of the second interface expansion device corresponding to the root port during the period when the universal input / output interface of the first interface expansion device outputs a high level for a preset time; the second in-position signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-position signal pin of the slot is related to the bandwidth of the slot;

[0121] The allocation module 30 is used to identify the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface extension device, and allocate bandwidth to the root port according to the bandwidth of the slot to which the root port is connected.

[0122] Based on the above embodiments, as a specific implementation method, the second in-place signal pins of different slots connected to the root port are all connected to the universal input and output interface of the same second interface expansion device corresponding to the root port, and the universal input and output interfaces connected to the second in-place signal pins of each slot connected to the same root port are different.

[0123] Based on the above embodiment, as a specific implementation method, the root port includes sixteen channels, and the second in-place signal pins of different slots connected to the sixteen channels are all connected to the universal input and output interface of the same second interface expansion device corresponding to the root port.

[0124] Based on the above embodiment, as a specific implementation mode, the second interface expansion device includes sixteen universal input and output interfaces, and the universal input and output interfaces of the second interface expansion device correspond one-to-one to the channels of the root port.

[0125] Based on the above embodiment, as a specific implementation manner, the second in-position signal pin of the slot is connected to the input-output interface corresponding to the channel with the largest sequence number among the channels used by the slot.

[0126] Based on the above embodiment, as a specific implementation manner, identifying the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface extension device includes:

[0127] According to the level of the universal input / output interface of the second interface expansion device corresponding to the root port, a level truth table is queried to identify the bandwidth of the slot to which the root port is connected; the level truth table includes the correspondence between the level of the universal input / output interface of the second interface expansion device and the bandwidth of the slot.

[0128] Based on the above embodiment, as a specific implementation mode, the first interface expansion device includes sixteen general input and output interfaces.

[0129] Based on the above embodiment, as a specific implementation manner, the level truth table further includes a correspondence between the channel of the root port and the universal input and output interface of the second interface extension device.

[0130] Based on the above embodiment, as a specific implementation mode, the control module 10 is specifically used for:

[0131] The universal input and output interfaces of the first interface expansion device are controlled to sequentially output high levels of a preset duration.

[0132] Based on the above embodiment, as a specific implementation method, it also includes:

[0133] The first setting module is used to set the first interface expansion device to output mode before the control module 10 controls the universal input / output interface of the first interface expansion device to output a high level for a preset time, and to set each universal input / output interface of the first interface expansion device to output a low level.

[0134] Based on the above embodiment, as a specific implementation method, it also includes:

[0135] The second setting module is used to set the second interface expansion device to an input mode.

[0136] In some embodiments, the second presence signal pin of each slot is further connected to a hot-swap monitoring logic circuit.

[0137] Based on the above embodiment, as a specific implementation method, it also includes:

[0138] The abnormality reporting module is used to report an abnormality if the second in-position signal pin of the slot to which the corresponding first in-position signal pin belongs is continuously at a low level during the period when the universal input / output interface of the first interface expansion device outputs a high level.

[0139] Based on the above embodiment, as a specific implementation method, it also includes:

[0140] The second control module is used to control the universal input / output interface of the first interface expansion device to stop outputting a high level if the second in-position signal pin of the slot to which the corresponding first in-position signal pin belongs is continuously at a low level during the period when the universal input / output interface of the first interface expansion device outputs a high level.

[0141] Based on the above embodiment, as a specific implementation mode, the control module 10 is specifically used for:

[0142] The universal input / output interface of the first interface expansion device is controlled via the system management bus to output a high level of a preset duration.

[0143] Based on the above embodiment, as a specific implementation mode, the reading module 20 is specifically used for:

[0144] The level of the general input / output interface of the second interface expansion device is read through the system management bus.

[0145] In the bandwidth allocation device provided by the present invention, the first in-place signal pin of the slot is not directly grounded, but connected to the universal input / output interface of the first interface expansion device, and the second in-place signal pin of the slot is connected to the universal input / output interface of the second interface expansion device. By controlling the universal input / output interface of the first interface expansion device to output a high level, the level of the first in-place signal pin connected to the universal input / output interface of the first interface expansion device can be pulled up. By reading the level of the universal input / output interface of the second interface expansion device, the level of the second in-place signal pin of the slot can be obtained, and then the bandwidth of the slot connected to the root port can be identified according to the level of the second in-place signal pin of the slot, and the corresponding bandwidth allocation is performed on the root port accordingly. The firmware is developed once to form a standard PCIe bandwidth resource adaptive allocation function module. When designing the server motherboard, the first in-place signal pin of the PCIe slot is connected to the universal input / output interface of the first interface expansion device, and the second in-place signal pin of the PCIe slot is connected to the universal input / output interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources of various platforms, various models, and various configurations can be achieved. This method does not need to occupy the general input and output interface resources of the south bridge, nor does it require the participation of the baseboard management controller, and can achieve the allocation of any bandwidth combination. In addition, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe Switch side.

[0146] The present invention also provides a bandwidth allocation device, referring to Figure 7 As shown, the device includes a memory 1 and a processor 2 .

[0147] Memory 1, used for storing computer programs;

[0148] Processor 2 is used to execute the computer program to implement the following steps:

[0149] The universal input / output interface of the first interface expansion device is controlled to output a high level of a preset duration; the first in-place signal pin of each slot is connected to the universal input / output interface of the first interface expansion device; during the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration, the level of the universal input / output interface of the second interface expansion device corresponding to the root port is read; the second in-place signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-place signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot to which the root port is connected is identified according to the level of the universal input / output interface of the second interface expansion device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected.

[0150] For an introduction to the device provided by the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0151] In some embodiments, the memory 1 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function, etc.; the data storage area may store data created during use.

[0152] In addition, the memory 1 may include a read-only memory and a random access memory, and provides instructions and data to the processor 2. A portion of the memory 1 may also include an NVRAM. The memory 1 stores an operating system and operating instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, wherein the operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic tasks and processing hardware-based tasks.

[0153] The processor 2 may be a central processing unit (CPU), an application specific integrated circuit, a digital signal processor, a field programmable gate array or other programmable logic device, a microprocessor or any conventional processor, etc. The processor 2 may call a program stored in the memory 1.

[0154] The communication interface is used to connect to other devices or systems. Figure 7 The structure shown does not constitute a limitation on the bandwidth allocation device in the embodiment of the present invention. In actual applications, the bandwidth allocation device may include Figure 7 More or fewer components than shown, or combinations of certain components.

[0155] In the bandwidth allocation device provided by the present invention, the first in-place signal pin of the slot is not directly grounded, but connected to the universal input / output interface of the first interface expansion device, and the second in-place signal pin of the slot is connected to the universal input / output interface of the second interface expansion device. By controlling the universal input / output interface of the first interface expansion device to output a high level, the level of the first in-place signal pin connected to the universal input / output interface of the first interface expansion device can be raised. By reading the level of the universal input / output interface of the second interface expansion device, the level of the second in-place signal pin of the slot can be obtained, and then the bandwidth of the slot connected to the root port can be identified according to the level of the second in-place signal pin of the slot, and the root port can be allocated bandwidth accordingly. The firmware is developed once to form a standard PCIe bandwidth resource adaptive allocation function module. When designing the server motherboard, the first in-place signal pin of the PCIe slot is connected to the universal input / output interface of the first interface expansion device, and the second in-place signal pin of the PCIe slot is connected to the universal input / output interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources of various platforms, various models, and various configurations can be achieved. This method does not need to occupy the general input and output interface resources of the south bridge, nor does it require the participation of the baseboard management controller, and can achieve the allocation of any bandwidth combination. In addition, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe Switch side.

[0156] The present invention also provides a computer program product, comprising a computer program / instruction, wherein when the computer program / instruction is executed by a processor, the following steps are implemented:

[0157] The universal input / output interface of the first interface expansion device is controlled to output a high level of a preset duration; the first in-place signal pin of each slot is connected to the universal input / output interface of the first interface expansion device; during the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration, the level of the universal input / output interface of the second interface expansion device corresponding to the root port is read; the second in-place signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-place signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot to which the root port is connected is identified according to the level of the universal input / output interface of the second interface expansion device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected.

[0158] In the computer program product provided by the present invention, the first in-place signal pin of the slot is not directly grounded, but connected to the universal input / output interface of the first interface expansion device, and the second in-place signal pin of the slot is connected to the universal input / output interface of the second interface expansion device. By controlling the universal input / output interface of the first interface expansion device to output a high level, the level of the first in-place signal pin connected to the universal input / output interface of the first interface expansion device can be raised. By reading the level of the universal input / output interface of the second interface expansion device, the level of the second in-place signal pin of the slot can be obtained, and then the bandwidth of the slot connected to the root port can be identified according to the level of the second in-place signal pin of the slot, and the corresponding bandwidth allocation is performed on the root port accordingly. The firmware is developed once to form a standard PCIe bandwidth resource adaptive allocation function module. When designing the server motherboard, the first in-place signal pin of the PCIe slot is connected to the universal input / output interface of the first interface expansion device, and the second in-place signal pin of the PCIe slot is connected to the universal input / output interface of the second interface expansion device. By running the firmware, efficient and accurate allocation of PCIe bandwidth resources of various platforms, various models, and various configurations can be achieved. This method does not need to occupy the general input and output interface resources of the south bridge, nor does it require the participation of the baseboard management controller, and can achieve the allocation of any bandwidth combination. In addition, this method can be used not only for PCIe root port bandwidth allocation on the CPU side, but also for PCIe root port bandwidth allocation on the PCIe Switch side.

[0159] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:

[0160] The universal input / output interface of the first interface expansion device is controlled to output a high level of a preset duration; the first in-place signal pin of each slot is connected to the universal input / output interface of the first interface expansion device; during the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration, the level of the universal input / output interface of the second interface expansion device corresponding to the root port is read; the second in-place signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-place signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot to which the root port is connected is identified according to the level of the universal input / output interface of the second interface expansion device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected.

[0161] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0162] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiment, and the present invention will not elaborate on it here.

[0163] The present invention also provides a bandwidth allocation system, comprising:

[0164] A processor, a first interface expansion device, and a second interface expansion device;

[0165] The processor is used to control the universal input / output interface of the first interface expansion device to output a high level of a preset duration; the first in-place signal pin of each slot is connected to the universal input / output interface of the first interface expansion device; during the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration, the level of the universal input / output interface of the second interface expansion device corresponding to the root port is read; the second in-place signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-place signal pin of the slot is related to the bandwidth of the slot; the bandwidth of the slot to which the root port is connected is identified according to the level of the universal input / output interface of the second interface expansion device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected.

[0166] For an introduction to the bandwidth allocation system provided by the present invention, please refer to the above method embodiment, and the present invention will not be elaborated here.

[0167] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0168] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0169] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0170] The bandwidth allocation method, device, equipment, system, medium and program product provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation method of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A bandwidth allocation method, characterized in that: include: Control the universal input / output interface of the first interface expansion device to output a high level of a preset duration; the first in-position signal pin of each slot is connected to the universal input / output interface of the first interface expansion device; During the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration, the level of the universal input / output interface of the second interface expansion device corresponding to the root port is read; the second in-position signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-position signal pin of the slot is related to the bandwidth of the slot; the universal input / output interface of the second interface expansion device has a one-to-one correspondence with the channels of the root port; the second in-position signal pin of the slot is connected to the universal input / output interface corresponding to the channel with the largest sequence number among the channels used by the slot; Identify the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface extension device, and allocate bandwidth to the root port according to the bandwidth of the slot to which the root port is connected; Identifying the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface expansion device includes: According to the level of the universal input / output interface of the second interface expansion device corresponding to the root port, a level truth table is queried to identify the bandwidth of the slot to which the root port is connected; the level truth table includes the correspondence between the level of the universal input / output interface of the second interface expansion device and the bandwidth of the slot.

2. The bandwidth allocation method according to claim 1, characterized in that: The second presence signal pins of different slots connected to the root port are all connected to the universal input and output interface of the same second interface expansion device corresponding to the root port, and the second presence signal pins of each slot connected to the same root port are connected to different universal input and output interfaces.

3. The bandwidth allocation method according to claim 2, characterized in that: The root port includes sixteen channels, and second in-place signal pins of different slots accessed by the sixteen channels are all connected to the universal input / output interface of the same second interface expansion device corresponding to the root port.

4. The bandwidth allocation method according to claim 3, characterized in that: The second interface expansion device includes sixteen general input and output interfaces.

5. The bandwidth allocation method according to claim 1, characterized in that: The level truth table also includes a correspondence between the channel of the root port and the universal input and output interface of the second interface expansion device.

6. The bandwidth allocation method according to claim 1, characterized in that: The first interface expansion device includes sixteen general input and output interfaces.

7. The bandwidth allocation method according to claim 1, characterized in that: Controlling the universal input / output interface of the first interface expansion device to output a high level of a preset duration includes: The universal input and output interfaces of the first interface expansion device are controlled to sequentially output high levels of a preset duration.

8. The bandwidth allocation method according to claim 1, characterized in that: Before controlling the universal input / output interface of the first interface expansion device to output a high level of a preset duration, the method further includes: The first interface expansion device is set to an output mode, and each general input / output interface of the first interface expansion device is set to output a low level.

9. The bandwidth allocation method according to claim 1, characterized in that: Also includes: The second interface expansion device is set to input mode.

10. The bandwidth allocation method according to claim 1, characterized in that: The second in-position signal pin of each slot is also connected to a hot-plug monitoring logic circuit.

11. The bandwidth allocation method according to claim 1, characterized in that: Also includes: If the second on-site signal pin of the slot to which the corresponding first on-site signal pin belongs is continuously at a low level during the period when the universal input / output interface of the first interface expansion device outputs a high level, an exception is reported.

12. The bandwidth allocation method according to claim 1, characterized in that: Also includes: If the second on-site signal pin of the slot to which the corresponding first on-site signal pin belongs is continuously at a low level during the period when the universal input / output interface of the first interface expansion device outputs a high level, the universal input / output interface of the first interface expansion device is controlled to no longer output a high level.

13. The bandwidth allocation method according to claim 1, characterized in that: Controlling the universal input / output interface of the first interface expansion device to output a high level of a preset duration includes: The universal input / output interface of the first interface expansion device is controlled via the system management bus to output a high level of a preset duration.

14. The bandwidth allocation method according to claim 1, characterized in that: Reading the level of the general input / output interface of the second interface expansion device corresponding to the root port includes: The level of the general input / output interface of the second interface expansion device is read through the system management bus.

15. A bandwidth allocation device, characterized in that: include: A control module, used for controlling the universal input / output interface of the first interface expansion device to output a high level of a preset duration; the first in-position signal pin of each slot is connected to the universal input / output interface of the first interface expansion device; a reading module, configured to read the level of the universal input / output interface of the second interface expansion device corresponding to the root port during the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration; the second in-position signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-position signal pin of the slot is related to the bandwidth of the slot; the universal input / output interface of the second interface expansion device corresponds to the channel of the root port one by one; the second in-position signal pin of the slot is connected to the universal input / output interface corresponding to the channel with the largest sequence number among the channels used by the slot; an allocation module, configured to identify the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface extension device, and allocate bandwidth to the root port according to the bandwidth of the slot to which the root port is connected; Identifying the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface expansion device includes: querying a level truth table to identify the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface expansion device corresponding to the root port; the level truth table includes a correspondence between the level of the universal input / output interface of the second interface expansion device and the bandwidth of the slot.

16. A bandwidth allocation device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the bandwidth allocation method according to any one of claims 1 to 14 when executing the computer program.

17. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the bandwidth allocation method according to any one of claims 1 to 14 are implemented.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the bandwidth allocation method according to any one of claims 1 to 14 are implemented.

19. A bandwidth allocation system, characterized in that: include: A processor, a first interface expansion device, and a second interface expansion device; The processor is used to control the universal input / output interface of the first interface expansion device to output a high level of a preset duration; the first in-place signal pin of each slot is connected to the universal input / output interface of the first interface expansion device; during the period when the universal input / output interface of the first interface expansion device outputs a high level of a preset duration, the level of the universal input / output interface of the second interface expansion device corresponding to the root port is read; the second in-place signal pin of each slot is connected to the universal input / output interface of the second interface expansion device, and the universal input / output interface of the second interface expansion device connected to the second in-place signal pin of the slot is related to the bandwidth of the slot; the universal input / output interface of the second interface expansion device has a one-to-one correspondence with the channels of the root port; the second in-place signal pin of the slot is connected to the universal input / output interface corresponding to the channel with the largest sequence number among the channels used by the slot; the bandwidth of the slot to which the root port is connected is identified according to the level of the universal input / output interface of the second interface expansion device, and the bandwidth of the root port is allocated according to the bandwidth of the slot to which the root port is connected; Identifying the bandwidth of the slot to which the root port is connected according to the level of the universal input / output interface of the second interface expansion device comprises: according to the level of the universal input / output interface of the second interface expansion device corresponding to the root port, querying a level truth table to identify the bandwidth of the slot to which the root port is connected; The level truth table includes a correspondence between the level of the universal input / output interface of the second interface expansion device and the bandwidth of the slot.

Images