Storage device, method for improving performance of a storage device, and electronic device

Abstract

Embodiments of the present disclosure provide a storage device, a method for improving performance of the storage device, and an electronic device. A storage device includes a storage chip including a plurality of storage units, an electrical pulse generator, and a processor. The processor is configured to determine a target storage unit in which a leakage current of a plurality of storage units is not lower than a threshold leakage current, and trigger the electrical pulse generator to apply an electrical pulse to the target storage unit, the applied electrical pulse causing the leakage current of the target storage unit to be lower than the threshold leakage current. In this way, embodiments of the present disclosure can improve the reliability of the storage device, so that the magnitude of the leakage current is within a desired range after, for example, a high-temperature process, meeting the needs of high-density integration.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor devices, and more particularly, to a storage device, a method for improving performance of the storage device, and an electronic device. BACKGROUND

[0002] With the booming development of big data and cloud computing, in order to realize high-density storage, the size of the storage unit in the memory array is getting smaller and the integration density of the memory is getting higher. However, there is a leakage path in the cross-matrix structure of the memory array. In some cases, a transistor is usually used as a selection device to select the corresponding storage unit to block the misoperation of the crosstalk current to other storage units. However, since the transistor itself is a three-terminal active device, it increases the complexity of the integrated process, and at the same time, due to the large occupied area, it is difficult to miniaturize the cross array, thereby affecting the high-density integration of the cross array.

[0003] In recent years, the selection device (1S) represented by the ovonic threshold switching (OTS) replaces the transistor, which can be connected in series with the new type of non-volatile storage unit (1R) such as phase change storage, resistive switching storage, and magnetic storage, to form a cross array structure based on the 1S1R unit. This cross array structure benefits from the two-terminal selection device to save the occupied area. In addition, such devices can be stacked in 3D layers, thereby further realizing extremely high integration density. However, such selection devices will undergo high-temperature processes such as post-interconnection during the preparation process. This may cause the material performance of such selection devices to deteriorate, resulting in an increase in leakage current, and even the disappearance of the selection characteristics. At present, the reliability is improved by element doping for composition optimization or deposition of a heat-resistant buffer film for structure optimization, but the effect of such solutions is limited and the complex processing process increases the cost. SUMMARY

[0004] In view of the above problems, embodiments of the present disclosure aim to provide a scheme for improving the performance of the memory, for example, to improve the reliability of the OTS device, so that the size of the leakage current of the OTS device after the high-temperature process is within the desired range, meeting the needs of high-density integration.

[0005] According to a first aspect of the present disclosure, a storage device is provided. The storage device comprises a storage chip, an electric pulse generator, and a processor, the storage chip comprising a plurality of storage units. The processor is configured to determine a target storage unit in the plurality of storage units whose leakage current is not lower than a threshold leakage current, and trigger the electric pulse generator to apply an electric pulse to the target storage unit, the applied electric pulse making the leakage current of the target storage unit lower than the threshold leakage current.

[0006] Therefore, in the embodiments of the present disclosure, the storage unit with low reliability or post-operation leakage deterioration is repaired, so that the storage unit after high-temperature process can still maintain the switching characteristics, and the magnitude of the leakage current thereof is within the expected range.

[0007] In some embodiments of the first aspect, the processor is configured to, when determining the target storage unit in the plurality of storage units with leakage current not lower than the threshold leakage current, perform a read operation on the plurality of storage units to determine the leakage current of each storage unit; and compare the leakage current of each storage unit with the threshold leakage current respectively; and determine the storage unit with leakage current not lower than the threshold leakage current as the target storage unit.

[0008] Therefore, by determining the storage unit with leakage current greater than the threshold leakage current as the target storage unit, the deteriorated storage unit can be repaired in a targeted manner, and the refresh efficiency is improved.

[0009] In some embodiments of the first aspect, the voltage of the electrical pulse is greater than the threshold voltage of the target storage unit, or the current of the electrical pulse is greater than the threshold current of the target storage unit.

[0010] Therefore, by applying the electrical pulse with voltage greater than the threshold voltage or current greater than the threshold current to the target storage unit, the OTS material in the deteriorated target storage unit can be molten and quenched to be amorphous, so as to eliminate crystallization or composition segregation aggregation, so that the reliability of the storage unit is improved.

[0011] In some embodiments of the first aspect, the processor is configured to, when triggering the electrical pulse generator to apply the electrical pulse to the target storage unit, trigger the electrical pulse generator to apply the electrical pulse to the target storage unit, the voltage of the electrical pulse being greater than the threshold voltage of the target storage unit, or the current of the electrical pulse being greater than the threshold current of the target storage unit. The processor further determines whether the leakage current of the target storage unit is lower than the threshold leakage current; in response to the leakage current not being lower than the threshold leakage current, increasing the amplitude of the voltage or current of the electrical pulse applied to the target storage unit until the leakage current of the target storage unit is lower than the threshold leakage current.

[0012] Therefore, the electrical pulse with gradually increasing amplitude is applied to the target storage unit with serious leakage, so as to ensure that the deteriorated target storage unit can restore the switching characteristics and maintain the corresponding leakage criterion.

[0013] In some embodiments of the first aspect, the electrical pulse applied by the electrical pulse generator to the target storage unit is a voltage pulse or a current pulse with pulse width greater than 20 ns and falling edge less than 100 ns.

[0014] Thus, by applying a series of electrical pulses with specific parameters to the deteriorated target memory cell, the crystallization and composition segregation of the OTS material due to heat, for example, is eliminated, so that the leakage current of the target memory cell is reduced, and the switching characteristics are maintained.

[0015] In some embodiments of the first aspect, the processor is further configured to: determine a first threshold voltage for a first target memory cell in the set of target memory cells; and compare the first threshold voltage with a reference voltage; and instruct the electrical pulse generator to apply an electrical pulse if the first threshold voltage is higher than the reference voltage.

[0016] Thus, by comparing the threshold voltage of the target memory cell with the reference voltage, the cell with a larger threshold voltage drift is selected, and the individual target memory cell with inconsistent threshold voltage distribution is repaired again, further improving the reliability.

[0017] In some embodiments of the first aspect, the reference voltage represents an arithmetic mean or a weighted mean of the threshold voltages of some or all of the memory cells in the set of target memory cells.

[0018] In some embodiments of the first aspect, the processor is configured to, when determining the first threshold voltage for the first target memory cell, apply a first test voltage to the first target memory cell; and determine the first threshold voltage based on a test result of the first target memory cell under the application of the first test voltage.

[0019] Thus, by determining the threshold voltage of each target memory cell in the set of target memory cells that meets the leakage criterion to obtain the reference voltage to determine the distribution of the threshold voltages of the target memory cells.

[0020] In some embodiments of the first aspect, if the first threshold voltage is higher than the reference voltage, the electrical pulse generator is continuously instructed to apply an electrical pulse to the target memory cell until the first threshold voltage is not higher than the reference voltage.

[0021] Thus, by applying multiple electrical pulses, the threshold voltage of each target memory cell tends to be consistent, thereby improving the reliability of the memory chip.

[0022] In some embodiments of the first aspect, the processor is configured to: apply an electrical pulse to the first target memory cell when the difference between the first threshold voltage and the reference voltage is greater than a predetermined margin.

[0023] Thus, the individual target memory cell with a larger threshold voltage drift is repaired again, which can ensure the reliability while improving the efficiency.

[0024] According to a second aspect of the present disclosure, there is provided an electronic device comprising a controller and a storage device according to the first aspect of the present disclosure, the controller being configured to read data from the storage device or write data to the storage device.

[0025] According to a third aspect of the present disclosure, there is provided a method for improving performance of a storage device, the storage device comprising a storage chip, an electrical pulse generator, a processor, the storage chip comprising a plurality of storage units. The method comprises: determining, by the processor, a target storage unit of the plurality of storage units whose leakage current is not lower than a threshold leakage current; and applying, by the electrical pulse generator, an electrical pulse to the target storage unit to make the leakage current of the target storage unit lower than the threshold leakage current.

[0026] According to some embodiments of the third aspect of the present disclosure, the method further comprises: determining, in response to applying the electrical pulse, the leakage current of the target storage unit; and increasing, in response to the leakage current not being lower than the threshold leakage current, a magnitude of the electrical pulse to be applied to the target storage unit.

[0027] Thus, the electrical pulse with gradually increasing magnitude is applied to the target storage unit with serious leakage, so as to ensure that the deteriorated target storage unit can restore the switching characteristic, and the corresponding leakage criterion is maintained.

[0028] According to a fourth aspect of the present disclosure, there is provided an electronic device comprising at least one processor and at least one memory. The at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor. The instructions, when executed by the at least one processor, cause the electronic device to perform the method according to the third aspect of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other features, advantages, and other aspects of embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which like reference characters refer to like elements throughout. In the drawings:

[0030] Figure 1 FIG. 1 shows a structural schematic diagram of a storage chip according to an embodiment of the present disclosure;

[0031] Figure 2 FIG. 2 shows a current-voltage characteristic curve diagram of an OTS device according to an embodiment of the present disclosure;

[0032] Figure 3 a shows a structural schematic diagram of a storage unit according to an embodiment of the present disclosure;

[0033] Figure 3 b shows a structural schematic diagram of a storage unit according to another embodiment of the present disclosure;

[0034] Figure 4 a schematic block diagram of a storage device according to an embodiment of the present disclosure is shown;

[0035] Figure 5 a flowchart of an example method according to an embodiment of the present disclosure is shown;

[0036] Figure 6 a current-voltage characteristic plot of a single OTS device after undergoing a high temperature process is shown;

[0037] Figure 6 a current-voltage characteristic plot of a single degraded OTS device after a repair operation according to an embodiment of the present disclosure is shown;

[0038] Figure 7 a plot of leakage current distribution comparison of multiple degraded OTS devices after a repair operation according to an embodiment of the present disclosure is shown;

[0039] Figure 8 a flowchart of an example method according to another embodiment of the present disclosure is shown;

[0040] Figure 9 a plot of threshold voltage distribution comparison of different storage cells before and after a refresh operation according to an embodiment of the present disclosure is shown;

[0041] Figure 10 a schematic diagram of an example integrated circuit for improving memory according to an embodiment of the present disclosure is shown;

[0042] Figure 11 a block diagram of a computing device according to embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0043] Embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be interpreted as being limited to the embodiments set forth herein, but rather, these embodiments are provided so that the present disclosure can be more thoroughly and completely understood. It is understood that the drawings and embodiments of the present disclosure are for exemplary purposes only and are not intended to limit the scope of protection of the present disclosure.

[0044] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below. The term "and / or" means at least one of the two items associated therewith. For example, "A and / or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below. In addition, even when describing specific numerical examples, they may be numerical values ​​exceeding a specific value or numerical values ​​less than a specific value, in addition to being theoretically obvious as being limited to numerical values.

[0045] It should be understood that the technical solutions provided in the embodiments of this application may not be repeated in the following description of specific embodiments, but it should be regarded as that there are mutual references between these specific embodiments and they can be combined with each other.

[0046] As mentioned above, memory cells suffer from decreased reliability due to the high-temperature processing of gating materials such as OTS materials. A common approach is to improve reliability by doping Ge-As-Se materials with elements like C and Si, such as Ge-Si-As-Se or Ge-Si-As-Te. However, Si, Se, and As are sensitive to moisture in the air and can easily generate highly toxic substances during fabrication. Secondly, the complex composition of these high-reliability systems, especially Ge and Se, can lead to element migration and segregation during repeated write / erase cycles, resulting in increased leakage current and device failure. Another common approach is to improve reliability through structural optimization using buffer layers, multilayer films, etc., such as the Ge / NSbSe multilayer film structure design. However, the improvement offered by buffer layers or multilayer films is currently limited. They still struggle to withstand the 400°C high-temperature processing for OTS materials with low crystallization (or glass transition) temperatures. Furthermore, the deposition cost of multilayer films is higher, reducing their cost advantage. Therefore, current solutions for improving reliability have limited effectiveness and introduce increased costs and safety issues.

[0047] Embodiments of this disclosure provide a method for improving the performance of a memory. This method improves the reliability of an 1S1R memory cell in a simple and efficient manner by applying an electrical pulse to a degraded memory cell using an electrical pulse generation device, thereby restoring the initial switching characteristics of the gating device in the memory cell before high-temperature annealing. Specifically, in some embodiments, by employing embodiments of this disclosure, the leakage current of memory cells that have undergone, for example, high-temperature back-end processes (e.g., temperature T > 400°C) can be kept within a desired range.

[0048] Figure 1 A schematic diagram of a memory chip 100 according to an embodiment of the present disclosure is shown. In some embodiments, the memory chip 100 may be implemented as a three-dimensional memory cell cross array, for example, including a plurality of memory cells 101-104 arranged in row and column directions. The memory cells 101-104 are respectively connected to corresponding bit lines BL0, BL1 and corresponding word lines WL0, WL1. It should be understood that... Figure 1 Only four memory cells are shown, but the example embodiment is not limited to this, and the number of rows (bit lines BL) and columns (word lines WL) can both be any integer greater than 1. Each memory cell may include a memory element and an OTS gate device connected in series therewith. The memory element may include, for example, at least one of phase-change, resistive-change, or magnetic tunnel junction memory elements. This disclosure is not limited thereto; the memory element may also be any two-terminal memory element that meets the circuit requirements.

[0049] In one embodiment, Figure 1 The gating device shown can be a two-terminal gating device with OTS characteristics. OTS devices typically exhibit nonlinear voltage-current (IV) characteristics, such as... Figure 2 As shown in the diagram. When the applied voltage is less than the threshold voltage (Vth), the current in the OTS device is very small, maintaining a high resistance and being in the off state (the off state shown by the dashed line in the diagram). When the applied voltage exceeds the threshold, the current in the OTS device increases rapidly, changing to a low resistance and being in the on state (the on state shown by the dashed line in the diagram). The OTS device has a holding voltage Vhold. As the voltage gradually decreases until it drops to Vhold, the current in the OTS device will not decrease rapidly, i.e., it will not easily turn off (the on state shown by the solid line in the diagram). When the voltage decreases below Vhold, the OTS returns to a high resistance and is in the off state (the off state shown by the solid line in the diagram). Figure 2 The IV characteristics of the OTS device shown are illustrated only with a curve when a positive voltage is applied, as an example. The OTS device, as a bidirectional threshold switch, also exhibits similar IV characteristics when a negative voltage is applied (not shown).

[0050] In some embodiments, the current at half the threshold voltage Vth of the OTS device is defined as the leakage current of a single device. A smaller leakage current allows for greater integration density of the memory array and correspondingly lower power consumption. In some embodiments, if the read current of a 1K×1K cross array is 1 microamp (mA), then the leakage current in a single bidirectional threshold switching device should be less than 1 nanoamp (nA). In other words, for this 1K×1K cross array, the threshold leakage current is 1 nA, and the leakage current must be less than the threshold leakage current to ensure normal read and write operations for each memory element. That is, in some embodiments, the threshold leakage current is set based on the size of the memory array and the read current for that array. It should be understood that in other embodiments, the current at 1 / 3 or other proportions of the threshold voltage Vth of the OTS device may also be defined as the leakage current of a single device. This disclosure does not limit this.

[0051] The following is combined Figure 3 a-3b will describe in detail the operation of the storage unit according to embodiments of the present disclosure. Figure 3 A schematic diagram of a storage unit 300 according to an embodiment of the present disclosure is shown. Before describing the operation of the storage unit 300, the following will be introduced: Figure 3 The memory cell structure shown in figure a. The memory cell 300 includes an integrated cell structure located between word line 301 and bit line 302. This integrated cell structure includes a top electrode 303, a memory element 304, an upper buffer layer 305, an OTS device 306, a lower buffer layer 307, and a lower electrode 308 stacked sequentially. Subsequently, the aforementioned stacked layers are processed using appropriate hard mask materials, double exposure lithography, multiple etching protection, ALD filling, and other processes to fabricate the structure shown in figure a. Figure 3 The unit structure shown in figure a integrates PCM components and OTS devices.

[0052] The upper electrode 303 and the lower electrode 308 are made of, for example, an inert metallic material, and may be made of the same or different materials. Inert metallic materials include at least one of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO, and IZO, or an alloy material composed of any two or more combinations of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO, and IZO. In some embodiments, the film thickness of the upper and lower electrodes can be any thickness from 35 nm to 100 nm. The upper and lower buffer layers 305 and 307 may, for example, include: an amorphous carbon layer (or C-Si, CS(Te, S) compounds), and one or more of MoTe2, MoS2, MnTe, HfO2 / TaO / Al2O3, WTe2, and WS2). The thickness of the upper and lower buffer layers 305 and 307 can be any thickness from 5 nm to 20 nm.

[0053] In one embodiment, the storage element 304 may be a phase-change memory (PCM) type storage element. The PCM element may be made of GST material along the GeTe-Sb2Te3 pseudo-binary line, such as ternary compounds and their dopants, such as Ge2Sb2Te5, Ge1Sb4Te7, Ge1Sb2Te4, Ge3Sb2Te6, etc. The PCM element may also be made by doping Sb2Te3 material with elements such as Ti, Ta, Zr, Hf, and In. The OTS device 306 is a Te / Se / S-based binary or multi-element OTS material with the switching characteristics described above, and may include, but is not limited to, GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, and GeSe, and may be doped with one or more of the following elements: small amounts of B, C, N, Ge, Si, Al, Zn, Ga, S, Se, and As.

[0054] The above materials can be formed using any preparation method in the art, and this disclosure does not impose any limitations. In some embodiments, physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, or metal-organic deposition processes can be used to prepare OTS materials and buffer layer materials. It should be understood that the numerical values ​​or ranges described above and in other parts of this document are merely exemplary and intended to help the reader understand the ideas of the embodiments of this disclosure. Any other suitable numerical values / ranges are possible, and the scope of this disclosure is not limited in this respect. Furthermore, the materials / elements exemplified in the embodiments of this disclosure are merely exemplary, and this disclosure does not impose any limitations on them.

[0055] As mentioned above Figure 2As described above, when the voltage applied to the OTS device is greater than the threshold voltage Vth or greater than the holding voltage Vhold, the OTS device is in the ON state, selecting the connected storage element 304. In this case, the operation of the storage element 304 depends on the magnitude of the voltage applied to it. When no voltage is applied to the OTS device or a voltage less than Vhold / Vth is applied, the current flowing through the OTS device is extremely small, and the OTS device is in the OFF state. Correspondingly, the current flowing through the storage element 304 connected in series with the OTS device is also extremely small. If the OTS device deteriorates, causing Vth to decrease, then when a small voltage is applied to the OTS, it will turn on, thereby selecting the storage element 304 connected in series with the OTS device, resulting in malfunction.

[0056] Due to this nonlinear IV-switching characteristic, OTS devices can not only be integrated into memory arrays as gating devices, but also achieve non-volatile storage by switching between high and low resistance states through electrical operations of different polarities, such as... Figure 3 As shown in b. Figure 3 b shows a schematic diagram of the structure of a storage unit 300' according to another embodiment of the present disclosure. The storage unit 300' has... Figure 3 The memory cell 300 in memory structure 300' has a similar structure. The difference is that the OTS device 306' in memory structure 300' combines gating and storage functions, eliminating the need for... Figure 3 Storage element 304 in a. Therefore, the overall material can be simplified during fabrication, process costs can be further reduced, and storage density can be further increased due to structural optimization. The upper and lower electrodes 303' and 308', and the upper and lower buffer layers 305' and 307' of storage cell 200' have the same or similar structure / material / composition as the upper and lower electrodes 303 and 308, and the upper and lower buffer layers 305 and 307 of memory structure 300. Therefore, regarding Figure 3 The various aspects described for memory structure 300 can be applied to Figure 3 The memory structure 300' in b will not be described in detail here.

[0057] Figure 4 An example block diagram of a storage device 400 according to an embodiment of the present disclosure is shown. The storage device 400 includes a storage chip 402, an electrical pulse generator 406, and a processor 408. The storage chip 402 includes a plurality of storage cells 404. In some embodiments, the structure of the storage cells 404 is similar to... Figure 3 The storage cells 300 and 300' have the same or similar structure, therefore regarding Figure 3 The described aspects can be applied to Figure 4 The storage devices will not be discussed further here.

[0058] Processor 408 identifies target memory cells among a plurality of memory cells 404 whose leakage current is not lower than a threshold leakage current. Processor 408 performs a read operation on the plurality of memory cells 404 to determine the leakage current for each memory cell, and compares the determined leakage current with the threshold leakage current to identify the memory cells among the plurality of memory cells whose leakage current is not lower than the threshold leakage current as target memory cells. Processor 408 also triggers electrical pulse generator 406 to apply an electrical pulse to the identified target memory cells, causing the leakage current of the target memory cells to fall below the threshold leakage current.

[0059] In some embodiments, the electrical pulses applied by the electrical pulse generator 406 include voltage pulses or current pulses with a pulse width greater than 20 ns and a fall edge less than 100 ns. (The following is in conjunction with...) Figure 5 The electrical pulses applied by the electrical pulse unit 406 are described in detail.

[0060] Figure 5 A flowchart of an example method 500 according to an embodiment of the present disclosure is shown. It will be understood that the above is aimed at... Figures 1 to 4 The various aspects described may be selectively applied to method 500. It should be understood that method 500 may also include additional boxes not shown and / or certain boxes shown may be omitted. The scope of this disclosure is not limited in this respect. Figure 5 Method 500 can be executed by a computer, and more specifically, by a processor according to instructions stored in a read-only memory, which is a transient memory storing volatile information whose data is volatile after power loss. It is understood that this read-only memory differs from the memory targeted by method 500, which is generally non-volatile memory. In the following description, unless otherwise stated, "memory" refers by default to the memory targeted by the various embodiments of this disclosure. Alternatively, method 500 can also be executed by other electronic devices with computing or processing capabilities, such as a field-programmable gate array (FPGA), without limitation by this disclosure. It is understood that method 500 can be executed after the memory device is manufactured and before it is sold to obtain optimized performance. Alternatively or additionally, it can also be executed after the user has used the memory for a period of time and the memory has deteriorated.

[0061] In block 510, processor 408 performs a read operation on memory cells 404 in memory chip 402 to determine the leakage current for each memory cell 404, and compares the determined leakage current with a threshold leakage current to identify the memory cells whose leakage current is not lower than the threshold leakage current as target memory cells. (As previously mentioned...) Figure 2The description uses the leakage current Ioff at half the threshold voltage of the OTS device as an example. This is illustrated by examining multiple memory cells 101-104 (…). Figure 1 Each cell in the memory cell is read to determine the leakage current Ioff for each memory cell.

[0062] The read voltage depends on the type of gating device in the memory. In some embodiments, taking an OTS device made of phase change material as an example, if the threshold voltage of the OTS device is set to Vth1, and the threshold voltage of the amorphous phase change material itself is Vth2, then the read voltage of the entire memory cell is Vth1 < Vread < (Vth1 + Vth2). In some embodiments, Vth1 ranges from 1V to 5V, and Vth2 ranges from 0.5V to 4V. In other embodiments, Vth1 is approximately 2V, and Vth2 is approximately 1V. In this embodiment, during a read operation, the read voltage can be slightly higher than the threshold voltage of Vth1 + 0.5V.

[0063] refer to Figure 1 In some embodiments, 1 / 2 Vread is applied to a selected bit line, such as BL0, and -1 / 2 Vread is applied to a selected word line WL0. The voltage applied to the memory cell 101 at the intersection of the bit line BL0 and the word line WL0 is then Vread. This selects the memory cell 101 and allows reading. However, if the leakage current of the memory cell 101 is too large, it can cause a large current to flow in the adjacent memory cell 102 on the same bit line BL0. In this case, the memory cell 102 may also be selected, leading to a read error.

[0064] At block 520, an electrical pulse generator 406 applies an electrical pulse to the target memory cell to reduce the leakage current of the target memory cell below a threshold leakage current. The electrical pulse generator 406 can generate a corresponding electrical pulse based on pulse waveform data, which may include at least one of pulse parameters such as amplitude, polarity, pulse width, frequency, duty cycle, rise edge width, and fall edge width. In some embodiments, the electrical pulse is a stepped-wave electrical pulse with an amplitude greater than the threshold voltage (current), a fall edge width less than 100 ns, and a pulse width greater than 1 μs. After the electrical pulse is applied to the degraded or high-leakage target memory cell, the OTS material undergoes melting and quenching, becoming amorphous, thereby eliminating crystallization or compositional segregation caused by high-temperature heating. Thus, the OTS device re-operates in an amorphous state, reducing the leakage current in the half-gated (1 / 2·Vread) state, thereby improving the performance of the memory cell integrating the OTS device. It is understood that the pulse parameters described above are merely examples and not intended to limit the scope of this disclosure. In some other cases, electrical pulses with different parameters can be used on other storage devices to eliminate crystallization or component segregation caused by high-temperature heating, thereby reforming the amorphous state.

[0065] The parameters of the repair electrical pulse can be set for different memory chips (OTS + different memory elements) and different phase change materials and component ratios. In some embodiments, the pulse width is greater than 20 ns and the falling edge is less than 100 ns. In other embodiments, the pulse width can be greater than 1 μs and the falling edge can be greater than 8 ns and less than 50 seconds. The parameters of the above electrical pulse can vary depending on different integrated cell structures and materials, that is, they can be other numerical ranges. This disclosure does not impose any limitations on the numerical range or magnitude.

[0066] Furthermore, in some embodiments, because different memory cells have different initial degradation levels, the leakage current of individual memory cells may recover to the desired range after only a single electrical pulse. In other embodiments, for memory cells with higher degradation levels, multiple electrical pulses need to be applied to restore their leakage current to the desired range.

[0067] At block 530, in response to the application of an electrical pulse at block 520, processor 408 determines the leakage current of the target memory cell to assess leakage. If the leakage criterion ("Yes" in the figure) is met, i.e., the leakage current is below the threshold leakage current, the process proceeds to block 560; if the leakage criterion ("No" in the figure) is not met, i.e., the leakage current is still not below the threshold leakage current, the process proceeds to block 550, where an electrical pulse with an amplitude increased by ΔV or ΔI is applied to the memory cell. In some embodiments, the pulse width and falling edge of the electrical pulse can be the same as the parameters used when the pulse was previously applied. The steps in blocks 530 to 550 are repeated, with the amplitude of the electrical pulse increased by nΔV or nΔI, until it is determined that the memory cell meets the leakage criterion, i.e., the leakage current is less than the threshold leakage current. Then, the process proceeds to block 560, and the method ends.

[0068] Figure 6 Figure 500 shows the current-voltage characteristic curve of a single gating device after high-temperature treatment. Taking the OTS gating device as an example, when the OTS material is Ge with a low crystallization temperature... 10 Te 90 、Ge 15 Te 85 C4Ge 14 Te 82 After undergoing 400°C annealing for back-end interconnects, most of the OTS devices become low-resistivity due to crystallization, such as... Figure 6 As shown in Figure a, the current gradually increases with increasing applied voltage, and remains constant at approximately 0.7V. Figure 6 The IV curve in a is approximately linear, and the OTS device loses its switching characteristics. The reliability of the memory cell containing this OTS device is reduced.

[0069] Figure 6 b shows Figure 6 A current-voltage characteristic curve 500' of a single degraded OTS device after a repair operation according to an embodiment of the present disclosure. An application such as... Figure 5 The described electrical pulse, when applied to a voltage pulse greater than 3V (or a current pulse greater than 200µs), with a pulse width greater than 500ns and a fall edge of 8ns, causes the OTS device to regain its switching characteristics, such as... Figure 6 As shown in b. At this time, the threshold voltage is about 1.6V and the leakage current is about 10nA. In the embodiments of this disclosure, the degraded memory cells in the memory array are selected and subjected to continuous electrical pulses for electrical repair, which reduces the leakage current generated after the high-temperature process and improves the reliability of the memory array.

[0070] Figure 7Curve 700 shows a comparison of leakage current distributions of multiple degraded OTS devices after a repair operation according to an embodiment of this disclosure. Curve 701, shown as a dashed line, represents the leakage current distribution of multiple memory cells after undergoing a high-temperature process. As can be seen from curve 701, the leakage current distribution of most memory cells, representing approximately 70% or more of the total, is between 100 nA and 1 μA. Curve 702, shown as a solid line, represents the leakage current distribution of multiple memory cells after one repair operation. As can be seen from curve 702, the leakage current of 68% of the memory cells has been reduced to below 10 nA. This demonstrates that after only one repair operation, the leakage current distribution of the memory cells has shifted to the left, i.e., the leakage current has been reduced, improving the overall reliability of the memory array. Furthermore, OTS devices with optimized leakage current distribution are better matched with PCM memory elements that have high drive current requirements, thus possessing significant commercial value in the industry.

[0071] However, in some embodiments, both the first and second target memory cells in the target memory cell set meet the leakage criterion after the repair operation. But their threshold voltages may differ, so only the larger of the two threshold voltages can be applied for read operations. In this case, a voltage much higher than the threshold voltage may still be applied to the memory cell with the smaller threshold voltage, leading to increased power consumption or even read / write errors. The following will refer to... Figure 8 Describe the process of performing operations on storage cells in memory, such as Figure 5 After the repair operation shown, a refresh operation is further applied to make the threshold voltage distribution of different memory cells consistent, thereby satisfying the uniformity requirement.

[0072] Figure 8 A flowchart of an example method 800 according to another embodiment of this disclosure is shown. It will be understood that the above refers to... Figure 1 , Figure 3 , Figure 4 and Figure 6 The various aspects described in a-6b may be selectively applied to method 800. It should be understood that method 800 may also include additional boxes not shown and / or some boxes shown may be omitted. The scope of this disclosure is not limited in this respect. Method 800 may be executed, for example, by a computer, and more specifically, by a processor according to instructions stored in memory. Alternatively, method 800 may also be executed by other electronic devices with computing or processing capabilities, such as by an FPGA, without limitation by this disclosure. It is understood that method 800 may be executed after the memory device is manufactured and before it is sold to obtain optimized performance. Alternatively or additionally, it may also be executed after the user has used the memory for a period of time and the memory has deteriorated.

[0073] At box 810, a read operation is performed on the memory cells in the memory to determine the leakage current. Figure 8 The read operation and the determination criterion for the leakage current in Figure 5 are the same as or similar to the read operation and the determination criterion for the leakage current described previously with respect to

[0074] At box 820, it is determined whether the leakage current of the read memory cell is less than the threshold leakage current. If it is not less than the threshold current ( Figure 8 the "No" in Figure 8 ), it generally means that the memory cell is deteriorated and a repair operation is required, then proceed to box 830. If it is less than the threshold leakage current (

[0075] At box 830, the electric pulse generating device applies an electric pulse with an amplitude greater than the threshold voltage (current) of the memory cell to the memory cell. In this step, the applied electric pulse is the same as or similar to the electric pulse applied in Figure 5 , and all aspects described with respect to boxes 520 to 550 can be applied to boxes 830 to 850, which will not be elaborated here.

[0076] At box 860, in response to determining that the memory cell meets the leakage criterion, the threshold voltage of the memory cell is determined. Determining the threshold voltage of the memory cell includes applying a first test voltage to the first target memory cell to obtain a test result, and based on this test result, determining the first threshold voltage. In some embodiments, assume that the memory cell is in a low resistance state, that is, storing the data "1". The test voltage is applied to the memory cell in the low resistance state from small to large. When the read current significantly increases, the test voltage at this moment is the first threshold voltage of the first target memory cell. Assume that the memory cell is in a high resistance state, then using Vread = first threshold voltage + ΔV (ΔV < Vth2) cannot read a large current. At this time, a write pulse SET is applied to place the memory cell in "1", and then its first threshold voltage is read again.

[0077] At box 860, the threshold voltage is compared with a reference voltage to determine whether the threshold voltage meets the uniformity requirement. In some embodiments, it is determined whether the difference between the threshold voltage of each target memory cell and the reference voltage is less than the margin. In box 870, if the difference is less than the margin ( Figure 8 the "Yes" in Figure 8 ), then end the method (proceed to box 890). If the difference is greater than the margin (

[0078] In block 880, an electrical pulse is applied to the memory cell to perform a refresh operation to further improve reliability. In some embodiments, the electrical pulse applied in block 880 may be the same as or different from the electrical pulse applied in block 830, and this disclosure is not limiting. The operations of blocks 860 to 880 are repeated until the threshold voltages of all memory cells meet the uniformity requirement. The margin may be a percentage or a specific voltage value, and this disclosure is not limiting. In some embodiments, the reference voltage may be the average of the threshold voltages of some or all memory cells in the target memory cell set. In other embodiments, the reference voltage may also be the variance or other mathematical statistical parameter of the threshold voltages of some or all memory cells. This disclosure does not limit the expression of statistical parameters.

[0079] Figure 9 The illustration shows a storage cell in a memory according to an embodiment of the present disclosure. Figure 8 Figure 900 shows a comparison of the threshold voltage distribution before and after the method described. Curve 901 represents the threshold voltage distribution of different memory cells before the refresh operation. It can be seen that the threshold voltage distribution of different memory cells is quite dispersed, with the maximum exceeding 3.5V and the minimum as low as 2V. Under these circumstances, the applied voltage during read operations on the memory array will be limited, leading to a decrease in the overall reliability of the memory array.

[0080] Curve 902 represents the threshold voltage distribution of different memory cells after the refresh operation. It can be seen that the threshold voltage distribution of different memory cells after the refresh operation is uniform, approximately around 2.5V. This allows for the selection of memory cells with larger threshold voltage drifts and their individual correction to achieve a more uniform threshold voltage across the entire memory array, thereby improving array consistency.

[0081] Figure 10 A schematic diagram of an example integrated circuit 1000 for improving a memory according to an embodiment of the present disclosure is shown. The integrated circuit 1000 may be formed as at least a part of a memory device 400. In one embodiment, the integrated circuit 1000 includes, but is not limited to, a read circuit 1001, a PCM-OTS integrated array 1002, and an electrical pulse generation device 1003. The read circuit 1001 is configured to perform a read operation on memory cells in the memory 1002 to obtain the leakage current for each memory cell. The read circuit 1001 also includes a comparator (not shown) configured to compare the leakage current of each memory cell with a threshold leakage current. The read circuit 1001 identifies memory cells with leakage currents greater than the threshold leakage current as a target set of memory cells.

[0082] The electrical pulse generating device 1003 includes an electrical pulse generating unit (not shown in the figure). The electrical pulse generating unit generates voltage or current pulses with an amplitude greater than a threshold voltage or threshold current, a pulse width greater than 20 ns, and a fall edge less than 100 ns. The electrical pulse generating device 1003 applies the aforementioned electrical pulses to each target memory cell in the target memory cell set to perform the above-mentioned... Figure 5 and Figure 8 The described electrical repair operation. It should be understood that the integrated circuit 900 may also include additional circuitry not shown and / or certain circuitry shown may be omitted. The scope of this disclosure is not limited in this respect.

[0083] Figure 11 A schematic block diagram of a computing device 1100 that can be used to implement embodiments of the present disclosure is shown. As shown, the device 1100 includes a central processing unit (CPU) 1101, which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 1102 or loaded from storage unit 1108 into random access memory (RAM) 1103. Various programs and data required for the operation of the device 1100 may also be stored in RAM 1103. The CPU 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. An input / output (I / O) interface 1105 is also connected to bus 1104.

[0084] Multiple components in device 1100 are connected to I / O interface 1105, including: input unit 1106, such as keyboard, mouse, etc.; output unit 1107, such as various types of monitors, speakers, etc.; storage unit 1108, such as disk, optical disk, etc.; and communication unit 1109, such as network card, modem, wireless transceiver, etc. Communication unit 1109 allows device 1100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0085] Processing unit 1101 performs the various methods and processes described above, such as any one of methods 500 and 800. For example, in some embodiments, any one of methods 500 and 800 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1108. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1100 via ROM 1102 and / or communication unit 1109. When the computer program is loaded into RAM 1103 and executed by CPU 1101, one or more steps of any one of methods 500 and 800 described above may be performed. Alternatively, in other embodiments, CPU 1101 may be configured to perform any one of methods 500 and 800 by any other suitable means (e.g., by means of firmware).

[0086] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload programmable logic devices (CPLDs), and so on.

[0087] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0088] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0089] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0090] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0091] The aspects disclosed herein can be embodied in hardware and instructions stored in that hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

Claims

1. A storage device, characterized in that, The storage device includes: A memory chip, comprising multiple memory cells; Electrical pulse generator; and A processor, configured to connect the memory chip to the electrical pulse generator, and configured to: Identify the target memory cell among the plurality of memory cells whose leakage current is not lower than the threshold leakage current; and After the target memory cell is determined, the electrical pulse generator is triggered to apply an electrical pulse to the target memory cell, and the applied electrical pulse causes the leakage current of the target memory cell to be lower than the threshold leakage current.

2. The storage device according to claim 1, characterized in that, The voltage of the electrical pulse is greater than the threshold voltage of the target memory cell, or the current of the electrical pulse is greater than the threshold current of the target memory cell.

3. The storage device according to claim 1, characterized in that, The processor is configured to, when the electrical pulse generator is triggered to apply an electrical pulse to the target memory cell: The electrical pulse generator is triggered to apply an electrical pulse to the target memory cell, wherein the voltage of the electrical pulse is greater than the threshold voltage of the target memory cell, or the current of the electrical pulse is greater than the threshold current of the target memory cell; Determine whether the leakage current of the target storage cell is lower than the threshold leakage current; In response to the leakage current not being lower than a threshold leakage current, the amplitude of the voltage or current of the electrical pulse applied to the target memory cell is increased until the leakage current of the target memory cell is lower than the threshold leakage current.

4. The storage device according to any one of claims 1 to 3, characterized in that, The processor is configured to, when determining a target memory cell among the plurality of memory cells whose leakage current is not lower than a threshold leakage current: Perform read operations on the plurality of memory cells to determine the leakage current for each memory cell; and The leakage current of each memory cell is compared with the threshold leakage current. as well as The storage cell whose leakage current is not lower than the threshold leakage current is determined as the target storage cell.

5. The storage device according to any one of claims 1-3, characterized in that, The electrical pulse generator applies a voltage pulse or current pulse with a pulse width greater than 20 ns and a falling edge of less than 100 ns to the target storage cell.

6. The storage device according to any one of claims 1-3, characterized in that, The processor is configured to: Determine a first threshold voltage for a first target memory cell in the set of target memory cells; and The first threshold voltage is compared with the reference voltage; as well as If the first threshold voltage is higher than the reference voltage, the electrical pulse generator is instructed to apply the electrical pulse.

7. The storage device according to claim 6, characterized in that, If the first threshold voltage is higher than the reference voltage, the electrical pulse generator is instructed to continue applying electrical pulses to the target memory cell until the first threshold voltage is no higher than the reference voltage.

8. The storage device according to claim 6, characterized in that, The processor is further configured to apply the electrical pulse to the first target memory cell when the difference between the first threshold voltage and the reference voltage is greater than a predetermined margin.

9. An electronic device, characterized in that, It includes a controller and a storage device according to any one of claims 1-8, wherein the controller is configured to read data from the storage device or write data to the storage device.

10. A method for improving the performance of a storage device, characterized in that, The method includes: The storage device processor determines the target storage cell among multiple storage cells in the storage chip of the storage device whose leakage current is not lower than the threshold leakage current; The processor triggers the electrical pulse generator of the storage device to apply an electrical pulse to the target storage cell so that the leakage current of the target storage cell is lower than the threshold leakage current.

11. The method according to claim 10, characterized in that, The method further includes: In response to the application of the electrical pulse, determine the leakage current of the target memory cell; and In response to the leakage current being not lower than a threshold leakage current, the amplitude of the electrical pulse to be applied to the target memory cell is increased.

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