Method of forming a semiconductor structure

Abstract

The application provides a semiconductor structure forming method, which comprises the following steps: providing a substrate; forming a first oxide layer on the surface of the substrate; forming a gate layer on the surface of part of the first oxide layer; forming a side wall on the sidewall of the gate layer; etching and removing the first oxide layer on both sides of the side wall to expose the surface of the substrate; forming a compensation layer on the exposed surface of the substrate, the top surface of the compensation layer being higher than the bottom surface of the gate layer; performing source-drain doping on the substrate on both sides of the side wall to form a source-drain doped region; and removing the compensation layer which is higher than the bottom surface of the gate layer, wherein the surface of the substrate on both sides of the side wall is compensated due to the existence of the compensation layer, and the top surface of the source-drain doped region is not lower than the bottom surface of the gate layer after the formation of the source-drain doped region, so that the defect of surface sag of the source-drain doped region is eliminated and the formation quality of the source-drain doped region is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a forming method of semiconductor structure. BACKGROUND

[0002] Silicon substrate damage, namely active area damage (AA Damage), generally refers to silicon loss caused in unhealthy process flow, which is generally caused by dry etching, wet etching, natural oxidation, and glue-removing process.

[0003] Severe active area damage can cause a device to lose function, and large silicon cavities can be easily detected by a defect analysis machine, which is not allowed. Weak active area damage, generally referred to as active area recess (AA Recess), can cause the contact resistance of a device on a wafer to increase and the electrical performance to decrease, and such a structural defect is difficult to be detected by a damage-free method.

[0004] Therefore, how to reduce or even eliminate active area recess and damage is a technical problem to be solved at present. SUMMARY

[0005] The present application solves the technical problem of providing a forming method of semiconductor structure to improve the performance of semiconductor structure.

[0006] To solve the above problems, the present application provides a forming method of semiconductor structure, comprising: providing a substrate; forming a first oxide layer on the surface of the substrate; forming a gate layer on the surface of part of the first oxide layer; forming a side wall on the sidewall of the gate layer; etching and removing the first oxide layer on both sides of the side wall to expose the surface of the substrate; forming a compensation layer on the exposed surface of the substrate, the top surface of the compensation layer being higher than the bottom surface of the gate layer; performing source-drain doping on the substrate on both sides of the side wall to form a source-drain doping region; removing the compensation layer higher than the bottom surface of the gate layer.

[0007] Optionally, a metal silicide is formed on the top of the gate layer and the top surface of the source-drain doping region, and the top surface of the metal silicide is flush with the top surface of the substrate.

[0008] Optionally, the material of the compensation layer comprises silicon and silicon germanium.

[0009] Optionally, after the gate layer is formed and before the side wall is formed, the method further comprises performing light doping drain ion implantation on the substrate on both sides of the gate layer to form a light doping drain structure.

[0010] Optionally, the ion type of the light doping drain ion implantation is the same as the ion type of the source-drain doping.

[0011] Optionally, after the compensation layer is formed, part of the compensation layer is oxidized, and a surface of the unoxidized compensation layer forms a compensation layer oxide.

[0012] Optionally, the method for removing the compensation layer comprises: removing the compensation layer oxide and part of the compensation layer until the surface is flush with the surface of the substrate.

[0013] Optionally, before the side wall is formed, the method further comprises: forming a second oxide layer on the side wall of the gate layer, and the second oxide layer is also formed on the top surface of the gate layer.

[0014] Optionally, the second oxide layer on the top surface of the gate layer is removed at the same time when the compensation layer is removed.

[0015] Optionally, during the process of source-drain doping, ions of the source-drain doping dope part of the compensation layer which is in contact with the surface of the substrate.

[0016] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0017] In the method for forming the semiconductor structure, after the gate layer is formed on the substrate, a side wall is formed on the side wall of the gate layer, the first oxide layer on both sides of the side wall is etched and removed until the surface of the substrate is exposed, during the etching and removing of the first oxide layer, the substrate at the bottom of the first oxide layer is damaged, the substrate is lost and a recess is caused, at this time, a compensation layer is formed on the exposed surface of the substrate, the top surface of the compensation layer is higher than the bottom surface of the gate layer, the substrate on both sides of the side wall is source-drain doped to form a source-drain doped region, during the forming of the source-drain doped region, the surface of the substrate on both sides of the side wall is compensated due to the existence of the compensation layer, after the source-drain doped region is formed, the top surface of the source-drain doped region is not lower than the bottom surface of the gate layer, thus the defect of the surface recess of the source-drain doped region is eliminated, and the forming quality of the source-drain doped region is improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figures 1 to 4 is a structure schematic diagram of each step of the method for forming the semiconductor structure in an embodiment;

[0019] Figures 5 to 12 is a structure schematic diagram of each step of the method for forming the semiconductor structure in an embodiment. DETAILED DESCRIPTION

[0020] As the background art, the performance of the existing semiconductor structure is poor, and the specific combination Figures 1 to 4 will be described.

[0021] First, refer to Figure 1, a substrate 100; oxidizing a surface of the substrate 100 to form an oxide layer 101; forming a gate layer 102 on a surface of a part of the oxide layer 101; forming a side wall layer 103 on the surface of the oxide layer 101 and the side wall and top surface of the gate layer 102.

[0022] Please refer to Figure 2 , etching the side wall layer 103 to form a side wall 104 on the side wall of the gate layer 102.

[0023] Please refer to Figure 3 , source-drain doping the substrate 100 on both sides of the side wall 104 to form a source-drain doped region 105 in the substrate 100 on both sides of the side wall 104.

[0024] Please refer to Figure 4 , etching and removing the oxide layer 102 on the surface of the substrate 100 on both sides of the side wall 104 to expose the top surface of the source-drain doped region 105, and forming a metal silicide 106 on the exposed top surface of the source-drain doped region 105.

[0025] The inventor found that the top surface of the source-drain doped region 105 formed by the above method is recessed, which increases the contact resistance of the device and reduces the electrical performance. Moreover, the recessed defect of the source-drain doped region 105 is difficult to be detected by a non-destructive method, which greatly reduces the performance and quality of the finally formed semiconductor structure. This is because the bottom oxide layer 101 of the side wall layer 103 is also etched in the process of etching the side wall layer 103, thereby exposing the bottom substrate 100. The exposed substrate 100 is also etched in the etching process of the side wall layer 103, which causes the recess of the substrate 100 on both sides of the side wall 104. Therefore, the source-drain doped region 105 formed in the process of source-drain doping the substrate 100 on both sides of the side wall 104 is also recessed.

[0026] The inventor found that after forming the gate layer on the substrate, forming the side wall on the side wall of the gate layer, etching and removing the first oxide layer on both sides of the side wall to expose the surface of the substrate, the substrate at the bottom of the first oxide layer is damaged in the process of etching and removing the first oxide layer, which causes the recess of the substrate. At this time, a compensation layer is formed on the exposed surface of the substrate, the top surface of the compensation layer is higher than the bottom surface of the gate layer, the source-drain doped region is formed by source-drain doping the substrate on both sides of the side wall. Due to the existence of the compensation layer, the surface of the substrate on both sides of the side wall is compensated during the formation of the source-drain doped region. After the formation of the source-drain doped region, the top surface of the source-drain doped region will not be lower than the bottom surface of the gate layer, thereby eliminating the defect of the recess of the surface of the source-drain doped region, improving the formation quality of the source-drain doped region, thereby reducing the contact resistance and improving the electrical performance.

[0027] In order to make the above objectives, features and advantages of the present application more obvious and comprehensible, specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0028] First, referring to Figure 5 , a substrate 200 is provided.

[0029] In the embodiment, the material of the substrate 200 is single crystal silicon.

[0030] In other embodiments, the material of the substrate 200 can also be polycrystalline silicon or amorphous silicon, germanium, silicon germanium, gallium arsenide, etc.

[0031] In the embodiment, after the substrate 200 is provided, the substrate 200 is doped to form a well region.

[0032] Referring to Figure 6 , a first oxide layer 201 is formed on the surface of the substrate 200.

[0033] In the embodiment, a thick first oxide layer 201 is grown on the surface of the substrate 200 by furnace tube thermal oxidation, and the first oxide layer 201 serves as a gate oxide layer.

[0034] In the embodiment, the first oxide layer 201 also serves to protect the substrate 200, preventing impurities in the photoresist from diffusing into the substrate 200 during subsequent photoresist processes, thereby ensuring the quality of the substrate 200.

[0035] Referring to Figure 7 , a gate layer 202 is formed on part of the surface of the first oxide layer 201.

[0036] In the embodiment, the material of the gate layer 202 is polycrystalline silicon.

[0037] In the embodiment, the method of forming the gate layer 202 includes: forming an initial gate layer 202 on the surface of the first oxide layer 201; and patterning the initial gate layer 202 to form the gate layer 202 on part of the surface of the first oxide layer 201.

[0038] In the embodiment, the substrate 200 on both sides of the gate layer 202 is subjected to light doping drain ion implantation to form a light doping drain structure 203.

[0039] In the embodiment, the light doping drain structure 203 forms a low-doped extension region between the source and the drain below the boundary of the gate layer 202, which forms an impurity concentration gradient between the source and the drain and the channel, thereby reducing the peak electric field near the drain and improving the reliability of the semiconductor structure.

[0040] In the embodiment, the ion type of the light doped drain ion implantation includes one of N type ion and P type ion. Specifically, for PMOS transistor, the ion of the light doped drain ion implantation can be BF2; for NMOS transistor, the ion of the light doped drain ion implantation can be As.

[0041] In the embodiment, a second oxide layer 204 is formed on the sidewall of the gate layer 202, and the second oxide layer 204 is also formed on the top surface of the gate layer 202.

[0042] In the embodiment, the purpose of forming the second oxide layer 204 on the sidewall and the top surface of the gate layer 202 by using oxidation process is to repair the gate layer 202, so as to improve the quality of the gate layer 202.

[0043] In the embodiment, the material of the second oxide layer 204 is silicon oxide.

[0044] Please refer to Figure 8 A sidewall 205 is formed on the sidewall of the gate layer 202.

[0045] In the embodiment, an initial sidewall layer is formed on the surface of the second oxide layer 204 and the first oxide layer 201; the initial sidewall layer is etched to form the sidewall 205 on the surface of the second oxide layer 204 of the sidewall of the gate layer 202.

[0046] In the embodiment, the sidewall 205 can protect the light doped drain structure 203 from ion implantation into the extension region of the light doped drain structure 203 in the subsequent source / drain doping process.

[0047] In the embodiment, the material of the sidewall 205 is silicon nitride.

[0048] In the embodiment, the process of etching the initial sidewall layer is anisotropic dry etching process, and the etching gas of the anisotropic dry etching is Cl2 and CF4.

[0049] Please refer to Figure 9 The first oxide layer 201 on both sides of the sidewall 205 is etched and removed to expose the surface of the substrate 200.

[0050] In the embodiment, the process of etching and removing the first oxide layer 201 on both sides of the sidewall 205 is wet etching process.

[0051] In other embodiments, the first oxide layer 201 on both sides of the sidewall 205 can also be removed by using dry etching process and the like.

[0052] Please refer to Figure 10 A compensation layer 206 is formed on the exposed surface of the substrate 200, and a top surface of the compensation layer 206 is higher than a bottom surface of the gate layer 202.

[0053] In this embodiment, the material of the compensation layer 206 is silicon.

[0054] In other embodiments, the material of the compensation layer 206 can also be silicon germanium.

[0055] In this embodiment, the formation process of the compensation layer 206 is an epitaxial growth process, and the process parameters of the epitaxial growth process include the gases used, including hydrogen (H2), hydrogen chloride (HCl) gas, DCS gas, SiH4 gas, and B2H6 gas. The gas flow rate of the hydrogen (H2) is 10-3000 sccm, the gas flow rate of the hydrogen chloride (HCl) gas is 10-250 sccm, the gas flow rate of the DCS gas is 20-2500 sccm, the gas flow rate of the SiH4 gas is 10-700 sccm, the gas flow rate of the B2H6 gas is 5-400 sccm, the pressure range is 8-300 mTorr, and the temperature range is 600-850°C.

[0056] In this embodiment, the compensation layer 206 fills the recess in the substrate 200, so that the recessed part is filled and compensated, the surface of the substrate 200 on both sides of the side wall 205 is raised, the defect of the recess of the substrate 200 is eliminated, thereby helping to reduce the contact resistance and improve the electrical performance in the subsequent process.

[0057] Please refer to Figure 11 The source-drain doped region 207 is formed by source-drain doping of the substrate 200 on both sides of the side wall 205.

[0058] In this embodiment, the ion type of the light-doped drain ion implantation is the same as the ion type of the source-drain doping.

[0059] In this embodiment, during the source-drain doping process, the ions of the source-drain doping are simultaneously doped into the part of the compensation layer 206 in contact with the surface of the substrate 200.

[0060] In this embodiment, since the silicon material is easy to be oxidized, after the compensation layer 206 is formed, part of the compensation layer 206 is oxidized, and the surface of the unoxidized compensation layer 206a forms a compensation layer oxide 206b.

[0061] Please refer to Figure 12, removing the compensation layer 206, forming a metal silicide 208 on the top surface of the gate layer 202 and the top surface of the source-drain doped region 207, the top surface of the metal silicide 208 is flush with the top surface of the substrate 200.

[0062] In the embodiment, the surface of the substrate 200 on both sides of the sidewall 205 is compensated due to the existence of the compensation layer 206, after forming the source-drain doped region 207, the top surface of the source-drain doped region 207 is not lower than the bottom surface of the gate layer 202, thus eliminating the defect of surface depression of the source-drain doped region 207, improving the forming quality of the source-drain doped region 207, and then reducing the contact resistance and improving the electrical performance.

[0063] In the embodiment, the method of removing the compensation layer 206 includes removing the oxide of the compensation layer 206 and part of the compensation layer 206 to flush with the surface of the substrate 200.

[0064] In the embodiment, the compensation layer 206 is removed at the same time as the second oxide layer 204 on the top surface of the gate layer 202 is removed.

[0065] In the embodiment, the method of forming the metal silicide 208 includes forming a metal layer on the top surface of the gate layer 202 and the surface of the source-drain doped region 207 and forming a barrier layer on the surface of the metal layer, the barrier layer prevents the metal layer from flowing during the rapid thermal annealing stage, resulting in uneven thickness of the metal silicide 208 and local non-uniform resistance value.

[0066] In the embodiment, the metal layer reacts with the substrate 200 and the gate layer 202 of the source-drain doped region 207 during the first rapid thermal annealing to generate high-resistance metal silicide 208; the barrier layer and the unreacted metal layer are removed by wet etching to prevent bridging and cause circuit short circuit; the second rapid thermal annealing is performed to convert the high-resistance metal silicide 208 into low-resistance metal silicide 208.

[0067] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope defined by the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a first oxide layer on a surface of the substrate; forming a gate layer on a surface of a portion of the first oxide layer; forming a sidewall spacer on sidewalls of the gate layer; etching the first oxide layer on both sides of the sidewall spacer to expose a surface of the substrate; forming a compensation layer on the exposed surface of the substrate, a top surface of the compensation layer being higher than a bottom surface of the gate layer; performing source-drain doping on the substrate on both sides of the sidewall spacer to form source-drain doped regions; removing the compensation layer higher than the bottom surface of the gate layer, the material of the compensation layer comprising silicon or silicon germanium.

2. The method of forming a semiconductor structure of claim 1, wherein, forming a metal silicide on a top surface of the gate layer and on a top surface of the source-drain doped regions, a top surface of the metal silicide being flush with a top surface of the substrate.

3. The method of forming a semiconductor structure of claim 1, wherein, After forming the gate layer and before forming the sidewall spacer, the method further comprises performing a light doping drain ion implantation on the substrate on both sides of the gate layer to form a light doping drain structure.

4. The method of forming a semiconductor structure of claim 3, wherein, The ion type of the light doping drain ion implantation is the same as the ion type of the source-drain doping.

5. The method of forming a semiconductor structure of claim 1, wherein, After forming the compensation layer, a portion of the compensation layer is oxidized to form a compensation layer oxide on a surface of the unoxidized compensation layer.

6. The method of forming a semiconductor structure of claim 5, wherein, The method of removing the compensation layer comprises removing the compensation layer oxide and a portion of the compensation layer to flush with a surface of the substrate.

7. The method of forming a semiconductor structure of claim 1, wherein, Before forming the sidewall spacer, the method further comprises forming a second oxide layer on sidewalls of the gate layer, the second oxide layer also being formed on a top surface of the gate layer.

8. The method of forming a semiconductor structure of claim 7, wherein, The second oxide layer on the top surface of the gate layer is removed at the same time as the compensation layer is removed.

9. The method of forming a semiconductor structure of claim 1, wherein, During the process of performing source-drain doping, the ions of the source-drain doping simultaneously dope into a portion of the compensation layer in contact with the surface of the substrate.

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