Semiconductor device

Abstract

The application provides a semiconductor device, which comprises: a substrate, the substrate comprising a first region and a second region surrounding the first region; a first shallow trench isolation structure located in the first region of the substrate, the first shallow trench isolation structure defining a plurality of first active regions; a second shallow trench isolation structure located in the second region of the substrate, the second shallow trench isolation structure surrounding the first shallow trench isolation structure and the first active regions, and the second shallow trench isolation structure being spaced apart from the first shallow trench isolation structure; a plurality of bit lines located on the substrate, the bit lines being arranged in a first direction across the first shallow trench isolation structure and the second shallow trench isolation structure and in a second direction perpendicular to the first direction; and at least one dummy bit line contact structure located in the second shallow trench isolation structure and in contact with the bit lines. The application at least solves the problem of bit line collapse and distortion in the peripheral region, which causes device defects and yield loss.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] With the miniaturization of semiconductor devices and the increasing complexity of integrated circuits, component size continues to decrease and their structures continue to change. Therefore, maintaining the performance of small-sized semiconductor components is currently a major goal of the industry. In the semiconductor manufacturing process, multiple first active areas are often defined on a substrate as a foundation, and then the required components are formed on these first active areas. Generally speaking, the first active areas are multiple patterns formed on the substrate using manufacturing processes such as photolithography and etching. However, due to the requirements of miniaturization, the width of the first active areas is gradually reduced, and the spacing between each first active area is also gradually reduced. This makes the manufacturing process face many limitations and challenges, making it impossible to meet product requirements. Summary of the Invention

[0003] The main purpose of the present application is to provide a semiconductor device to at least solve the problem in the prior art that the bit line collapses and twists in the peripheral area, causing device defects and yield loss.

[0004] To achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor device is provided, comprising: a substrate, the substrate comprising a first region and a second region surrounding the first region; a first shallow trench isolation structure located in the first region of the substrate, the first shallow trench isolation structure defining a plurality of first active regions; a second shallow trench isolation structure located in the second region of the substrate, the second shallow trench isolation structure surrounding the first shallow trench isolation structure and the first active region, and the second shallow trench isolation structure being spaced apart from the first shallow trench isolation structure; a plurality of bit lines located on the substrate, the bit lines crossing the first shallow trench isolation structure and the second shallow trench isolation structure along a first direction and being spaced apart along a second direction perpendicular to the first direction; and at least one dummy bit line contact structure, the dummy bit line contact structure being located in the second shallow trench isolation structure and in contact with the bit lines.

[0005] Optionally, the dummy bit line contact structure only contacts the second shallow trench isolation structure.

[0006] Optionally, at least one of the dummy bit line contact structures is located at an end of the bit line in the first direction.

[0007] Optionally, at least one of the dummy bit line contact structures extends along the second direction, and the dummy bit line contact structure contacts at least two of the bit lines.

[0008] Optionally, at least one of the dummy bit line contact structures extends beyond an end portion of the bit line in the first direction.

[0009] Optionally, the semiconductor device further includes a word line located in the first region of the substrate, wherein the word line includes a metal layer, a polysilicon layer, and a cap layer stacked in sequence.

[0010] Optionally, one side of at least one of the dummy bit line contact structures contacts the second shallow trench isolation structure, and the other side contacts the capping layer of the word line.

[0011] Optionally, the semiconductor device further includes: a plurality of bit line contact structures, wherein the bit line contact structures are located in the first region and contact the bit lines.

[0012] Optionally, a distribution density of the dummy bit line contact structures in the second region is the same as a distribution density of the bit line contact structures in the first region.

[0013] Optionally, a size of the dummy bit line contact structure is smaller than a size of the bit line contact structure.

[0014] By applying the technical solution of the present application, at least one dummy bit line contact structure is provided in the second shallow trench isolation structure. The dummy bit line structure is located below the bit line and in contact with the bit line. The dummy bit line contact structure can support the bit line portion located in the second area, and stabilize the bit line portion located in the second area, thereby preventing the bit line from collapsing or twisting in the peripheral area, causing device defects and yield loss, and avoiding the problem of short circuit of the bit line due to collapse, twisting, etc., so that the electrical signal in the bit line can be effectively transmitted to the first active area, thereby ensuring the normal operation of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0016] Figure 1 shows a top perspective view of a semiconductor device provided in accordance with a first embodiment of the present application;

[0017] Figure 2 1 shows a schematic top view of a semiconductor device after forming a first active area and a shallow trench isolation structure according to an embodiment of the present application;

[0018] Figure 3 Shown Figure 1 Schematic diagram of the cross section along the tangent line AA';

[0019] Figure 4shows a top perspective view of a semiconductor device provided in accordance with a second embodiment of the present application;

[0020] Figure 5 Shown Figure 4 Schematic diagram of a partial cross section along the tangent line AA'.

[0021] The accompanying drawings include the following reference numerals:

[0022] 10. Substrate; 11. First active region; 12. Bit line; 13. Word line; 14. Dummy bit line contact structure; 15. Bit line contact structure; 16. Second shallow trench isolation structure; 17. First conductive portion; 18. Second conductive portion; 19. Capping layer; 20. Metal layer; 21. Buried insulating layer; 22. First insulating film pattern; 23. Second insulating film pattern; 35. Third conductive portion; 36. Capping layer; 37. Insulating layer; 41. First shallow trench isolation structure; 42. Polysilicon layer; 111. Second active region; 1111. Third active region. DETAILED DESCRIPTION

[0023] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0025] Reference Figures 1 to 5 , an embodiment of the present application provides a semiconductor device, the semiconductor device comprising:

[0026] a substrate 10, wherein the substrate 10 includes a first region and a second region surrounding the first region;

[0027] Specifically, the first region is also called a device region, and the second region is also called a peripheral region.

[0028] a first shallow trench isolation structure 41 located in the first region of the substrate 10 , wherein the first shallow trench isolation structure 41 defines a plurality of first active regions 11 ;

[0029] a second shallow trench isolation structure 16 located in the second region of the substrate 10 , the second shallow trench isolation structure 16 surrounding the first shallow trench isolation structure and the first active area 11 , and the second shallow trench isolation structure 16 is spaced apart from the first shallow trench isolation structure;

[0030] a plurality of bit lines 12 located on the substrate 10, the bit lines 12 crossing the first shallow trench isolation structure 41 and the second shallow trench isolation structure 16 along a first direction and spaced apart along a second direction perpendicular to the first direction;

[0031] At least one dummy bit line contact structure 14 is located in the second shallow trench isolation structure 16 and contacts the bit line 12 .

[0032] In the embodiment, at least one dummy bit line contact structure is provided in the second shallow trench isolation structure. The dummy bit line structure is located below the bit line and in contact with the bit line. The dummy bit line contact structure can support the bit line portion located in the second area, and stabilize the bit line portion located in the second area, thereby preventing the bit line from collapsing or twisting in the peripheral area, causing device defects and yield loss, and avoiding the problem of short circuit of the bit line due to collapse, twisting, etc., so that the electrical signal in the bit line can be effectively transmitted to the first active area, thereby ensuring the normal operation of the semiconductor device.

[0033] Specifically, substrate 10 may include a semiconductor material. For example, substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, and / or a silicon-on-insulator (SOI) substrate, or may include a silicon substrate, a germanium substrate, a silicon-germanium substrate, and / or a silicon-on-insulator (SOI) substrate. Substrate 10 may include impurities; for example, substrate 10 may be lightly doped with boron and may have P-type conductivity; however, the present invention is not limited thereto.

[0034] The first active regions 11 may have a strip shape elongated in the BB' direction, and the first active regions 11 may be arranged at regular intervals to isolate each other. For example, the first active regions 11 may be arranged parallel to each other in the BB' direction. The BB' direction may correspond to a direction that is angled relative to the first and second directions. For example, the BB' direction may correspond to an angle of approximately 70 degrees with the second direction; however, the present invention is not limited thereto. The first shallow trench isolation structure 41 and the second shallow trench isolation structure 16 may include an insulating material. For example, the first shallow trench isolation structure 41 and the second shallow trench isolation structure 16 may include silicon oxide (SiO2) or silicon nitride (SiN). A photolithography process may be used to pattern and etch the substrate 10 to etch out a space for forming the first shallow trench isolation structure 41 to define the first active region 11, and a process such as spin-on dielectric deposition (SOD deposition) and / or high-density plasma deposition (HDP deposition) may be used to fill the space for forming the first shallow trench isolation structure 41 with a silicon oxide layer, thereby obtaining the first shallow trench isolation structure 41. The manufacturing process of the second shallow trench isolation structure 16 is similar and will not be described again here.

[0035] In addition, if Figure 2 As shown, the semiconductor device further includes a second active region 111 and a third active region 1111. The second active region 111 is disposed outside the first active region 11, and the third active region 1111 is further disposed outside the second active region 111. Thus, the second active region 111 may be located between the third active region 1111 and the first active region 11. The second shallow trench isolation structure 16 surrounds the active structure formed by the first active region 11 and the second active region 111. Furthermore, a portion of the second shallow trench isolation structure 16 may be disposed between the second active region 111 and the third active region 1111. In this embodiment, the second active region 111, for example, entirely surrounds the first active region 11, and the third active region 1111 also entirely surrounds the second active region 111, thereby surrounding both the second active region 111 and the first active region 11. However, the present invention is not limited thereto. The third active region 1111 disposed outside the second active region 111 and the first active region 11 can protect the inner structure, maintain its integrity, and avoid structural deformation.

[0036] Some options, such as Figure 3 As shown, the dummy bit line contact structure 14 only contacts the second shallow trench isolation structure 16 . In other words, the dummy bit line contact structure 14 is only located in the second shallow trench isolation structure 16 .

[0037] In another alternative, Figure 4As shown, at least one dummy bit line contact structure 14 is located at the end of the bit line 12 in the first direction. Because the end of the bit line is more prone to collapse, distortion, and other problems, this embodiment provides support for the end of the bit line by disposing the dummy bit line contact structure below the end of the bit line in the second region and contacting the end of the bit line, thereby further ensuring a better bit line stability.

[0038] Specifically, at least one of the dummy bit line contact structures 14 may be provided only at the end of the bit line 12 in the first direction; at least one of the dummy bit line contact structures 14 may be provided at other locations of the bit line 12 in the second region except for the end; the dummy bit line contact structure 14 may also be provided as Figure 4 The arrangement shown is at the end of the bit line 12 in the first direction and at other positions of the bit line 12 in the second region except the end.

[0039] It should be noted that Figure 4 The diagram only illustrates a case where there is only one dummy bit line contact structure 14 located at the end of the bit line 12 in the first direction, i.e., one dummy bit line contact structure 14 contacts the ends of multiple bit lines 12 in the first direction. In addition to the structure shown in the figure above, there may be multiple dummy bit line contact structures 14 located at the end of the bit line 12 in the first direction, with each dummy bit line contact structure 14 contacting one end of the bit line 12 in the first direction, or contacting more than one end of the bit line 12 in the first direction.

[0040] Some options, such as Figure 4 As shown, at least one dummy bit line contact structure 14 extends along the second direction, and the dummy bit line contact structure 14 contacts at least two of the bit lines 12. In this embodiment, one dummy bit line contact structure supports at least two bit lines, and the total number of dummy bit line contact structures in the semiconductor device is relatively small, making the manufacturing process of the semiconductor device relatively simple and controllable.

[0041] like Figure 4 As shown, the edge of the dummy bit line contact structure 14 located at the end of the bit line 12 in the first direction and close to the bit line 12 in the first direction may be a non-smooth surface.

[0042] This application Figure 5The case where the dummy bit line contact structure 14 extending along the second direction is located at the end of the bit line 12 in the first direction is shown only as an example. In addition to the case shown in the figure, the dummy bit line contact structure 14 extending along the second direction can also be located at other positions of the bit line 12 in the second region other than the end, and contact the bit line 12.

[0043] In order to further stabilize the bit line, some other options are available, such as Figure 4 As shown, at least one of the dummy bit line contact structures 14 extends in the first direction beyond the end of the bit line 12. By providing the dummy bit line contact structure beyond the bit line in the first direction, the end of the bit line in the first direction can be better supported, further preventing the end of the bit line in the first direction from collapsing, twisting, and other problems.

[0044] In addition, for the dummy bit line contact structure 14 that is not provided at the end of the bit line 12, the corresponding relationship between the bit line 12 and the dummy bit line contact structure 14 may be one-to-one, or may be one-to-one. Figure 1 The one bit line 12 shown corresponds to a plurality of the dummy bit line contact structures 14 ; it is also possible that a plurality of the bit lines 12 correspond to one dummy bit line contact structure 14 ; it is also possible that at least one dummy bit line contact structure 14 is provided only under a portion of the bit lines 12 .

[0045] In the case where there are multiple dummy bit line contact structures 14, the sizes of the dummy bit line contact structures 14 may be the same or different. The sizes of the dummy bit line contact structures 14 may be adjusted according to their locations. For example, the size of the dummy bit line contact structure 14 located at the end of the bit line 12 may be larger than the size of the dummy bit line contact structures 14 located at other locations.

[0046] Specifically, if Figure 3 As shown, the semiconductor device further includes a word line 13 located in the first region of the substrate 10. The word line 13 includes a metal layer 20, a polysilicon layer 42, and a cap layer 19 stacked in sequence. The metal layer 20 may be made of TiN and W, the polysilicon layer 42 may be made of polysilicon, and the cap layer 19 may be made of silicon nitride (SiN), but are not limited thereto.

[0047] like Figure 3 and Figure 5 As shown, the bit line 12 includes a first conductive portion 17, a second conductive portion 18, a third conductive portion 35, and a capping layer 36 stacked in sequence in a direction away from the substrate 10. The dummy bit line contact structure 14 contacts the first conductive portion 17.

[0048] The first conductive portion 17 may include doped polysilicon, the second conductive portion 18 may include TiN, the third conductive portion 35 may include at least one of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni) and cobalt (Co), and the cap layer may include silicon nitride.

[0049] In actual application, the plurality of word lines 13 extend along the second direction, are spaced apart and parallel to each other along the first direction. The semiconductor device further includes a buried insulating layer 21 and a capping layer 19. The capping layer 19 is located on a surface of the polysilicon layer 42 away from the metal layer 20. The buried insulating layer 21 extends along the sidewalls of the metal layer 20, the polysilicon layer 42, and the capping layer 19.

[0050] In some exemplary embodiments, one side of at least one dummy bit line contact structure 14 contacts the second shallow trench isolation structure 16, and the other side contacts the capping layer 19 of the word line 13. That is, the second shallow trench isolation structure 16 is located at the junction of the first region and the second region and contacts the capping layer 19 of the word line 13; the dummy bit line contact structure 14 is located at the junction of the second shallow trench isolation structure 16 and the word line 13, and contacts the second shallow trench isolation structure 16 and the capping layer 19, respectively.

[0051] In addition, the semiconductor device further includes a plurality of bit line contact structures 15 , wherein the bit line contact structures 15 are located in the first region and contact the bit lines 12 .

[0052] Specifically, a plurality of the bit line contact structures 15 are arranged at intervals.

[0053] The semiconductor device further includes: a first insulating film pattern 22 located between the substrate 10 and the bit line 12 and in contact with the substrate 10 and the bit line 12, respectively; a second insulating film pattern 23 located between the first insulating film pattern 22 and the bit line 12 and in contact with the first insulating film pattern 22 and the bit line 12, respectively; the dummy bit line contact structure 14 extends through the second insulating film pattern 23 and the first insulating film pattern 22 to the second shallow trench isolation structure 16 to contact the first conductive portion 17 of the bit line 12; a third conductive portion 35 located on a surface of the second conductive portion 18 away from the substrate 10; and a capping layer 36 located on a surface of the third conductive portion 35 away from the second conductive portion 18. An insulating layer 37 located on a surface of the second insulating film pattern 23 is flush with an upper surface of the capping layer 36 located on a surface of the third conductive portion 35.

[0054] The first insulating film pattern 22 and the second insulating film pattern 23 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride, or a combination thereof, and may be formed as a single layer or multiple layers. The first insulating film pattern 22 and the second insulating film pattern 23 may be formed using a chemical vapor deposition (CVD) process, such as a plasma enhanced chemical vapor deposition (PECVD) process; however, the present invention is not limited thereto.

[0055] According to some embodiments, the distribution density of the dummy bit line contact structures in the second region is the same as the distribution density of the bit line contact structures in the first region, which can reduce the non-uniformity of the semiconductor device and improve the stability and reliability of the semiconductor device.

[0056] In some embodiments of the present application, a size of the dummy bit line contact structure is smaller than a size of the bit line contact structure, where the size includes a vertical depth in the substrate.

[0057] In one embodiment, the semiconductor device can be formed by the following steps, but is not limited thereto. First, a substrate 10 is provided, the substrate 10 including a first region and a second region surrounding the first region; then, at least one first shallow trench isolation structure 41 is formed in the first region of the substrate 10, and at least one second shallow trench isolation structure 16 is formed in the second region of the substrate 10; then, a plurality of trenches are formed in the first region of the substrate 10, each trench being parallel to each other; thereafter, a buried insulating layer 21 covering the entire surface of the trench, a metal layer 20 and a polysilicon layer 42 filling the lower half of the trench, and a cap layer 19 filling the upper half of the trench are sequentially formed in each trench, so that the cap layer 19 is flush with the surface of the substrate 10, forming a structure as shown in FIG. Figure 3 The word line 13 shown is shown. After forming word line 13, an etching process is performed to form at least one bit line contact opening in the first region of substrate 10 and at least one dummy bit line contact opening in the second shallow trench isolation structure 16 of substrate 10. The formed bit line contact opening corresponds to and exposes a portion of the first region, and the formed dummy bit line contact opening corresponds to and exposes a portion of the second shallow trench isolation structure. Then, a bit line contact structure 15 is formed in the bit line contact opening, and a dummy bit line contact structure 14 is formed in the dummy bit line contact opening. One or more bit lines 12 are then formed on substrate 10, with bit lines 12 contacting the bit line contact structures 15 and the dummy bit line contact structures, respectively.

[0058] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0059] From the above description, it can be seen that the embodiments described in this application achieve the following technical effects:

[0060] The semiconductor device of the present application provides at least one dummy bit line contact structure in the second shallow trench isolation structure. The dummy bit line structure is located below the bit line and contacts the bit line. The dummy bit line contact structure can support the bit line portion located in the second area and stabilize the bit line portion located in the second area, thereby preventing the bit line from collapsing or twisting in the peripheral area, causing device defects and yield loss, and avoiding the problem of short circuit of the bit line due to collapse, twisting, etc., so that the electrical signal in the bit line can be effectively transmitted to the first active area, ensuring the normal operation of the semiconductor device.

[0061] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising a first region and a second region surrounding the first region; a first shallow trench isolation structure located in the first region of the substrate, wherein the first shallow trench isolation structure defines a plurality of first active areas; a second shallow trench isolation structure located in the second region of the substrate, the second shallow trench isolation structure surrounding the first shallow trench isolation structure and the first active area, and the second shallow trench isolation structure and the first shallow trench isolation structure being spaced apart; a plurality of bit lines located on the substrate, the bit lines crossing the first shallow trench isolation structure and the second shallow trench isolation structure along a first direction and being spaced apart along a second direction perpendicular to the first direction; At least one dummy bit line contact structure is provided, wherein the dummy bit line contact structure is located in the second shallow trench isolation structure and contacts the bit line.

2. The semiconductor device according to claim 1, wherein The dummy bit line contact structure only contacts the second shallow trench isolation structure.

3. The semiconductor device according to claim 1, wherein At least one dummy bit line contact structure is located at an end of the bit line in the first direction.

4. The semiconductor device according to claim 3, wherein At least one dummy bit line contact structure extends along the second direction, and the dummy bit line contact structure contacts at least two of the bit lines.

5. The semiconductor device according to claim 1, wherein At least one of the dummy bit line contact structures extends beyond an end portion of the bit line in the first direction. The semiconductor device according to claim 1 , wherein: The semiconductor device further includes: The word line is located in the first region of the substrate, and includes a metal layer, a polysilicon layer and a cap layer stacked in sequence.

7. The semiconductor device according to claim 6, wherein: One side of at least one of the dummy bit line contact structures contacts the second shallow trench isolation structure, and the other side contacts the capping layer of the word line.

8. The semiconductor device according to claim 1, wherein The semiconductor device further includes: A plurality of bit line contact structures are provided, wherein the bit line contact structures are located in the first region and contact the bit lines.

9. The semiconductor device according to claim 8, wherein The distribution density of the dummy bit line contact structures in the second region is the same as the distribution density of the bit line contact structures in the first region.

10. The semiconductor device according to claim 8, wherein The size of the dummy bit line contact structure is smaller than that of the bit line contact structure.

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