Bipolar transistor structure and preparation method thereof and radio frequency amplifier

Abstract

The embodiment of the present invention provides a bipolar transistor structure including an active region, wherein the active region has: a semiconductor layer having a first surface, wherein the semiconductor layer includes a collector layer, a base layer and an emitter layer stacked in sequence; the first surface is the surface of the emitter layer facing away from the base layer; the emitter step and the emitter metal are sequentially arranged on the emitter layer; a first dielectric layer covers the top surface of the emitter metal and extends along the side of the emitter metal to cover the portion of the first surface exposed outside the emitter metal; the first dielectric layer has a first opening; a second dielectric layer covers the first dielectric layer; the second dielectric layer has a second opening connected to the first opening; the base metal is connected to the base layer through the first opening and the second opening; and extends to cover at least the portion of the second dielectric layer adjacent to the second opening. The bipolar transistor and its preparation method and the radio frequency amplifier provided by the embodiment of the present invention can reduce junction capacitance and improve frequency characteristics.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bipolar transistor structure and a preparation method thereof, and a radio frequency amplifier. Background Art

[0002] Bipolar transistors are commonly known as triodes. With the development of technology, people have put forward higher and higher requirements on the frequency characteristics of triodes. Taking HBT (heterojunction bipolar transistor) as an example, the junction capacitance between the base layer and the collector layer (BC junction capacitance, C bc ) is one of the important factors affecting the frequency characteristics. The frequency characteristics of the transistor are negatively correlated with the BC junction capacitance. Therefore, how to reduce the BC junction capacitance to improve the frequency characteristics of the transistor is a problem of concern in the industry. Summary of the invention

[0003] Therefore, in order to overcome at least some of the defects in the prior art, the embodiments of the present invention provide a bipolar transistor structure and a preparation method thereof and a radio frequency amplifier, which are conducive to shrinking the device and reducing the BC junction area, thereby improving the frequency characteristics of the device.

[0004] An embodiment of the present invention provides a bipolar transistor structure including an active region, wherein the active region has:

[0005] A semiconductor layer having a first surface, wherein the semiconductor layer comprises a collector layer, a base layer and an emitter layer stacked in sequence; the first surface is a surface of the emitter layer facing away from the base layer;

[0006] An emitter step, disposed on the emitter layer;

[0007] An emitter metal is disposed on the emitter step;

[0008] a first dielectric layer, covering the top surface of the emitter metal, and extending along the side of the emitter metal to cover the portion of the first surface exposed outside the emitter metal; the first dielectric layer has a first opening;

[0009] A second dielectric layer covering the first dielectric layer; the second dielectric layer having a second opening communicating with the first opening;

[0010] A base metal is connected to the base layer through the first opening and the second opening, and extends to cover at least a portion of the second dielectric layer adjacent to the second opening.

[0011] Another embodiment of the present invention provides a method for preparing a bipolar transistor structure, comprising:

[0012] Step S1, pre-processing the epitaxial structure to obtain a semiconductor layer; the semiconductor layer has a first surface, and the semiconductor layer includes: a collector layer, a base layer and an emitter layer stacked in sequence; the first surface is the side of the emitter layer facing away from the base layer; an emitter step is arranged on the emitter layer; and an emitter metal is arranged on the emitter step;

[0013] Step S2, forming a first dielectric layer and a second dielectric layer in sequence on the semiconductor layer, wherein the first dielectric layer covers the top surface of the emitter metal and extends along the side of the emitter metal to cover the portion of the first surface exposed outside the emitter metal; and the second dielectric layer covers the first dielectric layer; the first dielectric layer has a first opening; and the second dielectric layer has a second opening connected to the first opening;

[0014] Step S3, forming a base metal, connecting the base metal to the base layer through the first opening and the second opening; and extending the base metal to cover at least a portion of the second dielectric layer adjacent to the second opening.

[0015] An embodiment of the present invention provides a radio frequency amplifier, comprising the aforementioned bipolar transistor structure or a bipolar transistor structure manufactured by the aforementioned method for manufacturing the bipolar transistor structure.

[0016] The above-mentioned embodiments of the present invention have at least one or more of the following beneficial effects: through the structure of the present embodiment, the distance between the base metal and the emitter step can be made smaller when the effective spacing between the base metal and the emitter step and other dimensions remain unchanged. That is, even if the distance between the portion of the base metal located above the second dielectric layer and the emitter structure is reduced, the appropriate effective spacing between the base metal and the emitter step can still be maintained. Therefore, while maintaining the appropriate effective spacing between the base metal and the emitter step, the base step area of ​​the bipolar transistor structure provided by the embodiment of the present invention can be made smaller, and the BC junction area is smaller, so the frequency characteristics can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The specific implementation of the present invention will be described in detail below in conjunction with the accompanying drawings. The drawings only show the spatial relationship of the various structural parts, not the actual thickness, size or relative proportion of the various structural parts.

[0018] Figure 1a A schematic top view of the active region of a bipolar transistor structure provided in one embodiment of the present invention.

[0019] Figure 1b for Figure 1a A partial enlarged schematic diagram of the C area in the middle.

[0020] Figure 2 The bipolar transistor structure provided in one embodiment of the present invention corresponds to Figure 1a Schematic diagram of the cross section along the AA direction.

[0021] Figure 3 A schematic structural diagram of a semiconductor layer provided in a method for preparing a bipolar transistor structure provided in one embodiment of the present invention.

[0022] Figure 4 For Figure 3 A schematic structural diagram of a first dielectric layer formed on the structure shown.

[0023] Figure 5 To use Figure 4 The structure shown forms a schematic diagram of the structure of an etching step.

[0024] Figure 6 for Figure 5 The structure shown is a schematic diagram of the structure forming a base region step.

[0025] Figure 7 for Figure 6 A schematic diagram of the structure from another perspective of the structure shown.

[0026] Figure 8 For Figure 6 Schematic diagram of a structure in which a second dielectric layer is formed on the structure shown.

[0027] Fig. 9 For Figure 8 A schematic diagram of the structure after the first opening, the second opening and the third opening are formed on the structure shown.

[0028] Fig.10 To use Fig. 9 Schematic diagram of the structure after base metal is formed in the structure shown.

[0029] Fig.11 To use Fig.10 The structure shown is a schematic diagram of the structure after the collector metal and the capacitor metal are formed.

[0030] [Description of Reference Numerals]

[0031] 100, bipolar transistor structure; 10, semiconductor layer; 11, substrate; 12, sub-collector layer; 121, second surface; 122, passive region; 13, etch stop layer; 14, collector layer; 15, base layer; 16, emitter layer; 161, first surface; 101, primary etching step; 171, first side; 1711, recessed portion; 172, second side; 1721, step portion; 102, base step; 20, emitter structure; 21, emitter step; 22, emitter metal; 30, dielectric layer; 31, first dielectric layer; 311, first opening; 32, second dielectric layer; 321, second opening; 322, third opening; 33, third dielectric layer; 40, base metal; 51, collector metal; 52, capacitor metal. DETAILED DESCRIPTION

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0036] An embodiment of the present invention provides a bipolar transistor structure 100 , wherein the bipolar transistor structure 100 is a triode structure having a semiconductor stacked structure, for example, an HBT device, or an integrated HBT device (a passive device is integrated on the HBT device).

[0037] Reference Figure 1a , the bipolar transistor structure 100 includes an active region, Figure 2 A bipolar transistor structure 100 corresponds to Figure 1a Schematic diagram of the AA section. Figure 2 The figure also shows a portion of the inactive region in the bipolar transistor structure 100. In order to more clearly show some structures in the bipolar transistor structure 100, Figure 1a The first dielectric layer 31, the second dielectric layer 32, and the third dielectric layer 33 are omitted, and the position of the first opening 311 is marked with a dotted line. The active area of ​​the bipolar transistor structure 100 has a semiconductor layer 10, an emitter metal 22, a dielectric layer 30, and a base metal 40. The semiconductor layer 10 has a first surface 161, and the semiconductor layer 10 includes a collector layer 14, a base layer 15, and an emitter layer 16 stacked in sequence. The first surface 161 is the surface of the emitter layer 16 facing away from the base layer 15. The emitter metal 22 is arranged on the emitter layer 16. Specifically, an emitter structure 20 is arranged in a partial area on the first surface 161, and the emitter structure 20 includes an emitter step 21 and an emitter metal 22 stacked in sequence, that is, the emitter step 21 is arranged on the emitter layer 16, and the emitter metal 22 is arranged on the emitter step 21. It should be noted that although Figures 1a to 11 The width of the emitter metal 22 shown in the figure is smaller than the width of the emitter step 21, but the present embodiment is not limited thereto. In some embodiments, the width of the emitter metal 22 can be equal to or substantially consistent with the width of the emitter step 21. In the present embodiment, the emitter step 21 is mainly composed of an InGaAs layer and a GaAs layer, wherein the InGaAs layer is a CAP layer used for making an emitter metal ohmic contact; and the GaAs layer is used to solve the problem of lattice matching between the InGaAs in the CAP layer and the InGaP in the emitter layer.

[0038] The dielectric layer 30 includes a first dielectric layer 31 and a second dielectric layer 32. The first dielectric layer 31 covers the top surface of the emitter metal 22 and extends along the side of the emitter metal to cover the portion of the first surface 161 exposed outside the emitter metal 22. The first dielectric layer 31 has a first opening 311. The second dielectric layer 32 covers the first dielectric layer 31. The second dielectric layer 32 has a second opening 321 connected to the first opening 311.

[0039] The base metal 40 is connected to the base layer 15 through the first opening 311 and the second opening 321 . The base metal 40 extends to cover at least a portion of the second dielectric layer 32 adjacent to the second opening 321 .

[0040] The semiconductor layer 10 , for example, further includes a substrate 11 , a sub-collector layer 12 , and an etching stop layer 13 which are stacked in sequence, and the collector layer 14 is disposed on the etching stop layer 13 .

[0041] The material of the substrate 11 may be, for example, a III-V semiconductor, such as any one or a combination of multiple of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, and InAlAs.

[0042] The sub-collector layer 12 may be, for example, a Group III-V semiconductor, and may include a Group III-V semiconductor, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, and InAlAs.

[0043] The etching stop layer 13 may be, for example, a III-V semiconductor, such as any one or a combination of InGaP, InGaAs, GaAsP, AlGaAs, InAlAs, and GaSb.

[0044] The collector layer 14 may be, for example, a III-V semiconductor, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, and InAlAs.

[0045] The base layer 15 may be, for example, a Group III-V semiconductor, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, and InAlAs.

[0046] The emitter layer 16 may be, for example, a III-V semiconductor, such as any one or a combination of GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InGaAs, InAlAs, InGaP, etc. The emitter layer 16 may be a multi-layer structure.

[0047] The doping types of the sub-collector layer 12, the collector layer 14, and the emitter layer 16 are the first doping type, and the doping type of the base layer 15 is the second doping type. When the first doping type is n-type, the second doping type is p-type. When the first doping type is p-type, the second doping type is n-type.

[0048] The material of the dielectric layer 30 can be any one or a combination of insulating materials such as SiN, Si3N4, Si2N3, SiO2, SiON, Al2O3, AlN, PI (polyimide), BCB (benzocyclobutene), PBO (polybenzoxazole), etc. The materials of the first dielectric layer 31 and the second dielectric layer 32 can be the same or different, and the thicknesses of the first dielectric layer 31 and the second dielectric layer 32 can be the same or different. In some embodiments, the thickness of the first dielectric layer 31 and the second dielectric layer 32 ranges from 200 to 1000 angstroms (Å, 1 angstrom = 10 -10 In some embodiments, at least one of the material and thickness of the first dielectric layer 31 and the second dielectric layer 32 is different, for example, the material of the first dielectric layer 31 and the second dielectric layer 32 is the same but the thickness is different, for example, the material of the first dielectric layer 31 and the second dielectric layer 32 is different but the thickness is the same, for example, the material and thickness of the first dielectric layer 31 and the second dielectric layer are different.

[0049] The emitter metal 22 and the base metal 40 are both conductive metal materials. The emitter metal 22 is, for example, Ti, Pt, Au, Al, Cu, W, Ni, Ge, etc. The base metal 40 can be, for example, a Pt / Ti / Pt / Au / Ti stack.

[0050] Reference Figure 2 As shown, a portion of the base metal 40 is connected to the base layer 15 through the first opening 311 and the second opening 321, and is located above the second dielectric layer 32 and partially extends to the edge of the second opening 321, and covers the portion of the second dielectric layer 32 adjacent to the second opening 321. It can also be understood that the width of the base metal 40 is greater than the width of the first opening 311 and the second opening 321. When the width of the base metal 40 is non-uniform, at least the width of the interface where the base metal 40 contacts the second dielectric layer 32 is greater than the maximum width of the first opening 311.

[0051] Specifically, the width of the portion of the base metal 40 located above the second dielectric layer 32 is greater than the width of the base metal 40 in contact with the base layer 15. Figure 1b and Figure 2D1 represents the effective spacing between the base metal and the emitter step, and D1 means the distance between the part where the base metal 40 contacts the base layer 15 and the emitter step 21. Through the structure of this embodiment, when the effective spacing between the base metal and the emitter step and other dimensions (the width of the base metal 40, the emitter structure 20, etc.) remain unchanged, the distance D2 between the base metal 40 (the part above the second dielectric layer 32) and the emitter step 21 can be made smaller. For example, D1 can be 0.2~1 microns, and D2 can be 0~1 microns. The difference between D1 and D2 ranges from 0.1 to 1 microns. That is, even if the distance between the part of the base metal 40 located above the second dielectric layer 32 and the emitter structure 20 is reduced, the appropriate effective spacing between the base metal and the emitter step can still be maintained. Therefore, when the appropriate effective spacing between the base metal and the emitter step is maintained, the base step 102 area of ​​the bipolar transistor structure 100 provided in the embodiment of the present invention can be made smaller, and the BC junction area is smaller, so the frequency characteristics can be improved.

[0052] The embodiment of the present invention further provides a method for preparing a bipolar transistor structure, which can prepare the above-mentioned bipolar transistor structure 100. The method comprises:

[0053] Step S1, pre-processing the epitaxial structure to obtain a semiconductor layer 10; the semiconductor layer 10 has a first surface 161, and the semiconductor layer 10 includes: a collector layer 14, a base layer 15 and an emitter layer 16 stacked in sequence; the first surface 161 is a surface of the emitter layer 16 facing away from the base layer 15; an emitter step 21 is arranged on the emitter layer 16; and an emitter metal 22 is arranged on the emitter step 21;

[0054] Step S2, forming a first dielectric layer 31 and a second dielectric layer 32 in the semiconductor layer 10 in sequence, so that the first dielectric layer 31 covers the top surface of the emitter metal 22 and extends along the side of the emitter metal 22 to cover the portion of the first surface 161 exposed outside the emitter metal 22; and the second dielectric layer 32 covers the first dielectric layer 31; the first dielectric layer 31 has a first opening 311; the second dielectric layer has a second opening 321 connected to the first opening 311;

[0055] Step S3 , forming a base metal 40 , connecting the base metal 40 to the base layer 15 through the first opening 311 and the second opening 321 ; and extending the base metal 40 to cover at least a portion of the second dielectric layer 32 adjacent to the second opening 321 .

[0056] The specific structure of the bipolar transistor structure 100 is described in detail below in conjunction with the specific steps of a method for manufacturing a bipolar transistor provided in a specific embodiment of the present invention.

[0057] The structure of the semiconductor layer 10 obtained in step S1 is as follows Figure 3 As shown in FIG. 1 (corresponding to the AA cross-sectional view), an emitter structure 20 is partially deposited on the first surface 161 , and the emitter structure 20 includes an emitter step 21 and an emitter metal 22 stacked in sequence.

[0058] Step S2 specifically includes step S21, step S22 and step S23.

[0059] Step S21, forming a first dielectric layer 31 on the semiconductor layer 10, so that the first dielectric layer 31 covers the top surface of the emitter metal 22 and extends along the side of the emitter metal 22 to cover the portion of the first surface 161 exposed outside the emitter metal 22. The structure after forming the first dielectric layer 31 in step S21 can be referred to Figure 4 (corresponding to the AA cross-sectional view). At this time, the first dielectric layer 31 covers the top surface of the emitter metal 22 , the side surface of the emitter metal 22 , the side surface of the emitter step 21 , and the portion of the first surface 161 exposed outside the emitter metal 22 .

[0060] Step S22 , etching the first dielectric layer 31 and the semiconductor layer 10 to form a base step 102 , wherein the base step 102 has a semiconductor side surface adjacent to the first surface 161 .

[0061] For example, step S22 specifically includes step S221 and step S222.

[0062] Step S221, using the first photoresist to complete the pattern transfer on the first dielectric layer 31 to form a primary etching step 101 (refer to Figure 5 , corresponding to the AA section view);

[0063] Step S222: Use a second photoresist to complete pattern transfer on the first etching step 101 to form a base step 102; the width of the second photoresist in the first direction is greater than the width of the first etching step 101 in the first direction, and the width of the second photoresist in the second direction is greater than the width of the first etching step 101 in the second direction, and the first direction and the second direction are cross-set.

[0064] For example, the first direction and the second direction are perpendicular to each other, and the first direction and the second direction are perpendicular to the stacking direction of each layer structure in the semiconductor layer 10. The structure of the base step 102 obtained in step S222 can refer to Figure 6 (corresponding to AA section view) and Figure 7 As shown in the cross-sectional view (corresponding to the BB view), the semiconductor layer 10 has a side surface adjacent to the first surface 161, and the side surface includes Figure 6 In the first direction, two first side surfaces 171 are opposite to each other, and Figure 7In the second direction, two second side surfaces 172 are opposite to each other. According to the requirements of the device structure, the width of the second photoresist in the first direction is greater than the width of the first etching step 101 in the first direction, so that a concave structure is formed on the semiconductor layer 10, and a recessed portion 1711 located at the collector layer 14 is formed on the two first side surfaces 171; the width of the second photoresist in the second direction is greater than the width of the first etching step 101 in the second direction, and a step portion 1721 is formed on the two second side surfaces 172, which can protect the two opposite sides in the second direction, so that when the wiring metal is formed later, the wiring metal can be formed on the second side surface 172, and the reliability of the metal wiring can be improved by the step portion 1721. The formation of the recessed portion 1711 removes part of the space of the PN junction in the bipolar transistor structure 100 obtained later, so that the effect of reducing the BC junction capacitance can be achieved.

[0065] It should be noted that the two first side surfaces 171 and the second side surface 172 may be inclined surfaces or vertical surfaces perpendicular to the substrate 11, and may be set as required, and this embodiment does not limit it. In step S222, the semiconductor layer 10 is etched to a thickness of 3000 to 7000 angstroms. Specifically, in step S222, the collector layer 14 is further etched, and part of the surface of the sub-collector layer 12 is exposed outside the base step 102. The part of the sub-collector layer 12 exposed outside the base step 102 (collector layer 14) may be referred to as the second surface 121 of the semiconductor layer 10.

[0066] In the above step S2, due to the presence of the first dielectric layer 31, passivation can be formed on the surface of the emitter layer 16 to protect the emitter layer 16 from being affected during the etching process, thereby improving the reliability of the structure. When the reliability is higher, a smaller effective spacing between the base metal and the emitter step can be designed, thereby reducing the area of ​​the device, thereby further reducing the BC junction area.

[0067] If the bipolar transistor structure 100 is an integrated transistor structure, for example, step S24 is performed after step S22, and an active region and a passive region 122 are formed corresponding to the sub-collector layer 12; the base step 102 is located in the active region. The bipolar transistor structure 100 includes an active region and a passive region 122, and the active region and the passive region 122 share the sub-collector layer 12. Specifically, in step S24, a photoresist may be covered on the structure formed in step S22, and the active region may be defined by a mask and then photolithography development may be performed, the active region may be protected by the photoresist, and ion implantation may be performed on the portion exposed outside the photoresist to form the passive region 122 to complete device isolation.

[0068] Step S23 is performed after step S22 or step S24.

[0069] Step S23, forming a second dielectric layer 32 on the base step 102, so that the second dielectric layer 32 covers the first dielectric layer 31 and the side surface of the semiconductor. Figure 8 (corresponding to the AA cross-sectional view), specifically, the second dielectric layer 32 covers the first dielectric layer 31 and extends along the edge of the first dielectric layer 31 to the semiconductor side surface and the second surface 121. This can achieve more comprehensive protection for the base step 102 and the sub-collector layer 12.

[0070] Step S23 further includes step S25, forming a third opening 322 in the region of the second dielectric layer 32 located in the active area and located on the second surface 121. In step S25, the first opening 311 is formed in the region of the first dielectric layer 31 located on the first surface 161, and the second opening 321 is formed in the region of the second dielectric layer 32 corresponding to the first opening 311.

[0071] For details, please refer to Fig. 9 (Corresponding to the AA cross-sectional view), using a mask photoresist on the second dielectric layer 32, the first opening 311, the second opening 321 and the third opening 322 can be formed synchronously by pattern transfer. In this embodiment, the maximum width of the first opening 311 is 0.2~1 micron. The maximum width of the second opening 321 is 0.2~1 micron. The minimum spacing between the first opening 311 and the emitter step 21 is 0.2~1 micron, or the width of the first opening 311 located at the contact interface between the first dielectric layer 31 and the emitter layer 16 is 0.2~1 micron to the emitter step 21. Among them, the side of the first dielectric layer 31 facing the first opening 311 and the side of the second dielectric layer 32 facing the second opening 321 can be an inclined surface or perpendicular to the first surface 161. In some embodiments, the inclination angle of the side wall of the first dielectric layer 31 toward the first opening 311 is less than or equal to 90°, and the inclination angle of the side wall of the second dielectric layer 32 toward the second opening 321 is less than or equal to 90°. The inclination angle here refers to the angle θ between the corresponding side wall and the first surface 161 (refer to Fig. 9 ). In some embodiments, the widths of the first opening 311 and the second opening 321 gradually decrease along the direction from the first dielectric layer 31 to the second dielectric layer 32 .

[0072] After step S25, proceed to step S3. Specifically, in step S3, a photomask and photoresist are used on the second dielectric layer 32 to deposit a base metal material by pattern transfer to form a base metal 40. Part of the formed base metal 40 is connected to the base layer 15 through the first opening 311 and the second opening 321. The base metal 40 extends to cover at least a portion of the second dielectric layer 32 adjacent to the second opening 321. The thickness (or height) of the base metal 40 is greater than or equal to 1000 angstroms and less than or equal to 10000 angstroms. By setting a larger height, the resistance of the base metal 40 can be made smaller. Since the frequency characteristics of the bipolar transistor are also negatively correlated with the resistance of the base metal, the effect of improving the frequency characteristics can also be achieved. In some embodiments, the thickness of the base metal 40 can be designed according to actual needs. For example, when used in a RF amplifier in the 5G frequency band, the thickness of the base metal 40 can be designed to be 3500~6500 angstroms. For example, when used in a RF amplifier in the 2G frequency band, the thickness of the base metal 40 can be selected to be around 1000 angstroms, which can reduce the cost of the device.

[0073] In step S3, a high temperature treatment may be performed after the base metal material is deposited, so that the bottom component of the base metal material infiltrates and contacts the base layer 15, and forms a good contact with the base layer 15. Alternatively, before depositing the base metal material, the emitter layer 16 corresponding to the first opening 311 and the second opening 321 may be removed by dry etching (using gas or plasma) or wet etching (using etching liquid), and then the base metal material is deposited, and finally a high temperature treatment is performed, so that the base metal material forms a good contact with the base layer 15. Of course, the method of forming the base metal 40 is not limited to the above example.

[0074] After step S3 is completed, the photoresist is removed to obtain Fig.10 (corresponding to the AA section view) shown in the structure.

[0075] Then, step S4 is performed, in which a first metal material is deposited on the second dielectric layer 32 by using a photomask and a photoresist to realize pattern transfer. A portion of the first metal material is located in the active area and connected to the sub-collector layer 12 through the third opening 322 to form a collector metal 51, and another portion is located in the passive area 122 and isolated from the sub-collector layer 12 through the second dielectric layer 32 to form a capacitor metal 52 (refer to Fig.11 , corresponding to the AA section view).

[0076] The material of the first metal layer may be, for example, AuGe / Ni / Au or Au / Ge / Ni / Au structure.

[0077] The capacitor metal 52 is located on the passive area 122. The capacitor metal 52 can be used as the lower plate of the capacitor of a passive device, such as a stack capacitor. In the related art, the lower plate of the capacitor directly contacts the semiconductor material. During the subsequent high-temperature treatment, the bottom surface of the capacitor lower plate in contact with the semiconductor material will become uneven, resulting in a decrease in device reliability. In this embodiment, the capacitor metal 52 is disposed on the second dielectric layer 32, and remains flat after the capacitor metal 52 is subjected to high-temperature treatment, which can improve the reliability of the capacitor.

[0078] After step S5, for example, step S6 is further included to form a third dielectric layer 33, where the third dielectric layer 33 covers the second dielectric layer 32 and the base metal 40. Figure 2 After the third dielectric layer 33 is formed on the second dielectric layer 32, the third dielectric layer 33 also covers the collector metal 51 and the capacitor metal 52. The third dielectric layer 33 covers the second dielectric layer 32, so the third dielectric layer 33 also covers the emitter metal 22. The third dielectric layer 33 can provide more comprehensive protection, and when the connecting wire metal is subsequently prepared, the corresponding position of the third dielectric layer 33 can be opened to achieve the connection of the corresponding connecting wire metal with the base metal 40, the collector metal 51 and the emitter metal 22. The material of the third dielectric layer 33 can be the same as or different from the material of the second dielectric layer 32, and the thickness of the third dielectric layer 33 can be the same as or different from the thickness of the second dielectric layer 32.

[0079] The bipolar transistor structure 100 and the method for preparing the bipolar transistor structure provided by the embodiment of the present invention can reduce the device area, reduce the BC junction area, and reduce the resistance of the base metal 40 while maintaining a suitable effective spacing between the base metal and the emitter step through the design of the base metal 40. The PN junction volume can be reduced by the recessed portion 1711. The emitter layer 16 can be protected by the first dielectric layer 31 to improve reliability, and the effect of reducing the BC junction capacitance of the device can be achieved through the comprehensive design of multiple locations, thereby improving the frequency characteristics of the device.

[0080] In some embodiments, the invention embodiment further provides a radio frequency amplifier, the radio frequency amplifier includes any of the aforementioned bipolar transistor structures 100, or the radio frequency amplifier includes a bipolar transistor structure manufactured by any of the aforementioned manufacturing methods. The radio frequency amplifier has the same effect as the bipolar transistor structure, which will not be described in detail here.

[0081] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A bipolar transistor structure, characterized in that: comprising an active region, the active region having: A semiconductor layer having a first surface, wherein the semiconductor layer comprises a collector layer, a base layer and an emitter layer stacked in sequence; the first surface is a surface of the emitter layer facing away from the base layer; An emitter step, disposed on the emitter layer; An emitter metal is disposed on the emitter step; A first dielectric layer, covering the top surface of the emitter metal, and extending along the side of the emitter metal to cover a portion of the first surface exposed outside the emitter metal; The first dielectric layer has a first opening; a second dielectric layer, covering the first dielectric layer; The second dielectric layer has a second opening communicating with the first opening; A base metal connected to the base layer through the first opening and the second opening; and extending to cover at least a portion of the second dielectric layer adjacent to the second opening; The thickness of the first dielectric layer and the second dielectric layer ranges from 200 to 1000 angstroms respectively; the maximum width of the first opening is 0.2 to 1 micrometer, and the maximum width of the second opening is 0.2 to 1 micrometer; the minimum distance between the first opening and the emitter step is 0.2 to 1 micrometer.

2. The bipolar transistor structure according to claim 1, wherein: The semiconductor layer also has a semiconductor side surface adjacent to the first surface; the second dielectric layer also covers the semiconductor side surface.

3. The bipolar transistor structure according to claim 2, wherein: The invention also includes a third dielectric layer, wherein the third dielectric layer covers the second dielectric layer and the base metal.

4. The bipolar transistor structure according to claim 1, wherein: An inclination angle of the first dielectric layer toward the side wall in the first opening is less than or equal to 90°, and an inclination angle of the second dielectric layer toward the side wall in the second opening is less than or equal to 90°.

5. The bipolar transistor structure according to claim 1, wherein: The thickness of the base metal is 1000-10000 angstroms.

6. The bipolar transistor structure according to claim 2, wherein: The semiconductor side surface has two first side surfaces opposite to each other in a first direction and two second side surfaces opposite to each other in a second direction, the first direction is arranged to intersect with the second direction, and recessed portions located in the collector layer are formed on the two first side surfaces.

7. The bipolar transistor structure according to claim 6, characterized in that: The semiconductor side surface has two second side surfaces that are opposite to each other in the second direction, and step portions are formed on the two second side surfaces.

8. The bipolar transistor structure according to claim 3, wherein: The semiconductor layer further comprises a sub-collector layer located on a side of the collector layer facing away from the base layer, and the semiconductor layer further comprises a second surface, which is a surface of the sub-collector layer facing the collector layer and exposed outside the collector layer; The second dielectric layer also covers the second surface; the area of ​​the second dielectric layer located on the second surface has a third opening; the semiconductor layer also includes a collector metal, the collector metal is connected to the sub-collector layer through the third opening, and the third dielectric layer also covers the collector metal.

9. The bipolar transistor structure according to claim 8, characterized in that: It also includes a passive area, which shares the sub-collector layer with the active area; the bipolar transistor structure also includes a capacitor metal arranged in the passive area, the capacitor metal is arranged on the second dielectric layer, and the third dielectric layer covers the capacitor metal.

10. A method for preparing a bipolar transistor structure, characterized in that: include: Step S1, pre-treating the epitaxial structure to obtain a semiconductor layer; The semiconductor layer has a first surface, and the semiconductor layer includes: a collector layer, a base layer and an emitter layer stacked in sequence; the first surface is the side of the emitter layer facing away from the base layer; an emitter step is arranged on the emitter layer; an emitter metal is arranged on the emitter step; Step S2, forming a first dielectric layer and a second dielectric layer in sequence on the semiconductor layer, so that the first dielectric layer covers the top surface of the emitter metal and extends along the side of the emitter metal to cover the portion of the first surface exposed outside the emitter metal; and the second dielectric layer covers the first dielectric layer; the first dielectric layer has a first opening; the second dielectric layer has a second opening connected to the first opening; wherein the thickness range of the first dielectric layer and the second dielectric layer is 200 to 1000 angstroms respectively; the maximum width of the first opening is 0.2 to 1 micron, and the maximum width of the second opening is 0.2 to 1 micron; the minimum distance between the first opening and the emitter step is 0.2 to 1 micron; Step S3, forming a base metal, connecting the base metal to the base layer through the first opening and the second opening; and extending the base metal to cover at least a portion of the second dielectric layer adjacent to the second opening.

11. The method for preparing a bipolar transistor structure according to claim 10, wherein: The step S2 comprises: Step S21, forming a first dielectric layer on the semiconductor layer, so that the first dielectric layer covers the top surface of the emitter metal and extends along the side of the emitter metal to cover the portion of the first surface exposed outside the emitter metal; Step S22, etching the first dielectric layer and the semiconductor layer to form a base step, wherein the base step has a semiconductor side surface adjacent to the first surface; Step S23, forming a second dielectric layer on the base step, so that the second dielectric layer covers the first dielectric layer and covers the side surface of the semiconductor.

12. The method for preparing a bipolar transistor structure according to claim 11, characterized in that: The step S22 includes: step S221, completing pattern transfer on the first dielectric layer using a first photoresist to form a primary etching step; step S222: completing pattern transfer on the primary etching step using a second photoresist to form the base step.

13. The method for preparing a bipolar transistor structure according to claim 11, characterized in that: The semiconductor layer further includes a sub-collector layer, the sub-collector layer being located on a side of the collector layer facing away from the base layer; and after the base step is formed in step S22, a portion of the surface of the sub-collector layer is exposed outside the base step to form a second surface; After step S22 and before step S23, step S24 is performed to form an active region and an inactive region corresponding to the sub-collector layer; the base region step is located in the active region; After step S23, the method further includes step S25 of forming a third opening in a region of the second dielectric layer located in the active region and on the second surface; Step S2 also includes step S4, depositing a first metal material on the second dielectric layer, wherein a portion of the first metal material is located in the active area and connected to the sub-collector layer through the third opening to form a collector metal, and another portion of the first metal material is located in the passive area and isolated from the sub-collector layer through the second dielectric layer to form a capacitor metal.

14. A radio frequency amplifier, characterized in that: A bipolar transistor structure comprising the bipolar transistor structure as described in any one of claims 1 to 9 or a bipolar transistor structure manufactured by the method for manufacturing the bipolar transistor structure as described in any one of claims 10 to 13.

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