A method for improving electrode contact based on flattening of N-type heterojunction battery substrate

Abstract

The present invention relates to the field of solar cells, and discloses an electrode contact improvement method based on the flattening of the N-type heterojunction battery substrate, the steps of which are: cleaning and texturing the silicon wafer; performing laser ablation flattening treatment on the bottom layer of the silicon wafer after texturing, and then depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer in sequence; depositing an ITO transparent conductive layer on the surface of the doped microcrystalline silicon layer; vacuum sputtering a buffer layer on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3, Pt and tungsten-molybdenum alloy in a mass ratio of 3~5:1~3:1; printing a conductive silver paste on the buffer layer, and curing to obtain a silver electrode. The present invention flattens the bottom layer of the silicon wafer substrate after texturing, enhances the planar effect of the bottom layer of the substrate, generates more photons, and improves the utilization rate of light; and adds a buffer layer between the metal Ag electrode and the ITO conductive film, which can improve the current collection rate and the conversion efficiency of the battery cell.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to an electrode contact improvement method based on flattening of an N-type heterojunction cell substrate. Background Art

[0002] HJT cells (intrinsic thin film heterojunction cells) have a symmetrical double-sided cell structure with an N-type single crystal silicon wafer in the middle. Intrinsic amorphous silicon thin film and N-type microcrystalline silicon thin film are deposited on the front to form a PN junction, while intrinsic amorphous silicon thin film and P-type microcrystalline silicon thin film are deposited on the back to form a back surface field. In view of the poor conductivity of amorphous silicon, transparent conductive films are deposited on both sides of the cell for conduction, and finally screen printing technology is used to form double-sided electrodes.

[0003] In the prior art, when preparing HJT cells, an amorphous silicon film layer is directly deposited after the silicon substrate is textured, and a metal Ag electrode is directly printed on the ITO transparent conductive film. For example, in the "A Method for Preparing HJT Cells and HJT Components" disclosed in the Chinese patent literature, with the publication number CN110429149A, the HJT cell preparation method specifically includes: providing an original silicon wafer; cutting the original silicon wafer; performing a texture operation on the cut silicon wafer to form a texture surface on the silicon wafer surface; depositing an intrinsic amorphous silicon layer on the surface of the textured silicon wafer; depositing a doped amorphous silicon layer on the intrinsic amorphous silicon layer; depositing a transparent conductive oxide layer on the doped amorphous silicon layer; and forming a gate electrode on the transparent conductive oxide layer.

[0004] However, the amorphous silicon film layer is directly deposited after texturing, and the bottom layer of the substrate material has a velvet surface, resulting in a large contact area and a high recombination rate. The bottom layer of the pyramid reduces the photon generation rate, thus affecting the battery efficiency. In addition, the Ag electrode is directly printed on the ITO film. Due to the difference in energy level matching between the Ag electrode and the ITO transparent conductive film, it will affect the transmission and collection of carriers, which is not conducive to improving the battery performance. Summary of the invention

[0005] The present invention aims to overcome the above-mentioned problems existing in HJT batteries in the prior art and provides an electrode contact improvement method based on flattening of N-type heterojunction battery substrates. After texturing, the bottom layer of the silicon wafer substrate is flattened to enhance the planar effect of the bottom layer of the substrate, generate more photons, and improve the utilization rate of light; and a buffer layer is added between the metal Ag electrode and the ITO conductive film to improve the current collection rate and improve the conversion efficiency of the battery cell.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0008] (1) Cleaning and texturing the silicon wafer to produce a pyramid texture on the surface of the silicon wafer;

[0009] (2) Performing laser ablation and flattening treatment on the bottom layer of the silicon wafer after texturing, so that the bottom layer becomes a flat tower base;

[0010] (3) depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation treatment;

[0011] (4) depositing an ITO transparent conductive layer on the surface of the doped microcrystalline silicon layer;

[0012] (5) vacuum sputtering a buffer layer on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3, Pt and tungsten-molybdenum alloy in a mass ratio of 3-5:1-3:1, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 30-50%;

[0013] (6) Printing conductive silver paste on the buffer layer and curing it to obtain a silver electrode.

[0014] The present invention performs laser ablation and flattening treatment on the bottom layer of the silicon wafer substrate after texturing. The laser is irradiated on the bottom layer of the substrate to instantly heat and melt it, so that its pyramid gradually disappears, and finally the bottom layer becomes a flattened tower base. After the tower base is flattened, the contact surface is reduced, the number of dangling bonds is correspondingly reduced, the recombination is reduced, and the passivation effect of the bottom layer is improved. At the same time, the planar effect formed by the flattening of the bottom layer will increase the reflectivity of the bottom layer, which can increase the reuse of light and improve the utilization rate of light. At the same time, in order to alleviate the difference in energy level matching between the Ag electrode and the ITO conductive layer, the present invention sets a buffer layer between the ITO conductive layer and the Ag electrode. The MoO3 in the buffer layer has high transmittance, high work function, and matches the ITO layer in energy band, and is a good buffer layer material; but MoO3 has poor conductivity, and using it only as a buffer layer will affect the conductive effect. Therefore, the present invention also adds Pt and tungsten-molybdenum alloy to the buffer layer to ensure the conductivity of the buffer layer. By adjusting the amount of MoO3, Pt and tungsten-molybdenum alloy, the buffer layer and the ITO layer have high energy level matching and good conductivity, which can improve the current collection rate and improve the conversion efficiency and stability of the battery cell.

[0015] Preferably, in step (1), the silicon wafer is textured by wet etching with alkaline solution, and the silicon wafer uses an N-type substrate silicon wafer with a thickness of 90-120 μm.

[0016] Preferably, the laser ablation depth in step (2) is 3-4 μm.

[0017] Preferably, in step (3), the intrinsic amorphous silicon layer and the doped microcrystalline silicon layer are deposited by PECVD method.

[0018] Preferably, the thickness of the intrinsic amorphous silicon layer deposited in step (3) is 5-15 nm, and the thickness of the doped microcrystalline silicon layer is 15-35 nm.

[0019] Preferably, in step (4), the ITO layer is deposited by PVD method.

[0020] Preferably, the thickness of the ITO layer deposited in step (4) is 50-130 nm.

[0021] Preferably, the thickness of the buffer layer in step (5) is 2-4 nm.

[0022] Preferably, in step (6), the thickness of the silver electrode is 8-25 μm.

[0023] Preferably, the curing temperature of step (6) is 200°C to 220°C.

[0024] Therefore, the present invention has the following beneficial effects:

[0025] (1) After the heterojunction silicon wafer is textured, the bottom layer of the substrate is laser flattened to enhance the planar effect of the bottom layer of the substrate, generate more photons, and improve the utilization rate of light; at the same time, after the bottom layer of the substrate is laser flattened, the interface contact area is reduced, the number of dangling bonds is reduced accordingly, the recombination is reduced, and the bottom layer passivation effect is improved;

[0026] (2) A buffer layer including MoO3, Pt and tungsten-molybdenum alloy is set between the metal Ag electrode and the ITO conductive layer to improve the contact between the Ag electrode and the ITO layer, increase the current collection rate, and improve the conversion efficiency of the battery cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of the heterojunction battery of the present invention.

[0028] In the figure: 1-silicon wafer, 2-intrinsic amorphous silicon layer, 3-doped microcrystalline silicon layer, 4-ITO transparent conductive layer, 5-buffer layer, 6-silver electrode. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0030] In the present invention, unless otherwise specified, all equipment and raw materials can be purchased from the market or are commonly used in the industry. The methods in the following embodiments, unless otherwise specified, are conventional methods in the art.

[0031] Overall embodiment:

[0032] A structure based on Figure 1The electrode contact improvement method for flattening the N-type heterojunction battery substrate shown in the figure comprises the following steps:

[0033] (1) Cleaning and texturing the silicon wafer 1 to form a pyramid texturing surface on the surface of the silicon wafer;

[0034] (2) Performing laser ablation and flattening treatment on the bottom layer of the silicon wafer after texturing, so that the bottom layer becomes a flat tower base;

[0035] (3) depositing an intrinsic amorphous silicon layer 2 and a doped microcrystalline silicon layer 3 in sequence on the surface of the silicon wafer after the ablation treatment;

[0036] (4) depositing an ITO transparent conductive layer 4 on the surface of the doped microcrystalline silicon layer;

[0037] (5) vacuum sputtering a buffer layer 5 on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3, Pt and tungsten-molybdenum alloy in a mass ratio of 3-5:1-3:1, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 30-50%;

[0038] (6) Printing a conductive silver paste on the buffer layer and curing it to obtain a silver electrode 6.

[0039] As a specific implementation method, in step (1), the silicon wafer is textured by wet etching with alkaline solution, and the silicon wafer uses an N-type substrate silicon wafer with a thickness of 90-120 μm.

[0040] As a specific implementation, the laser ablation depth in step (2) is 3-4 μm.

[0041] As a specific implementation, in step (3), the intrinsic amorphous silicon layer and the doped microcrystalline silicon layer are deposited by PECVD method.

[0042] As a specific implementation, the thickness of the intrinsic amorphous silicon layer deposited in step (3) is 5-15 nm, and the thickness of the doped microcrystalline silicon layer is 15-35 nm.

[0043] As a specific implementation, in step (4), the ITO layer is deposited by PVD method.

[0044] As a specific implementation, the thickness of the ITO layer deposited in step (4) is 50-130 nm.

[0045] As a specific implementation, the thickness of the buffer layer in step (5) is 2-4 nm.

[0046] As a specific implementation, the thickness of the silver electrode in step (6) is 8-25 μm.

[0047] As a specific implementation, the curing temperature of step (6) is 200°C~220°C.

[0048] Embodiment 1:

[0049] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0050] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0051] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2 , the ablation depth is about 3 μm;

[0052] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0053] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0054] (5) vacuum sputtering a buffer layer with a thickness of 3 nm on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3, Pt and tungsten-molybdenum alloy in a mass ratio of 4:2:1, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 40%;

[0055] (6) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0056] Embodiment 2:

[0057] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0058] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0059] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2, the ablation depth is about 4 μm;

[0060] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0061] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0062] (5) vacuum sputtering a buffer layer with a thickness of 2 nm on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3, Pt and tungsten-molybdenum alloy in a mass ratio of 3:1:1, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 40%;

[0063] (6) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0064] Embodiment 3:

[0065] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0066] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0067] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2 , the ablation depth is about 4 μm;

[0068] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0069] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0070] (5) vacuum sputtering a buffer layer with a thickness of 4 nm on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3, Pt and tungsten-molybdenum alloy in a mass ratio of 5:3:1, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 40%;

[0071] (6) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0072] Comparative Example 1 (without flattening):

[0073] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0074] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0075] (2) Using the PECVD method, an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer are sequentially deposited on the surface of the silicon wafer after texturing; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0076] (3) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0077] (4) vacuum sputtering a buffer layer with a thickness of 3 nm on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3, Pt and tungsten-molybdenum alloy in a mass ratio of 4:2:1, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 40%;

[0078] (5) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0079] Comparative Example 2 (no buffer layer):

[0080] A method for preparing an N-type heterojunction battery comprises the following steps:

[0081] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0082] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2 , the ablation depth is about 3 μm;

[0083] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0084] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0085] (5) A conductive silver paste was printed on the ITO transparent conductive layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0086] Comparative Example 3 (buffer layer is MoO3 layer):

[0087] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0088] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0089] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2 , the ablation depth is about 3 μm;

[0090] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0091] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0092] (5) A buffer layer with a thickness of 3 nm is vacuum sputtered on the surface of the ITO transparent conductive layer; the raw material of the buffer layer is MoO3;

[0093] (6) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0094] Comparative Example 4 (buffer layer is Pt):

[0095] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0096] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0097] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2 , the ablation depth is about 3 μm;

[0098] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0099] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0100] (5) A buffer layer with a thickness of 3 nm is vacuum sputtered on the surface of the ITO transparent conductive layer; the raw material of the buffer layer is Pt;

[0101] (6) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0102] Comparative Example 5 (buffer layer is tungsten-molybdenum alloy):

[0103] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0104] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0105] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2 , the ablation depth is about 3 μm;

[0106] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0107] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0108] (5) A buffer layer with a thickness of 3 nm is vacuum sputtered on the surface of the ITO transparent conductive layer; the raw material of the buffer layer is tungsten-molybdenum alloy, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 40%;

[0109] (6) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0110] Comparative Example 6 (the buffer layer does not include tungsten-molybdenum alloy):

[0111] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0112] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0113] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2 , the ablation depth is about 3 μm;

[0114] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0115] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0116] (5) vacuum sputtering a buffer layer with a thickness of 3 nm on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3 and Pt in a mass ratio of 4:2;

[0117] (6) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0118] Comparative Example 7 (Pt is not included in the buffer layer):

[0119] A method for improving electrode contact based on flattening of an N-type heterojunction battery substrate comprises the following steps:

[0120] (1) A silicon wafer with a thickness of 110 μm, a size of 210 × 105 mm, and a resistivity of 1.0 Ω·cm was taken and cleaned to remove organic dirt, metal impurities, and a surface damage layer on the surface of the silicon wafer. After cleaning, the silicon wafer was textured with an alkaline solution to produce a pyramid texture surface on the surface of the silicon wafer. The alkaline solution was a NaOH solution with a mass concentration of 45%, and the alkaline solution treatment time was 420 s.

[0121] (2) The bottom layer of the silicon wafer after texturing is subjected to laser ablation and flattening treatment to make the bottom layer a flat tower base. The laser intensity is 30 W / m 2 , the ablation depth is about 3 μm;

[0122] (3) Depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation in sequence by PECVD; the thickness of the intrinsic amorphous silicon layer is 10 nm, and the thickness of the doped microcrystalline silicon layer is 25 nm;

[0123] (4) Depositing an ITO transparent conductive layer with a thickness of 100 nm on the surface of the doped microcrystalline silicon layer by PVD method;

[0124] (5) vacuum sputtering a buffer layer with a thickness of 3 nm on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3 and tungsten-molybdenum alloy with a mass ratio of 4:1, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 40%;

[0125] (6) A conductive silver paste was printed on the buffer layer by screen printing and cured at 210°C to obtain a silver electrode with a thickness of 15 μm.

[0126] The performance of the heterojunction batteries prepared in the above embodiments and comparative examples was tested, and the results are shown in Table 1.

[0127] Table 1: Heterojunction cell performance test results

[0128]

[0129] As can be seen from Table 1, in Examples 1 to 3, the method of the present invention is adopted to flatten the bottom layer of the silicon wafer after texturing, and a buffer layer is arranged between the ITO layer and the Ag electrode. The obtained heterojunction battery has high photoelectric conversion efficiency, open circuit voltage, short circuit current and fill factor.

[0130] In comparative example 1, the bottom layer of the silicon wafer after texturing is not subjected to laser ablation and flattening, the contact surface area between the bottom layer and the amorphous silicon film layer is large, and the interface recombination rate is large, resulting in a significant decrease in the filling factor of the battery compared with that in example 1.

[0131] In Comparative Example 2, no buffer layer is provided between the ITO layer and the Ag electrode. Due to the imperfectly matched energy levels between the ITO material and the Ag metal electrode, various performances of the battery are reduced compared with those in Example 1.

[0132] In Comparative Example 3, only MoO3 is used as the buffer layer. Although the energy level matching with the ITO layer can be improved, the conductivity of the buffer layer is poor and the battery performance is also reduced compared with that in Example 1.

[0133] In Comparative Examples 4 and 5, only a metal Pt layer or a tungsten-molybdenum alloy layer is used as a buffer layer. Although the conductivity is good, the energy level matching of the buffer layer and the ITO layer is reduced. In Comparative Examples 6 and 7, no tungsten-molybdenum alloy and Pt are added to the buffer layer, and the energy band matching of the buffer layer and the ITO layer is also reduced, and the battery performance cannot reach the effect in the embodiment.

Claims

1. A method for improving electrode contact based on flattening of N-type heterojunction battery substrate, characterized in that: The steps include: (1) Cleaning and texturing the silicon wafer to produce a pyramid texture on the surface of the silicon wafer; (2) Performing laser ablation and flattening treatment on the bottom layer of the silicon wafer after texturing, so that the bottom layer becomes a flat tower base; (3) depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the surface of the silicon wafer after ablation treatment; (4) depositing an ITO transparent conductive layer on the surface of the doped microcrystalline silicon layer; (5) vacuum sputtering a buffer layer on the surface of the ITO transparent conductive layer; the raw materials of the buffer layer include MoO3, Pt and tungsten-molybdenum alloy in a mass ratio of 3-5:1-3:1, and the mass fraction of tungsten in the tungsten-molybdenum alloy is 30-50%; (6) Printing conductive silver paste on the buffer layer and curing it to obtain a silver electrode.

2. The electrode contact improvement method based on N-type heterojunction battery substrate flattening according to claim 1 is characterized in that: In step (1), the silicon wafer is textured by wet etching with alkaline solution, and the silicon wafer uses an N-type substrate silicon wafer with a thickness of 90-120 μm.

3. The electrode contact improvement method based on flattening of N-type heterojunction battery substrate according to claim 1 is characterized in that: The laser ablation depth in step (2) is 3~4μm.

4. The electrode contact improvement method based on N-type heterojunction battery substrate flattening according to claim 1 is characterized in that: In step (3), the intrinsic amorphous silicon layer and the doped microcrystalline silicon layer are deposited by PECVD method.

5. The electrode contact improvement method based on flattening of N-type heterojunction battery substrate according to claim 1 or 4, characterized in that: The thickness of the intrinsic amorphous silicon layer deposited in step (3) is 5-15 nm, and the thickness of the doped microcrystalline silicon layer is 15-35 nm.

6. The electrode contact improvement method based on flattening of N-type heterojunction battery substrate according to claim 1 is characterized in that: In step (4), the ITO layer is deposited by PVD method.

7. The electrode contact improvement method based on flattening of N-type heterojunction battery substrate according to claim 1 or 6, characterized in that: The thickness of the ITO layer deposited in step (4) is 50-130 nm.

8. The electrode contact improvement method based on N-type heterojunction battery substrate flattening according to claim 1 is characterized in that: The thickness of the buffer layer in step (5) is 2-4 nm.

9. The electrode contact improvement method based on N-type heterojunction battery substrate flattening according to claim 1 is characterized in that: The thickness of the silver electrode in step (6) is 8-25 μm.

10. The electrode contact improvement method based on flattening of N-type heterojunction battery substrate according to claim 1 or 9, characterized in that: The curing temperature of step (6) is 200°C to 220°C.

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