Light emitting diode with improved pad breakage and method of making the same

Abstract

This disclosure provides a light-emitting diode (LED) with improved pad damage and its fabrication method, belonging to the field of optoelectronic manufacturing technology. The LED includes an epitaxial layer, a first electrode, and a passivation layer. The first electrode includes a marking electrode block and a connecting electrode block, which are spaced apart on the surface of the epitaxial layer. The passivation layer is located on the surface of the epitaxial layer and covers the first electrode. The passivation layer has marking holes exposing the marking electrode blocks and connecting holes exposing the connecting electrode blocks. The shape of the marking holes is different from the shape of the connecting holes. The orthographic projection of the marking holes onto the surface of the epitaxial layer is a first projection, and the orthographic projection of the marking electrode blocks onto the surface of the epitaxial layer is a second projection. The first projection is located within the second projection, and the shape of the first projection is the same as that of the second projection, and the geometric center of the first projection coincides with the geometric center of the second projection. This embodiment of the disclosure can improve the problem of uneven thickness in the film layer formed above the marking holes.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode with improved pad damage and its fabrication method. Background Technology

[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. An LED consists of an epitaxial layer, a passivation layer, and two pads. The passivation layer is located on the surface of the epitaxial layer, and the two pads are located on the surface of the passivation layer and are connected to different semiconductor layers of the epitaxial layer through vias on the surface of the passivation layer.

[0003] In related technologies, when fabricating pads, a V-shaped notch is typically created on the surface of one pad as a marker to facilitate identification by technicians. However, when viewed from the side of the epitaxial layer away from the pad, the marker on the pad is difficult to observe. Therefore, a marking hole is formed on the passivation layer, through which one of the two pads is connected to the corresponding semiconductor layer on the epitaxial layer. The shape of the marking hole differs from the shape of other vias on the passivation layer, allowing technicians to determine the location of different types of pads by observing the position of the marking hole.

[0004] Marker vias are typically designed with a different shape than other vias to facilitate identification. However, the metal film layer fabricated over irregularly shaped marker vias can exhibit inconsistent thickness in certain areas. If the solder pads are too thin, pad breakage may occur. Summary of the Invention

[0005] This disclosure provides a light-emitting diode with improved pad damage and its fabrication method, which can improve the problem of uneven film thickness formed above the marking hole. The technical solution is as follows:

[0006] On one hand, this disclosure provides a light-emitting diode (LED) comprising: an epitaxial layer, a first electrode, and a passivation layer. The first electrode includes a marking electrode block and a connecting electrode block, which are spaced apart on the surface of the epitaxial layer. The passivation layer is located on the surface of the epitaxial layer and covers the first electrode. The passivation layer has a marking hole exposing the marking electrode block and a connecting hole exposing the connecting electrode block. The shape of the marking hole is different from the shape of the connecting hole. The orthographic projection of the marking hole on the surface of the epitaxial layer is a first projection, and the orthographic projection of the marking electrode block on the surface of the epitaxial layer is a second projection. The first projection is located within the second projection, and the shape of the first projection is the same as the shape of the second projection, and the geometric center of the first projection coincides with the geometric center of the second projection.

[0007] Optionally, the ratio of the distance from the inner contour of the first projection to the outer contour of the second projection to the maximum width of the marking electrode block is greater than or equal to 0.08.

[0008] Optionally, the ratio of the distance from the inner contour of the first projection to the outer contour of the second projection to the maximum width of the marking electrode block is less than or equal to 0.33.

[0009] Optionally, the orthographic projection of the connecting electrode block on the surface of the epitaxial layer is a third projection, and the area of ​​the third projection is smaller than the area of ​​the second projection.

[0010] Optionally, the marking electrode block is located at the peripheral edge of the epitaxial layer.

[0011] Optionally, the thickness of the marking electrode block is 1 μm to 1.5 μm.

[0012] Optionally, the outer contour of the first projection includes two arcs, which are symmetrically distributed and whose endpoints are connected to form a closed curve; or, the shape of the first projection is a polygon or an ellipse.

[0013] Optionally, the light-emitting diode further includes a current blocking layer located between the epitaxial layer and the marking electrode block; the orthographic projection of the current blocking layer on the surface of the epitaxial layer is a fourth projection, the second projection is located within the fourth projection, the shape of the fourth projection is the same as the shape of the second projection, and the geometric center of the fourth projection coincides with the geometric center of the second projection.

[0014] Optionally, the light-emitting diode further includes: an insulating layer, a second electrode, and a pad; the second electrode is located on the surface of the passivation layer away from the epitaxial layer, and the second electrode is electrically connected to the marking electrode block through the marking hole, and the second electrode is electrically connected to the connecting electrode block through the connecting hole; the insulating layer is located on the surface of the passivation layer away from the epitaxial layer, the insulating layer has a through hole, the pad is located on the surface of the insulating layer away from the epitaxial layer, and is electrically connected to the second electrode through the through hole.

[0015] This disclosure provides a method for fabricating a light-emitting diode (LED). The method includes: fabricating an epitaxial layer; forming a first electrode on the surface of the epitaxial layer, the first electrode including a marking electrode block and a connecting electrode block, the marking electrode block and the connecting electrode block being arranged at intervals on the surface of the epitaxial layer; forming a passivation layer on the surface of the epitaxial layer, the passivation layer covering the first electrode, the passivation layer having a marking hole exposing the marking electrode block and a connecting hole exposing the connecting electrode block, the shape of the marking hole being different from the shape of the connecting hole; the orthographic projection of the marking hole on the surface of the epitaxial layer being a first projection, the orthographic projection of the marking electrode block on the surface of the epitaxial layer being a second projection, the first projection being located within the second projection, the shape of the first projection being the same as the shape of the second projection, and the geometric center of the first projection coinciding with the geometric center of the second projection.

[0016] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0017] The light-emitting diode provided in this embodiment includes an epitaxial layer, a first electrode, and a passivation layer. The first electrode includes marking electrode blocks and connecting electrode blocks spaced apart on the epitaxial layer. The passivation layer is located on the surface of the epitaxial layer and covers the marking electrode blocks and connecting electrode blocks. The passivation layer has marking holes at positions corresponding to the marking electrode blocks and connecting holes at positions corresponding to the connecting electrode blocks. The marking holes and connecting holes have different shapes, so that the location of different types of pads can be quickly determined from the surface of the epitaxial layer away from the first electrode by the location of the marking holes.

[0018] Simultaneously, the first projection of the marking hole lies within the second projection of the marking electrode block. The first and second projections have the same shape, and their geometric centers coincide, thus placing the marking hole in the central region of the marking electrode block. During the etching of the marking hole on the passivation layer, points on the passivation layer at the same distance from the geometric center of the marking hole are also at the same distance from the peripheral edge of the marking electrode block. Therefore, after etching the passivation layer, the morphology of areas on the passivation layer at the same distance from the geometric center of the marking hole is also identical. This prevents excessive thickness differences in certain areas from appearing on the surface of the passivation layer, mitigating the problem of easily damaged solder pads. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1This is a top view of a light-emitting diode provided by related technologies;

[0021] Figure 2 yes Figure 1 Provided AA section diagram;

[0022] Figure 3 This is a top view of a light-emitting diode provided in an embodiment of this disclosure;

[0023] Figure 4 yes Figure 3 A BB cross-sectional view is provided;

[0024] Figure 5 yes Figure 4 A magnified view of a portion at point C is provided.

[0025] Figure 6 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure.

[0026] The markings in the diagram are explained as follows:

[0027] 10. Substrate;

[0028] 20. Epitaxial layer;

[0029] 30. Passivation layer; 31. Marking hole; 32. Connecting hole;

[0030] 40. First electrode; 41. Marking electrode block; 42. Connecting electrode block;

[0031] 51. Transparent conductive layer; 52. Current blocking layer;

[0032] 60. Insulation layer;

[0033] 70. Second electrode;

[0034] 80. Solder pads. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0036] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0037] Figure 1 This is a top view of a light-emitting diode provided by related technologies. Figure 2 yes Figure 1 The provided AA cross-sectional diagram. (For example...) Figure 1 , 2 As shown, the light-emitting diode in the related technology includes: an epitaxial layer 20, a passivation layer 30, and a first electrode 40. The first electrode 40 is located on the surface of the epitaxial layer 20, and the passivation layer 30 is located on the surface of the epitaxial layer 20, and the passivation layer 30 covers the first electrode 40.

[0038] like Figure 1 As shown, the first electrode 40 includes a marking electrode block 41 distributed in the corner region of the epitaxial layer 20 and a connecting electrode block 42 distributed in the central region of the epitaxial layer 20.

[0039] The connecting electrode block 42 is circular, while the marking electrode block 41 is finger-shaped. That is, the marking electrode block 41 and the connecting electrode block 42 have different shapes, and the marking electrode block 41 is typically located below a pad 80. This allows technicians to determine the location of different types of pads 80 by observing the position of the marking electrode block 41.

[0040] like Figure 2As shown, the passivation layer 30 has a marking hole 31 exposing the marking electrode block 41. Typically, the marking electrode block 41 includes a finger strip and a circular block, with the circular block located at one end of the finger strip. The width of the finger strip is smaller than the diameter of the circular block. The circular block is used to achieve conductivity with other metal film layers. Therefore, providing a circular block increases the conductive area of ​​the marking electrode block 41. Thus, the marking hole 31 is typically located above the circular block, which results in the marking hole 31 being distributed to the left or right of the marking electrode block 41, i.e., the marking hole 31 is offset from the central region of the marking electrode block 41.

[0041] See Figure 2 During the fabrication of the marking hole 31 on the passivation layer 30, points on the passivation layer 30 that are equidistant from the geometric center of the marking hole 31 have different distances from the peripheral edge of the marking electrode block 41. Furthermore, the thickness fluctuation is greater in the region of the passivation layer 30 closer to the peripheral edge of the marking electrode block 41. This results in inconsistent thickness in certain areas of the passivation layer 30 (see areas indicated by arrows M and N). If the second electrode 70 and the pad fabricated above the marking hole 31 are too thin, damage to the second electrode 70 and the pad may occur.

[0042] Therefore, this disclosure provides a light-emitting diode. Figure 3 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 4 yes Figure 3 A BB cross-sectional view is provided. For example... Figure 3 , 4 As shown, the light-emitting diode includes an epitaxial layer 20, a first electrode 40, and a passivation layer 30. The first electrode 40 includes a marking electrode block 41 and a connecting electrode block 42. The marking electrode block 41 and the connecting electrode block 42 are arranged at intervals on the surface of the epitaxial layer 20. The passivation layer 30 is located on the surface of the epitaxial layer 20 and covers the first electrode 40.

[0043] like Figure 3 As shown, the passivation layer 30 has a marking hole 31 that exposes the marking electrode block 41 and a connection hole 32 that exposes the connection electrode block 42. The shape of the marking hole 31 is different from the shape of the connection hole 32.

[0044] like Figure 3 As shown, the orthographic projection of the marking hole 31 on the surface of the epitaxial layer 20 is the first projection, and the orthographic projection of the marking electrode block 41 on the surface of the epitaxial layer 20 is the second projection. The first projection is located within the second projection, the shape of the first projection is the same as the shape of the second projection, and the geometric center of the first projection coincides with the geometric center of the second projection.

[0045] The light-emitting diode provided in this embodiment includes an epitaxial layer 20, a first electrode 40, and a passivation layer 30. The first electrode 40 includes marking electrode blocks 41 and connecting electrode blocks 42 spaced apart on the epitaxial layer 20. The passivation layer 30 is located on the surface of the epitaxial layer 20 and covers the marking electrode blocks 41 and connecting electrode blocks 42. The passivation layer 30 has marking holes 31 at positions corresponding to the marking electrode blocks 41 and connecting holes 32 at positions corresponding to the connecting electrode blocks 42. The marking holes 31 and connecting holes 32 have different shapes, so that the location of different types of pads 80 can be quickly determined from the surface of the epitaxial layer 20 away from the first electrode 40 by the location of the marking holes 31.

[0046] Simultaneously, the first projection of the marking hole 31 lies within the second projection of the marking electrode block 41. The shapes of the first and second projections are identical, and their geometric centers coincide, thus positioning the marking hole 31 in the central region of the marking electrode block 41. During the etching of the marking hole 31 on the passivation layer 30, points on the passivation layer 30 at the same distance from the geometric center of the marking hole 31 are also at the same distance from the peripheral edge of the marking electrode block 41. Therefore, after etching the passivation layer 30, the morphology of the regions on the passivation layer 30 at the same distance from the geometric center of the marking hole 31 is also identical. This makes it less likely for excessive thickness differences to occur in certain areas on the surface of the passivation layer 30, mitigating the problem of easy breakage of the pad 80.

[0047] Figure 5 yes Figure 4 A magnified view of a portion at point C is provided. For example... Figure 5 As shown, the ratio of the distance L1 from the inner contour of the first projection to the outer contour of the second projection to the maximum width L2 of the marking electrode block 41 is greater than or equal to 0.08.

[0048] For example, such as Figure 5 As shown, the marking hole 31 is a tapered opening; therefore, the first projection of the marking hole 31 is an annular shape. The inner contour of the first projection is the projection contour of the end of the marking hole 31 with a smaller inner diameter on the surface of the epitaxial layer 20, and the outer contour of the first projection is the projection contour of the end of the marking hole 31 with a larger inner diameter on the surface of the epitaxial layer 20.

[0049] For example, such as Figure 5 As shown, the marking electrode block 41 is a regular trapezoid. Therefore, the outer contour of the second projection of the marking electrode block 41 is the projection contour of the lower bottom surface of the marking electrode block 41 on the surface of the epitaxial layer 20.

[0050] For example, the maximum width of the marking electrode block 41 refers to the distance between the two furthest points on the outer contour of the second projection.

[0051] By limiting the ratio of the distance from the inner contour of the first projection to the outer contour of the second projection to the maximum width of the marking electrode block 41 to be no less than 0.08, the diameter of the marking hole 31 can be prevented from being too large, thus avoiding the edge of the marking hole 31 being too close to the edge of the marking electrode block 41. Since there is a height difference in the passivation layer 30 above the edge of the marking electrode block 41, if the marking hole 31 is also close to the edge of the marking electrode block 41, the passivation layer 30 at the edge of the marking hole 31 will form a larger height difference during etching, leading to damage to the subsequently formed solder pad 80.

[0052] Optionally, such as Figure 5 As shown, the ratio of the distance L1 from the inner contour of the first projection to the outer contour of the second projection to the maximum width L2 of the marking electrode block 41 is less than or equal to 0.33.

[0053] By limiting the ratio of the distance from the inner contour of the first projection to the outer contour of the second projection to the maximum width of the marking electrode block 41 to no more than 0.33, the aperture of the marking hole 31 can be prevented from being too small. If the aperture of the marking hole 31 is too small, the hole wall of the prepared marking hole 31 will be too steep, that is, the angle between the hole wall of the marking hole 31 and the horizontal plane will be large. Compared with a gentle hole wall, a steep hole wall is more likely to cause the film layer formed in the marking hole 31 to break, reducing the reliability of subsequent film layer preparation.

[0054] Optionally, such as Figure 3 As shown, the orthographic projection of the connecting electrode block 42 on the surface of the epitaxial layer 20 is the third projection, and the area of ​​the third projection is smaller than the area of ​​the second projection.

[0055] By setting the area of ​​the connecting electrode block 42 to be smaller than that of the marking electrode block 41, technicians can quickly determine the position of the marking electrode block 41 by identifying the size of the area. This uses both shape and area as features to identify the marking electrode block 41, avoiding misidentification by technicians.

[0056] Optionally, such as Figure 3 As shown, the marked electrode block 41 is located at the peripheral edge of the epitaxial layer 20.

[0057] Since the area of ​​the marking electrode block 41 is larger than that of the connecting electrode block 42, the area over which the marking electrode block 41 injects current into the epitaxial layer 20 is also larger, meaning the luminous intensity in the area where the marking electrode block 41 is located is also greater. Therefore, placing the marking electrode block 41 at the peripheral edge of the epitaxial layer 20 can improve the luminous intensity of the edge region of the epitaxial layer 20, making the overall luminous emission of the epitaxial layer 20 more uniform.

[0058] For example, the marker electrode block 41 is located in the corner region of the epitaxial layer 20.

[0059] Optionally, the thickness of the marking electrode block 41 is 1 μm to 1.5 μm.

[0060] By setting the thickness of the marking electrode block 41 within the above range, it is possible to avoid the marking electrode block 41 being too thick, which would result in a large height difference in the passivation layer 30 above the edge of the marking electrode block 41, thus preventing damage to the film layer prepared subsequently.

[0061] For example, the thickness of the marked electrode block 41 is 1.2 μm.

[0062] Optionally, such as Figure 3 As shown, the outer contour of the first projection includes two arcs, which are symmetrically distributed and whose endpoints are connected to form a closed curve. The shape of the marking hole 31 formed in this way is significantly different from that of a circular hole, making it easy to quickly distinguish between the marking hole 31 and the connecting electrode hole.

[0063] For example, such as Figure 3 As shown, both arcs are major arcs.

[0064] Optionally, the shape of the first projection is a polygon. Setting the shape of the marking hole 31 to a regular shape like a polygon facilitates rapid production and improves processing efficiency.

[0065] For example, the shape of the first projection is a triangle.

[0066] Optionally, the shape of the first projection is elliptical. Setting the shape of the marking hole 31 to a regular shape like an ellipse facilitates rapid production and improves processing efficiency.

[0067] Optionally, such as Figure 5 As shown, the light-emitting diode also includes a current blocking layer 52, which is located between the epitaxial layer 20 and the marking electrode block 41.

[0068] like Figure 3 As shown, the orthographic projection of the current blocking layer 52 on the surface of the epitaxial layer 20 is the fourth projection. The second projection is located within the fourth projection. The shape of the fourth projection is the same as that of the second projection, and the geometric center of the fourth projection coincides with the geometric center of the second projection.

[0069] By setting a current blocking layer 52 below the marking electrode block 41, current can be blocked from being injected directly downwards from the marking electrode block 41 into the epitaxial layer 20, so as to prevent excessive local current in the area near the marking electrode block 41 on the epitaxial layer 20, which would cause uneven light emission.

[0070] For example, the current blocking layer 52 may be a silicon oxide layer. Silicon oxide material has good insulation properties and can block current from being injected directly downwards from the marked electrode block 41 into the epitaxial layer 20.

[0071] Optionally, such as Figure 5 As shown, the surface of the epitaxial layer 20 is also provided with a transparent conductive layer 51, which covers the current blocking layer 52, and the marking electrode block 41 is located on the transparent conductive layer 51.

[0072] In the above implementation, the current blocking layer 52 is set between the current blocking layer 52 and the marking electrode block 41, which allows the current to spread laterally through the transparent conductive layer 51, allowing current to be injected into each area of ​​the epitaxial layer 20, making the light emission of the LED more uniform.

[0073] Optionally, the transparent conductive layer 51 may be an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer.

[0074] For example, the transparent conductive layer 51 is an indium tin oxide (ITO) layer. ITO layers have good transmittance and low resistivity, and using ITO layers as transparent conductive layers 51 facilitates carrier conduction and improves injection efficiency.

[0075] For example, the transparent conductive layer 51 is an indium zinc oxide (IZO) layer. IZO layers have good transmittance and low resistivity, and using IZO as the transparent conductive layer 51 facilitates carrier conduction and improves injection efficiency.

[0076] For example, the thickness of the transparent conductive layer 51 is from 100 angstroms to 300 angstroms. For instance, the thickness of the transparent conductive layer 51 is 200 angstroms.

[0077] Optionally, such as Figure 4 As shown, the light-emitting diode also includes an insulating layer 60, a second electrode 70, and a pad 80. The second electrode 70 is located on the surface of the passivation layer 30 away from the epitaxial layer 20, and the second electrode 70 is electrically connected to the marking electrode block 41 through the marking hole 31, and the second electrode 70 is electrically connected to the connecting electrode block 42 through the connecting hole 32.

[0078] like Figure 4 As shown, the insulating layer 60 is located on the surface of the passivation layer 30 away from the epitaxial layer 20. The insulating layer 60 has a through hole, and the pad 80 is located on the surface of the insulating layer 60 away from the epitaxial layer 20 and is electrically connected to the second electrode 70 through the through hole.

[0079] In this embodiment, the second electrode 70 is a solid film structure formed above the epitaxial layer 20, which allows the second electrode 70 to be electrically connected to all the marking electrode blocks 41 and connecting electrode blocks 42. Subsequently, the pads 80 only need to inject current into the second electrode 70 to inject current into each marking electrode block 41 and connecting electrode block 42.

[0080] Optionally, the pad 80 can be a rectangular block, which increases the area and facilitates conductivity. Furthermore, two pads 80 are spaced apart on the surface of the insulating layer 60.

[0081] For example, the pad 80 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer and an Au layer stacked in sequence.

[0082] The thickness of the first Al layer is 8,000 to 12,000 angstroms, the thickness of the first Ti layer is 100 to 500 angstroms, the thickness of the second Al layer is 8,000 to 12,000 angstroms, the thickness of the second Ti layer is 500 to 1,500 angstroms, and the thickness of the Au layer is 2,000 to 5,000 angstroms.

[0083] For example, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0084] Optionally, the epitaxial layer 20 includes a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially.

[0085] The surface of the second semiconductor layer has a groove that exposes the first semiconductor layer.

[0086] In this embodiment of the disclosure, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, and the other of the first semiconductor layer and the second semiconductor layer is an n-type layer.

[0087] For example, the first semiconductor layer is an n-type layer and the second semiconductor layer is a p-type layer.

[0088] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0089] Optionally, the multi-quantum-well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0090] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0091] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0092] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0093] Optionally, such as Figure 4 As shown, the light-emitting diode also includes a substrate 10, and an epitaxial layer is located on the surface of the substrate 10.

[0094] For example, the substrate is a sapphire substrate. Sapphire substrates have high light transmittance, meaning they are transparent. Furthermore, sapphire material is relatively hard and chemically stable, giving the light-emitting diode (LED) good luminous efficacy and stability.

[0095] Optionally, the passivation layer 30 is a silicon oxide layer or a distributed Bragg mirror layer; the insulating layer 60 is a silicon oxide layer or a distributed Bragg mirror layer.

[0096] As an example, in this embodiment of the disclosure, both the passivation layer 30 and the insulating layer 60 are silicon oxide layers.

[0097] The silicon oxide layer has good insulation properties, which can prevent the film from contacting other impurities and causing leakage, thus improving the reliability of the light-emitting diode.

[0098] As an example, in this embodiment of the disclosure, both the passivation layer 30 and the insulating layer 60 include alternating layers of silicon oxide and titanium oxide.

[0099] Among them, multiple periodically alternating SiO2 layers and TiO2 layers can form a distributed Bragg reflector layer.

[0100] For example, the number of cycles in a DBR layer can be between 20 and 50. For instance, the number of cycles in a DBR layer is 32.

[0101] The thickness of the SiO2 layer in the DBR layer can be from 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be from 500 angstroms to 900 angstroms.

[0102] In addition to passivation, the DBR layer also reflects light emitted from the multi-quantum well layer back to the substrate, improving light extraction efficiency.

[0103] Figure 6 This is a flowchart illustrating a method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. This method is used to fabricate... Figures 3 to 5 The light-emitting diode shown. For example... Figure 6 As shown, the preparation method includes:

[0104] S11: Create the epitaxial layer.

[0105] S12: A first electrode is formed on the surface of the epitaxial layer.

[0106] The first electrode includes a marking electrode block and a connecting electrode block, which are arranged at intervals on the surface of the epitaxial layer.

[0107] S13: A passivation layer is formed on the surface of the epitaxial layer.

[0108] The passivation layer covers the first electrode and has a marking hole that exposes the marking electrode block and a connection hole that exposes the connecting electrode block. The shape of the marking hole is different from the shape of the connection hole. The orthographic projection of the marking hole on the surface of the epitaxial layer is the first projection, and the orthographic projection of the marking electrode block on the surface of the epitaxial layer is the second projection. The first projection is located within the second projection, and the shape of the first projection is the same as the shape of the second projection. The geometric center of the first projection coincides with the geometric center of the second projection.

[0109] The light-emitting diode fabricated by this method includes an epitaxial layer, a first electrode, and a passivation layer. The first electrode includes marker electrode blocks and connection electrode blocks spaced apart on the epitaxial layer. The passivation layer is located on the surface of the epitaxial layer and covers the marker electrode blocks and connection electrode blocks. The passivation layer has marker holes at positions corresponding to the marker electrode blocks and connection holes at positions corresponding to the connection electrode blocks. The marker holes and connection holes have different shapes, allowing for rapid determination of the location of different types of pads from the surface of the epitaxial layer away from the first electrode by observing the location of the marker holes. Simultaneously, the first projection of the marker hole falls within the second projection of the marker electrode block. The first and second projections have the same shape, and their geometric centers coincide, placing the marker hole in the central region of the marker electrode block. During the etching of the marker holes on the passivation layer, points on the passivation layer at the same distance from the geometric center of the marker hole are also at the same distance from the peripheral edge of the marker electrode block. Therefore, after etching the passivation layer, the morphology of the regions on the passivation layer at the same distance from the geometric center of the marker hole is also identical. This makes it less likely that there will be large differences in thickness in some areas on the surface of the passivation layer, thus improving the problem of easy damage to the pads.

[0110] The detailed process for fabricating a light-emitting diode in this embodiment may include the following steps:

[0111] The first step is to grow an epitaxial layer on the substrate.

[0112] The substrate can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0113] As an example, in this embodiment of the disclosure, the substrate is a sapphire substrate. Sapphire substrates are a commonly used substrate, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate.

[0114] The sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment, the sapphire substrate is baked for 15 minutes.

[0115] Specifically, the baking temperature can be from 1000℃ to 1200℃, and the pressure inside the MOCVD reaction chamber during baking can be from 100mbar to 200mbar.

[0116] Growing an epitaxial layer on a substrate can include: sequentially forming a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer on a sapphire substrate using MOCVD technology.

[0117] The first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0118] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0119] The growth temperature of the n-type GaN layer can be from 1000℃ to 1100℃, and the growth pressure of the n-type GaN layer can be from 100 torr to 300 torr.

[0120] Optionally, the multi-quantum-well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0121] When growing multiple quantum well layers, the MOCVD reaction chamber pressure is controlled at 200 torr. When growing InGaN quantum well layers, the reaction chamber temperature is 760℃ to 780℃. When growing GaN quantum barrier layers, the reaction chamber temperature is 860℃ to 890℃.

[0122] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.

[0123] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.

[0124] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0125] When growing p-type GaN layers, the growth pressure of p-type GaN layers can be from 200 Torr to 600 Torr, and the growth temperature of p-type GaN layers can be from 800℃ to 1000℃.

[0126] After forming the epitaxial layer, the fabrication method also includes etching the second semiconductor layer to form a groove that exposes the first semiconductor layer.

[0127] The second step is to form a current blocking layer on the surface of the epitaxial layer.

[0128] For example, the current blocking layer may be a silicon oxide layer.

[0129] The third step is to form a transparent conductive layer on the surface of the epitaxial layer.

[0130] The transparent conductive layer is located outside the groove and covers the current blocking layer.

[0131] Specifically, this can include sputtering a transparent conductive layer onto an epitaxial layer.

[0132] For example, the transparent conductive layer is an indium tin oxide layer or an indium zinc oxide layer.

[0133] For example, the thickness of the transparent conductive layer is between 100 angstroms and 300 angstroms. For instance, the thickness of the transparent conductive layer is 200 angstroms.

[0134] The fourth step is to deposit the first electrode on the surface of the transparent conductive layer by vapor deposition.

[0135] The first electrode includes a marking electrode block and a connecting electrode block, which are arranged at intervals on the surface of the epitaxial layer.

[0136] Optionally, the shape of the marking electrode block is different from the shape of the connecting electrode block.

[0137] The fifth step is to form a passivation layer on the surface of the transparent conductive layer, so that the passivation layer covers the marking electrode block and the connecting electrode block.

[0138] The sixth step is to etch marking holes and connecting electrode holes on the surface of the passivation layer to expose the marking electrode blocks and the connecting electrode blocks.

[0139] For example, the passivation layer may be a silicon oxide layer. The thickness of the passivation layer is 4000 angstroms to 6000 angstroms.

[0140] For example, the passivation layer may include a DBR layer.

[0141] The thickness of the SiO2 layer in the DBR layer can be from 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer can be from 500 angstroms to 900 angstroms.

[0142] Step 7: A second electrode is formed on the surface of the passivation layer away from the epitaxial layer, and the second electrode is connected to the marking electrode block through the marking hole and to the connecting electrode block through the connecting electrode hole.

[0143] Optionally, the second electrode can be deposited with gold and beryllium as the main components or with gold and germanium as the base material. When the gold and germanium alloy is evaporated, the evaporation power must be guaranteed and the evaporation time must be avoided from exceeding a few seconds to prevent the alloy composition from deviating and to perform annealing.

[0144] Step 8: An insulating layer is formed on the surface of the passivation layer and the second electrode.

[0145] For example, the insulating layer comprises a silicon oxide layer. The thickness of the insulating layer is from 8,000 angstroms to 12,000 angstroms.

[0146] The ninth step is to deposit solder pads on the surface of the insulating layer, so that the solder pads are connected to the second electrode through through-holes.

[0147] For example, the pads may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked sequentially.

[0148] The thickness of the first Al layer is 8,000 to 12,000 angstroms, the thickness of the first Ti layer is 100 to 500 angstroms, the thickness of the second Al layer is 8,000 to 12,000 angstroms, the thickness of the second Ti layer is 500 to 1,500 angstroms, and the thickness of the Au layer is 2,000 to 5,000 angstroms.

[0149] For example, the thickness of the first Al layer is 10,000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10,000 angstroms, the thickness of the second Ti layer is 1,000 angstroms, and the thickness of the Au layer is 3,000 angstroms.

[0150] Finally, the sapphire substrate can be stealth-cut and scratched, which can effectively reduce brightness loss. Then, the light-emitting diode is obtained through testing.

[0151] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes an epitaxial layer (20), a first electrode (40), and a passivation layer (30). The first electrode (40) includes a marking electrode block (41) and a connecting electrode block (42). The marking electrode block (41) and the connecting electrode block (42) are arranged at intervals on the surface of the epitaxial layer (20). The passivation layer (30) is located on the surface of the epitaxial layer (20) and covers the first electrode (40). The passivation layer (30) has a marking hole (31) exposing the marking electrode block (41) and a connection hole (32) exposing the connection electrode block (42), the shape of the marking hole (31) being different from the shape of the connection hole (32); The orthographic projection of the marking hole (31) on the surface of the epitaxial layer (20) is the first projection, and the orthographic projection of the marking electrode block (41) on the surface of the epitaxial layer (20) is the second projection. The first projection is located within the second projection, the shape of the first projection is the same as the shape of the second projection, and the geometric center of the first projection coincides with the geometric center of the second projection.

2. The light-emitting diode according to claim 1, characterized in that, The ratio of the distance (L1) from the inner contour of the first projection to the outer contour of the second projection to the maximum width (L2) of the marking electrode block (41) is greater than or equal to 0.

08.

3. The light-emitting diode according to claim 2, characterized in that, The ratio of the distance (L1) from the inner contour of the first projection to the outer contour of the second projection to the maximum width (L2) of the marking electrode block (41) is less than or equal to 0.

33.

4. The light-emitting diode according to claim 1, characterized in that, The orthographic projection of the connecting electrode block (42) on the surface of the epitaxial layer (20) is a third projection, and the area of ​​the third projection is smaller than the area of ​​the second projection.

5. The light-emitting diode according to claim 4, characterized in that, The marked electrode block (41) is located at the peripheral edge of the epitaxial layer (20).

6. The light-emitting diode according to any one of claims 1 to 5, characterized in that, The thickness of the marked electrode block (41) is 1 μm to 1.5 μm.

7. The light-emitting diode according to any one of claims 1 to 5, characterized in that, The outer contour of the first projection includes two arcs, which are symmetrically distributed and whose endpoints are connected to form a closed curve; or... The shape of the first projection is a polygon or an ellipse.

8. The light-emitting diode according to any one of claims 1 to 5, characterized in that, The light-emitting diode further includes a current blocking layer (52) located between the epitaxial layer (20) and the marking electrode block (41); The orthographic projection of the current blocking layer (52) on the surface of the epitaxial layer (20) is the fourth projection, the second projection is located within the fourth projection, the shape of the fourth projection is the same as the shape of the second projection, and the geometric center of the fourth projection coincides with the geometric center of the second projection.

9. The light-emitting diode according to any one of claims 1 to 5, characterized in that, The light-emitting diode further includes: an insulating layer (60), a second electrode (70), and a pad (80); The second electrode (70) is located on the surface of the passivation layer (30) away from the epitaxial layer (20), and the second electrode (70) is electrically connected to the marking electrode block (41) through the marking hole (31), and the second electrode (70) is electrically connected to the connecting electrode block (42) through the connecting hole (32); The insulating layer (60) is located on the surface of the passivation layer (30) away from the epitaxial layer (20), the insulating layer (60) has a through hole, the pad (80) is located on the surface of the insulating layer (60) away from the epitaxial layer (20), and is electrically connected to the second electrode (70) through the through hole.

10. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: Fabricate the epitaxial layer; A first electrode is formed on the surface of the epitaxial layer. The first electrode includes a marking electrode block and a connecting electrode block, which are arranged at intervals on the surface of the epitaxial layer. A passivation layer is formed on the surface of the epitaxial layer, the passivation layer covering the first electrode, the passivation layer having a marking hole exposing a marking electrode block and a connection hole exposing a connection electrode block, the shape of the marking hole being different from the shape of the connection hole; the orthographic projection of the marking hole on the surface of the epitaxial layer is a first projection, the orthographic projection of the marking electrode block on the surface of the epitaxial layer is a second projection, the first projection being located within the second projection, the shape of the first projection being the same as the shape of the second projection, and the geometric center of the first projection coinciding with the geometric center of the second projection.

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