Data transmission method and data transmission device

Abstract

An embodiment of the present application provides a data transmission method and a data transmission device. The data transmission method includes: generating a bit stream, where the bit stream includes data and a control word, and the control word includes: a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; and sending the bit stream through the wired serial link. This data transmission method can reduce the complexity of the control signals transmitted at the physical layer.

Description

[0001] This application is a divisional application. The application number of the original application is 202280087546.8, the original application date is January 20, 2022, and the entire content of the original application is incorporated herein by reference. Technical Field

[0002] Embodiments of the present application relate to the field of communication networks, and in particular, to a data transmission method and a data transmission device. Background Art

[0003] In communication network technology, communication between communication devices is usually carried out through a data link. The physical layer in the signal sending end transmits a bit stream through the link to the physical layer in the signal receiving end, thereby realizing signal communication between communication devices. In order to enable the signal receiving end to accurately decode data from the bit stream, in addition to the encoded data signal, the bit stream usually further includes a variety of control signals indicating information such as link configuration or link state. For example, the variety of control signals include a control signal indicating packet frame delimitation, a control signal indicating link bandwidth, etc. The variety of control signals are respectively independent encoded segments. In addition, the plurality of control signals are usually transmitted at specific positions of the data signal.

[0004] However, with the continuous evolution of the working rate of the physical layer and more precise control of the link, etc., it is necessary to set more control signals to meet the requirements, resulting in a large number of control signals, and further resulting in extremely complex design of the physical layer in the communication device and increasing the cost of the physical layer. Therefore, how to reduce the complexity of the control signals transmitted by the physical layer has become a problem to be solved. Summary of the Invention

[0005] The data transmission method and data transmission device provided by the present application can reduce the complexity of the control signals transmitted by the physical layer. To achieve the above object, the present application adopts the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a data transmission method. The data transmission method is applied to a sending end, and the data transmission method includes: generating a bit stream, the bit stream including data and a control word, the control word including: a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; and transmitting the wired serial link through the bit stream.

[0007] In this implementation manner, the sending end may be, for example, Figure 1 , Figure 4 and Figure 5 the interface controller shown in. The first field for indicating the start position information of the control word may be, for example, Figure 2The start field shown in; a second field for indicating the end position information of the control word, for example, it can be Figure 2 The end field shown in; a third field for carrying the link information indicating the wired serial link, for example, it can be Figure 2 The payload field shown in

[0008] In a traditional wired serial link, various link information for achieving link alignment between two communication devices for transmitting data is usually an encoded segment, and one piece of information is an encoded segment. For example, the information indicating the link power consumption is an encoded segment, and the information indicating the states of each circuit in the link is an encoded segment, that is, there are multiple encoded segments for achieving link alignment. However, with the continuous evolution of the physical layer working rate and more precise control of the link, etc., more link information needs to be set to meet the requirements, resulting in a large number of link information, that is, a large number of encoded segments, and further leading to extremely complex design of the physical layer in the communication device and increasing the physical layer design cost. The control word provided in the embodiments of the present application, by being set to include a first field, a second field, and a third field, carries the link information in the third field, so that various link information can be indicated in one control word, reducing the complexity of the control signals transmitted by the physical layer and simplifying the design of the physical layer. In addition, since the second field of the control word is used to indicate the end position information of the control word, that is, the second field of the control word can define the length of the control word; furthermore, by flexibly adjusting the end position information of the control word, the number of link information carried in the control word can be flexibly adjusted, thus providing the flexibility of the control word.

[0009] Optionally, the end position information can be the length or the end position of the control word. The end position can be, for example: a preset number of bit positions starting from the second field.

[0010] Optionally, the data is service data or training data.

[0011] In a possible implementation manner, the link information includes at least one of the following: the number of channels for transmitting the first bit stream, the power consumption state of the hardware in the link, the working state of the circuits in the link, or the codec gain used in the link.

[0012] In order to reduce the power consumption of the hardware in the physical layer link, the power consumption of each piece of hardware in the link usually includes various types, such as low power consumption, medium power consumption, and high power consumption. For example, when hardware such as scramblers and data distributors included in the link are in one of standby, sleep, or power-down states, the hardware in the link is in a low power consumption state; when some of the component hardware included in the link is in one of standby, sleep, or power-down states and another part of the hardware is in the working state, the hardware in the link is in medium power consumption; when all the devices in the link are working, the hardware in the link is in high power consumption. For example, when the data being transmitted is training data, it can be indicated that the power consumption of each piece of hardware in the link is low power consumption; when the data being transmitted is service data, it can be indicated that the power consumption of each piece of hardware in the link is medium power consumption or high power consumption. The working state of the circuit in the link can include, for example, the power-on state or the power-down state. For example, when the data being transmitted is training data, the state of the codec circuit can be made the power-down state; when the data being transmitted is service data, the state of the codec circuit can be made the power-on state. Thus, the sending end can carry information such as one of multiple power consumption states, one indicating the working state of the circuit in the link, and the gain of the codec in the third field and transmit it to the receiving end.

[0013] In one possible implementation manner, the first field and the second field are used to indicate to the receiving end to delimit the data frame.

[0014] In this possible implementation manner, the data content of the data can be after the control word; that is to say, the first field and the second field of the control word can serve as the frame header of the data frame. When the receiving end recognizes the first field and the second field of the control word, it can determine the starting position of the data (i.e., frame delimitation) to read the data from the bit stream. By using the first field and the second field of the control word as the frame header of the data frame in the embodiments of the present application, it is not necessary to additionally set the frame header of the data frame, thereby simplifying the design of the bit stream.

[0015] In one possible implementation manner, there are multiple bit streams, the wired serial link includes multiple channels, and the multiple bit streams correspond to the multiple channels one by one; the sending of the bit stream through the wired serial link specifically includes: sending the corresponding multiple bit streams through the multiple channels.

[0016] When the wired serial link includes multiple channels, by respectively setting a control word in each channel, the receiving end can accurately read the data from the bit stream transmitted through each channel based on the control word in each channel, improving the accuracy of data reading at the receiving end.

[0017] In one possible implementation manner, the control word further includes a fourth field for indicating the channel number.

[0018] The fourth field can be, for example, Figure 2 the channel identification field shown.

[0019] In this implementation manner, by setting the fourth field in the control word that indicates the channel number, the receiving end can adjust the order of the data received from each channel based on each channel number, thereby improving the accuracy of the data received by the receiving end.

[0020] In a possible implementation manner, the first field includes multiple groups of identical fields, and each group of fields includes multiple bits; the multiple groups of identical fields are used to compensate for the difference between the clock cycle of the sending end and the clock cycle of the receiving end.

[0021] In this implementation manner, the sending end can encode the above-mentioned first field into a continuous "0" "1" signal, and then send the bit stream to the receiving end through a wired serial link based on the local clock cycle; when the receiving end receives the bit stream, it first recovers the clock cycle of the sending end from the first field; then, the receiving end adds or deletes at least one group of the multiple groups of identical fields based on the deviation between the recovered clock cycle and the local cycle.

[0022] For example, a buffer queue can be set in the receiving end. The receiving end writes the data carried by the first field into the buffer queue based on the clock cycle recovered from the first field. In addition, the receiving end can also read data from the buffer queue based on the local clock cycle, and both operations are performed simultaneously. When the receiving end detects that the rate of writing data into the buffer queue is greater than the rate of reading data from the buffer queue, it means that the clock cycle of the sending end is greater than the clock cycle of the receiving end. At this time, at least one group of the multiple groups of identical fields included in the first field is deleted to ensure the clock cycle synchronization between the sending end and the receiving end; when the receiving end detects that the rate of writing data into the buffer queue is less than the rate of reading data from the buffer queue, it means that the clock cycle of the sending end is less than the clock cycle of the receiving end. At this time, at least one group of the multiple groups of identical fields is added to the first field to achieve the clock cycle synchronization between the sending end and the receiving end.

[0023] In the traditional technology, since a structured control word is not set, a sequence dedicated to compensating for the difference between the clock cycle of the sending end and the clock cycle of the receiving end is usually set in the transmitted bit stream, and this sequence does not carry any useful data. In the embodiments of the present application, by setting multiple groups of identical fields in the first field of the control word, the control word can implement more functions, that is, there is no need to additionally set a sequence dedicated to compensating for the difference between the clock cycle of the sending end and the clock cycle of the receiving end in the bit stream; compared with the prior art, the design of the physical layer can be simplified.

[0024] In a possible implementation, when the data is training data, the generated bitstream includes: adding the control word after the data to generate the bitstream.

[0025] In a second aspect, an embodiment of the present application provides a data transmission method. The data transmission method is applied to a receiving end and includes: receiving a bitstream, where the bitstream includes data and a control word. The control word includes a first field for indicating information about the start position of the control word, a second field for indicating information about the end position of the control word, and a third field for carrying link information indicating a wired serial link; reading the control word from the bitstream based on the first field and the second field; and reading the data from the bitstream based on the control word.

[0026] In this implementation, the receiving end can be, for example, Figure 1 , Figure 4 and Figure 5 the network card shown in. The first field for indicating information about the start position of the control word can be, for example, the start field shown in Figure 2 ; the second field for indicating information about the end position of the control word can be, for example, the end field shown in Figure 2 ; and the third field for carrying link information indicating a wired serial link can be, for example, the payload field shown in Figure 2 .

[0027] The control word provided by the embodiment of the present application is configured to include a structure of a first field, a second field, and a third field, and the link information is carried in the third field, so that various link information can be indicated in one control word, simplifying the design of the physical layer. In addition, since the second field of the control word is used to indicate the end position information of the control word, that is, the second field of the control word can define the length of the control word; furthermore, by flexibly adjusting the end position information of the control word, the number of link information carried in the control word can be flexibly adjusted, thereby providing flexibility for the control word.

[0028] In a possible implementation, the method further includes: adjusting at least one of the following of the wired serial link based on the link information: the power consumption state of the hardware in the link, the working state of the circuit in the link, or the codec gain used in the link.

[0029] To reduce the power consumption of the hardware in the physical layer link, the power consumption of each piece of hardware in the link usually includes various types, such as low power consumption, medium power consumption, and high power consumption. For example, when the data being transmitted is training data, the power consumption of each piece of hardware in the link can be indicated as low power consumption; when the data being transmitted is service data, the power consumption of each piece of hardware in the link can be indicated as medium power consumption or high power consumption. The working state of the circuit in the link can include, for example, the powered-on state or the powered-off state. For example, when the data being transmitted is training data, the state of the codec circuit can be made the powered-off state; when the data being transmitted is service data, the state of the codec circuit can be made the powered-on state. The receiving end adjusts the power consumption state of the hardware in the link to the power consumption state indicated in the third field, adjusts the working state of the circuit in the link to the working state indicated in the third field, and adjusts the gain of the codec to the gain indicated in the third field based on one of the various power consumption states indicated in the third field, one of the working states of the circuit in the link, and the gain of the codec.

[0030] In a possible implementation manner, the reading of the data from the bitstream based on the control word includes: determining the coding length of the control word based on the first field and the second field; identifying the frame start position of the data from the bitstream based on the coding length of the control word, where the frame start position of the data is located after the control word; and reading the data based on the frame start position of the data.

[0031] In this possible implementation manner, the data content of the data can be after the control word; that is to say, the first field and the second field of the control word can serve as the frame header of the data frame. When the receiving end identifies the first field and the second field of the control word, it can determine the start position of the data to read the data from the bitstream. By using the first field and the second field of the control word as the frame header of the data frame in the embodiments of the present application, it is not necessary to additionally set the frame header of the data frame, thereby simplifying the design of the bitstream.

[0032] In a possible implementation manner, there are multiple bitstreams, the wired serial link includes multiple channels, and the multiple bitstreams are received from the sending end through the corresponding multiple channels; the link information further includes the number of channels for transmitting the bitstreams; the control word further includes a fourth field for indicating the channel number; the reading of the data from the bitstream based on the control word includes: reading the data from the bitstream received by the corresponding channel based on the number of channels for transmitting the bitstreams and the fourth field.

[0033] The fourth field can be, for example, Figure 2 the channel identification field shown.

[0034] In a possible implementation, the method further includes: eliminating data skew between each of the multiple channels based on the order of receipt of the multiple bitstreams and a fourth field in each control word of the multiple control words in the multiple bitstreams.

[0035] In a possible implementation, the first field includes multiple groups of identical fields, each group of fields including multiple bits; and the method further includes: performing one of the following operations based on a clock frequency deviation from the sending end: deleting at least one of the multiple groups of identical fields, or adding at least one of the multiple groups of identical fields.

[0036] In this implementation, the sending end may encode the first field into a continuous "0" "1" signal, and then send the bitstream to the receiving end through a wired serial link based on the local clock cycle; when the receiving end receives the bitstream, it first recovers the clock cycle of the sending end from the first field; then, the receiving end adds or deletes at least one of the multiple groups of identical fields based on the deviation between the recovered clock cycle and the local cycle.

[0037] For example, a buffer queue may be set in the receiving end. The receiving end writes the data carried by the first field into the buffer queue based on the clock cycle recovered from the first field. In addition, the receiving end may also read data from the buffer queue based on the local clock cycle, and both operations are performed simultaneously. When the receiving end detects that the rate of data written into the buffer queue is greater than the rate of data read from the buffer queue, it indicates that the clock cycle of the sending end is greater than the clock cycle of the receiving end. At this time, at least one of the multiple groups of identical fields included in the first field is deleted to ensure clock cycle synchronization between the sending end and the receiving end; when the receiving end detects that the rate of data written into the buffer queue is less than the rate of data read from the buffer queue, it indicates that the clock cycle of the sending end is less than the clock cycle of the receiving end. At this time, at least one of the multiple groups of identical fields is added to the first field to achieve clock cycle synchronization between the sending end and the receiving end.

[0038] In the prior art, since a structured control word is not set, a sequence dedicated to compensating for the difference between the clock cycle of the sending end and the clock cycle of the receiving end is usually set in the transmitted bitstream, and this sequence does not carry any useful data. By setting multiple groups of identical fields in the first field of the control word in the embodiments of the present application, the control word can implement more functions, that is, there is no need to additionally set a sequence dedicated to compensating for the difference between the clock cycle of the sending end and the clock cycle of the receiving end in the bitstream; compared with the prior art, the design of the physical layer can be simplified.

[0039] In a third aspect, an embodiment of the present application provides a data transmission device, which includes a processor and an interface; the processor is configured to generate a bitstream, the bitstream includes data and a control word, and the control word includes: a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; the interface transmits the bitstream through the wired serial link.

[0040] In a possible implementation, the link information includes at least one of the following: the number of channels for transmitting the bitstream, the power consumption state of the hardware in the link, the operating state of the circuit in the link, or the codec gain used in the link.

[0041] In a possible implementation, the first field and the second field are used to delimit the data frame at the receiving end.

[0042] In a possible implementation, there are multiple bitstreams, the wired serial link includes multiple channels, and the multiple bitstreams correspond to the multiple channels one by one; specifically, the interface is configured to: transmit the corresponding multiple bitstreams through the multiple channels.

[0043] In a possible implementation, the control word further includes a fourth field for indicating the channel number.

[0044] In a possible implementation, the first field includes multiple groups of identical fields, and each group of fields includes multiple bits; the multiple groups of identical fields are used to compensate for the difference between the clock cycle of the sending end and the clock cycle of the receiving end.

[0045] In a fourth aspect, an embodiment of the present application provides a data transmission device, which includes a processor and an interface; the interface is configured to receive a bitstream, the bitstream includes data and a control word, and the control word includes a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; the processor is configured to, based on the first field and the second field, read the control word from the bitstream; and based on the control word, read the data from the bitstream.

[0046] In a possible implementation, the processor is further configured to: based on the link information, adjust at least one of the following of the wired serial link: the power consumption state of the hardware in the link, the operating state of the circuit in the link, or the codec gain used in the link.

[0047] In a possible implementation, the processor is specifically configured to: determine the encoding length of the control word based on the first field and the second field; identify the frame start position of the data from the bitstream based on the encoding length of the control word, where the frame start position of the data is located after the control word; and read the data based on the frame start position of the data.

[0048] In a possible implementation, there are multiple bitstreams, the wired serial link includes multiple channels, and the multiple bitstreams are received from the sending end through the corresponding multiple channels; the link information further includes the number of channels for transmitting the bitstreams; the control word further includes a fourth field for indicating the channel number; and the processor is specifically configured to: read the data from the bitstream received by the corresponding channel based on the number of channels for transmitting the bitstreams and the fourth field.

[0049] In a possible implementation, the processor is further configured to: eliminate data skew between each of the multiple channels based on the order of receipt of the multiple bitstreams and the fourth field in each control word of the multiple control words in the multiple bitstreams.

[0050] In a possible implementation, the first field includes multiple groups of identical fields, and each group of fields includes multiple bits; and the processor is further configured to: perform one of the following operations based on the clock frequency deviation from the sending end: delete at least one group of the multiple groups of identical fields, or add at least one group of the multiple groups of identical fields.

[0051] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium for storing a computer program, and when the computer program is run by a processor, it implements the data transmission method as described in the first aspect above or the data transmission method as described in the second aspect above.

[0052] In a sixth aspect, an embodiment of the present application provides a computer program product, and when the computer program product runs on a processor, it implements the data transmission method as described in the first aspect above or the data transmission method as described in the second aspect above.

[0053] It should be understood that the technical solutions of the second aspect to the sixth aspect of the present application are consistent with those of the first aspect of the present application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation manners are similar and will not be repeated. Description of the Drawings

[0054] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0055] Figure 1 is a schematic diagram of a hardware architecture of an electronic device provided by an embodiment of the present application;

[0056] Figure 2 is a schematic diagram of a frame structure of a control word provided by an embodiment of the present application;

[0057] Figure 3A is a schematic diagram of a set of eBCH codewords provided by an embodiment of the present application;

[0058] Figure 3B is a schematic diagram of an encoding structure of a channel identifier provided by an embodiment of the present application;

[0059] Figure 4 is a schematic diagram of a hardware architecture of a physical layer provided by an embodiment of the present application;

[0060] Figure 5 is a flowchart of a data transmission method provided by an embodiment of the present application;

[0061] Figure 6 is another flowchart of a data transmission method provided by an embodiment of the present application;

[0062] Figure 7 is a schematic diagram of a structure of a data transmission device provided by an embodiment of the present application;

[0063] Figure 8 is another schematic diagram of a structure of a data transmission device provided by an embodiment of the present application. Detailed implementation manners

[0064] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0065] As used herein, terms such as "first" or "second" and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a quantity limitation, but rather indicate the presence of at least one. Terms such as "coupled" are not limited to a physical or mechanical direct connection, but may include an electrical connection, whether direct or indirect, equivalent to a connection in a broad sense.

[0066] In the embodiments of the present application, words such as "exemplary" or "for example" are used to denote examples, illustrations, or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" refers to two or more. For example, a plurality of channels refers to two or more channels.

[0067] The data transmission system provided by the embodiments of the present application may include a sending end and a receiving end. Both the sending end and the receiving end may be an electronic device, which may be, for example, a terminal device, such as a mobile phone, a PC, a tablet computer, a laptop computer, or a wearable device (such as a smart watch, an AR device, a VR device), etc., various types of portable devices); the electronic device may also be a switch device or a router device, etc. In an application scenario, the sending end may be a terminal device, and the receiving end may be a router device. The terminal device communicates with the router device through a wired serial link to transmit a signal to the router device. In this application scenario, when the router device transmits a signal to the terminal device, the router device may also be referred to as the sending end, and the terminal device may also be referred to as the receiving end.

[0068] In addition, the sending end and the receiving end can also be modules, chips, chip sets, circuit boards or components with chips or chip sets mounted therein, which are disposed in an electronic device. The electronic device is, for example, the electronic device as described above. A network card can be disposed in the electronic device, so that the electronic device can access a network through the network card for communication. The network can be, for example, an Ethernet network. In an application scenario, the sending end can be an interface controller integrated in the electronic device; the receiving end can be a network card disposed in the electronic device. The interface controller and the network card can communicate through a wired serial link. The interface controller transmits a bit stream to the network card through the wired serial link, and the network card encapsulates the received bit stream into an Ethernet frame and sends it to the Ethernet. In this application scenario, when the network card receives a bit stream from the Ethernet, it needs to transmit the received bit stream to the interface controller. At this time, the interface controller is the sending end and the network card is the receiving end. The embodiments of the present application are described by taking the interface controller as the sending end and the network card as the receiving end as an example, but are not used to limit the solution.

[0069] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an electronic device 100 provided by an embodiment of the present application. In Figure 1 , the electronic device 100 includes one or more processors. The one or more processors include, for example, an interface controller 10, a central processing unit (CPU) 12, etc. Optionally, the one or more processors can be integrated in one or more chips, and the one or more chips can be regarded as a chip set. In an optional implementation manner, the interface controller 10 and the CPU 12 can be integrated in a system on chip (SOC) as shown in Figure 1 . Devices or components such as a memory 13 and a direct memory access controller (DMAC) 14 can also be integrated in the SOC. Among them, signals are transmitted between the interface controller 10, the CPU 12, the memory 13, and the DMAC 14 through a bus. Software programs or software plugins such as an operating system software and application software can run in the CPU 12, and software programs or software plugins required for the operation of the CPU 12 can be stored in the memory 13. In addition, instructions and data required for the operation of the CPU 12 can also be stored in the memory 13, and the CPU 12 obtains the instructions and data from the memory 13 through the DMAC 14.

[0070] As Figure 1 shown, the electronic device 100 further includes a network card 11. The network card 11 can be disposed in Figure 1Outside the SOC shown. The interface controller 10 includes an interface 101 and a processor 102, and the network card 11 includes an interface 111 and a processor 112. The network card 11 is coupled to the interface 101 in the interface controller 10 through the interface 111. In an alternative implementation, the interface 101 and the interface 111 can be serdes (serializer and deserializer) interfaces respectively. The interface 101 and the interface 111 can be coupled through various physical media (such as twisted pairs or cables, etc.). Thus, the electronic device 100 accesses the network through the network card 11 and communicates with other devices (such as server devices or terminal devices, etc.) in the network for data exchange. In a possible implementation, the processor 102 and the processor 112 can respectively include components such as an encoder, a decoder, a control word generator, and a link training state machine. In addition, the processor 102 and the processor 112 can also selectively include components such as a scrambler and a descrambler. Among them, for a more detailed structure of the interface controller 10 and the network card 11, refer to Figure 4 the relevant description.

[0071] In the embodiments of the present application, the communication network model of the electronic device 100 can comply with the OSI (Open System Interconnection Reference Model) standard. OSI can specifically include the application layer, the transportation layer, the data link layer, and the physical layer. In addition, it can also include more layers, which are not specifically limited in the embodiments of the present application. The application layer can include application software running in the CPU 12. Such as video playback applications, instant messaging applications, etc. The transportation layer is used to describe the system's transportation layer protocol specifications, including the definition and arrangement of data types and structures, routing control, bandwidth management, etc. The data link layer is used to encapsulate the data packets provided by the transportation layer into data frames and provide transparent transmission. The physical layer is used to define the link state, clock reference, data encoding, and circuits, etc. of the wired serial link required for data transmission and reception, and to provide a standard interface to the data link layer. The physical layer encodes the data frame to generate a bit stream and transmits the bit stream through the wired serial link. It should be noted that the interface controller 10 and the network card 11 provided in the embodiments of the present application generally operate in the physical layer of the OSI standard.

[0072] During the operation of the electronic device 100, the processor 102 in the interface controller 10 can obtain the original data packet (for example, the CPU 12 can trigger the processor 102 to read the data packet from the memory 13); the processor 102 processes the obtained data packet (for example, encapsulates it into a data frame and performs Hamming coding), generates a bit stream and outputs it to the network card 11 through the interface 101; the interface 111 in the network card 11 receives the bit stream, and the processor 112 in the network card 11 further processes the received bit stream (for example, decodes to obtain a data frame, performs Ethernet frame encapsulation and Manchester coding on the data frame, etc.), and then transmits it to the network. Similarly, after the network card 11 receives a data frame from the network, it processes it (for example, performs Manchester decoding, removes the Ethernet frame and Hamming coding, etc.), and then transmits it to the interface controller 10 through the interface 111; after the interface controller 10 further processes the obtained data frame (for example, performs decoding and de-encapsulation), it generates a data packet and stores it in the memory 13 or directly provides it to the CPU 12.

[0073] In the embodiments of the present application, in order to achieve signal transmission with a low bit error rate, in the bit stream transmitted from the interface controller 10 (i.e., the transmitter) to the network card 11 (i.e., the receiver), in addition to the data obtained by encoding the data frame, it also includes a control word, such as Figure 2 shown Figure 2 schematically shows the bit stream transmitted from the interface controller 10 to the network card 11. This control word is used to indicate information such as the link state, clock reference, and data frame delimiter of the wired serial link. Thus, the physical layer of the receiver determines the frame delimiter of the data, adjusts the clock reference, adjusts the link state, etc. based on the control word. Among them, the control word includes a start field for indicating the start position information of the control word, an end field for indicating the end position information of the control word, and a payload field for carrying the indication information. The indication information carried by this payload field is used to indicate the link information of the wired serial link.

[0074] In a traditional wired serial link, various link information for achieving link alignment between two communication devices for data transmission is usually in the form of coding segments, with one piece of information being one coding segment. For example, the information indicating the link power consumption is one coding segment, and the information indicating the states of the circuits in the link is one coding segment. That is to say, there are multiple coding segments for achieving link alignment. However, with the continuous evolution of the physical layer working rate and more precise control of the link, etc., more link information needs to be set to meet the requirements, resulting in a large number of link information, that is, a large number of coding segments, and further leading to extremely complex design of the physical layer in the communication device and increasing the physical layer design cost. The control word provided in the embodiments of this application, by being set to include a start field, an end field, and a payload field, carries the link information in the payload field, so that multiple link information can be indicated in one control word, simplifying the design of the physical layer. In addition, since the end field of the control word is used to indicate the end position information of the control word, that is, the end field of the control word can define the length of the control word; furthermore, by flexibly adjusting the end position information of the control word, the number of link information carried in the control word can be flexibly adjusted, thus providing the flexibility of the control word.

[0075] It should be noted that, in the bit stream as Figure 2 shown, the data is on the left side of the control word. During the bit stream transmission process, the signal of the control word is sent first, and then the data signal is sent. Figure 2 In the implementation manner as

[0076] shown, the data can be service data, for example. Optionally, the data can also be on the right side of the control word. During the bit stream transmission process, the data signal is sent first, and then the control word signal is sent. In this implementation manner, the data can be training data, for example. In addition, since the data and the control word are encoded as "0", "1" signals in the physical layer, the control word can also be set at any position of the data.

[0076] Please continue to refer to Figure 2 , Figure 2 which further schematically shows the frame structure of the control word. In Figure 2 ,the control word includes a start field U_I indicating the start position information of the control word, an end field U_END for indicating the end position of the control word, and a payload field payload for indicating the link information of the wired serial link. The control word will be described in more detail below in combination with the frame structure of the control word as Figure 2 shown.

[0077] In the start field U_I, there are at least a group of multiple bit positions U_ID0 to U_IDN. That is to say, Figure 2In the frame structure shown, the first N + 1 bits are the header of the control word, and this N + 1 - bit header enables the network card 11 to identify the start field of the control word. To ensure that the control word has a certain fault - tolerance ability and to compensate for the difference between the clock cycles of the sending end and the receiving end, in an optional implementation manner of the embodiments of the present application, the length of the start field U_I can vary within a preset range. For example, the start field U_I can include multiple groups of repeated U_ID0 to U_IDN, and the variable length of the start field U_I can be, for example, 8 bytes. Assuming N is 4 and U_ID0 to U_IDN are 00101, the start field U_I can be the three - group repeated bit stream of 001010010100101.

[0078] The interface controller 10 can encode the start field into a continuous "0" "1" signal and then send the bit stream to the network card 11 through a wired serial link based on the local clock cycle; when the network card 11 receives the bit stream, it first recovers the clock cycle of the interface controller 10 from the start field; then, based on the deviation between the recovered clock cycle and the local cycle, the network card 11 adds or deletes at least one group of fields from multiple groups of identical fields. Specifically, a buffer queue can be set in the network card 11. The network card 11 writes the data carried by the start field into the buffer queue based on the clock cycle recovered from the start field. In addition, the network card 11 can also read data from the buffer queue based on the local clock cycle, and both operations are carried out simultaneously. When the network card 11 detects that the rate of writing data into the buffer queue is greater than the rate of reading data from the buffer queue, it indicates that the clock cycle of the interface controller 10 is greater than the clock cycle of the network card 11. At this time, one or more groups of U_ID0 to U_IDN in the start field U_I are deleted to ensure the clock - cycle synchronization between the interface controller 10 and the network card 11; when the network card 11 detects that the rate of writing data into the buffer queue is less than the rate of reading data from the buffer queue, it indicates that the clock cycle of the interface controller 10 is less than the clock cycle of the network card 11. At this time, one or more groups of U_ID0 to U_IDN are added to the start field U_I to achieve the clock - cycle synchronization between the interface controller 10 and the network card 11.

[0079] The end field U_END is used to indicate the end - position information of the control word. This end - position information can be, for example, the length of the control word or the end position. This end position can be, for example, a preset number of bit positions starting from the end field U_END. Thus, after the network card 11 identifies the end field U_END from the control word and then counts backward a preset number of bit positions, it can determine the end of the control - word bit stream.

[0080] In this possible implementation, data content can follow the control word; that is to say, the start field and end field of the control word can serve as the frame header of the data frame. When the receiving end recognizes the start field and end field of the control word, it can determine the start position of the data (i.e., frame delimitation) to read the data from the bit stream. By using the start field and end field of the control word as the frame header of the data frame in the embodiments of this application, it is not necessary to additionally set the frame header of the data frame, thus simplifying the design of the bit stream.

[0081] The payload field is used to carry link information. The link information can include, but is not limited to, one or more of the following: the clock cycle for adding the control word to the data, the power consumption state of the hardware in the link, the working state of the circuit in the link, and the output gain of the codec circuit in the link. For example, the power consumption state of the hardware in the link includes three states: low power consumption, medium power consumption, and high power consumption. When the hardware in the link, such as scramblers and data distributors, is in one of standby, sleep, or power-down, the hardware in the link is in a low power consumption state; when some of the component hardware in the link is in one of standby, sleep, or power-down and another part of the hardware is in a working state, the hardware in the link is in a medium power consumption state; when all the devices in the link are working, the hardware in the link is in a high power consumption state. For example, when the data transmitted is training data, it can indicate that the power consumption of each hardware in the link is in a low power consumption state; when the data transmitted is service data, it can indicate that the power consumption of each hardware in the link is in a medium power consumption state or a high power consumption state. The working state of the circuit in the link can include, for example, a powered-on state or a powered-off state. For example, when the data transmitted is training data, it can make the state of the codec circuit be in a powered-off state; when the data transmitted is service data, it can make the state of the codec circuit be in a powered-on state. The gain of the codec in the link includes, for example, gain 1, gain 2, and gain 3.

[0082] In an alternative implementation, the payload field can include two parts: a type field and a detail field. The type field is used to indicate various link information, and the detail field is used to indicate the specific parameters corresponding to each type of link information. For example, the link information includes three types of information: the power consumption state of the hardware in the link, the working state of the circuit in the link, or the gain of the codec in the link. The type field is used to indicate that the link information includes the power consumption state of the hardware in the link and the gain of the codec in the link; the detail field further indicates that the power consumption state of the hardware in the link is in a medium power consumption state and the gain of the codec in the link is gain 2. Thus, network card 11 can determine each link information and the parameters corresponding to various link information based on the type field and the detail field to adjust the link.

[0083] In the embodiment of the present application, in the wired serial link for transmitting bitstreams between the interface controller 10 and the network card 11, based on the bandwidth of the wired serial link, it may include one lane or multiple lanes. That is to say, the bitstreams can be transmitted between the interface controller 10 and the network card 11 through one lane or multiple lanes. When the interface controller 10 transmits bitstreams to the network card 11 through multiple lanes, in an optional implementation, in addition to data, each lane's transmitted bitstream also includes control words. In addition to the above-mentioned fields, each control word may further include a channel identification field Lane indicating the link number, such as Figure 2 shown. The network card 11 can implement lane flipping based on the channel identification field Lane and can also eliminate data skew between the data transmitted by each lane. Further, the interface controller 10 can transmit bitstreams to the network card 11 through a fixed number of lanes or a variable number of lanes. When the interface controller 10 transmits bitstreams to the network card 11 through a variable number of lanes, in an optional implementation, the link information carried by the payload field may further include the link bandwidth (i.e., the number of lanes for transmitting bitstreams). The network card 11 can receive bitstreams from the corresponding lanes based on this link information.

[0084] In summary, by setting the start field, end field, payload field, and optionally the channel identification field, the control word can indicate more information, thereby reducing the complexity of the control word transmitted at the physical layer.

[0085] Based on the frame structure of the control word described above, in a possible implementation, in the embodiments of the present application, error correction coding can be used to encode the control word. The interface controller 10 sends a code that can be error-corrected, and the network card 11 can automatically detect errors and automatically correct errors in the transmission of the codeword. Error correction coding can include, for example, but is not limited to: forward error correction coding, Hamming coding, eBCH (extended Bose Ray-Chaudhuri Hocquenghem) coding, etc. Among them, Hamming coding is a linear code. For a coding block with a length of m bits, there are n redundant bits, and the rest are payload bits; each redundant bit is obtained by performing an exclusive OR operation on some payload bits in a certain manner. Hamming coding can correct any single-bit error. eBCH coding is also a linear code, and eBCH coding can correct multiple-bit errors in the coding block. Below, taking eBCH coding as an example, the coding method of the control word will be described in detail through a specific example. In the embodiments of the present application, an eBCH coding set can be constructed first. The eBCH coding set can include, for example, 32 codings, and the structure of each coding can be BCH(16, 5, 1), where 16 (bits) is the coding length, 5 (bits) is the payload length, and 1 (bit) is the check code length. The Hamming distance between any two codings in the eBCH coding set is 8. That is to say, the number of different bits between any two codings is 8. The eBCH codeword set is as Figure 3A shown.

[0086] From Figure 3A it can be seen that eBCH includes 32 codings from CW0 to CW31, and the length of each coding is 16 bits. The number of different bits between any two codings is 8. Based on Figure 3A the constructed eBCH coding, a specific example of the control word described in the embodiments of the present application is shown in Table 1.

[0087] Table 1 Control word example

[0088] Symbol Number Description 0 to (4*N - 1), N ranges from [1 to 5] Control Word Start Field, CW21, CW28 4*N to (4*N + 3) Control Word End Field, CW22, CW8 (4*N + 4) to (4*N + 11) Channel identification field, specifically refer to Figure 3B (4*N + 12) to (4*N + 19) payload_type Field, refer to Table 2 for details (4*N + 20) to (4*N + 27) payload_detail Field, refer to Table 3 for details

[0089] From the control word example shown in Table 1, it can be seen that a control word includes (4*N + 27) bytes from 0 to (4*N + 27). The number of bytes in the start field of the control word can be variable within 4 to 20. The coding of the start field of the control word is CW21, CW28; that is, the lower 16 bits of the start field of the control word are the coding CW28 shown in Table 1, and the upper 16 bits are the coding CW21 shown in Table 1. The coding of the end field of the control word is CW22, CW8; that is, the lower 16 bits of the end field of the control word are the coding CW22 shown in Table 1, and the upper 16 bits are the coding CW8 shown in Table 1.

[0090] The channel identification field is asFigure 3B As shown. Assume that the maximum link bandwidth between the interface controller 10 and the network card 11 is 32 lanes, that is, Figure 3B lanes 0 to 31 shown in. Then the identifier of each lane can be represented by four codes, that is, 64 bits. Taking Figure 3B lane 2 shown in as an example, from Figure 3B it can be seen that lane 2 is indicated by the four codes CW3, CW9, CW3, and CW9. Among them, the specific bits of CW3 and CW9 refer to Table 1. From Figure 3B it can also be seen that among these 64 bits, bits [0 to 15] are CW3, bits [16 to 31] are CW9, bits [32 to 47] are CW3, and bits [48 to 63] are CW9. The detailed codes of the remaining lanes refer to Figure 3A and Figure 3B and will not be elaborated here.

[0091] It should be noted that Table 1, Table 2, Table 3, and Figure 3A and Figure 3B the tables shown can be pre-stored in the interface controller 10 and the network card 11 respectively.

[0092] Table 2 Payload Type

[0093] Link Information Bit [31 - 16] Bit [15 - 0] FEC Gain CW8 CW10 Link Bandwidth CW10 CW22 Power Consumption of Hardware CW8 CW13 Control Word Addition Period CW10 CW15

[0094] Table 3 Payload Detail

[0095]

[0096] As can be seen from Table 2, the link information includes four types of information: the forward error correction (FEC) encoder gain, the link bandwidth, the power consumption of the hardware, and the control word addition period. Each type of information is indicated by two codes (i.e., 32 bits). Table 2 shows that the codes for the FEC gain are CW8 and CW10, that is, among the 32 bits indicating the FEC gain, the lower 16 bits are CW10 and the higher 16 bits are CW8. The FEC gain further includes four modes: bypass FEC, FEC gain 1, FEC gain 2, and FEC gain 3 shown in Table 3. Assume that the type field in the control word transmitted by interface controller 10 to network card 11 includes CW8 and CW10, and the detail field includes CW9 and CW10. After receiving the bit stream, network card 11 parses the type field and the detail field of the control word. Network card 11 queries from Table 2 that CW8 and CW10 indicate the FEC gain; then, network card 11 further compares CW3 and CW9 with the respective codes corresponding to the FEC gain in Table 3 and queries that the FEC gain is FEC gain 1. Then network card 11 can adjust the FEC gain to gain 1.

[0097] Table 2 shows that the encoding of the link bandwidth is CW10 and CW22, that is, among the 32 bits indicating the link bandwidth, the lower 16 bits are CW10 and the higher 16 bits are CW22. The link bandwidth further includes the seven modes of X0, X1, X2, X4, X8, X16, and X32 shown in Table 3. Assume that in the type field of the control word transmitted by the interface controller 10 to the network card 11, the first 32 bits are CW8 and CW10, and the last 32 bits are CW10 and CW22; in the detail field, the first 32 bits are CW9 and CW10, and the last 32 bits are CW9 and CW21. After receiving the bit stream, the network card 11 parses that the first 32 bits of the type field of the control word indicate the FEC gain, and the last 32 bits indicate the link bandwidth. Then, the network card 11 compares the first 32 bits in the detail field with the information corresponding to the FEC gain in Table 3, and compares the last 32 bits in the detail field with the information corresponding to the link bandwidth in Table 3, so as to query that the FEC gain is FEC gain 1 and the link bandwidth is X1. Then the network card 11 can adjust the FEC gain to gain 1 and obtain data from one channel. It should be noted that the physical layer between the interface controller 10 and the network card 11 can also pre-agree on the channels used under each link bandwidth in advance. For example, it can be pre-agreed that when transmitting service data through one channel, the service data is transmitted through the channel with the channel identifier of lane0; it can also be pre-agreed that when transmitting service data through four channels, the service data is transmitted through the channels with the channel identifiers of lane0 to lane3. It should also be noted that when the type field of the control word indicates the link bandwidth information and the detail field is encoded with CW3 and CW9, it means that the interface controller 10 has finished transmitting service data to the network card 11, and the data transmitted in the next cycle is training data. That is to say, when the information indicating the link bandwidth in the control word is X0, it indicates the end of the transmission of service data, and the data transmitted in the next cycle is training data; when the information indicating the link bandwidth in the control word is any one other than X0, it means that the data transmitted by the interface controller 10 to the network card 11 is service data. Thus, the encoding used to indicate the link bandwidth can also be used to indicate the switching between service data and training data.

[0098] When the control word transmitted by the interface controller 10 to the network card 11 includes information indicating the power consumption of the hardware and the addition period of the control word, the parsing of the control word by the network card 11 and how to determine the link information to be adjusted are similar to those of the FEC encoder and the link bandwidth, and will not be elaborated here.

[0099] Based on Figure 1 the structure of the electronic device 100 shown in Figure 2 and the frame structure of the control word shown in Figure 4 Please continue to refer to Figure 4It is a schematic diagram of the physical layer hardware structure of the interface controller 10 provided by an embodiment of the present application. It should be noted that the hardware structure of the physical layer of the network card 11 may be the same as that of the physical layer hardware structure of the interface controller 10. An embodiment of the present application describes it taking the physical layer hardware of the interface controller 10 as an example. As Figure 4 shown, the physical layer of the interface controller 10 includes an encoder 101, a data distributor 102, a control word generator 103, a multiplexer 104, a link training state machine 105, a scrambler 106, a serializer / deserializer 107, a descrambler 108, a control word decoder 109, a data skew eliminator 1010, and a decoder 1011. It can be understood that the physical layer of the interface controller 10 may further include more circuits, modules or components, and an embodiment of the present application does not make specific limitations. These components included in the physical layer of the interface controller 10 may be integrated into one or more chips, and these components may be implemented by hardware circuits, and some components may also be implemented by software driving hardware. In a possible implementation manner, some components may be integrated into the same processor, and the processor executes the functions corresponding to each component or module. For example, the encoder 101 and the data distributor 102 may be integrated into the same processor, and the processor implements the functions of data encoding and distribution. In addition, the physical layer of the network card 11 may have components the same as or similar to those of the interface controller 10, Figure 4 and it is shown in that the physical layer of the network card 11 includes an encoder 111, a data distributor 112, a control word generator 113, a multiplexer 114, a link training state machine 115, a scrambler 116, a serializer / deserializer 117, a descrambler 118, a control word decoder 119, a data skew eliminator 1110, and a decoder 1111. Taking the transmission of a bit stream from the physical layer of the interface controller 10 to the physical layer of the network card 11 as an example, the following describes each component or function in the physical layers of the interface controller 10 and the network card 11.

[0100] In the physical layer of the interface controller 10, the encoder 101 is used to encode the data frame sent by the data link layer to generate encoded data. This encoding may be, for example, forward error correction coding, error detection and retransmission coding, or hybrid error correction coding, etc. The data distributor 102 is used to divide the encoded data into multiple data streams (hereinafter referred to as service data) and distribute them to multiple lanes, with one lane corresponding to one piece of data. The link training state machine 105 is used to generate link information and provide the generated link information to the control word generator 103. The control word generator 103 is based on the link information and as Figure 2The frame structure of the control word shown generates the control word. The link information may include, for example, link power consumption status, link output gain, and link coding mode. In addition, the link training state machine 105 is further configured to control the multiplexer 104 to selectively form a path between one of the multiple input terminals and the output terminal based on the current state (such as service data transmission state, link training state, or link reset state, etc.) and the clock cycle. Figure 4 It is shown that the multiplexer 104 includes three input terminals, one of which is coupled to the data distributor 102, one of which is used to input training data, and the other is coupled to the control word generator 103. That is to say, based on the control of the link training state machine 105, the multiplexer 104 outputs one of the service data, training data, or control word to the scrambler 106. It should be noted that the service data in the embodiments of the present application may be, for example, data such as audio data and video data input by the user through the application program, and is data generated after being encapsulated and encoded by the application layer, transport layer, data link layer, and physical layer; the training data is used to test and adjust the multiple lanes during the link training phase. The scrambler 106 adds scrambling to the received data stream or control word and provides it to the serializer / deserializer 107. The serializer / deserializer 107 converts the received multiple parallel low-speed bit streams into a high-speed serial bit stream and transmits it to the network card 11 through multiple lanes. It should also be noted that the number of lanes is the same as the number of bit streams transmitted, and each bit stream includes data and a control word. Based on the control of the link training state machine 105, the control word can be added at any position of the corresponding data. Preferably, the control word can be added before the data.

[0101] In the physical layer of the network card 11, the serializer / deserializer 117 receives the serial bit stream signal from the lane, converts the serial bit stream into multiple parallel bit streams, and provides them to the descrambler 118. The descrambler 118 descrambles the multiple parallel bit streams and outputs the descrambled bit stream to the control word decoder 119. Based on Figure 4For the frame structure of the control word shown, the control word decoder 119 identifies the control word from each bitstream and parses the control word to obtain the indication information in the payload field, where the indication information is used to indicate link information. For example, the indication information indicates that the link enters the medium power consumption state and indicates that the link coding mode is the forward error coding mode. The control word decoder 119 provides the obtained indication information to the link training state machine 115, and provides the data and the channel identifier corresponding to each piece of data to the data skew eliminator 1110. The link training state machine 115 performs corresponding actions based on the indication information. For example, the link is set to the medium power consumption state, and the coding mode (such as the above-mentioned forward error coding) is provided to the decoder 1111. The data skew eliminator 1110 performs skew elimination processing on each data stream and provides the skew-eliminated data stream to the decoder 1111. The decoder 1111 decodes the data stream using the corresponding decoding mode based on the above coding mode and provides the decoded data to the data link layer of the network card 11.

[0102] Based on Figure 1 the architecture of the electronic device 100 shown, Figure 2 the frame structure of the control word shown and Figure 4 the hardware architecture of the physical layer of the interface controller 10 (or network card 11) shown, an embodiment of the present application further provides a data transmission method, which can be applied to Figure 1 the electronic device 100 shown. Taking the interface controller 10 as the sending end and the network card 11 as the receiving end as an example, the data transmission method provided by the embodiment of the present application will be described below. For the data transmission method provided by the embodiment of the present application, its sending end and receiving end can be executed by Figure 2 one or more components shown. It should be noted that in the embodiment of the present application, the interface controller 10 can transmit the control word to the network card 11 at any data transmission stage. For example, the control word is added to the training data transmitted in the link training stage, or the control word can be added to the service data transmitted in the service data transmission stage, or the control word can be added to the training data transmitted in the link reset stage. It should also be noted that the control word can be set before the service data, or can be set at any position of the service data based on the clock cycle, or can be set before the training data, or can be set after the training data. The embodiment of the present application does not make specific limitations on this. Please refer to Figure 5 , Figure 5 FIG. 500 is a process of the data transmission method provided by the embodiment of the present application, and the data transmission method includes:

[0103] Step 501, the interface controller 10 generates a bitstream, which includes data and a control word. The control word includes: a start field for indicating the start position information of the control word, an end field for indicating the end position information of the control word, and a payload field for carrying the link information indicating the wired serial link. Step 502, the interface controller 10 sends the bitstream through the wired serial link.

[0104] Step 503, the network card 11 reads the control word from the bitstream based on the start field and the end field; Step 504, based on the control word, reads the data from the bitstream.

[0105] In this implementation manner, the data can be, for example, one of service data or training data. The control word is, for example, Figure 2 the structure shown. The link information may include, but is not limited to, one or more of the following: the clock cycle for adding the control word to the data, the power consumption state of the hardware in the link, the working state of the circuit in the link, and the output gain of the codec circuit in the link.

[0106] In this implementation manner, the start field and the end field of the control word can indicate the length of the control word. For example, after the network card 11 reads the start field, it recognizes that the bitstream includes a control word; after reading the end field, it recognizes that a preset number of bits starting from this field is the end position of the control word. Additionally, the data content of the data can be after the control word. That is to say, the start field and the end field of the control word can act as the frame header of the data frame. When the receiving end recognizes the start field and the end field of the control word, it can determine the start position of the data to read the data from the bitstream.

[0107] The control word provided in the embodiment of the present application, by being set to include a start field, an end field, and a payload field, carries the link information in the payload field, so that various link information can be indicated in one control word, simplifying the design of the physical layer. Additionally, since the end field of the control word is used to indicate the end position information of the control word, that is, the end field of the control word can define the length of the control word; furthermore, by flexibly adjusting the end position information of the control word, the number of link information carried in the control word can be flexibly adjusted, thus providing the flexibility of the control word.

[0108] Next, taking the bitstream including training data and a control word, and the bitstream including service data and a control word as examples, and taking the interface controller 10 transmitting data to the network card 11 through four lanes as an example, in combination with Figure 6 through a more specific scenario, the data transmission method provided in the embodiment of the present application will be described. Please continue to refer to Figure 6 , Figure 6 is a process 600 of the data transmission method provided in the embodiment of the present application. The data transmission method includes:

[0109] Step 601: The interface controller 10 adds control words C0 to C3 to the training data D0 to D3 respectively to generate bitstreams B0 to B3. This step is in the link training phase. The link training phase is used to align the link state of the interface controller 10 with the link state of the network card 11. In this step, the interface controller 10 can allocate the pre-set training data D0 to D3 to lanes 0 to 3. The interface controller 10 can also generate control words C0 to C3 based on the current link information (such as the link entering medium power consumption, each hardware circuit in the physical layer being powered on, the gain of the link encoder in the physical layer being "1", and the link coding mode being forward error coding), the clock cycle for adding the control word to the training data, and the frame structure of the control word as Figure 2 shown. Among them, the channel identification field of control word C0 is used to indicate lane 0, the channel identification field of control word C1 is used to indicate lane 1, the channel identification field of control word C2 is used to indicate lane 2, and the channel identification field of control word C3 is used to indicate lane 3. In addition, the data carried by the start field, end field, and payload field in control words C0 to C3 can be the same. Then, the interface controller 10 adds control words C0 to C3 to the training data D0 to D3 respectively to generate bitstreams B0 to B3. Step 602: The interface controller 10 transmits the bitstreams B0 to B3 to the network card 11 through lanes 0 to 3 simultaneously.

[0110] Step 603: The network card 11 respectively identifies control words C0 to C3 from bitstreams B0 to B3 based on the start fields indicating the start positions of control words C0 to C3 and the end fields indicating the end positions of control words C0 to C3. Step 604: The network card 11 adjusts the link docking sequence based on the channel identifiers carried in the channel identifier fields of control words C0 to C3. This step is used to align the link numbers with the order of data streams. For example, the interface controller 10 transmits bitstreams B0 - B1 - B2 - B3 through lane0 - lane1 - lane2 - lane3 respectively; while the data streams received by the network card 11 from lane0 - lane1 - lane2 - lane3 are actually B3 - B2 - B1 - B0, that is, the numbers of lanes in the interface controller 10 are completely inverse to the numbers of lanes in the network card 11. The network card 11 can re-label the numbers of lanes in the network card 11 based on the channel identifier fields in each control word to achieve alignment with the numbers of lanes in the interface controller 10. Step 605: The network card 11 adjusts the link state based on the link information indicated by the payload fields in control words C0 to C3. For example, the link information is used to indicate that the link enters the medium power consumption state, all hardware circuits in the physical layer are powered on, and the gain of the link encoder in the physical layer is "1". The network card 11 adjusts the power consumption states of hardware circuits such as amplifiers and encoders in the link to the medium power consumption state and adjusts the gain of the link encoder to "1" based on this link information. Step 606: The network card 11 aligns the data transmitted by each lane based on the order in which bitstreams B0 to B3 are received.

[0111] Step 607: The interface controller 10 respectively adds control words C4 to C7 to the training data D4 to D7 to generate bitstreams B4 to B7, where the payload fields of control words C4 to C7 carry the indication information indicating the transmission of service data in the next cycle. This step is in the link training phase. After the interface controller 10 provides the link information in the payload field to the network card 11 in Step 601, it can also carry the indication information indicating the transmission of service data in the next cycle in the payload fields of control words C4 to C7. The payload fields of control words C4 to C7 can also include the link information as described in Step 601. In addition, control words C4 to C7 also include start fields, end fields, and channel identifier fields. The interface controller 10 adds control words C4 to C7 to the training data D4 to D7 respectively to generate bitstreams B4 to B7. Step 608: The interface controller 10 simultaneously transmits bitstreams B4 to B7 to the network card 11 through lane0 to lane3 respectively.

[0112] Step 609, the interface controller 10 adds control words C8 to C111 to the service data D8 to D111 respectively to generate bitstreams B8 to B111. In this step, the interface controller 10 can obtain data frames from the data link layer. Based on a pre-set coding format (such as forward error coding format), the interface controller 10 encodes the data frames to generate service data D8 to D11. Then, the interface controller 10 can distribute the service data D8 to D11 to lanes 0 to 3. Then, the interface controller 10 generates control words C8 to C11 based on the current link information, the number of lanes used, the clock cycle for adding control words to the training data, and the frame structure of the control words as Figure 2 shown. Among them, the number of lanes used is carried in the payload fields of control words C8 to C11. Finally, the interface controller 10 adds control words C8 to C111 to the training data D8 to D111 respectively to generate bitstreams B8 to B111. In an optional implementation, the control words C8 to C111 can be added to preset positions of the service data D8 to D111 respectively. The preset position can be, for example, before the service data. Step 610, the interface controller 10 transmits the bitstreams B8 to B111 to the network card 11 through lanes 0 to 3 simultaneously.

[0113] Step 611, the network card 11 identifies the control words C8 to C111 from the bitstreams B8 to B111 respectively based on the start field indicating the start position of the control words C8 to C111 and the end field indicating the end position of the control words C8 to C111, and reads out the service data D8 to D111 from the bitstreams B8 to B111. In this step, based on the position of the control words in the bitstream, the network card 11 can delimit the service data frames, that is, determine the start position of the service data. In an optional implementation, the position of the service data in the bitstream is at a preset position after the control words. For example, the second bit after the end bit of the control word is the start position bit of the service data. After the network card 11 reads out the end field of the control word, it can determine the end bit of the control word, and then the network card 11 can start reading the service data from the second bit after the end bit of the control word. Step 612, the network card 11 decodes the read service data D8 to D111 based on the coding format used by the interface controller 10 to obtain the decoded data frames.

[0114] It should be noted that the process 600 of the data transmission method described above is illustrative. It can be understood that the data transmission method provided by the embodiments of the present application may include more or fewer processes than process 600. For example, before step 604 and after step 603, the network card 11 may also transmit information indicating that the link is set up to the interface controller 10. For another example, before step 604 and after step 603, the network card 11 may also send a bit stream to the interface controller 10, and the bit stream includes training data and a control word added to the training data, and the control word is used to indicate the link state of the physical layer of the network card 11.

[0115] It can be understood that in order to implement the above functions, the interface controller includes corresponding hardware and / or software modules for executing each function. Combining the steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the present application.

[0116] This embodiment can perform a functional module division on each component included in the Figure 1 shown interface controller 10 according to the above method example. For example, each different component can be corresponding to each function, or two or more components with functions can be integrated into one processor module. The above integrated processor module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is illustrative, only a logical function division, and there may be other division methods in actual implementation. In the case of adopting an integrated module, Figure 7 shows a possible schematic diagram of the data transmission device 700. As Figure 7 shown, the data transmission device 700 may include: a processing unit 701 and a sending unit 702, and the previously mentioned device can be further expanded. The processing unit 701 is used to generate a bit stream, and the bit stream includes data and a control word. The control word includes: a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link. The sending unit 702 is used to send the bit stream through the wired serial link.

[0117] In a possible implementation manner, the link information includes at least one of the following: the number of channels for transmitting the bit stream, the power consumption state of the hardware in the link, the working state of the circuit in the link, or the codec gain used in the link.

[0118] In a possible implementation, the first field and the second field are used to indicate that the receiving end delimits the data frame.

[0119] In a possible implementation, the bit stream includes multiple ones, the wired serial link includes multiple channels, and the multiple bit streams correspond to the multiple channels one by one; the sending unit 702 is specifically configured to: send the corresponding multiple bit streams through the multiple channels.

[0120] In a possible implementation, the control word further includes a fourth field for indicating a channel number.

[0121] In a possible implementation, the first field includes multiple groups of identical fields, and each group of fields includes multiple bits; the multiple groups of identical fields are used to compensate for the difference between the clock period of the sending end and the clock period of the receiving end.

[0122] The data transmission device 700 provided in this embodiment is used for the data transmission method executed by the interface controller 10, and can achieve the same effect as the above implementation method or device. Specifically, the above Figure 7 corresponding respective modules can be implemented by software, hardware, or a combination of both. For example, each module can be implemented in software form, corresponding to Figure 1 the processor 102 and the interface 101 corresponding to the module, and are used to drive the corresponding components to work. Alternatively, each module can include two parts, namely the corresponding component and the corresponding driving software, that is, implemented by a combination of software and hardware. Therefore, the data transmission device 700 can be considered to logically include Figure 1 、 Figure 4 the interface controller 10 shown, and each module includes at least a driving software program with corresponding functions. This embodiment will not expand on this.

[0123] This embodiment can perform functional module division on each component included in the network card 11 shown in Figure 1 according to the above method example. For example, each different component can be divided corresponding to each function, or two or more components with functions can be integrated into a processor module. The above integrated processor module can be implemented in hardware form. It should be noted that the division of modules in this embodiment is illustrative, only a logical function division, and there may be other division methods in actual implementation. In the case of adopting an integrated module, Figure 8 shows a possible schematic diagram of the data transmission device 800. As shown in Figure 8As shown, the data transmission device 800 may include: a receiving unit 801 and a processing unit 802, and the previously mentioned device can be further extended. The receiving unit 801 is used to receive a bitstream, and the bitstream includes data and a control word. The control word includes a first field for indicating the starting position information of the control word, a second field for indicating the ending position information of the control word, and a payload field for carrying link information indicating a wired serial link. The processing unit 802 is used to read the control word from the bitstream based on the first field and the second field; and read the data from the bitstream based on the control word.

[0124] In a possible implementation, the processing unit 802 is further used to: based on the link information, adjust at least one of the following of the wired serial link: the power consumption state of the hardware in the link, the working state of the circuit in the link, or the codec gain used in the link.

[0125] In a possible implementation, the processing unit 802 is specifically used to: determine the coding length of the control word based on the first field and the second field; identify the frame start position of the data from the bitstream based on the coding length of the control word, where the frame start position of the data is located after the control word; and read the data based on the frame start position of the data.

[0126] In a possible implementation, there are multiple bitstreams, and the wired serial link includes multiple channels. The multiple bitstreams are received from the sending end through the corresponding multiple channels; the link information further includes the number of channels for transmitting the bitstreams; the control word further includes a channel identification field for indicating the channel number; the processing unit 802 is specifically used to: read the data from the bitstream received by the corresponding channel based on the number of channels for transmitting the bitstream and the channel identification field.

[0127] In a possible implementation, the processing unit 802 is further used to: eliminate data skew between each of the multiple channels based on the order of reception of the multiple bitstreams and the channel identification field in each control word of the multiple control words in the multiple bitstreams.

[0128] In a possible implementation, the first field includes multiple groups of identical fields, and each group of fields includes multiple bits; and the processing unit 802 is further used to: based on the clock frequency deviation from the sending end, perform one of the following operations: delete at least one of the multiple groups of identical fields, or add at least one of the multiple groups of identical fields.

[0129] The data transmission device 800 provided in this embodiment, using the data transmission method executed by the network card 11, can achieve the same effect as the above implementation method or device. Specifically, the above Figure 8 The corresponding respective modules can be implemented by software, hardware, or a combination of both. For example, each module can be implemented in software form, corresponding to Figure 1 the interface 111 and the processor 112 corresponding to the module in, for driving the corresponding components to work. Or, each module can include two parts, the corresponding components and the corresponding driving software, that is, implemented by a combination of software or hardware. Therefore, the data transmission device 500 can be considered to logically include Figure 1 、 Figure 4 the network card 11 shown. Each module at least includes a driving software program with corresponding functions. This embodiment will not expand on this.

[0130] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0131] In several embodiments provided in this application, it should be understood that the disclosed systems and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0132] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0133] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0134] When the above-mentioned function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium or memory includes: various media such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0135] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of various embodiments of this application.

Claims

1. A data transmission method for a wired serial link, applied to a sending end, characterized in that, Including: Generating a bitstream, the bitstream including data and a control word, the control word including: a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; Sending the bitstream to a receiving end via the wired serial link; Wherein, the length of the first field is a variable length.

2. The data transmission method according to claim 1, wherein The link information includes at least one of the following: the number of channels for transmitting the bitstream, the power consumption state of the hardware in the link, the operating state of the circuit in the link, or the codec gain used in the link.

3. The data transmission method according to claim 1 or 2, characterized in that The first field and the second field are used to delimit a data frame for the receiving end.

4. The method according to any one of claims 1 to 3, characterized in that, The first field includes a group of bit strings or multiple groups of repeated bit strings.

5. The method according to claim 4, wherein The multiple groups of repeated bit strings are multiple groups of repeated code streams.

6. The method according to claim 5, wherein The number of bytes of the first field is variable within 4 to 20 bytes.

7. The method according to any one of claims 1 to 6, characterized in that The control word end position information is an end field, and the second field includes the length or end position of the control word.

8. The method according to claim 7, characterized in that The end position is a preset number of bit positions starting from the second field.

9. The data transmission method according to any one of claims 1-8, characterized in that There are multiple bitstreams, the wired serial link includes multiple channels, and the multiple bitstreams correspond to the multiple channels one by one; Then the step of sending the bitstream to the receiving end via the wired serial link specifically includes: Sending the corresponding multiple bitstreams to the receiving end via the multiple channels.

10. The data transmission method according to claim 9, wherein The control word further includes a fourth field for indicating a channel number.

11. The method according to claim 9, wherein The identifier of each channel in the multiple channels is represented by four encodings.

12. The method according to claim 11, wherein The identifier of each channel in the multiple channels is represented by 64 bit positions.

13. The data transmission method according to any one of claims 1-12, characterized in that, The first field includes multiple groups of identical fields, and each group of fields includes multiple bit positions; The multiple groups of identical fields are used to compensate for the difference between the clock cycle of the sending end and the clock cycle of the receiving end.

14. The data transmission method according to any one of claims 1-13, characterized in that, The data is service data or training data; When the data is training data, the generating of the bitstream includes: Adding the control word after the data to generate the bitstream.

15. A data transmission method for a wired serial link, applied to a receiving end, characterized in that, Including: Receiving a bitstream from a sending end, the bitstream including data and a control word, the control word including a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; wherein, the length of the first field is a variable length; Reading the control word from the bitstream based on the first field and the second field; Reading the data from the bitstream based on the control word.

16. The data transmission method according to claim 15, wherein The method further includes: Adjusting at least one of the following of the wired serial link based on the link information: the power consumption state of the hardware in the link, the operating state of the circuit in the link, or the codec gain used in the link.

17. The data transmission method according to claim 15 or 16, characterized in that, The step of reading the data from the bitstream based on the control word includes: Determining the encoding length of the control word based on the first field and the second field; Identifying the frame start position of the data from the bitstream based on the encoding length of the control word. Read the data based on the frame start position of the data.

18. The method according to any one of claims 15 to 17, characterized in that The first field includes a set of bit strings or multiple sets of repeated bit strings.

19. The method according to claim 18, wherein The multiple sets of repeated bit strings are multiple sets of repeated code streams.

20. The method according to claim 19, wherein The number of bytes of the first field is variable within 4 to 20 bytes.

21. The method according to any one of claims 15 to 20, characterized in that The control word end position information is an end field, and the second field includes the length or end position of the control word.

22. The method according to claim 21, wherein The end position is a preset number of bit positions starting from the second field.

23. The data transmission method according to any one of claims 15-22, characterized in that, There are multiple bit streams, the wired serial link includes multiple channels, and the multiple bit streams are received from the sending end through the corresponding multiple channels; the link information further includes the number of channels for transmitting the multiple bit streams; The control word further includes a fourth field for indicating the channel number; Reading the data from the bit stream based on the control word includes: Based on the number of channels for transmitting the multiple bit streams and the fourth field, read the data from the bit stream received by the corresponding channel.

24. The data transmission method according to claim 23, wherein The method further includes: Based on the order of receipt of the multiple bit streams and the fourth field in each control word of the multiple control words in the multiple bit streams, eliminate data skew between each of the multiple channels.

25. The data transmission method according to any one of claims 15-24, characterized in that, The first field includes multiple sets of identical fields, and each set of fields includes multiple bit positions; and The method further includes: Based on the clock frequency deviation from the sending end, perform one of the following operations: delete at least one of the multiple sets of identical fields, or add at least one of the multiple sets of identical fields.

26. The method according to claim 23 or 24, characterized in that, The identifier of each channel in the multiple channels is represented by four encodings.

27. The method according to claim 26, wherein The identifier of each channel in the multiple channels is represented by 64 bit positions.

28. A transmitting end, characterized in that, The receiving end includes a processor and an interface controller; The processor is configured to generate a bit stream, the bit stream includes data and a control word, and the control word includes: a first field for indicating the control word start position information, a second field for indicating the control word end position information, and a third field for carrying link information indicating a wired serial link; The interface controller sends the bit stream to the receiving end through the wired serial link; Wherein, the length of the first field is a variable length.

29. The transmitter according to claim 28, characterized in that, The link information includes at least one of the following: the number of channels for transmitting the bit stream, the power consumption state of the hardware in the link, the working state of the circuit in the link, or the codec gain used in the link.

30. The transmitting end according to claim 28 or 29, characterized in that, The first field and the second field are used to indicate the receiving end to delimit the data frame.

31. The transmitter according to any one of claims 28 to 30, characterized in that, The first field includes a set of bit strings or multiple sets of repeated bit strings.

32. The transmitter according to claim 31, wherein, The multiple sets of repeated bit strings are multiple sets of repeated code streams.

33. The transmitter according to claim 32, wherein The number of bytes of the first field is variable within 4 to 20 bytes.

34. The transmitter according to any one of claims 28 to 30, characterized in that, The control word end position information is an end field, and the second field includes the length or end position of the control word.

35. The transmitting end according to claim 34, wherein The end position is a preset number of bit positions starting from the second field.

36. The transmitting end according to any one of claims 28-35, characterized in that, There are multiple bit streams, the wired serial link includes multiple channels, and the multiple bit streams correspond to the multiple channels one by one; the interface is specifically configured to: Send the corresponding multiple bitstreams through the multiple channels.

37. The transmitter according to claim 36, characterized in that, The control word further includes a fourth field for indicating a channel number.

38. The transmitter according to any one of claims 28 to 37, characterized in that, The first field includes multiple groups of identical fields, and each group of fields includes multiple bits; The multiple groups of identical fields are used to compensate for the difference between the clock cycle of the sending end and the clock cycle of the receiving end.

39. The transmitting end according to claim 36 or 37, characterized in that, The identifier of each channel in the multiple channels is represented by four encodings.

40. The transmitter according to claim 39, characterized in that, The identifier of each channel in the multiple channels is represented by 64 bits.

41. A receiving end, characterized in that, The data transmission device includes a processor and an interface controller; The interface controller is configured to receive a bitstream, the bitstream includes data and a control word, and the control word includes a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a payload field for carrying link information indicating a wired serial link; The processor is configured to read the control word from the bitstream based on the first field and the second field; Read the data from the bitstream based on the control word.

42. The receiving end according to claim 41, wherein The processor is further configured to: Based on the link information, adjust at least one of the following of the wired serial link: the power consumption state of the hardware in the link, the operating state of the circuit in the link, or the codec gain used in the link.

43. The receiving end according to claim 41 or 42, characterized in that, Specifically, the processor is configured to: Determine the encoding length of the control word based on the first field and the second field; Identify the frame start position of the data from the bitstream based on the encoding length of the control word; Read the data based on the frame start position of the data.

44. The receiving end according to any one of claims 41 to 43, characterized in that, The first field includes a group of bit strings or multiple groups of repeated bit strings.

45. The receiving end according to claim 44, wherein The multiple groups of repeated bit strings are multiple groups of repeated code streams.

46. The receiving end according to claim 45, wherein The number of bytes of the first field is variable within 4 to 20 bytes.

47. The receiving end according to any one of claims 41 to 46, characterized in that, The control word end position information is an end field, and the second field includes the length or end position of the control word.

48. The receiving end according to claim 47, wherein The end position is a preset number of bits starting from the second field.

49. The receiving end according to any one of claims 41-48, characterized in that, There are multiple bitstreams, the wired serial link includes multiple channels, and the multiple bitstreams are received from a sending end through the corresponding multiple channels; the link information further includes the number of channels for transmitting the multiple bitstreams; the control word further includes a fourth field for indicating a channel number; specifically, the processor is configured to: Read the data from the bitstream received by the corresponding channel based on the number of channels for transmitting the multiple bitstreams and the fourth field.

50. The receiving end according to claim 49, wherein The processor is further configured to: Based on the order of the received multiple bitstreams and the fourth field in each control word of the multiple control words in the multiple bitstreams, eliminate the data skew between each channel in the multiple channels.

51. The receiving end according to any one of claims 41-48, characterized in that, The first field includes multiple groups of identical fields, and each group of fields includes multiple bits; and the processor is further configured to: Based on the clock frequency deviation from the sending end, perform one of the following operations: delete at least one group of the multiple groups of identical fields, or add at least one group of the multiple groups of identical fields.

52. The receiving end according to claim 49 or 50, characterized in that, The identifier of each channel in the multiple channels is represented by four encodings.

53. The receiving end according to claim 52, characterized in that, The identifier of each channel among the multiple channels is represented by 64 bits.

54. A computer-readable storage medium, characterized in that, For storing a computer program, when the computer program is run by a processor, it implements the method described in any one of claims 1-6 above or the method described in any one of claims 7-12 above.

55. A data transmission system for a wired serial link of a wired link, characterized in that, The data transmission system includes a sending end and a receiving end. The sending end is used to implement the method described in any one of claims 1-14 above, and the receiving end is used to implement the method described in any one of claims 15-27 above.

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