Receiving circuit and communication interface

Abstract

The present invention discloses a receiving circuit and a communication interface. The receiving circuit includes a comparison unit, a logic output unit and a failure protection unit; the input end of the comparison unit and the input end of the failure protection unit are used to input a differential signal, the output end of the comparison unit is connected to the first input end of the logic output unit, the output end of the failure protection unit is connected to the second input end of the logic output unit, and the output end of the logic output unit is used as the output end of the receiving circuit; the comparison unit is used to output a first comparison signal according to the differential signal, the first comparison signal is valid when the differential signal is greater than the first threshold value, and is invalid when the differential signal is less than the second threshold value; the failure protection unit is used to output a valid failure protection signal when the differential signal is greater than the third threshold value, and the logic output unit is used to output a valid receiving signal when at least one of the first comparison signal and the failure protection signal is valid. The anti-interference ability and failure protection function of the receiving circuit are improved, and the performance of the receiving circuit is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of communications, and in particular to a receiving circuit and a communication interface. Background Art

[0002] The communication interface includes a driving circuit and at least one receiving circuit, and the signal can be transmitted from the driving circuit to the receiving circuit through a differential bus. During the signal transmission process, the signal is easily subject to various external interferences or damage on the transmission path. The output state of the receiving circuit is uncertain, and it is easy to receive data errors. To avoid this problem, it is usually necessary to make the hysteresis of the receiving threshold of the receiving circuit large enough to improve the anti-interference ability. In addition, the receiving circuit is also required to have a failure protection function to characterize the abnormal open or short circuit state of the differential bus network. In the prior art, the anti-interference ability and failure protection function of the receiving circuit have certain limitations and cannot meet the needs of the receiving circuit. Summary of the invention

[0003] The present invention provides a receiving circuit and a communication interface to improve the anti-interference capability and failure protection function of the receiving circuit and enhance the performance of the receiving circuit.

[0004] In a first aspect, an embodiment of the present invention provides a receiving circuit, which is applied to a communication interface; the receiving circuit includes a comparison unit, a logic output unit and a failure protection unit;

[0005] The input end of the comparison unit and the input end of the failure protection unit are used to input a differential signal, the output end of the comparison unit is connected to the first input end of the logic output unit, the output end of the failure protection unit is connected to the second input end of the logic output unit, and the output end of the logic output unit serves as the output end of the receiving circuit; the comparison unit includes a first threshold value and a second threshold value, the first threshold value is greater than 0, and serves as a positive input threshold value of the receiving circuit, and the second threshold value is less than 0, and serves as a negative input threshold value of the receiving circuit; the comparison unit is used to output a first comparison signal according to the differential signal, the first comparison signal is valid when the differential signal is greater than the first threshold value, and is invalid when the differential signal is less than the second threshold value;

[0006] The failure protection unit includes a third threshold and a fourth threshold, wherein the third threshold and the fourth threshold are smaller than the first threshold and larger than the second threshold, and the third threshold is larger than the fourth threshold; the failure protection unit is used to output a valid failure protection signal when the differential signal is larger than the third threshold, and to output an invalid failure protection signal when the differential signal is smaller than the fourth threshold; the logic output unit is used to output a valid reception signal when at least one of the first comparison signal and the failure protection signal is valid.

[0007] Optionally, the failure protection unit includes a first comparator; the positive input terminal of the first comparator is used to input the positive voltage signal of the differential signal, and the negative input terminal of the first comparator is used to input the negative voltage signal of the differential signal; the output terminal of the first comparator is connected to the second input terminal of the logic output unit, and the first comparator is used to output a valid second comparison signal when the differential signal is greater than the third threshold, and output an invalid second comparison signal when the differential signal is less than the fourth threshold.

[0008] Optionally, the failure protection unit also includes a delay module; the input end of the delay module is connected to the output end of the first comparator, the output end of the delay module is connected to the second input end of the logic output unit, the reset end of the delay module is connected to the output end of the comparison unit, the delay module is used to start timing when the second comparison signal is valid, and output a valid failure protection signal when the timing reaches a preset time; the delay module is also used to reset when the level of the first comparison signal is flipped.

[0009] Optionally, the comparison unit includes a second comparator; the positive input terminal of the second comparator is used to input the positive voltage signal of the differential signal, and the negative input terminal of the second comparator is used to input the negative voltage signal of the differential signal; the output terminal of the second comparator is connected to the first input terminal of the logic output unit.

[0010] Optionally, a response rate of the second comparator is greater than a response rate of the first comparator.

[0011] Optionally, the third threshold is less than 0.

[0012] Optionally, the absolute values ​​of the first threshold and the second threshold are equal.

[0013] Optionally, the logic output unit includes an OR gate;

[0014] The first input end of the OR gate is connected to the output end of the comparison unit, the second input end of the OR gate is connected to the output end of the failure protection unit, and the output end of the OR gate serves as the output end of the receiving circuit.

[0015] In a second aspect, an embodiment of the present invention further provides a communication interface, comprising a driving circuit and at least one receiving circuit as described in the first aspect; the driving circuit is connected to the receiving circuit via a differential bus.

[0016] Optionally, when the communication interface includes multiple receiving circuits, the structures of different receiving circuits are the same.

[0017] The technical solution of the embodiment of the present invention, by setting the first threshold of the comparison unit to be greater than 0 and serving as the positive input threshold of the receiving circuit. The second threshold is less than 0 and serves as the negative input threshold of the receiving circuit, which can increase the hysteresis voltage of the receiving circuit and improve the anti-interference ability of the receiving circuit. Moreover, when the voltage of the differential signal is less than the first threshold and greater than the third threshold, the failure protection unit can output a valid failure protection signal according to the differential signal, and the logic output unit can output a high-level receiving signal according to the valid failure protection signal, that is, the receiving circuit outputs a valid receiving signal when the voltage of the differential signal is less than the first threshold and greater than the third threshold. Therefore, when the differential signal is between the first threshold and the third threshold, the failure protection unit can convert the uncertain output state of the receiving circuit into a high-level receiving signal output by the receiving circuit, thereby avoiding the uncertain output state of the receiving circuit. At the same time, it can avoid setting an additional resistor on the differential bus, reduce the load on the differential bus, and improve the driving ability of the driving circuit connected to the receiving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the structure of a communication interface provided for related technologies;

[0019] Figure 2 A schematic diagram of the structure of a receiving circuit provided by an embodiment of the present invention;

[0020] Figure 3 A schematic diagram of a threshold value of a differential signal defined by a communication protocol of an RS485 interface provided in an embodiment of the present invention;

[0021] Figure 4 A schematic diagram of the logic output level of a receiving circuit in an RS485 interface provided by an embodiment of the present invention;

[0022] Figure 5 A schematic diagram of logic output levels of a receiving circuit in an RS485 interface under interference provided by an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of the structure of another receiving circuit provided by an embodiment of the present invention;

[0024] Figure 7 A schematic diagram of the structure of another receiving circuit provided by an embodiment of the present invention;

[0025] Figure 8 A logic diagram of input signals and output signals of a receiving circuit provided in an embodiment of the present invention;

[0026] Fig. 9 A schematic diagram of the structure of another receiving circuit provided by an embodiment of the present invention;

[0027] Fig.10 A schematic diagram of the structure of a communication interface provided by an embodiment of the present invention;

[0028] Fig.11 A schematic diagram of the structure of another communication interface provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0030] Figure 1 A schematic diagram of a communication interface structure provided for related technologies. Figure 1 As shown, the driving circuit D1 is connected to the receiving circuit R1 through a differential bus. A pull-up resistor Rfs1 is provided on the input path A1 of the positive voltage signal of the differential bus, a pull-down resistor Rfs2 is provided on the input path B1 of the negative voltage signal of the differential bus, and a voltage-dividing resistor Rt is connected between the input path A1 of the positive voltage signal of the differential bus and the input path B1 of the negative voltage signal of the differential bus. When the driving circuit D1 is turned off, the voltage between the power supply terminal Vcc and the fixed potential terminal V1 is divided by the pull-up resistor Rfs1, the voltage-dividing resistor Rt and the pull-down resistor Rfs2, so that the voltage difference between the two ends of the voltage-dividing resistor Rt is greater than the differential bus voltage corresponding to the logic high defined by the communication protocol, so that the receiving circuit R1 outputs a logic high signal, avoiding the output state uncertainty of the receiving circuit R1 when the driving circuit D1 is turned off. When an abnormal short circuit occurs in the differential bus, the voltage between the input path A1 of the positive voltage signal of the differential bus and the input path B1 of the negative voltage signal is still equal to 0, and the receiving circuit R1 cannot achieve failure protection at this time. Moreover, the additional pull-up resistor Rfs1 , the voltage-dividing resistor Rt, and the pull-down resistor Rfs2 increase the load of the differential bus and reduce the driving capability of the driving circuit D1 .

[0031] In some related technologies, the threshold corresponding to the logic high of the receiving circuit R1 can also be set to be less than 0. At this time, when the driving circuit D1 is turned off or the differential bus is abnormally short-circuited, the voltage between the input path A1 of the positive voltage signal of the differential bus and the input path B1 of the negative voltage signal is equal to 0, which is greater than the threshold corresponding to the logic high of the receiving circuit R1, so that the receiving circuit R1 outputs a logic high signal, avoiding the output state uncertainty of the receiving circuit R1 when the driving circuit D1 is turned off or the differential bus is abnormally short-circuited. Since the threshold corresponding to the logic high of the receiving circuit R1 is less than 0, the threshold corresponding to the logic high of the receiving circuit R1 can only be limited between 0 and the voltage corresponding to the logic low defined by the communication protocol, which reduces the hysteresis voltage of the receiving circuit R1 and reduces the anti-interference ability of the receiving circuit R1. Exemplarily, when the communication interface is a serial communication standard (Recommended Standard 485, RS485) interface, the highest threshold defined by the communication protocol is 200mV and the lowest threshold is -200mV. At this time, the threshold corresponding to the logic high of the receiving circuit R1 can be set to -100mV, and the threshold corresponding to the logic low can be set to -120mV. When the driving circuit D1 is turned off or the differential bus is abnormally short-circuited, a high-level receiving signal can be output to avoid the output state uncertainty of the receiving circuit R1. At this time, the hysteresis voltage of the receiving circuit R1 is -100mV-(-120mV)=20mV, and the hysteresis voltage of the receiving circuit R1 is relatively small, which reduces the anti-interference ability of the receiving circuit R1.

[0032] In view of the above technical problems, an embodiment of the present invention provides a receiving circuit, which is applied to a communication interface. In the embodiment of the present invention, a high level is effective and a low level is invalid. Figure 2 A schematic diagram of a receiving circuit provided by an embodiment of the present invention is shown in FIG. Figure 2As shown, the receiving circuit includes a comparison unit 10, a logic output unit 20 and a failure protection unit 30; the input end of the comparison unit 10 and the input end of the failure protection unit 30 are used to input a differential signal, the output end of the comparison unit 10 is connected to the first input end of the logic output unit 20, the output end of the failure protection unit 30 is connected to the second input end of the logic output unit 20, and the output end of the logic output unit 20 serves as the output end R of the receiving circuit; the comparison unit 10 includes a first threshold value Vth+ and a second threshold value Vth-, the first threshold value Vth+ is greater than 0, and serves as a positive input threshold value of the receiving circuit, and the second threshold value Vth- is less than 0, and serves as a negative input threshold value of the receiving circuit; the comparison unit 10 is used to output a first comparison value according to the differential signal The first comparison signal is valid when the differential signal is greater than the first threshold value Vth+, and is invalid when the differential signal is less than the second threshold value Vth-; the failure protection unit 30 includes a third threshold value Vth3 and a fourth threshold value Vth4, the third threshold value Vth3 and the fourth threshold value Vth4 are less than the first threshold value Vth+, and greater than the second threshold value Vth-, and the third threshold value Vth3 is greater than the fourth threshold value Vth4; the failure protection unit 30 is used to output a valid failure protection signal when the differential signal is greater than the third threshold value Vth3, and output an invalid failure protection signal when the differential signal is less than the fourth threshold value Vth4, and the logic output unit 20 is used to output a valid reception signal when at least one of the first comparison signal and the failure protection signal is valid.

[0033] Specifically, the differential signal can be transmitted by a differential bus. Figure 2 exemplarily shows that the comparison unit 10 includes a positive input terminal V+ and a negative input terminal V-. The positive input terminal V+ of the comparison unit 10 can be connected to the positive output terminal of the driving circuit through a data transmission signal line of the differential bus, and is used to receive the positive voltage signal of the differential signal. The negative input terminal V- of the comparison unit 10 can be connected to the negative output terminal of the driving circuit through another data transmission signal line of the differential bus, and is used to receive the negative voltage signal of the differential signal. This allows the comparison unit 10 to input a differential signal.

[0034] When the receiving circuit is applied to different communication interfaces, different communication interfaces have different communication protocols. Different communication protocols have different definitions of the threshold of the differential signal transmitted on the differential bus. The differential signal is the voltage difference between the two data transmission signal lines of the differential bus. For example, when the communication interface is an RS485 interface, Figure 3 A schematic diagram of a threshold value of a differential signal defined in a communication protocol of an RS485 interface provided in an embodiment of the present invention. Figure 4The following is a schematic diagram of the logic output level of a receiving circuit in an RS485 interface provided by an embodiment of the present invention. Wherein, a is a voltage timing diagram of a positive voltage signal in a differential signal, b is a voltage timing diagram of a negative voltage signal in a differential signal, ab is a timing diagram of a differential signal input to the receiving circuit, and r is a signal timing diagram of an output of the receiving circuit. Figure 3 and Figure 4 As shown, when the voltage of the differential signal of the differential bus is greater than the highest threshold 200mV defined by the communication protocol of the RS485 interface, the receiving circuit outputs a logic high signal 1. When the voltage of the differential signal of the differential bus is less than the lowest threshold -200mV defined by the communication protocol of the RS485 interface, the receiving circuit outputs a low signal 0. In other embodiments, the communication interface may also be an RS422 interface, a Low-Voltage Differential Signaling (LVDS) interface, and a Multipoint Low-Voltage Differential Signaling (MLVDS) interface, etc., which are not limited here.

[0035] The comparison unit 10 has a first threshold value Vth+ and a second threshold value Vth-, the first threshold value Vth+ is the positive threshold voltage of the comparison unit 10, and the first threshold value Vth+ can be set according to the threshold voltage corresponding to the logic high defined by the communication protocol, that is, according to the highest threshold value of the communication protocol, as the positive input threshold of the receiving circuit. The second threshold value Vth- is the negative threshold voltage of the comparison unit 10, and the second threshold value Vth- can be set according to the threshold voltage corresponding to the logic low defined by the communication protocol, that is, according to the lowest threshold value of the communication protocol, as the negative input threshold of the receiving circuit. The first threshold value Vth+ is greater than 0 and less than the highest threshold value of the communication protocol, and the second threshold value Vth- is less than 0 and greater than the lowest threshold value of the communication protocol, which can ensure that the hysteresis voltage of the receiving circuit is relatively large and improve the anti-interference ability of the receiving circuit. Among them, the hysteresis voltage is the difference between the first threshold value Vth+ and the second threshold value Vth- of the receiving circuit. For example, the first threshold value Vth+=120mV, the second threshold value Vth-=-120mV, then the hysteresis voltage of the receiving circuit is Vhys=120–(-120)=240mV. Compared with the related art, the hysteresis voltage range is doubled, thereby improving the anti-interference ability of the receiving circuit. Exemplarily, when the communication interface is an RS485 interface, Figure 5 The following is a schematic diagram of the logic output level of a receiving circuit in an RS485 interface under interference provided by an embodiment of the present invention. Wherein, ab is a timing diagram of a differential signal input to the receiving circuit, and r is a timing diagram of a signal output from the receiving circuit. Figure 5As shown, under the influence of interference, the jitter amplitude of the differential signal exceeds the range of the first threshold value Vth+ and the second threshold value Vth- of the receiving circuit, and the receiving circuit will respond by outputting an erroneous receiving signal. Figure 5 In the interference stage t0, under the effect of interference, the voltage of the differential signal changes from less than the second threshold value Vth- to greater than the first threshold value Vth+, and the receiving signal of the receiving circuit changes from a low level to an erroneous high level. In the present application, the first threshold value Vth+ is greater than 0, and the second threshold value Vth- is less than 0. By setting the range of the first threshold value Vth+ and the second threshold value Vth- to be relatively large, that is, the hysteresis voltage of the receiving circuit is relatively large, the anti-interference ability of the receiving circuit can be improved.

[0036] During the operation of the receiving circuit, when the voltage of the differential signal is less than the second threshold value Vth-, the first comparison signal output by the comparison unit 10 is at a low level. At the same time, the differential signal is less than the fourth threshold value Vth4, and the failure protection signal output by the failure protection unit 30 according to the differential signal is at a low level. At this time, the logic output unit 20 outputs a low-level receiving signal according to the first comparison signal and the failure protection signal. That is, the receiving circuit outputs an invalid receiving signal when the voltage of the differential signal is less than the second threshold value Vth-. Moreover, the fourth threshold value Vth4 is greater than or equal to the second threshold value Vth-, so that before the comparison unit 10 outputs the low-level first comparison signal, it can be ensured that the failure protection unit 30 outputs a low-level failure protection signal to avoid the failure protection signal interfering with the normal operation of the receiving circuit.

[0037] When the voltage of the differential signal is less than the third threshold value Vth3 and greater than the fourth threshold value Vth4, the first comparison signal output by the comparison unit 10 maintains the level state of the previous stage. The failure protection signal output by the failure protection unit 30 can also maintain the level state of the previous stage. The logic output unit 20 maintains the level state of the previous stage. That is, the receiving signal output by the receiving circuit maintains the level state of the previous stage when the voltage of the differential signal is less than the third threshold value Vth3 and greater than the fourth threshold value Vth4.

[0038] When the voltage of the differential signal is less than the first threshold value Vth+ and greater than the third threshold value Vth3, if the first comparison signal output by the comparison unit 10 in the previous stage is low, the first comparison signal output by the comparison unit 10 is low at this time. If the first comparison signal output by the comparison unit 10 in the previous stage is high, the first comparison signal output by the comparison unit 10 is high at this time. At the same time, the differential signal is greater than the third threshold value Vth3, and the failure protection signal output by the failure protection unit 30 according to the differential signal is high. At this time, the logic output unit 20 outputs a high-level receiving signal according to the first comparison signal and the failure protection signal. That is, the receiving circuit outputs a valid receiving signal when the voltage of the differential signal is less than the first threshold value Vth+ and greater than the third threshold value Vth3. Therefore, when the differential signal is between the first threshold value Vth+ and the third threshold value Vth3, the failure protection unit 30 can convert the output uncertain state of the receiving circuit into a receiving signal output by the receiving circuit at a high level, thereby improving the output uncertain state of the receiving circuit. At the same time, it is possible to avoid setting additional resistors on the differential bus, reduce the load on the differential bus, avoid the potential shift phenomenon caused by the resistor, and improve the driving capability of the driving circuit corresponding to the receiving circuit.

[0039] When the voltage of the differential signal is greater than the first threshold Vth+, the first comparison signal output by the comparison unit 10 is high. The logic output unit 20 can output a high level signal according to the first comparison signal, and the receiving circuit outputs a valid receiving signal when the voltage of the differential signal is greater than the first threshold Vth+.

[0040] The technical solution of this embodiment, by setting the first threshold of the comparison unit to be greater than 0 and serving as the positive input threshold of the receiving circuit. The second threshold is less than 0 and serves as the negative input threshold of the receiving circuit, which can increase the hysteresis voltage of the receiving circuit and improve the anti-interference ability of the receiving circuit. Moreover, when the voltage of the differential signal is less than the first threshold and greater than the third threshold, the failure protection unit can output a valid failure protection signal according to the differential signal, and the logic output unit can output a high-level receiving signal according to the valid failure protection signal, that is, the receiving circuit outputs a valid receiving signal when the voltage of the differential signal is less than the first threshold and greater than the third threshold. Therefore, when the differential signal is between the first threshold Vth+ and the third threshold Vth3, the failure protection unit can convert the uncertain output state of the receiving circuit into a high-level receiving signal output by the receiving circuit, thereby avoiding the uncertain output state of the receiving circuit. At the same time, it can avoid setting an additional resistor on the differential bus, reduce the load on the differential bus, and improve the driving ability of the driving circuit connected to the receiving circuit.

[0041] Figure 6 A structural diagram of another receiving circuit provided by an embodiment of the present invention is shown in FIG. Figure 6As shown, the failure protection unit 30 includes a first comparator Comp1; the positive input terminal 1+ of the first comparator Comp1 is used to input a positive voltage signal of the differential signal, and the negative input terminal 1- of the first comparator Comp1 is used to input a negative voltage signal of the differential signal; the output terminal of the first comparator Comp1 is connected to the second input terminal of the logic output unit 20, and the first comparator Comp1 is used to output a valid second comparison signal when the differential signal is greater than a third threshold value Vth3, and output an invalid second comparison signal when the differential signal is less than a fourth threshold value Vth4.

[0042] Specifically, when the output end of the first comparator Comp1 is directly connected to the second input end of the logic output unit 20, the second comparison signal output by the first comparator Comp1 is used as a failure protection signal. When the differential signal is greater than the third threshold value Vth3, the second comparison signal output by the first comparator Comp1 is high level. At this time, the logic output unit 20 outputs a high level receiving signal according to the high level second comparison signal. Therefore, the output uncertain state of the receiving circuit can be converted into a receiving signal output by the receiving circuit at a high level by the first comparator Comp1, thereby improving the output uncertain state of the receiving circuit. When the differential signal is less than the fourth threshold value Vth4, the second comparison signal output by the first comparator Comp1 is low level. At this time, the logic output unit 20 determines the state of the receiving signal according to the first comparison signal. When the differential signal is greater than the fourth threshold value Vth4 and less than the third threshold value Vth3, the second comparison signal output by the first comparator Comp1 maintains the level state of the previous stage.

[0043] Figure 7 A structural diagram of another receiving circuit provided by an embodiment of the present invention is shown in FIG. Figure 7 As shown, the failure protection unit 30 also includes a delay module Timer; the input end of the delay module Timer is connected to the output end of the first comparator Comp1, the output end of the delay module Timer is connected to the second input end of the logic output unit 20, and the reset end of the delay module Timer is connected to the output end of the comparison unit 10. The delay module Timer is used to start timing when the second comparison signal is valid, and output a valid failure protection signal when the timing reaches a preset time; the delay module Timer is also used to reset when the level of the first comparison signal is flipped.

[0044] Specifically, the delay module Timer has a delay function, for example, the delay module Timer can be a delay device. When the differential signal is greater than the third threshold value Vth3 and the second comparison signal output by the first comparator Comp1 is at a high level, the delay module Timer starts timing. When the timing reaches the preset time, the delay module Timer outputs a high-level delay signal, and outputs it to the second input end of the logic output unit 20 as a failure protection signal. The logic output unit 20 outputs a high-level receiving signal according to the high-level failure protection signal, so that when the differential signal is greater than the third threshold value Vth3, the output uncertainty state of the receiving circuit can be converted into a high-level receiving signal output by the receiving circuit, thereby improving the output uncertainty state of the receiving circuit. In addition, the delay signal output by the delay module Timer has a lag relative to the second comparison signal. After the delay module Timer starts timing, it can be reset according to the level flip signal of the first comparison signal. That is, when the differential signal changes up and down at the first threshold value Vth+, the level of the first comparison signal flips. The delay module Timer is reset according to the level flipping of the first comparison signal, outputs a low-level delay signal, and outputs it as a failure protection signal to the second output terminal of the logic output unit 20. At this time, the level of the receiving signal output by the logic output unit 20 is consistent with the level of the first comparison signal, so that the priority of the first comparison signal can be guaranteed to be higher than the priority of the failure protection signal. When the comparison unit 10 can transmit the signal normally, the failure protection signal is prevented from interfering with the receiving signal, and the failure protection unit is prevented from affecting the normal operation of the receiving circuit.

[0045] Continue to refer Figure 7 The comparison unit 10 includes a second comparator Comp2; the positive input terminal 2+ of the second comparator Comp2 is used to input a positive voltage signal of the differential signal, and the negative input terminal 2- of the second comparator Comp2 is used to input a negative voltage signal of the differential signal; the output terminal of the second comparator Comp2 is connected to the first input terminal of the logic output unit 20.

[0046] Specifically, when the differential signal is greater than the first threshold value Vth+, the first comparison signal output by the second comparator Comp2 is a high level. When the differential signal is less than the first threshold value Vth+, the first comparison signal output by the second comparator Comp2 maintains the level state of the previous stage. When the differential signal changes from less than the first threshold value Vth+ to greater than the first threshold value Vth+, the first comparison signal flips from a low level to a high level, and has a rising edge. When the differential signal changes from greater than the second threshold value Vth- to less than the second threshold value Vth-, the first comparison signal flips from a high level to a low level, and has a falling edge. When the first comparison signal has a rising edge or a falling edge, the delay module Timer can be reset according to the rising edge or the falling edge of the first comparison signal, and output a low-level failure protection signal to avoid the failure protection signal interfering with the receiving signal when the receiving circuit can output a certain state.

[0047] In some embodiments, the response rate of the second comparator Comp2 is greater than the response rate of the first comparator Comp1.

[0048] Specifically, the response rate of the second comparator Comp2 is relatively large, which can ensure that the receiving circuit has a relatively high signal transmission speed. The response rate of the first comparator Comp1 can be relatively small, which is used to implement the failure protection function of the receiving circuit. By setting the response rate of the second comparator Comp2 to be greater than the response rate of the first comparator Comp1, the reliability of the failure protection can be guaranteed on the basis of ensuring the signal transmission speed of the receiving circuit. Exemplarily, the response rate of the second comparator Comp2 can be 10 nanoseconds, and the response rate of the first comparator Comp1 can be microseconds.

[0049] In some embodiments, the absolute values ​​of the first threshold Vth+ and the second threshold Vth- are equal.

[0050] Specifically, when the absolute values ​​of the first threshold value Vth+ and the second threshold value Vth- are equal, the values ​​of the first threshold value Vth+ and the second threshold value Vth- are symmetrical about 0. During the operation of the receiving circuit, a first difference between a positive voltage signal in a differential signal provided by the differential bus and the first threshold value Vth+ and a second difference between a negative voltage signal in a differential signal provided by the differential bus and the second threshold value Vth- are symmetrical about 0, so that the delay of the receiving signal output by the receiving circuit at the rising edge and the delay at the falling edge can be symmetrical about 0, thereby improving the consistency of the delay of the receiving signal when flipping, thereby improving the signal transmission rate of the receiving circuit.

[0051] In some embodiments, continue to refer to Figure 6 and Figure 7 , the third threshold Vth3 is less than 0.

[0052] Specifically, when the third threshold value Vth3 is less than 0, the voltage difference between the first threshold value Vth+ and the third threshold value Vth3 can be relatively large. When the failure protection unit 30 performs failure protection on the differential signal between the first threshold value Vth+ and the third threshold value Vth3, the voltage range for the failure protection unit 30 to perform failure protection can be increased, thereby improving the failure protection effect. Moreover, the third threshold value Vth3 is greater than the second threshold value Vth-, so that the third threshold value Vth3 is greater than the lowest threshold value of the communication protocol. Thus, the failure protection unit 30 can output a low-level failure protection signal when the differential signal is less than the second threshold value Vth-, thereby preventing the failure protection signal from interfering with the normal operation of the receiving circuit. Exemplarily, when the failure protection unit 30 includes a first comparator Comp1, the third threshold value Vth3 can be the positive threshold value of the first comparator Comp1. When the receiving circuit is applied to an RS485 interface, the highest threshold value of the communication protocol is 200mV and the lowest threshold value is -200mV. The first threshold Vth+ may be 120 mV, the second threshold Vth- may be -120 mV, and the third threshold Vth3 may be -100 mV.

[0053] In addition, the difference between the third threshold value Vth3 and the second threshold value Vth- can be used as the protection threshold voltage of the failure protection unit 30. Among them, the protection threshold voltage of the failure protection unit 30 is the minimum threshold voltage for the receiving circuit to perform failure protection on the differential signal. When the voltage of the differential signal is greater than the protection threshold voltage of the failure protection unit 30, the failure protection unit 30 performs failure protection according to the differential signal. When the voltage of the differential signal is less than or equal to the protection threshold voltage of the failure protection unit 30, the failure protection unit 30 will not act according to the differential signal. By setting the protection threshold voltage of the failure protection unit 30, it is possible to avoid the failure protection unit 30 from over-protecting when the differential signal fluctuates, thereby improving the stability of the receiving circuit.

[0054] For example, Figure 8 A logic diagram of input signals and output signals of a receiving circuit provided by an embodiment of the present invention. Among them, out1 is a timing diagram of a first comparison signal, out2 is a timing diagram of a second comparison signal, ab is a timing diagram of a differential signal input to the receiving circuit, timeout is a timing diagram of a delay signal, and r is a timing diagram of a signal output by the receiving circuit. Figure 8 As shown:

[0055] In the first stage t1, when the differential signal is less than the third threshold value Vth3, when the differential signal is less than the second threshold value Vth-, the first comparison signal and the second comparison signal are both low level. When the differential signal is greater than the second threshold value Vth- and less than the fourth threshold value Vth4, the second comparison signal is low level, and the first comparison signal maintains the low level of the previous stage. When the differential signal is greater than the fourth threshold value Vth4 and less than the third threshold value Vth3, the second comparison signal maintains the low level of the previous stage, and the first comparison signal maintains the low level of the previous stage. That is, the first comparison signal and the second comparison signal of the first stage t1 are low level. At this time, the delay module Timer cannot time, and the delay module Timer outputs a low-level delay signal, and outputs it to the second input end of the logic output unit 20 as a failure protection signal. At the same time, the first comparison signal is output to the first input end of the logic output unit 20, and the logic output unit 20 outputs a low-level receiving signal according to the low-level first comparison signal and the low-level failure protection signal. That is, the receiving circuit outputs an invalid receiving signal when the voltage of the differential signal is less than the third threshold value Vth3.

[0056] In the second stage t2, when the differential signal is less than the first threshold value Vth+ and greater than the third threshold value Vth3, the first comparison signal maintains the low level of the previous stage, and the second comparison signal is high. At this time, the delay module Timer starts timing. Before timing to the preset time t', the delay module Timer outputs a low-level delay signal, and outputs it to the second input end of the logic output unit 20 as a failure protection signal. The logic output unit 20 outputs a low-level receiving signal according to the low-level first comparison signal and the low-level failure protection signal. When timing to the preset time t', the delay module Timer outputs a high-level delay signal, and outputs it to the second input end of the logic output unit 20 as a failure protection signal. The logic output unit 20 outputs a high-level receiving signal according to the high-level failure protection signal. Therefore, when the differential signal is less than the first threshold value Vth+ and greater than the third threshold value Vth3, the output uncertain state of the receiving circuit can be converted into a high-level receiving signal output by the receiving circuit, thereby avoiding the output uncertain state of the receiving circuit.

[0057] In the third stage t3, when the differential signal is greater than the first threshold value Vth+, the first comparison signal is flipped from a low level to a high level, and the second comparison signal is a high level. The delay module Timer is reset according to the level flip of the first comparison signal, and outputs a low-level delay signal. At this time, the logic output unit 20 outputs a high-level receiving signal according to the high-level first comparison signal, so that the priority of the first comparison signal is higher than the priority of the failure protection signal. The receiving circuit can output a valid receiving signal when the differential signal is greater than the first threshold value Vth+, thereby ensuring the normal operation of the receiving circuit. After the delay module Timer is reset, the delay module Timer continues to start timing according to the second comparison signal. Before timing to the preset time t', the delay module Timer outputs a low-level delay signal.

[0058] In the fourth stage t4, when the differential signal is less than the first threshold value Vth+ and greater than the fourth threshold value Vth4, when the differential signal is less than the first threshold value Vth+ and greater than the third threshold value Vth3, the first comparison signal maintains the high level of the third stage t3, and the second comparison signal is high. When the differential signal is less than the third threshold value Vth3 and greater than the fourth threshold value Vth4, the first comparison signal maintains the high level of the previous stage, and the second comparison signal maintains the high level of the previous stage. The delay module Timer continues to time according to the second comparison signal. When the timing reaches the preset time t', the delay module Timer outputs a high-level delay signal and outputs it to the second input end of the logic output unit 20 as a failure protection signal. The logic output unit 20 outputs a high-level receiving signal according to the high-level failure protection signal and the high-level first comparison signal. Therefore, when the differential signal is less than the first threshold value Vth+ and greater than the third threshold value Vth3, the output uncertainty state of the receiving circuit can be converted into a receiving signal output by the receiving circuit at a high level, thereby avoiding the output uncertainty state of the receiving circuit.

[0059] In the fifth stage t5, when the differential signal is less than the fourth threshold value Vth4 and greater than the second threshold value Vth-, the first comparison signal maintains the high level of the fourth stage t4, and the second comparison signal is low. At this time, the delay module Timer cannot time, and the delay module Timer outputs a low-level delay signal, and outputs it to the second input end of the logic output unit 20 as a failure protection signal. At the same time, the first comparison signal is output to the first input end of the logic output unit 20, and the logic output unit 20 outputs a high-level receiving signal according to the high-level first comparison signal. That is, the receiving circuit outputs a valid receiving signal when the voltage of the differential signal is less than the fourth threshold value Vth4 and greater than the second threshold value Vth-.

[0060] In the sixth stage t6, when the differential signal is less than the second threshold value Vth-, the first comparison signal is low level and the second comparison signal is low level. At this time, the delay module Timer cannot time, and the delay module Timer outputs a low level delay signal, and outputs it to the second input end of the logic output unit 20 as a failure protection signal. At the same time, the first comparison signal is output to the first input end of the logic output unit 20, and the logic output unit 20 outputs a low level receiving signal according to the low level first comparison signal. That is, the receiving circuit outputs an invalid receiving signal when the voltage of the differential signal is less than the second threshold value Vth-. When the differential signal is less than the third threshold value Vth3 and greater than the second threshold value Vth-, the first comparison signal and the second comparison signal are both maintained at a low level. The delay module Timer cannot time, and the delay module Timer outputs a low level delay signal, and outputs it to the second input end of the logic output unit 20 as a failure protection signal. At the same time, the first comparison signal is output to the first input end of the logic output unit 20, and the logic output unit 20 outputs a low level receiving signal according to the low level first comparison signal. That is, the receiving circuit outputs an invalid receiving signal when the voltage of the differential signal is less than the second threshold value Vth-.

[0061] In the seventh stage t7, when the differential signal is less than the first threshold value Vth+ and greater than the third threshold value Vth3, the first comparison signal is maintained at a low level and the second comparison signal is at a high level. At this time, the delay module Timer starts timing. Before timing to the preset time t', the delay module Timer outputs a low-level delay signal and outputs it to the second input end of the logic output unit 20 as a failure protection signal. The logic output unit 20 outputs a low-level receiving signal according to the low-level first comparison signal and the low-level failure protection signal. Before the delay module Timer times to the preset time t', the differential signal jumps from the current value to a value greater than the first threshold value Vth+, so that the first comparison signal flips from a low level to a high level, and the second comparison signal is a high level. The delay module Timer resets according to the level flip of the first comparison signal and outputs a low-level delay signal. At this time, the logic output unit 20 outputs a high-level receiving signal according to the high-level first comparison signal, so that the priority of the first comparison signal is higher than the priority of the failure protection signal, and the receiving circuit can output a valid receiving signal when the differential signal is greater than the first threshold value Vth+, thereby ensuring the normal operation of the receiving circuit. At the same time, the delay module Timer starts timing according to the second comparison signal after being reset. Before timing reaches the preset time t', the delay module Timer outputs a low-level delay signal. When timing reaches the preset time t', the delay module Timer outputs a high-level delay signal.

[0062] Fig. 9 A structural diagram of another receiving circuit provided by an embodiment of the present invention is shown in FIG. Fig. 9As shown, the logic output unit 20 includes an OR gate OR; a first input terminal of the OR gate OR is connected to the output terminal of the comparison unit 10, a second input terminal of the OR gate OR is connected to the output terminal of the failure protection unit 30, and an output terminal of the OR gate OR serves as an output terminal R of the receiving circuit.

[0063] Specifically, when at least one of the first comparison signal input to the first input terminal of the OR gate OR and the fail-safe signal input to the second input terminal is a high-level signal, the OR gate OR can output a high-level signal, that is, the receiving circuit outputs a high-level receiving signal. When the level state of the logic signal is uncertain, the fail-safe signal can be set to a high-level signal, so that the OR gate OR outputs a high-level signal according to the fail-safe signal, thereby achieving fail-safe of the receiving circuit.

[0064] The embodiment of the present invention also provides a communication interface. Fig.10 A schematic diagram of the structure of a communication interface provided by an embodiment of the present invention. Fig.10 As shown, the communication interface includes a driving circuit Driver and a receiving circuit Receiver provided by any embodiment of the present invention; the driving circuit Driver is connected to the receiving circuit Receiver via a differential bus DTL.

[0065] Specifically, Fig.10 The communication interface includes a receiving circuit Receiver as exemplified in the figure. The positive output terminal OUT+ of the driving circuit Driver is connected to the positive input terminal IN+ of the receiving circuit Receiver through a transmission line of the differential bus DTL, and the negative output terminal OUT- of the driving circuit Driver is connected to the negative input terminal IN- of the receiving circuit Receiver through another transmission line of the differential bus DTL. The signal provided by the driving circuit Driver is output to the receiving circuit Receiver through the differential bus DTL to realize the communication of the communication interface. Since the receiving circuit Receiver is the receiving circuit provided by any embodiment of the present invention, it has the same beneficial effects as the receiving circuit provided by any embodiment of the present invention, which will not be repeated here.

[0066] Fig.11 A schematic diagram of another communication interface provided by an embodiment of the present invention. Fig.11 As shown, when the communication interface includes multiple receiving circuits Receivers, the structures of different receiving circuits Receivers are the same.

[0067] Specifically, Fig.11The communication interface exemplarily shown in FIG. 1 includes three receiving circuits Receiver. Different receiving circuits Receiver may be the receiving circuits provided by any embodiment of the present invention, so that each receiving circuit Receiver may realize failure protection on the basis of improving anti-interference capability.

[0068] Continue to refer Fig.10 and Fig.11 A terminal resistor Rc may be connected between the positive input terminal IN+ and the negative input terminal IN- of the receiving circuit Receiver. The terminal resistor Rc may perform impedance matching with the driving circuit Driver, reduce reflection of the differential signal, and improve the transmission quality of the signal on the differential bus DTL.

[0069] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A receiving circuit, characterized in that: The receiving circuit is applied to a communication interface; the receiving circuit comprises a comparison unit, a logic output unit and a failure protection unit; The input end of the comparison unit and the input end of the failure protection unit are used to input a differential signal, the output end of the comparison unit is connected to the first input end of the logic output unit, the output end of the failure protection unit is connected to the second input end of the logic output unit, and the output end of the logic output unit serves as the output end of the receiving circuit; the comparison unit includes a first threshold value and a second threshold value, the first threshold value is greater than 0 and serves as a positive input threshold value of the receiving circuit, and the second threshold value is less than 0 and serves as a negative input threshold value of the receiving circuit; The comparison unit is used to output a first comparison signal according to the differential signal, wherein the first comparison signal is valid when the differential signal is greater than the first threshold value, and is invalid when the differential signal is less than the second threshold value; The failure protection unit includes a third threshold and a fourth threshold, the third threshold and the fourth threshold are smaller than the first threshold and larger than the second threshold, and the third threshold is larger than the fourth threshold; the failure protection unit is used to output a valid failure protection signal when the differential signal is larger than the third threshold, and output an invalid failure protection signal when the differential signal is smaller than the fourth threshold; the logic output unit is used to output a valid reception signal when at least one of the first comparison signal and the failure protection signal is valid.

2. The receiving circuit according to claim 1, characterized in that: The failure protection unit includes a first comparator; the positive input terminal of the first comparator is used to input the positive voltage signal of the differential signal, and the negative input terminal of the first comparator is used to input the negative voltage signal of the differential signal; the output terminal of the first comparator is connected to the second input terminal of the logic output unit, and the first comparator is used to output a valid second comparison signal when the differential signal is greater than the third threshold, and output an invalid second comparison signal when the differential signal is less than the fourth threshold.

3. The receiving circuit according to claim 2, characterized in that: The failure protection unit also includes a delay module; the input end of the delay module is connected to the output end of the first comparator, the output end of the delay module is connected to the second input end of the logic output unit, and the reset end of the delay module is connected to the output end of the comparison unit. The delay module is used to start timing when the second comparison signal is valid, and output a valid failure protection signal when the timing reaches a preset time; the delay module is also used to reset when the level of the first comparison signal is flipped.

4. The receiving circuit according to claim 3, characterized in that: The comparison unit includes a second comparator; the positive input terminal of the second comparator is used to input the positive voltage signal of the differential signal, and the negative input terminal of the second comparator is used to input the negative voltage signal of the differential signal; the output terminal of the second comparator is connected to the first input terminal of the logic output unit.

5. The receiving circuit according to claim 4, characterized in that: The response rate of the second comparator is greater than the response rate of the first comparator.

6. The receiving circuit according to any one of claims 1 to 5, characterized in that: The third threshold is less than 0.

7. The receiving circuit according to claim 1, characterized in that: The absolute values ​​of the first threshold and the second threshold are equal.

8. The receiving circuit according to claim 1, characterized in that: The logic output unit includes an OR gate; The first input end of the OR gate is connected to the output end of the comparison unit, the second input end of the OR gate is connected to the output end of the failure protection unit, and the output end of the OR gate serves as the output end of the receiving circuit.

9. A communication interface, characterized in that: It comprises a driving circuit and at least one receiving circuit according to any one of claims 1 to 8; the driving circuit is connected to the receiving circuit via a differential bus.

10. The communication interface according to claim 9, characterized in that: When the communication interface includes a plurality of the receiving circuits, the structures of different receiving circuits are the same.

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