A three-dimensional dynamic random access memory array and its preparation method

Abstract

The present invention relates to a method for fabricating a three-dimensional dynamic random access memory array, and relates to the field of semiconductor technology. It solves the technical problem of low integration density of existing 3D DRAM solutions. The method for fabricating a three-dimensional dynamic random access memory array comprises the following steps: sequentially forming a plurality of vertically stacked layers; forming grooves spaced apart along a first horizontal direction on the plurality of vertically stacked layers, and forming through holes on the plurality of vertically stacked layers between adjacent grooves; forming a sacrificial layer in the through hole, and laterally etching a first electrode layer and a second electrode layer along the first horizontal direction to separate the first electrode layer and the second electrode layer at the sacrificial layer; forming an isolation layer in the groove and removing the sacrificial layer to leave the through hole; oxidizing the sidewalls of the first metal layer at the through hole to form a gate dielectric; and sequentially forming a channel layer, a channel passivation layer, and a word line layer in the through hole.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional dynamic random access memory array and a preparation method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a commonly used computer memory technology that represents binary data by storing charge in capacitors. Because capacitors naturally discharge over time, DRAM requires periodic refreshes to maintain stored data. A DRAM memory cell typically consists of a transistor and a capacitor. Compared to static random access memory (SRAM), DRAM offers higher storage density and lower cost.

[0003] Conventional planar DRAM faces several technical and physical barriers when scaling to sub-10nm nodes. These barriers include the following:

[0004] 1. Short channel effect:

[0005] As transistor size shrinks, channel length decreases and short-channel effects (SCE) become more significant, which may lead to increased leakage current and lower threshold voltage.

[0006] 2. Quantum tunneling:

[0007] At the sub-10-nanometer scale, quantum tunneling causes current to pass through the transistor's insulating layer without sufficient voltage difference, increasing power consumption and reducing performance.

[0008] 3. Capacitor problem:

[0009] DRAM memory cells rely on capacitors to store charge, and as size shrinks, the capacitors become smaller, which can make stored data more susceptible to loss.

[0010] Three-dimensional DRAM (3D DRAM) technology has attracted widespread attention due to its potential to achieve higher integration density and lower power consumption. However, the integration density of existing 3D DRAM memory cells still has significant room for improvement, and it still cannot meet the memory requirements of applications such as high-performance computing, big data storage, and artificial intelligence. Summary of the Invention

[0011] In view of the above analysis, embodiments of the present invention aim to provide a three-dimensional dynamic random access memory array and a method for manufacturing the same, so as to solve the technical problem of low integration density of existing 3D DRAM solutions.

[0012] In one aspect, an embodiment of the present invention provides a method for fabricating a three-dimensional dynamic random access memory array, comprising the following steps:

[0013] forming a plurality of vertically stacked layers in sequence, wherein each layer in sequence comprises a first electrode layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second electrode layer, and a third dielectric layer;

[0014] forming grooves spaced apart along a first horizontal direction on the plurality of vertically stacked laminates, and forming through holes on the plurality of vertically stacked laminates between adjacent grooves;

[0015] forming a sacrificial layer in the through hole, and laterally etching the first electrode layer and the second electrode layer along a first horizontal direction to separate the first electrode layer and the second electrode layer at the sacrificial layer;

[0016] forming an isolation layer in the groove and removing the sacrificial layer, leaving the through hole;

[0017] The first metal layer is oxidized on the sidewall of the through hole to form a gate dielectric; and a channel layer, a channel passivation layer and a word line layer are sequentially formed in the through hole.

[0018] Based on a further improvement of the above preparation method, forming a sacrificial layer in the through hole includes:

[0019] Filling the through hole with a sacrificial material using an atomic layer deposition process;

[0020] A wet etching process is used to remove the sacrificial material on the surfaces of the plurality of vertically stacked layers, leaving the sacrificial material in the through hole.

[0021] Based on a further improvement of the above preparation method, forming an isolation layer in the groove includes:

[0022] filling the groove with an isolation material;

[0023] The isolation material on the surface of the plurality of vertically stacked layers is polished by a chemical mechanical polishing process to expose the sacrificial layer in the through hole.

[0024] Based on a further improvement of the above preparation method, the material of the first metal layer is tantalum.

[0025] Based on a further improvement of the above preparation method, oxidizing the sidewall of the first metal layer at the through hole to form a gate dielectric includes:

[0026] The plurality of vertically stacked layers are placed in a high temperature, oxygen atmosphere to oxidize the sidewalls of the first metal layer at the through hole into tantalum pentoxide.

[0027] Based on a further improvement of the above preparation method, forming a channel layer in the through hole includes:

[0028] Depositing a channel material into the through hole using an atomic layer deposition process;

[0029] A dry etching process is used to remove the channel material on the surface of the plurality of vertically stacked layers, leaving the channel material in the through hole.

[0030] Based on a further improvement of the above preparation method, forming a channel passivation layer in the through hole includes:

[0031] Depositing a high dielectric constant medium covering the channel layer into the through hole using an atomic layer deposition process;

[0032] The high dielectric constant medium on the surface of the plurality of vertically stacked layers is removed by a dry etching process, leaving the high dielectric constant medium in the through hole and covering the channel layer.

[0033] Based on a further improvement of the above preparation method, forming a word line layer in the through hole includes:

[0034] Depositing an electrode material covering the channel passivation layer into the through hole using an atomic layer deposition process;

[0035] The electrode material on the surface of the plurality of vertically stacked layers is removed by a dry etching process, leaving the electrode material in the through hole and covering the channel passivation layer.

[0036] Based on further improvement of the above preparation method, the channel material is indium gallium zinc oxide.

[0037] Based on a further improvement of the above preparation method, the high dielectric constant medium is hafnium oxide or aluminum oxide.

[0038] Based on a further improvement of the above preparation method, the electrode material is indium zinc oxide or indium tin oxide.

[0039] According to a further improvement of the above preparation method, the through hole is located at the bottom of the plurality of vertically stacked layers between adjacent grooves along a second horizontal direction, wherein the first horizontal direction and the second horizontal direction are perpendicular to each other.

[0040] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0041] This invention proposes a 3D DRAM integration scheme based on vertical channel transistors, offering a promising solution for overcoming the size limitations of future DRAM technology. The proposed 3D DRAM structure with vertically stacked memory cells is considered a potential development direction for the next generation of DRAM due to its higher memory cell integration density and lower cost.

[0042] 2. The present invention realizes the parallel integration of multi-layer vertical dual-gate 1T1C (1Transistor-1Capacitor) DRAM arrays, which has 6F 2 The memory cell feature size of 1 / 4N (N is the number of parallel integrated layers) has great application prospects in high-integration applications such as high-resolution displays and high-density dynamic random access memory.

[0043] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following description, and some advantages will become apparent from the description or be learned through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the drawings, the same reference symbols denote the same components.

[0045] Figure 1 FIG. 4 is a flow chart of a method for fabricating a three-dimensional dynamic random access memory array according to an embodiment of the present invention.

[0046] Figure 2 FIG. 4 is a conceptual 3D structural diagram illustrating a plurality of vertically stacked layers according to an embodiment of the present invention.

[0047] Figure 3 A conceptual 3D structural diagram of a stacked structure formed in step 101 according to an embodiment of the present invention is shown.

[0048] Figure 4-1 to Figure 4-2 A conceptual 3D schematic diagram of grooves and through-holes formed on a plurality of vertically stacked layers according to an embodiment of the present invention is shown.

[0049] Figure 5-1 to Figure 5-2 FIG. 4 is a conceptual 3D structural diagram illustrating a sacrificial layer formed on a plurality of vertically stacked layers according to an embodiment of the present invention.

[0050] Figure 6-1 to Figure 6-2 Shows the formation Figure 5-1 to Figure 5-2Schematic diagram of a conceptual intermediate process flow for the 3D structure shown.

[0051] Figure 7-1 to Figure 7-2 FIG. 4 is a conceptual 3D structural diagram illustrating separation of a first electrode layer and a second electrode layer on a plurality of vertically stacked layers according to an embodiment of the present invention.

[0052] Figure 8-1 to Figure 8-2 FIG. 4 is a conceptual 3D structural diagram of an isolation layer formed on a plurality of vertically stacked layers according to an embodiment of the present invention.

[0053] Figure 9-1 to Figure 9-2 FIG. 4 is a conceptual 3D structural diagram showing the removal of a sacrificial layer in a plurality of vertically stacked layers according to an embodiment of the present invention.

[0054] Figure 10 A schematic diagram of the 3D structure of a three-dimensional dynamic random access memory array device finally formed by the method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0055] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0056] Figure 1 FIG. 4 is a flow chart of a method for fabricating a three-dimensional dynamic random access memory array according to an embodiment of the present invention.

[0057] The following combination Figure 1 An embodiment of the present invention will be described.

[0058] like Figure 1 As shown, the method for preparing the three-dimensional dynamic random access memory array includes the following steps:

[0059] Step 101: forming a plurality of vertically stacked layers in sequence.

[0060] Figure 2 A conceptual 3D structural diagram of a plurality of vertically stacked layers according to an embodiment of the present invention is shown. Figure 2 Step 101 will be described.

[0061] In this embodiment, a repeated stacking structure of the first electrode layer / first dielectric layer / first metal layer / second dielectric layer / second electrode layer / third dielectric layer can be formed on the substrate by a deposition process such as magnetron sputtering, plasma enhanced chemical vapor deposition, or atomic layer deposition. Figure 2 As shown, each stacked structure of the first electrode layer / first dielectric layer / first metal layer / second dielectric layer / second electrode layer / third dielectric layer is a stack in this embodiment.

[0062] For example, the first electrode layer can be formed by depositing a certain thickness of electrode material on a substrate via a magnetron sputtering deposition process and then patterning the material. Patterning here refers to transferring the pattern on the mask to the deposited first electrode layer through exposure using a photolithography process. The electrode material of the first electrode layer can be titanium nitride.

[0063] For example, the first dielectric layer can be formed by depositing a predetermined thickness of dielectric material on the first electrode layer using a magnetron sputtering deposition process and then patterning the material. Patterning herein refers to transferring a pattern on a mask to the deposited dielectric material through exposure using a photolithography process. The dielectric material of the first dielectric layer can be silicon oxide.

[0064] For example, the first metal layer can be formed by depositing a certain thickness of metal material on the first dielectric layer using a magnetron sputtering deposition process and then patterning the metal material. Patterning herein refers to transferring the pattern on the mask to the deposited metal material through exposure using a photolithography process. The metal material of the first metal layer can be tantalum.

[0065] For example, the second dielectric layer can be formed by depositing a predetermined thickness of dielectric material on the first metal layer using a magnetron sputtering deposition process and then patterning the material. Patterning here refers to transferring the pattern on the mask to the deposited dielectric material through exposure using a photolithography process. The dielectric material of the second dielectric layer can be silicon oxide.

[0066] For example, the second electrode layer can be formed by depositing a predetermined thickness of electrode material on the second dielectric layer using a magnetron sputtering deposition process and then patterning the material. Patterning herein refers to transferring the pattern on the mask to the deposited electrode material through exposure using a photolithography process. The electrode material of the second electrode layer can be titanium nitride.

[0067] For example, the third dielectric layer can be formed by depositing a predetermined thickness of dielectric material on the second electrode layer using a magnetron sputtering deposition process and then patterning the material. Patterning here refers to transferring the pattern on the mask to the deposited dielectric material through exposure using a photolithography process. The dielectric material of the third dielectric layer can be silicon oxide.

[0068] exist Figure 2 In the embodiment, stack 1 includes, from bottom to top, a first electrode layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second electrode layer, and a third dielectric layer. Stack 2 also includes, from bottom to top, a first electrode layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second electrode layer, and a third dielectric layer. Figure 2Each stack represents a stack structure of "first electrode layer / first dielectric layer / first metal layer / second dielectric layer / second electrode layer / third dielectric layer". The stacks are stacked together in the vertical direction to form Figure 2 The structure shown.

[0069] In other embodiments, a repeated stacking structure of electrode material / dielectric material / metal material / dielectric material / electrode material / dielectric material can be first deposited on a substrate by a magnetron sputtering deposition process, wherein each layer of electrode material / dielectric material / metal material has a certain thickness, and then the repeated stacking structure is patterned to obtain Figure 2 The repeated stacking structure of the first electrode layer / first dielectric layer / first metal layer / second dielectric layer / second electrode layer / third dielectric layer is shown.

[0070] Step 102: forming grooves spaced apart along a first horizontal direction on the plurality of vertically stacked laminates, and forming through holes on the plurality of vertically stacked laminates between adjacent grooves.

[0071] Below Figure 3 Step 102 is described using the stacked structure shown as an example. Figure 4-1 to Figure 4-2 FIG2 shows a conceptual 3D structure diagram of grooves and through holes formed on multiple vertically stacked layers according to an embodiment of the present invention. Figure 4-1 to Figure 4-2 Yes Figure 3 Further processing of the schematic 3D structure diagram shown. Figure 3 The stacked structure shown is described. Figure 3 The stacked structure shown includes 11 layers, which are the first electrode layer, the first dielectric layer, the first metal layer, the second dielectric layer, the second electrode layer, the third dielectric layer, the first electrode layer, the first dielectric layer, the first metal layer, the second dielectric layer, and the second electrode layer formed according to step 101. Figure 3 A top view of the 11-layer stacked structure is also shown.

[0072] like Figure 4-1 to Figure 4-2 As shown, it can be Figure 3 The 11-layer stacked structure shown is etched with a plurality of grooves spaced apart along the first horizontal direction. In this embodiment, a plurality of grooves spaced apart along the first horizontal direction can be etched by dry etching techniques such as reactive ion etching, inductively coupled plasma etching, and magnetic neutral line plasma etching. The first horizontal direction in this embodiment can be Figure 3 The vertical direction of the top view shown, the second horizontal direction can be Figure 3 The horizontal direction of the top view is shown.

[0073] like Figure 4-1 to Figure 4-2As shown, through holes can also be etched on the 11-layer stacked structure between adjacent grooves. In this embodiment, a plurality of through holes spaced apart along the first horizontal direction can be etched by dry etching techniques such as reactive ion etching, inductively coupled plasma etching, and magnetic neutral line plasma etching. In some embodiments, the position of the through holes is located at the bottom of the stacked structure between adjacent grooves along the second horizontal direction. Figure 4-2 In the top view shown, "bottom" refers to the left position of the stacked structure between adjacent grooves along the second horizontal direction, and "top" (opposite to "bottom") refers to the right position of the stacked structure between adjacent grooves along the second horizontal direction. Since the position of the through-hole determines the capacitance of the capacitor in the final 3D DRAM structure (described in detail below), the closer the through-hole is to the "bottom," the greater the capacitance of the capacitor and the more stable the performance of the 3D DRAM. Therefore, preferably, the through-hole is located at the bottom of the multiple vertically stacked layers between adjacent grooves along the second horizontal direction.

[0074] Step 103 : forming a sacrificial layer in the through hole, and laterally etching the first electrode layer and the second electrode layer along a first horizontal direction to separate the first electrode layer and the second electrode layer at the sacrificial layer.

[0075] Figure 5-1 to Figure 5-2 FIG. 4 is a conceptual 3D structural diagram illustrating a sacrificial layer formed on a plurality of vertically stacked layers according to an embodiment of the present invention. Figure 6-1 to Figure 6-2 Shows the formation Figure 5-1 to Figure 5-2 A conceptual intermediate process flow diagram of the 3D structure shown below. Figure 6-1 to Figure 6-2 Step 103 will be described.

[0076] It should be noted that Figure 6-1 to Figure 6-2 Yes Figure 4-1 to Figure 4-2 In this embodiment, the atomic layer deposition process can be used to further process the schematic 3D structure shown in FIG. Figure 4-1 to Figure 4-2 The surface of the stacked structure shown is continuously deposited with sacrificial material until the sacrificial material is completely filled. Figure 4-1 to Figure 4-2 through-holes in the . Figure 6-1 The sacrificial material is completely filled to Figure 4-1 to Figure 4-2 Schematic diagram of the 3D structure of the through hole in the Figure 6-1 Represented by gray pigment. Figure 6-2 for Figure 6-1 It should be noted that the vertical direction is Figure 6-2 In the image, a certain degree of depth of field is used. Figure 6-2 As shown, the sacrificial material is completely filled to Figure 4-1 to Figure 4-2 through-holes in the .

[0077] Next, if Figure 5-1 to Figure 5-2 As shown, wet etching process can be used to remove Figure 6-2 for Figure 6-1 The sacrificial material is removed from the surface of the stacked structure, leaving the sacrificial material in the through hole, thereby obtaining a sacrificial layer.

[0078] Figure 7-1 to Figure 7-2 A conceptual 3D structure diagram of separating the first electrode layer and the second electrode layer on a plurality of vertically stacked layers according to an embodiment of the present invention is shown. Figure 7-1 to Figure 7-2 Step 103 will be described.

[0079] It should be noted that Figure 7-1 to Figure 7-2 Yes Figure 5-1 to Figure 5-2 In this embodiment, a wet etching process can be used to laterally etch the first electrode layer and the second electrode layer in the 11-layer stacked structure between the grooves along the first horizontal direction until the first electrode layer and the second electrode layer are separated at the sacrificial layer. Figure 7-2 Schematic diagram showing the first electrode layer and the second electrode layer being separated. Figure 7-2 As shown, the second electrode layer represented by the yellow area is divided into two sections by the sacrificial layer represented by the dark gray area. The two sections are the yellow area on the left side of the sacrificial layer and the yellow area on the right side of the sacrificial layer. Figure 7-1 Schematic diagram of simultaneously etching the first electrode layer and the second electrode layer. Figure 7-1 As shown, the blue area represents the first electrode layer. Through lateral etching, the widths of the first electrode layer and the second electrode layer in the first horizontal direction are shortened simultaneously. Figure 7-2 for Figure 7-1 The top view of the 3D structure is shown in the vertical direction. Figure 7-2 Indicated by a certain degree of depth of field. Figure 7-1 and Figure 7-2 It can be seen that the first electrode layer is divided into two sections by the sacrificial layer.

[0080] Step 104: forming an isolation layer in the groove and removing the sacrificial layer, leaving the through hole.

[0081] Figure 8-1 to Figure 8-2 FIG. 1 shows a conceptual 3D structural diagram of an isolation layer formed on a plurality of vertically stacked layers according to an embodiment of the present invention. Figure 8-1 to Figure 8-2 Step 104 will be described.

[0082] It should be noted that Figure 8-1 to Figure 8-2 Yes Figure 7-1 to Figure 7-2 In this embodiment, the 3D structure can be further processed by magnetron sputtering, plasma enhanced chemical vapor deposition, atomic layer deposition and other deposition processes. Figure 7-1 to Figure 7-2The isolation material is deposited in the groove of the stacked structure and patterned to obtain the isolation layer. The patterning here can be to grind the isolation material on the surface of the stacked structure by a chemical mechanical polishing process until the sacrificial layer in the through hole is exposed.

[0083] Figure 9-1 to Figure 9-2 A conceptual 3D structural diagram of removing a sacrificial layer from a plurality of vertically stacked layers according to an embodiment of the present invention is shown. Figure 9-1 to Figure 9-2 Step 104 will be described.

[0084] It should be noted that Figure 9-1 to Figure 9-2 Yes Figure 8-1 to Figure 8-2 In this embodiment, a wet etching process can be used to remove Figure 8-1 to Figure 8-2 The sacrificial material in the through-hole in the stacked structure is shown, leaving the through-hole, thereby obtaining Figure 9-1 to Figure 9-2 The stacking structure shown.

[0085] Step 105: oxidizing the sidewalls of the first metal layer at the through hole to form a gate dielectric.

[0086] Figure 10 The 3D structure diagram of the device of the three-dimensional dynamic random access memory array finally formed by the method of the embodiment of the present invention is shown. Figure 10 Step 105 will be described.

[0087] In this embodiment, the stacked structure formed according to steps 101 to 104 can be placed in a high temperature, oxygen atmosphere to oxidize the sidewalls of the first metal layer at the through hole to form a gate dielectric. Figure 9-1 to Figure 9-2 The stacked structure shown is placed in an oxygen environment at 400 degrees, and the sidewalls of the through holes in the first metal layer are oxidized to form a gate dielectric. Figure 9-1 to Figure 9-2 The middle is blocked, and the following is combined Figure 10 This process is explained in Figure 10 In the figure, the red material represents the first metal layer in this embodiment. Each first metal layer has a through hole. There is a pink ring around the through hole. Before being oxidized, the pink ring is made of the same material as the first metal layer (both are metal materials, such as tantalum). When high-temperature oxygen is continuously injected into the through hole, the metal material around the through hole can be oxidized into metal oxide (such as tantalum pentoxide), thereby forming a gate dielectric. Figure 10 In FIG, the pink ring at the through hole position in the first metal layer represents the gate dielectric formed in step 105.

[0088] Step 106: forming a channel layer, a channel passivation layer and a word line layer in sequence in the through hole.

[0089] Figure 10 A conceptual 3D structural diagram of a channel layer, a channel passivation layer, and a word line layer formed in a through hole of a plurality of vertically stacked layers according to an embodiment of the present invention is shown. Figure 10 Step 106 will be described.

[0090] In this embodiment, a channel material film can be deposited into the through-holes in the stacked structure formed according to steps 101 to 105 by an atomic layer deposition process, and then the deposited channel material film can be patterned to obtain a channel layer. The patterning process here can be to grind the channel material film on the surface of the stacked structure by a chemical mechanical polishing process, and retain the channel material film in the through-holes. It should be noted that the channel material film deposited in this embodiment covers the sidewalls of the through-holes and does not completely fill the through-holes. Figure 10 In FIG, the green pigment represents the channel layer formed according to this embodiment. In some embodiments, the channel material can be indium gallium zinc oxide.

[0091] Next, a dielectric material film can be deposited into the through-holes in the stacked structure through an atomic layer deposition process, and then the deposited dielectric material film can be patterned to obtain a channel passivation layer. The patterning process here can be to grind the dielectric material film on the surface of the stacked structure through a chemical mechanical polishing process, and retain the dielectric material film in the through-holes. It should be noted that the dielectric material film deposited in this embodiment covers the channel layer and does not completely fill the through-holes. Figure 10 In the figure, the milky white pigment represents the channel passivation layer formed according to this embodiment. In some embodiments, the dielectric material can be a high-k dielectric. Preferably, the dielectric material can be hafnium oxide or aluminum oxide.

[0092] Afterwards, the electrode material can be deposited into the through-holes in the stacked structure through the atomic layer deposition process, and then the deposited electrode material can be patterned to obtain the word line layer. The patterning process here can be to grind the electrode material on the surface of the stacked structure through a chemical mechanical polishing process and retain the electrode material in the through-holes. It should be noted that the electrode material deposited in this embodiment covers the channel passivation layer. Figure 10 In FIG, the gold pigment represents the word line layer formed according to this embodiment. In some embodiments, the electrode material can be indium zinc oxide or indium tin oxide. Figure 10 In the embodiment, the electrode material of the word line layer completely fills the through-holes in the stacked structure, thereby forming a solid word line layer, but the present invention is not limited to this. In other embodiments, the electrode material of the word line layer may cover the channel passivation layer and not completely fill the through-holes in the stacked structure. In this embodiment, the word line layer may have a ring structure.

[0093] Figure 10 The 3D structure diagram of the device of the three-dimensional dynamic random access memory array finally formed by the method of the embodiment of the present invention is shown. Figure 10 The 3D DRAM array in the embodiment of the present invention is described. Figure 10 In the figure, only the functional device structure of the 3D DRAM array is shown. The first dielectric layer, the second dielectric layer and the third dielectric layer as the isolation dielectric are shown. Figure 10 is omitted. Figure 10 As shown in the figure, the blue pigment represents the first electrode layer, and the yellow pigment represents the second electrode layer. Together, they form the source and drain of the transistor. The red pigment represents the first metal layer, which forms the gate of the transistor. The black pigment represents the capacitor. As can be seen from the above description, the black pigment portion is the area to the right of the first and second electrode layers separated by the through hole. The longer the black pigment portion, the greater the capacitance of the capacitor and the better the performance of the 3D DRAM.

[0094] Compared with the prior art, the embodiments of the present invention can achieve at least one of the following beneficial effects:

[0095] This invention proposes a 3D DRAM integration scheme based on vertical channel transistors, offering a promising solution for overcoming the size limitations of future DRAM technology. The proposed 3D DRAM structure with vertically stacked memory cells is considered a potential development direction for the next generation of DRAM due to its higher memory cell integration density and lower cost.

[0096] 2. The present invention realizes the parallel integration of multi-layer vertical dual-gate 1T1C (1Transistor-1Capacitor) DRAM arrays, which has 6F 2 The memory cell feature size of 1 / 4N (N is the number of parallel integrated layers) has great application prospects in high-integration applications such as high-resolution displays and high-density dynamic random access memory.

[0097] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for preparing a three-dimensional dynamic random access memory array, characterized in that: The steps include: forming a plurality of vertically stacked layers in sequence, wherein each layer in sequence comprises a first electrode layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second electrode layer, and a third dielectric layer; forming grooves spaced apart along a first horizontal direction on the plurality of vertically stacked laminates, and forming through holes on the plurality of vertically stacked laminates between adjacent grooves; forming a sacrificial layer in the through hole, and laterally etching the first electrode layer and the second electrode layer along a first horizontal direction to separate the first electrode layer and the second electrode layer at the sacrificial layer; forming an isolation layer in the groove and removing the sacrificial layer, leaving the through hole; oxidizing the sidewalls of the first metal layer at the through hole to form a gate dielectric; and A channel layer, a channel passivation layer and a word line layer are sequentially formed in the through hole.

2. The preparation method according to claim 1, characterized in that Forming a sacrificial layer in the through hole comprises: Filling the through hole with a sacrificial material using an atomic layer deposition process; A wet etching process is used to remove the sacrificial material on the surfaces of the plurality of vertically stacked layers, leaving the sacrificial material in the through hole.

3. The preparation method according to claim 1, characterized in that Forming an isolation layer in the groove includes: filling the groove with an isolation material; The isolation material on the surface of the plurality of vertically stacked layers is polished by a chemical mechanical polishing process to expose the sacrificial layer in the through hole.

4. The preparation method according to claim 1, characterized in that The material of the first metal layer is tantalum.

5. The preparation method according to claim 4, characterized in that Oxidizing the sidewall of the first metal layer at the through hole to form a gate dielectric includes: The plurality of vertically stacked layers are placed in a high temperature, oxygen atmosphere to oxidize the sidewalls of the first metal layer at the through hole into tantalum pentoxide.

6. The preparation method according to claim 1, characterized in that Forming a channel layer in the through hole includes: Depositing a channel material into the through hole using an atomic layer deposition process; A dry etching process is used to remove the channel material on the surface of the plurality of vertically stacked layers, leaving the channel material in the through hole.

7. The preparation method according to claim 1, characterized in that Forming a channel passivation layer in the through hole includes: Depositing a high dielectric constant medium covering the channel layer into the through hole using an atomic layer deposition process; The high dielectric constant medium on the surface of the plurality of vertically stacked layers is removed by a dry etching process, leaving the high dielectric constant medium in the through hole and covering the channel layer.

8. The preparation method according to claim 1, characterized in that Forming a word line layer in the through hole includes: Depositing an electrode material covering the channel passivation layer into the through hole using an atomic layer deposition process; The electrode material on the surface of the plurality of vertically stacked layers is removed by a dry etching process, leaving the electrode material in the through hole and covering the channel passivation layer.

9. The preparation method according to claim 6, characterized in that The channel material is indium gallium zinc oxide.

10. The preparation method according to claim 7, characterized in that The high dielectric constant medium is hafnium oxide or aluminum oxide.

11. The preparation method according to claim 8, characterized in that The electrode material is indium zinc oxide or indium tin oxide.

12. The preparation method according to claim 1, characterized in that The through holes are located at the bottom of the plurality of vertically stacked layers between adjacent grooves along a second horizontal direction, wherein the first horizontal direction and the second horizontal direction are perpendicular to each other.

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