A code generation method and related device

Abstract

The present application discloses a code generation method, which is applied to a simulation system, comprising: adding a target module to generate hardware code in a simulation interface, the target module being used to implement data processing based on hardware bit operations. Then receiving the type and bit width of input data configured by the user through the property configuration interface of the target module, and generating the input port definition in the hardware code of the target module according to the type and bit width of the input data. Then, according to the operation type of the target module, determining at least one bit operator corresponding to the operation type, and generating hardware code for operating the input data. This method realizes automatic generation of hardware code for the module design of hardware circuits in the simulation system, thereby improving design efficiency. At the same time, the method supports setting parameters such as input data type and input data bit width according to user requirements, and has high flexibility.

Description

Technical Field

[0001] The present application relates to the field of hardware programming, and in particular to a code generation method, a simulation system, an electronic device, and a computer-readable storage medium. Background Art

[0002] In order to verify the rationality of hardware circuit design (or simply design), it is usually necessary to perform simulation experiments on the hardware circuit design. The simulation experiment can be performed through formal verification, virtual simulation or physical simulation.

[0003] Among them, formal verification is a static verification method, which verifies whether the sample to be tested is logically equivalent to the existing credible sample, thereby determining the accuracy of the sample to be tested. However, this method is too dependent on the quality of existing samples, so it is not common in practical applications. Virtual simulation, also known as logic simulation or software simulation, is a verification method based on simulation software that simulates the operation process or scenario of hardware circuit components or systems. Physical simulation requires the verification of the design process and performance in combination with real hardware circuits. In practical applications, a combination of virtual simulation and physical simulation can be used to comprehensively simulate the hardware circuit design to verify the rationality of the hardware circuit design.

[0004] When performing virtual simulation or physical simulation of hardware circuits, the hardware description language (HDL) can be used to describe the structure, function, timing, performance and other characteristics of the hardware circuit. By combining the hardware circuit design with programming languages ​​such as HDL, it is beneficial to test and verify the hardware circuit design. Among them, Verilog HDL (hereinafter referred to as Verilog) is widely used for its flexibility and ability to perform hierarchical design.

[0005] However, traditional simulation systems cannot automatically generate hardware code based on the user's modular design of the hardware circuit, but require the user to write it manually, which affects the simulation efficiency of the hardware circuit design and increases the design cost of the hardware circuit. Summary of the invention

[0006] In view of this, the present application provides a code generation method and related equipment to solve the problem that the related technology cannot automatically generate corresponding hardware code according to the hardware circuit design, improve the simulation efficiency of the hardware circuit design, and reduce the design cost of the hardware circuit.

[0007] In a first aspect, the present application provides a code generation method, which is applied to a simulation system, and the method comprises:

[0008] The simulation system adds a target module for which hardware code is to be generated in the simulation interface. The target module is used to implement data processing based on hardware bit operations. Then, the simulation system receives the type and bit width of input data configured by the user through the property configuration interface of the target module, and generates the input port definition in the hardware code of the target module according to the type and bit width of the input data. Next, the simulation system determines at least one bit operator corresponding to the operation type according to the operation type of the target module, and generates hardware code for operating the input data.

[0009] In this way, the hardware code is automatically generated for the hardware circuit design in the simulation system, which improves the user experience. At the same time, parameters such as input data type and input data bit width can be set according to user needs to meet the needs of different users with high flexibility.

[0010] In some possible implementations, the simulation system can also receive the attributes and bit width of the output data configured by the user through the attribute configuration interface of the target module, and generate hardware code for intercepting or expanding the bit width of the operation result according to the attributes and bit width of the output data. In this way, the simulation system can support the user to configure the format of the output data and output the hardware code according to the format to meet personalized needs, and the method supports intercepting the operation result and reducing unnecessary redundant length.

[0011] In some possible implementations, the simulation system generates hardware code for operating the input data according to at least one bit operator in the following manner: the simulation system generates hardware code for format alignment of the input data based on the type and bit width of the input data, and then generates hardware code for operating the aligned input data according to at least one bit operator.

[0012] Optionally, the format of the aligned input data is a binary format, and the decimal place width of the aligned input data is the maximum value of the decimal place width of the input data. In this way, the input signed data or unsigned data can be uniformly converted into binary data that can be read, stored and calculated by the computing device. At the same time, since there is no intuitive representation of the decimal point in binary data, it is necessary to limit the decimal place width and align it to facilitate subsequent operations on the input data.

[0013] In some possible implementations, the simulation system generates hardware code for operating on the aligned input data according to at least one bit operator in the following manner: the simulation system generates hardware code for expanding the bit width of the aligned input data according to the bit width of the aligned input data and the operation type of the target module, and generates hardware code for operating on the input data with the expanded bit width according to at least one bit operator.

[0014] Since the input data may generate carry after operation, which may cause data overflow, it is necessary to expand the bit width of the input data before operation to avoid overflow of the operation result and cause errors. Due to the different operation types of the target module, the overflow bit width that may be generated after the input data operation is different, so it is necessary to expand the bit width of the input data accordingly for the target modules of different operation types.

[0015] In some possible implementations, before the simulation system expands the aligned input data, it should also supplement the input data with a sign bit according to the type of the input data, that is, the aligned input data should be converted into a complement code form.

[0016] In some possible implementations, the target module is an addition and subtraction module or a gain module. The addition and subtraction module can implement addition or subtraction operations on multiple input data, wherein the subtraction operation of the input data is equivalent to the addition operation of the opposite number of the input data, which is reflected in the computing device as the addition operation of the complement of the opposite number. Since the addition and subtraction module can implement operations on multiple input data, a delay module needs to be added when adding them one by one in sequence to ensure that each operation is in step with each other.

[0017] The gain module performs operations based on an input data and gain data. Specifically, based on the characteristics of binary, the gain data is shifted according to the number of bits and the number of bits with the value "1" in the input data, and the generated multiple shifted data are stored in a register for iterative addition.

[0018] In some possible implementations, when multiple shifted data generated by the gain module are iteratively added, a parallel method can be used to add a clock according to the number of shifted data, so that all shifted data can be added one by one in a non-sequential manner. In this way, the calculation efficiency can be improved and the generated hardware code can be optimized.

[0019] In a second aspect, the present application provides a simulation system, which includes various modules for executing the code generation method in the first aspect or any possible implementation of the first aspect, specifically including:

[0020] The communication module is used to receive the type and bit width of the input data configured by the user through the property configuration interface of the target module;

[0021] The code generation module is used to generate an input port definition in the hardware code of the target module according to the type and bit width of the input data, and to determine at least one bit operator corresponding to the operation type according to the operation type of the target module, and to generate hardware code for operating the input data according to the at least one bit operator.

[0022] In a third aspect, the present application provides an electronic device. The device includes a processor and a memory. The memory is used to store computer instructions; the processor is used to execute the method described in the first aspect of the present application or any possible implementation of the first aspect according to the computer instructions.

[0023] In a fourth aspect, the present application provides a computer-readable medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer device, enables the computer device to execute the method described in the first aspect of the present application or any possible implementation of the first aspect.

[0024] In a fifth aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect of the present application or any possible implementation of the first aspect.

[0025] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A flowchart of a code generation method according to an embodiment of the present application;

[0027] Figure 2A and Figure 2B A schematic diagram of a simulation interface disclosed in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of an addition and subtraction module and its module information attribute configuration page disclosed in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of an attribute configuration interface for inputting data in a target module disclosed in an embodiment of the present application;

[0030] Figure 5 A schematic diagram of an input data structure disclosed in an embodiment of the present application;

[0031] Figure 6 A code schematic diagram disclosed in an embodiment of the present application;

[0032] Figure 7 A code schematic diagram disclosed in an embodiment of the present application;

[0033] Figure 8 A code schematic diagram disclosed in an embodiment of the present application;

[0034] Fig. 9 A code schematic diagram disclosed in an embodiment of the present application;

[0035] Fig.10A code schematic diagram disclosed in an embodiment of the present application;

[0036] Fig.11 A schematic diagram of an attribute configuration interface for output data disclosed in an embodiment of the present application;

[0037] Fig.12 A code schematic diagram disclosed in an embodiment of the present application;

[0038] Fig.13 A schematic diagram of the structure of a simulation system disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0040] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. The terms "first" and "second" in the embodiments of the present application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0041] When performing virtual simulation or physical simulation of hardware circuits, the hardware description language HDL can be used to describe the structure, function, timing, performance and other characteristics of the hardware circuit. By combining the hardware circuit design with programming languages ​​such as HDL, it is beneficial to test and verify the hardware circuit design. Among them, Verilog is widely used for its flexibility and ability to perform hierarchical design. However, most simulation systems cannot automatically generate hardware code, such as Verilog code, based on the user's modular design of the circuit, but require the user to write it manually, which affects the simulation efficiency of the hardware circuit design and increases the design cost of the hardware circuit.

[0042] Based on this, the present application provides a code generation method. The method is applied to a simulation system. Specifically, the simulation system adds a target module for generating hardware code in a simulation interface, and the target module is used to implement data processing based on hardware bit operations, such as an addition and subtraction module or a gain module. Then the simulation system receives the type and bit width of the input data configured by the user through the property configuration interface of the target module, and generates the input port definition in the hardware code of the target module. Then the simulation system determines at least one bit operator corresponding to the operation type according to the operation type of the target module, and generates the hardware code for operating the input data.

[0043] On the one hand, the method realizes the automatic generation of hardware code for the design of modules (such as addition and subtraction modules and gain modules) in the simulation system, improves the simulation efficiency of hardware circuit design, and reduces the design cost of hardware circuits; on the other hand, the method can set parameters such as input data type, input data bit width, and output data bit width according to user needs, meet the needs of different users, and has high flexibility. In addition, the hardware codes in the embodiments of the present application are all written and implemented in sequential logic, which is more in line with the needs of sequential circuits and is conducive to comprehensive rectification for physical simulation.

[0044] It should be noted that the code generation method provided by the present invention can be used in the field of hardware programming. The following is only an example and does not limit the application field of the code generation method provided by the present invention. In addition, the embodiment of the present application may not limit the execution subject of the code generation method. For example, the code generation method of the embodiment of the present application can be applied to computing devices such as terminal devices or servers. Among them, the terminal device can be a smart phone, a computer or a tablet computer. The server can be an independent server, a cluster server or a cloud server. The present application does not specifically limit the terminal device or server mentioned above.

[0045] The method provided in this application is introduced below in conjunction with specific embodiments.

[0046] Figure 1 This is a flow chart of a code generation method disclosed in an embodiment of the present application. The method is applied to a simulation system, and the method includes:

[0047] S102: The simulation system adds a target module to generate hardware code in the simulation interface.

[0048] The target module is a module for implementing data processing based on hardware bit operations. For example, the target module may include at least one of an addition and subtraction module or a gain module.

[0049] The addition and subtraction module is used to perform addition or subtraction mathematical operations or logical operations on input data. Since the subtraction operation of input data is equivalent to adding the opposite number of the input data, the reflection in the computing device is the addition of the complement of its opposite number. Therefore, under normal circumstances, an adder can be used to complete the addition or subtraction operation of input data. For example, the true values ​​of the input data are 3 and 1 respectively. When calculating the difference between the two input data, the sum of 3 and -1 can be calculated by the adder, and the true value of the operation result is 2. Common adders include: Half Adder (HA), Full Adder (FA), Ripple-Carry Adder, Carry-Lookahead Adder, Static CMOS Adder, Mirror Adder, etc.

[0050] The gain module is used to adjust the amplitude of the input data or signal, amplify or attenuate the input data or signal to meet specific simulation requirements. For example, if the true value of the input data is 2 and the true value of the gain data is 1.5, the true value of the operation result is 3. Common gain modules include: operational amplifier (Operational Amplifier, Op-Amp), power amplifier (PowerAmplifier), fixed gain amplifier (Fixed Gain Amplifier), variable gain amplifier (Variable GainAmplifier), etc.

[0051] It should be noted that the gain data of the gain module can be a pre-set and stored gain value, or it can be a gain value set together with the input data, that is, the gain module in the embodiment of the present application can be either a fixed gain module or an adjustable gain module, and the corresponding gain module can be selected according to the actual simulation needs of the user.

[0052] After the user creates a new or opens a saved hardware circuit design file, the simulation system responds to the user's selection of the target module and adds the target module for which the hardware code is to be generated in the simulation system interface. Subsequently, the simulation system responds to the configuration operation of the target module triggered by the user and displays the property configuration interface. The user can configure the properties and parameters of the target module based on this. When the user selects two or more target modules, the connection method between the modules can also be set to achieve more functions. After completing the hardware circuit design, the simulation system can support the user to implement the hardware code generation function, generate the corresponding hardware code according to the existing hardware circuit design, and display the code generation interface. In addition, the simulation system also supports users to perform virtual simulation on existing module designs to obtain running results.

[0053] refer to Figure 2A and Figure 2B A schematic diagram of a simulation interface in an embodiment of the present application.

[0054] The simulation interface 200 includes a menu bar 202 , a model library 204 and a system page 206 , wherein the menu bar 202 may include operation options for hardware circuit design, and the toolbar 204 may include basic modules 2042 , basic operations 2044 , basic functions 2046 , and the like.

[0055] The user enters the simulation interface 200, selects the menu bar 202 to create or open a saved hardware circuit design file, and displays the system page 206. The user can select a corresponding module in the model library 204, such as an addition and subtraction module or a gain module in the basic operation 2044, and add it to the system page 206 by clicking or dragging the mouse, and complete the design of the hardware circuit by setting parameters and setting connection methods.

[0056] In some possible implementations, the user can run the "Code Generation" option in menu bar 202 to generate corresponding hardware code based on the existing hardware circuit design, which is conducive to combining with physical simulation. It should be noted that the generated hardware code can be used for the simulation of this simulation system, and can also be output to other Field Programmable Gate Array (FPGA) platforms for use, without being restricted by the platform chip model, and has high versatility.

[0057] In addition, the user can run the "Start" option in the menu bar 202 to perform virtual simulation on the existing module design to obtain the running results, and can also stop and clear the simulation process by running the "Reset" option in the menu bar 202. It should be noted that the above-mentioned code generation function does not depend on this virtual simulation function, that is, the user can directly choose to generate the corresponding code after completing the design of the hardware circuit.

[0058] In some possible implementations, the addition and subtraction modules can implement operations on multiple input data, and the user can set the input terminals of the addition and subtraction modules when adding the addition and subtraction modules. Figure 3 Shown is a schematic diagram of an addition and subtraction module and its module information attribute configuration page disclosed in an embodiment of the present application. Figure 3 The addition and subtraction module shown is a three-input addition and subtraction module, in which the specific operation logic is the first input data plus the second input data minus the third input data. The user can enter the corresponding operation logic relationship in the module information attribute configuration page, so that the module can modify the number of input ports and the operation logic relationship accordingly.

[0059] S104: The simulation system receives the type and bit width of the input data configured by the user through the property configuration interface of the target module.

[0060] In response to the user's operation on the property configuration interface of the target module, the simulation system receives the type and bit width of the input data configured by the user through the property configuration interface of the target module.

[0061] In some possible implementations, the simulation system may present a property configuration interface to the user in response to a configuration operation triggered by the user on the target module, and then receive the type and bit width of input data configured by the user through the property configuration interface of the target module.

[0062] refer to Figure 4 The present invention is a schematic diagram of a property configuration interface for input data in a target module. The signal property source represents the source property of the input data. The input data in the embodiment of the present application can be either customized or pre-stored data. The data type option can configure the type and bit width of the input data. For example, the data type options may include: int8, uint8, int16, uint16, int32, uint32, etc. Among them, "int" in int8 represents that the input data is a signed integer, and "8" represents that the bit width of the input data is 8 bits.

[0063] like Figure 5 As shown in the upper part, the input data width is 8 bits, of which the first bit is the sign bit, "0" represents the data is a positive number, and "1" represents the data is a negative number. The data range of the input data of the data type int8 is [-255, 255]. Figure 5 As shown in the upper part, the first bit of the data is the sign bit, the integer bits are 4, and the remaining bits are automatically filled with zeros during calculation. The decimal true value of the data is 11.

[0064] Figure 4 When selecting fixed-point calculation, you also need to select the calibration value of the input data. Since there is no intuitive representation of decimal points in binary data, it is necessary to limit the decimal width of the input data to facilitate accurate representation of the input data. The calibration value is the decimal width of the defined input data, which is equivalent to adding a fixed point to the input data.

[0065] like Figure 5 As shown in the lower part, the first bit of the data is the sign bit, the integer bit is 4, and the decimal bit is 1. At this time, the decimal true value of the data is 5.5.

[0066] S106: The simulation system generates an input port definition in the hardware code of the target module according to the type and bit width of the input data.

[0067] Hardware code is a code that describes the structure, function, timing, performance and other characteristics of a hardware circuit. It is written in a hardware description language, such as Verilog or VHDL. Input ports usually refer to interfaces on a hardware device or circuit board that are used to receive external signals or data. These interfaces can be physical jacks, connectors, or logical signal pins that are used to receive information from external devices, sensors, or other systems. Input ports usually require the definition of port type, access standards, and how input data is processed.

[0068] The simulation system can automatically generate the input port definition in the corresponding hardware code according to the type and bit width of the input data. For example, when the input data is a signed number, the generated input port definition code can be: inputsigned[IN_TOTAL_LEN-1:0]in; when the input data is an unsigned number, the generated input port definition code can be: input[IN_TOTAL_LEN-1:0]in. Among them, IN_TOTAL_LEN is the input data bit width, which is filled with a specific value according to the above input data attribute configuration.

[0069] S108: The simulation system determines at least one corresponding bit operator according to the operation type of the target module, and generates hardware code for operating the input data according to the at least one bit operator.

[0070] Bitwise operators are operators used to operate data variables, including AND operator, OR operator, XOR operator, negation operator, shift operator, etc.

[0071] In some possible implementations, the simulation system may generate hardware code for format alignment of the input data based on the type and bit width of the input data, and then generate hardware code for operating the aligned input data based on at least one bit operator.

[0072] Optionally, the format of the aligned input data is a binary format, and the decimal place width of the aligned input data is the maximum value of the decimal place width of the input data. In this way, the input signed data or unsigned data can be uniformly converted into binary data that can be read, stored and operated by the computing device. At the same time, by aligning the decimal place width of the input data, it is convenient to perform subsequent operations on the input data.

[0073] Figure 6A code schematic diagram generated for an embodiment of the present application. Among them, always@(posedge clk) indicates that its internal logic is executed when triggered by the rising edge of the clock signal clk. reset is used for reset operation. i_valid is used to indicate the validity of the input data and to indicate whether the input data is shifted. r_in1_fraction_cast represents a register storing in1 and moving the value of in1 to a suitable position through a shift operation. IN_FRACTION_MAX-IN1_FRACTION_LEN is used to determine the number of bits in1 is moved. Similar operations are taken for in2 and possibly in3.

[0074] It should be noted that the type and bit width of the input data have been set in step S104, but the type and bit width of each input data are not necessarily the same. For example, the two input data are respectively uint8 data type, calibration value 1, and the first input data of decimal true value 5.5 and int8 data type, calibration value 2, and the second input data of decimal true value -1.25, and an addition operation is performed between the two. At this time, the above two data are formatted and aligned, and the two data need to be converted into binary form first. At this time, the decimal digits of the first input data are 1 bit and the integer digits are 3 bits; the decimal digits of the second input data are 2 bits and the integer digits are 1 bit. Next, the decimal digit width of the input data is aligned. Specifically, the maximum decimal digit width of the input data is selected as the decimal digit width of the aligned input data. For the above-mentioned first input data and second input data, the decimal digit width of the second input data is selected as the decimal digit width of the aligned input data. The aligned first input data is represented as "in1=10110", and the second input data is represented as "in2=1011". At this time, the decimal place widths of the two are aligned, both of which are two digits.

[0075] In some possible implementations, the simulation system may generate hardware code for expanding the bit width of the aligned input data based on the bit width of the aligned input data and the operation type of the target module, and then generate hardware code for operating on the input data after the bit width expansion based on at least one bit operator.

[0076] Since the input data may generate carry after operation, which may cause data overflow, it is necessary to expand the bit width of the input data before operation to avoid overflow of the operation result and cause errors. Due to the different operation types of the target module, the overflow bit width that may be generated after the input data operation is different, so it is necessary to expand the bit width of the input data accordingly for the target modules of different operation types.

[0077] In some possible implementations, before the aligned input data is expanded, a sign bit should be added to the input data according to the type of the input data, that is, the aligned input data should be converted into a complement code form.

[0078] In some possible implementations, for the addition and subtraction modules, the bit width of the input data that needs to be expanded can be determined as follows:

[0079] AUTO_OUT_LEN=IN_FRACTION_MAX+IN_INT_MAX+(IN_COUNT>>1+IN_COUNT%2)+1

[0080] Figure 7 A code diagram generated for an embodiment of the present application. Among them, AUTO_OUT_LEN is the data width required when no overflow occurs after addition and subtraction operations; IN_FRACTION_MAX is the maximum value of the decimal width of the input data, that is, the decimal width of the input data after format alignment; IN_INT_MAX is the maximum value of the integer width of the input data; IN_COUNT is the number of input data, where the right shift calculation value and the modulo 2 remainder are taken; and the 1-bit sign bit is calculated. The decimal width of the expanded data remains unchanged.

[0081] For example, for the above two input data, the maximum value of the decimal bit width of the input data is 2, the maximum value of the integer bit width of the input data is 3, the number of input data is 2, and the sign bit is 1. According to the formula, the input data needs to be expanded to 7 bits, of which the sign bit is 1, the decimal bit is 2, and the integer bit is 4. According to the complement rule, the first input data is represented as "in1 = 0010110", and the second input data is represented as "in2 = 1111011".

[0082] According to the binary addition rule, the first input data and the second input data are added, and the result is taken from the lower bit to determine the number of extended bits, that is, 7 bits, and the overflow part is discarded. At this time, the result "sum = 0010001" is obtained, in which the sign bit is 1 bit, the decimal bit is 2 bits, and the integer bit is 4 bits. Its decimal true value is 4.25.

[0083] In some possible implementations, since the subtraction operation of input data is equivalent to the addition operation of the opposite number of the input data, which is reflected in the computing device as the addition operation of the complement of its opposite number, the addition or subtraction operation of input data can usually be completed using only an adder.

[0084] Figure 8A code diagram generated for an embodiment of the present application. IN2_SYMBOL represents the operator before the input data in2. Its specific value is: when IN2_SYMBOL = 0, it means that the operator before in2 is a plus sign; when IN2_SYMBOL = 1, it means that the operator before in2 is a minus sign. r_in2_int_cast stores in2, and r_in2_complement stores the complement form of in2. When IN2_SYMBOL = 1 and the operator before in2 is a minus sign, the data in r_in2_int_cast is inverted and added by 1, and assigned to r_in2_complement to obtain the complement form of in2.

[0085] In addition, since the addition and subtraction modules can realize operations on multiple input data, a delay module, such as at least one shift operator, needs to be added when performing sequential addition one by one to ensure that each operation is in step with each other.

[0086] Fig. 9 A code diagram generated for an embodiment of the present application. Wherein, delay is a delay module, and add_cell is a two-input accumulator with consistent data format. When in3 exists, the result of adding in1 and in2 is added to in3 to obtain the result of adding the three input data.

[0087] In some possible implementations, for the gain module, the number of input data involved in the calculation is 2, one of which is used as gain data. The bit width of the input data that needs to be expanded can be determined as follows:

[0088] The extended bit width is the nearest integer power of 2 not less than AUTO_OUT_LEN, where AUTO_OUT_LEN = (IN_FRACTION_MAX + IN_INT_MAX + 1) × 2. IN_FRACTION_MAX is the maximum value of the input data decimal bit width, that is, the input data decimal bit width after format alignment; IN_INT_MAX is the maximum value of the input data integer bit width; and 1 sign bit.

[0089] For example, the decimal true value of the existing third input data is 4.5, and the decimal true value of the fourth input data is -1.25. The fourth input data is used as gain data. After the input data is aligned in the above format and the decimal bit width is aligned, the third input data is expressed as "in3 = 010010", where the sign bit is 1, the decimal bit is 2, and the integer bit is 3; the fourth input data is expressed as "in4 = 1011", where the sign bit is 1, the decimal bit is 2, and the integer bit is 1. According to the bit width expansion formula, AUTO_OUT_LEN = 12 is obtained, and the extended bit width is 16 bits. Then the expanded third input data is expressed as "in3 = 0000000000010010", and the expanded fourth input data is expressed as "in4 = 1111111111111011", where the sign bit is 1, the decimal bit is 2, and the integer bit is 13.

[0090] According to the law of binary operation, the gain operation is performed by shifting and adding. Specifically, according to the number of bits and the number of "1" in the input data, the gain data is shifted, and the generated multiple shifted data are stored in a register for iterative addition.

[0091] Fig.10 A code schematic diagram generated for an embodiment of the present application. The first half of the code performs a shift operation. According to the value of each element in the r_in1_cast array, the result of r_in2_cast shifted left by i bits or the integer zero is selectively stored in the corresponding position in the r_mult_shift_tmp array. The second half of the code performs an iterative addition operation, adding the values ​​of two adjacent elements in the r_mult_shift_tmp array, and storing the result in r_mult_add_tmp1[i]. The number of times the iterative addition is performed is determined according to the number of gain data after the specific shift.

[0092] For example, the fourth input data is used as gain data, and the fourth input data is shifted and added according to the number of bits and the number of bits with the value "1" in the third data, to obtain 16 shifted data. Including: the two shifted values ​​obtained according to the number of bits and the number of bits with the value "1" in the third data are "1111111111110110" shifted left by 1 bit, "11111111110110000" shifted left by 4 bits, and the remaining 12 values ​​are 0. The above 16 data are iteratively added, and the overflow bit is discarded to obtain the operation result of "11111111110100110". Among them, the sign bit is 1 bit, the decimal bit is twice the width of the decimal bit aligned before the operation, that is, 4 bits, and the integer bit is 11 bits, and its decimal true value is -5.625.

[0093] In some possible implementations, when multiple shifted data generated by the gain module are iteratively added, a parallel method can be used to add a clock according to the number of shifted data, so that all shifted data can be added one by one in a non-sequential manner. In this way, the calculation efficiency can be improved and the generated hardware code can be optimized.

[0094] In some possible implementations, the simulation system can also respond to user operations, receive the attributes and bit width of the output data configured by the user through the attribute configuration interface of the target module, generate hardware code for intercepting or expanding the bit width of the calculation results based on the attributes and bit width of the output data, and display the code generation interface.

[0095] See also Fig.11 A schematic diagram of an output data attribute configuration interface is shown. In some possible implementations, the simulation system can also receive the attributes and bit width of the output data configured by the user through the attribute configuration interface of the target module, and generate hardware code for intercepting or expanding the bit width of the operation result according to the attributes and bit width of the output data. Among them, the data type option can configure the type and bit width of the input data, for example, the data type option can include: int8, uint8, int16, uint16, int32, uint32, etc.

[0096] The following method can be used to truncate the calculation result: when the integer part needs to be truncated, the sign bit remains unchanged, and the integer part truncates the corresponding number of digits from low to high; when the decimal part needs to be truncated, the decimal part truncates the corresponding number of digits from high to low; finally, the truncated integer digits and decimal digits are concatenated to obtain the truncated calculation result. It should be noted that the truncated calculation result may be different from the original true value, causing errors, but when the calculation accuracy is low, this method can minimize data redundancy and improve storage efficiency.

[0097] Fig.12 A code schematic diagram generated for an embodiment of the present application. The simulation system determines the corresponding bit width limit according to the integer bit width and decimal bit width of the output data. Then, according to the bit width limit and the integer bit width and decimal bit width of the operation result, the different processing of the integer part and the decimal part is determined. Among them, according to different processing requirements, it is divided into four situations: integer part expansion, decimal part expansion; integer part expansion, decimal part truncation; integer part truncation, decimal part expansion; integer part truncation, decimal part expansion.

[0098] In some possible implementations, the simulation system can also generate hardware code for displaying the output data according to the attributes and bit width of the output data. For example, the displayed data can be converted into decimal to facilitate the user's intuitive experience. In this way, the user can flexibly choose the display form of the output data to meet the personalized needs of different users.

[0099] Based on the above description, the embodiment of the present application provides a code generation method, which, on the one hand, realizes the automatic generation of hardware code for the design of hardware circuit modules (such as addition and subtraction modules and gain modules) in the simulation system, improves the simulation efficiency of hardware circuit design, and reduces the design cost of hardware circuits; on the other hand, parameters such as input data type, input data bit width, and output data bit width can be set according to user needs to meet the needs of different users, with high flexibility. In addition, the hardware codes in the embodiments of the present application are all written and implemented in sequential logic, which is more in line with the needs of sequential circuits and is conducive to comprehensive rectification for physical simulation.

[0100] The present application also provides a code generation device. The device of the present application is described in detail below in conjunction with the accompanying drawings.

[0101] See also Fig.13 The schematic diagram of the structure of a code generating device shown in FIG. 1 , the code generating device 1300 may include:

[0102] The communication module 1301 is used to receive the type and bit width of input data configured by the user through the property configuration interface of the target module;

[0103] The code generation module 1302 is used to generate an input port definition in the hardware code of the target module according to the type and bit width of the input data, and to determine at least one bit operator corresponding to the operation type according to the operation type of the target module, and to generate hardware code for operating the input data according to the at least one bit operator.

[0104] In some possible implementations, the communication module 1301 is further configured to:

[0105] The properties and bit width of the output data configured by the user through the property configuration interface of the target module are received, so that the code generation module 1302 generates hardware code for intercepting or extending the bit width of the operation result according to the properties and bit width of the output data. In this way, the user can flexibly select the form of the output data and reduce unnecessary redundant length.

[0106] In some possible implementations, the communication module 1301 is further configured to:

[0107] In response to the configuration operation triggered by the user on the target module, the code generation apparatus 1300 presents a property configuration interface to the user and receives the type and bit width of the input data configured by the user through the property configuration interface of the target module.

[0108] In some possible implementations, the communication module 1301 is further configured to:

[0109] The attributes and bit width of the output data configured by the user through the attribute configuration interface of the target module are received, so that the code generation module 1302 generates hardware code for intercepting or extending the bit width of the operation result according to the attributes and bit width of the output data.

[0110] In some possible implementations, the code generation module 1302 is used to:

[0111] Based on the type and bit width of the input data, a hardware code for format alignment of the input data is generated, and based on at least one bit operator, a hardware code for operating the aligned input data is generated.

[0112] Optionally, the format of the aligned input data is a two's complement format, and the decimal place width of the aligned input data is the maximum value of the decimal place width of the input data. In this way, the input signed data or unsigned data can be uniformly converted into binary data that can be read, stored and calculated by the computing device, usually in a two's complement format. At the same time, since there is no intuitive representation of the decimal point in binary data, it is necessary to limit the decimal place width and align it to facilitate subsequent operations on the input data.

[0113] In some possible implementations, the code generation module 1302 is used to:

[0114] According to the bit width of the aligned input data and the operation type of the target module, a hardware code for extending the bit width of the aligned input data is generated, and according to at least one bit operator, a hardware code for operating the input data after the bit width extension is generated.

[0115] Since the input data may generate carry after operation, which may cause data overflow, it is necessary to expand the bit width of the input data before operation to avoid overflow of the operation result and cause errors. Due to the different operation types of the target module, the overflow bit width that may be generated after the input data operation is different, so it is necessary to expand the bit width of the input data accordingly for the target modules of different operation types.

[0116] In some possible implementations, the code generation module 1302 is further used to:

[0117] According to the attributes and bit width of the output data, hardware code is generated to intercept or expand the bit width of the operation result. It should be noted that the intercepted operation result may be different from the original true value, causing errors, but when the calculation accuracy is low, this method can minimize data redundancy and improve storage efficiency.

[0118] In some possible implementations, the code generation module 1302 is further used to:

[0119] According to the attributes and bit width of the output data, the hardware code for displaying the output data is generated. In this way, the user can flexibly choose the display form of the output data to meet the personalized needs of different users.

[0120] The modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple virtual modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0121] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0122] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the part of the technical solution of the present application that essentially contributes or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the process of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

[0123] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A code generation method, characterized in that: Applied to a simulation system, the method comprises: Add the target module to generate the hardware code in the simulation interface, where the target module is used to implement data processing based on hardware bit operations; Receiving the type and bit width of the input data of the target module configured by the user through the property configuration interface of the target module; Generating an input port definition in the hardware code of the target module according to the type and bit width of the input data; According to the operation type of the target module, determining at least one bit operator corresponding to the operation type; Based on the type and bit width of the input data, generate hardware code for format alignment of the input data; Generate hardware code for extending the bit width of the aligned input data according to the bit width of the aligned input data and the operation type of the target module; According to the at least one bit operator, a hardware code for operating the input data after the bit width is expanded is generated.

2. The method according to claim 1, characterized in that The method further comprises: Receiving the attributes and bit width of the output data of the target module configured by the user through the attribute configuration interface of the target module; According to the attributes and bit width of the output data, a hardware code for intercepting or expanding the bit width of the operation result is generated.

3. The method according to claim 1, characterized in that The format of the aligned input data is a complement format, and the decimal place width of the aligned input data is the maximum value of the decimal place width of the input data.

4. The method according to any one of claims 1 to 3, characterized in that The target module is an addition and subtraction module or a gain module.

5. The method according to any one of claims 1 to 3, characterized in that The receiving the type and bit width of the input data of the target module configured by the user through the property configuration interface of the target module also includes: In response to a configuration operation triggered by the user on the target module, presenting a property configuration interface to the user; The type and bit width of the input data of the target module configured by the user through the property configuration interface of the target module are received.

6. A simulation system, characterized in that: The simulation system comprises: A communication module, used for receiving the type and bit width of input data of the target module configured by the user through the property configuration interface of the target module; A code generation module, configured to generate an input port definition in the hardware code of the target module according to the type and bit width of the input data, and to determine at least one bit operator corresponding to the operation type according to the operation type of the target module; The code generation module is also used to generate hardware code for format alignment of the input data based on the type and bit width of the input data; generate hardware code for bit width expansion of the aligned input data according to the bit width of the aligned input data and the operation type of the target module; and generate hardware code for operating on the input data after bit width expansion according to the at least one bit operator.

7. An electronic device, characterized in that: The electronic device comprises: Memory for storing computer programs or computer instructions; A processor, configured to execute a computer program or computer instruction stored in the memory, so that the electronic device executes the method as claimed in any one of claims 1 to 5.

8. A computer storage medium, characterized in that: The computer storage medium is used to store a computer program, and when the computer program is executed, it is used to implement the method according to any one of claims 1 to 5.

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