SOC Android system fast startup method, equipment, system, device and medium

Abstract

This application discloses a method, device, system, apparatus, and medium for quickly booting a SOC Android system. The method includes: obtaining a CMD instruction sent by a host; the CMD instruction includes a first sub-instruction, a second sub-instruction, and a read data instruction; the first sub-instruction, the second sub-instruction, and the read data instruction are instructions sent sequentially; upon receiving the first sub-instruction, initializing a first memory area of an eMMC; upon receiving the second sub-instruction, reading data of a preset memory capacity from nandFlash and storing it in the SRAM of the eMMC, so that the host reads the data from the SRAM via the read data instruction, and initializing the second memory area of the eMMC after the host reads the data. This application can be widely applied in the field of semiconductor technology.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method, device, system, apparatus and storage medium for quickly starting a SOC Android system. Background Art

[0002] Many current OTT and TV products' CPU controllers, often referred to as APs or SoCs, lack the boot functionality of eMMC. This results in Android boot times being approximately 1-2 seconds slower than with BOOT functionality. This BOOT functionality resides in the SoC's hardware BROM code and cannot be modified via software. Therefore, to address the issue of SoCs lacking boot support while still requiring faster boot times, related technologies have proposed optimizing the eMMC firmware.

[0003] However, the aforementioned method in the related art requires the standard eMMC protocol. This standard eMMC protocol must be implemented by modifying the host's command requirements. This results in older SoCs (systems on a chip) not supporting this function, which in turn increases boot time. Furthermore, the aforementioned method cannot modify the hardware to support SoCs that do not support this function, reducing its practicality. Therefore, there are still technical issues that need to be addressed in the related art. Summary of the Invention

[0004] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0005] To this end, one purpose of the embodiments of the present application is to provide a SOC Android system fast startup method, equipment, system, device and storage medium, which can reduce the startup time and improve product practicality.

[0006] In order to achieve the above-mentioned technical objectives, the technical solutions adopted in the embodiments of the present application include: a SOC Android system quick startup method, comprising the following steps: obtaining a CMD instruction sent by a host; the CMD instruction includes a first sub-instruction, a second sub-instruction and a read data instruction; the first sub-instruction, the second sub-instruction and the read data instruction are instructions sent successively in sequence; when the first sub-instruction is received, the first memory area of the eMMC is initialized; when the second sub-instruction is received, data of a preset memory capacity is read from nandFlash and stored in the Sram of the eMMC, so that the host reads data from the Sram through the read data instruction, and after the host reads the data, the second memory area of the eMMC is initialized.

[0007] In addition, the SOC Android system fast startup method according to the above embodiment of the present invention may also have the following additional technical features:

[0008] Furthermore, in an embodiment of the present application, the first memory area is the first 100MB memory area in the eMMC memory.

[0009] Furthermore, in an embodiment of the present application, the preset memory capacity is 290KB-350KB.

[0010] Furthermore, in an embodiment of the present application, the first sub-instruction includes several handshake instructions.

[0011] Furthermore, in an embodiment of the present application, the number of the several handshake instructions is greater than or equal to 3.

[0012] Furthermore, in an embodiment of the present application, the number of the data read instructions is greater than or equal to 3.

[0013] On the other hand, an embodiment of the present application also provides an integrated circuit system, which is started using the SOC Android system fast startup method described above.

[0014] On the other hand, an embodiment of the present application further provides a SOC Android system fast boot device, comprising:

[0015] an acquiring unit, configured to acquire a CMD instruction sent by a host; the CMD instruction includes a first sub-instruction, a second sub-instruction, and a read data instruction; the first sub-instruction, the second sub-instruction, and the read data instruction are instructions sent sequentially;

[0016] A first processing unit, configured to initialize a first memory area of the eMMC upon receiving the first sub-instruction;

[0017] The second processing unit is used to read data of a preset memory capacity from nandFlash and store it in the SRAM of the eMMC when receiving the second sub-instruction, so that the host reads data from the SRAM through the read data instruction, and initializes the second memory area of the eMMC after the host reads the data.

[0018] On the other hand, the present application also provides a SOC Android system fast startup device, comprising:

[0019] at least one processor;

[0020] at least one memory for storing at least one program;

[0021] When the at least one program is executed by the at least one processor, the at least one processor implements the SOC Android system fast startup method as described in any one of the invention contents.

[0022] In addition, the present application also provides a computer-readable storage medium, which stores processor-executable instructions. When the processor-executable instructions are executed by the processor, they are used to execute the SOC Android system fast startup method as described in any one of the above items.

[0023] The advantages and benefits of this application will be partially given in the following description, and partially become apparent from the following description, or learned through practice of this application:

[0024] The present application can obtain the first sub-command, the second sub-command, and the read data command that are sent sequentially, and simultaneously initialize the two eMMC areas according to the different commands. In the gap between the initialization of the two areas, the data of the preset memory capacity read from the nandFlash is stored in the SRAM of the eMMC so that the host can read the data from the SRAM via the read data command. The present application does not require modifying the command requirements of the host, and can quickly initialize the system. The present application can improve the defect of long system startup time and improve the practicality of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the standard protocol for supporting Boot on eMMC5.1 in the prior art;

[0026] Figure 2 A schematic diagram of the steps of a SOC Android system quick startup method in a specific embodiment of the present invention;

[0027] Figure 3 This is a flow chart of a method for quickly starting a SOC Android system in the prior art;

[0028] Figure 4 A schematic diagram of the steps of a method for quickly starting a SOC Android system in another specific embodiment of the present invention;

[0029] Figure 5 This is a structural diagram of an Android system quick startup device of a SOC in a specific embodiment of the present invention;

[0030] Figure 6 This is a structural diagram of an Android system quick startup device of a SOC in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following describes in detail the embodiments of the present invention with reference to the accompanying drawings to illustrate the principles and processes of the SOC Android system fast startup method, equipment, system, device and storage medium in the embodiments of the present invention.

[0032] The following are necessary explanations of the nouns that appear in this application:

[0033] First, the technical defects of the relevant technologies are explained:

[0034] In related technologies, such as Figure 1 As shown, many SoC products' eMMC5.1 supports Boot. This method can accelerate SoC product startup by modifying host command requirements. Boot works by modifying the Brom hardware code in the host and using Boot, thereby accelerating SoC product initialization.

[0035] While many SoCs now support boot-up, not all do. Some manufacturers' SoCs still lack support, and code modifications are impossible to implement. This results in longer boot times for SoC products. This time discrepancy between the host hardware and the product hardware is unfixable. Furthermore, supporting this feature in existing SoCs requires the host to modify command requirements, which is risky and difficult to modify, reducing the practicality and adaptability of existing SoC products.

[0036] In order to solve the above technical problems, refer to Figure 2 The present application provides a method for quickly starting a SOC Android system. The method for quickly starting a SOC Android system may include steps S101 to S103.

[0037] S101, obtaining a CMD instruction sent by a host; the CMD instruction includes a first sub-instruction, a second sub-instruction, and a read data instruction; the first sub-instruction, the second sub-instruction, and the read data instruction are instructions sent sequentially.

[0038] S102. When the first sub-command is received, initialize the first memory area of the eMMC.

[0039] S103. When the second sub-instruction is received, data of the preset memory capacity is read from nandFlash and stored in the Sram of the eMMC, so that the host reads the data from the Sram through the read data instruction, and after the host reads the data, the second memory area of the eMMC is initialized.

[0040] In some feasible embodiments of the present application, the processor in the eMMC can obtain a CMD instruction sent by the host. The CMD instruction may include a first sub-instruction, a second sub-instruction, and a read data instruction. The first sub-instruction, the second sub-instruction, and the read data instruction are instructions sent in sequence. After obtaining the CMD instruction, when the first sub-instruction is received, the processor in the eMMC can initialize the first memory area of the eMMC; when the second sub-instruction is received, the processor in the eMMC can read data of a preset memory capacity from nandFlash and store it in the Sram of the eMMC, so that the host reads data from the Sram through the read data instruction, and after the host reads the data, the processor in the eMMC can initialize the second memory area of the eMMC.

[0041] In summary, the present application can obtain the first sub-command, the second sub-command, and the read data command that are sent sequentially, and simultaneously initialize the two eMMC areas according to the different commands. In the gap between the initialization of the two areas, the data of the preset memory capacity read from the nandFlash is stored in the eMMC's SRAM so that the host can read the data from the SRAM via the read data command. The present application does not require modifying the host's command requirements, and can quickly initialize the system. This application can improve the system's long startup time and enhance the system's practicality.

[0042] Furthermore, in an embodiment of the present application, the first memory area is the first 100MB memory area in the eMMC memory.

[0043] Furthermore, in an embodiment of the present application, the preset memory capacity may be 290KB-350KB.

[0044] Furthermore, in an embodiment of the present application, the first sub-instruction may include several handshake instructions.

[0045] Furthermore, in the embodiment of the present application, the number of the handshake instructions may be greater than or equal to 3. 3 or more handshake instructions can enable the host and the eMMC to smoothly perform data transmission.

[0046] Furthermore, in the embodiment of the present application, the number of read data instructions may be greater than or equal to 3. 3 or more read data instructions can enable the host to smoothly read data from the eMMC.

[0047] The specific implementation principle of this application is described below with reference to the accompanying drawings:

[0048] The current method is as follows Figure 3 :

[0049] Traditional eMMC is managed by a flash transfer layer: flash transfer layer.

[0050] For example: the eMMC is 8100MB. During the startup process of the eMMC, the host sends the HwReset signal and then starts to send command C0, several handshake instructions C1 and instructions C1 to C7.

[0051] While the host is sending command C1, the eMMC internally rebuilds the flash translation layer. This rebuild is affected by several factors, including the power failure prior to the boot and the eMMC's internal data ECC limitations. This typically takes 500ms to 1000ms for OTT and TV products. After this operation is complete, the host begins reading data from the eMMC using command C17. When sending command C17, the eMMC reads data from nand flash and then sends it to the host. Each C17 cycle takes 800µs. Repeated C17 commands require data to be read from nand flash, increasing boot time.

[0052] In view of these shortcomings, this embodiment proposes an improved method. Figure 4 , the method may include:

[0053] 1. Two sets of flash translation layers are configured in the eMMC. The first 100MB of eMMC memory is flash translation layer 1, and the subsequent 8000MB of eMMC memory is flash translation layer 2.

[0054] 2. When the host initializes the eMMC, the eMMC first initializes the Flash Translation Layer 1, which is the first 100MB of data. For the Android system, the first 100MB of data is a read-only area and there is no power failure. Therefore, the time of the Flash Translation Layer 1 is fixed at about 100ms.

[0055] 3. During the process of instructions C2~C7 after the host sends instruction C1, the eMMC reads 300KB of data from nandFlash to the SRAM of the eMMC in advance.

[0056] 4. When the host reads data from SRAM through the read data instruction C17, the eMMC does not need to read data from nandflash.

[0057] 5. After the host completes data reading, the eMMC completes the initialization of the flash translation layer 2, which is 8000MB of eMMC memory.

[0058] In summary, the SOC Android system fast startup method of this application has the following advantages:

[0059] 1. This application does not modify the host's commands. Instead, it modifies the eMMC firmware, which initializes the eMMC memory into two firmwares: one for the first 100MB of data and one for the last 8000MB of data. Even if the host does not support Boot, this can speed up the boot time by about one second. Compared to modifying the SoC hardware, this application is easier to modify the eMMC firmware.

[0060] 2. This application modifies the eMMC firmware so that it can adapt to more SOCs that do not support boot.

[0061] In addition, refer to Figure 5 ,and Figure 2 Corresponding to the method, an embodiment of the present application also provides an Android system fast boot device for SOC. The device may include: an acquisition unit 1001, a first processing unit 1002 and a second processing unit 1003. The acquisition unit 1001 can be used to obtain a CMD instruction sent by the host; the CMD instruction includes a first sub-instruction, a second sub-instruction and a read data instruction; the first sub-instruction, the second sub-instruction and the read data instruction are instructions sent in sequence; the first processing unit 1002 can be used to initialize the first memory area of the eMMC when receiving the first sub-instruction; the second processing unit 1003 can be used to read data of a preset memory capacity from the nandFlash and store it in the Sram of the eMMC when receiving the second sub-instruction, so that the host can read data from the Sram through the read data instruction, and initialize the second memory area of the eMMC after the host reads the data.

[0062] It should be noted that the acquisition unit can be any integrated circuit unit or microprocessor unit obtained by integrating a chip having processing functions and its peripheral circuits using existing integration technology. The first processing unit and the second processing unit can also be any integrated circuit module or microprocessor module obtained by integrating a chip having processing functions and its peripheral circuits using existing integration technology. The first processing unit and the second processing unit can also include one or more memories. One or more memories can be used to store the specific algorithm for fast startup in this application.

[0063] The specific device connection method and device configuration of the acquisition unit 1001 and the first processing unit 1002, and the first processing unit 1002 and the second processing unit 1003 are not limited.

[0064] It should be noted that the contents of the above-mentioned SOC Android system fast startup method embodiment are all applicable to the Android system fast startup system embodiment of this SOC. The functions specifically implemented by the Android system fast startup system embodiment of this SOC are the same as those of the above-mentioned SOC Android system fast startup method embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned SOC Android system fast startup method embodiment.

[0065] On the other hand, an embodiment of the present application also provides an integrated circuit system, which is started using the SOC Android system fast startup method described above.

[0066] and Figure 2 Corresponding to the method, the embodiment of the present application also provides a SOC Android system fast startup device, the specific structure of which can be referred to Figure 6 ,include:

[0067] at least one processor 1011;

[0068] at least one memory 1012, configured to store at least one program;

[0069] When the at least one program is executed by the at least one processor, the at least one processor implements the SOC Android system fast startup method.

[0070] The contents of the above method embodiments are all applicable to the present device embodiments. The functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0071] and Figure 2 Corresponding to the method, an embodiment of the present application further provides a computer-readable storage medium, which stores processor-executable instructions, and the processor-executable instructions are used to execute the SOC Android system fast startup method when executed by the processor.

[0072] The contents of the above-mentioned SOC Android system fast startup method embodiment are all applicable to the present storage medium embodiment. The functions specifically implemented by the present storage medium embodiment are the same as those of the above-mentioned SOC Android system fast startup method embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned SOC Android system fast startup method embodiment.

[0073] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiments presented and described in the flow chart of the present application are provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operations and logical flows presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0074] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present application. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the routine skills of an engineer. Therefore, a person skilled in the art can implement the present application as set forth in the claims using ordinary techniques without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the appended claims and their equivalents.

[0075] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several programs for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program code.

[0076] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable programs for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, a program execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can retrieve and execute a program from a program execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, a program execution system, apparatus, or device.

[0077] More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting, or processing it in another suitable manner as necessary, and then storing it in a computer memory.

[0078] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having logic gate circuits for implementing logical functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0079] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples.

[0080] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0081] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A SOC Android system quick startup method, characterized in that: The following steps are involved: Obtain a CMD instruction sent by a host; the CMD instruction includes a first sub-instruction, a second sub-instruction, and a read data instruction; the first sub-instruction, the second sub-instruction, and the read data instruction are instructions sent sequentially; When the first sub-instruction is received, initializing the first memory area of the eMMC; When the second sub-instruction is received, data of the preset memory capacity is read from nandFlash and stored in the Sram of the eMMC, so that the host reads data from the Sram through the read data instruction, and after the host reads the data, the second memory area of the eMMC is initialized; the first memory area is the first 100MB memory area in the flash translation layer of the eMMC; the second memory area is the 8000MB memory area outside the first 100MB memory area in the flash translation layer of the eMMC.

2. The SOC Android system fast startup method according to claim 1, characterized in that: The preset memory capacity is 290KB-350KB.

3. The SOC Android system fast startup method according to claim 1, characterized in that: The first sub-instruction includes several handshake instructions.

4. The SOC Android system fast startup method according to claim 3, characterized in that: The number of the handshake instructions is greater than or equal to 3.

5. The SOC Android system fast startup method according to claim 1, characterized in that: The number of the data read instructions is greater than or equal to 3.

6. An integrated circuit system, characterized in that: Start up by the SOC Android system quick start method according to any one of claims 1 to 5.

7. A SOC Android system fast boot device, characterized in that: include: an acquiring unit, configured to acquire a CMD instruction sent by a host; the CMD instruction includes a first sub-instruction, a second sub-instruction, and a read data instruction; the first sub-instruction, the second sub-instruction, and the read data instruction are instructions sent sequentially; A first processing unit, configured to initialize a first memory area of the eMMC upon receiving the first sub-instruction; The second processing unit is used to read data of a preset memory capacity from nandFlash and store it in the Sram of the eMMC when receiving the second sub-instruction, so that the host reads data from the Sram through the read data instruction, and initialize the second memory area of the eMMC after the host reads the data; the first memory area is the first 100MB memory area in the flash translation layer of the eMMC; the second memory area is the 8000MB memory area outside the first 100MB memory area in the flash translation layer of the eMMC.

8. A SOC Android system fast startup device, characterized in that include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the SOC Android system fast startup method as described in any one of claims 1-5.

9. A computer-readable storage medium storing instructions executable by a processor, characterized in that: The processor-executable instructions are used to execute the SOC Android system fast startup method as described in any one of claims 1-5 when executed by the processor.

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