USB low-power-consumption awakening system and method, chip, chip module and terminal

Abstract

The invention discloses a USB low-power-consumption awakening system and method, a chip, a chip module and a terminal. The system comprises a USB physical layer interface for receiving a differential signal DP / DM of a USB bus, a wake-up signal generation circuit for generating a hardware wake-up signal in a USB low power consumption state, and a system interrupt controller for receiving the hardware wake-up signal and outputting system wake-up interrupt, the USB controller enters or exits from a low-power-consumption state under the control of the on-chip processing logic; and the on-chip processing logic responds to system wakeup interruption to recover a clock and a power supply for the USB controller. The USB controller turns off the master clock in a USB low power state, retaining only a small amount of holding power for saving register context. The USB controller bypassing a low-power-consumption state is directly connected to the interrupt pin of the chip, so that the system is firstly interrupted and awakened and then is electrified / clocked, and thus the power consumption of the Suspen is reduced to the minimum.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a USB low-power wakeup system, method, chip, chip module and terminal for shutting down the main clock and main power supply of a USB controller in a USB low-power state and directly waking up through a hardware line state. BACKGROUND

[0002] In USB communication, in order to save energy, a device supports a Suspend state. When the bus is in an Idle state for more than 3 ms, the specification (USB 2.0) requires that the USB host or device should complete entering the Suspend state within 7 ms. In this state, the USB host or device will reduce current consumption, for example, in the Suspend state, the current from the VBUS of a low-power device must be ≤ 500 µA. The existing wakeup mechanism includes two wakeup approaches: host-initiated wakeup (host-driven Resume) and device-initiated remote wakeup.

[0003] Among them, in the host-initiated wakeup, when the host needs to communicate with the device again, it first drives a resume signal (Resume signaling) on the bus: on a low-speed / full-speed link, the differential pair is pulled from the J state to the opposite polarity K state and maintained ≥ 20 ms. On a high-speed link, the same first completes 20 ms of Resume in the full-speed electrical layer K state, and then performs high-speed handshake to return to the high-speed mode. After the device detects the resume signal on the bus, it exits the Suspend state and returns to the normal working state without having to re-enumerate.

[0004] In the device-initiated remote wakeup, if the device has declared and enabled the remote wakeup function by the host in the configuration descriptor during enumeration, it can initiate the wakeup by itself when the bus is idle: the device first drives the K state for at least 1 ms (not more than 15 ms), and then continues to be driven by the downstream port until the host takes over. After the downstream hub or root port receives this signal, it continues to drive the Resume signal until the host takes over. Typical scenarios of this mode: mouse movement, keyboard key press on a standby notebook, or detection of a device inserted into a downstream port by a USB hub.

[0005] Whether it is the host-initiated wakeup or the device-initiated remote wakeup mechanism, both require the USB controller to still maintain the clock and power supply during Suspend in order to detect the Resume (K state) signal at any time, resulting in further reduction of power consumption.

[0006] To this end, the existing technology discloses a kind of patent for invention with disclosure number CN113094105A, a kind of method for guaranteeing low-power state of USB equipment and being awakened, it mentions increasing a double-pole double-throw analog switch on the USB path between processor and host, with double-pole double-throw analog switch guaranteeing USB2.0 bus signal integrity, and maintaining Suspended state on USB bus;By double-pole double-throw analog switch: when USB equipment receives Suspended signal sent by host and enters a lower power consumption Suspended state, i.e. processor enters sleep state, processor turns off the power and clock and bus of kernel;K or SE0 signal sent by host to USB equipment through USB bus is detected as the interrupt signal of processor to make processor exit sleep state, restore USB bus, so that USB equipment exits Suspended state.

[0007] The patent CN113094105A is applied to the wake-up mechanism initiated by host, mainly through the device (double-pole double-throw switch) outside SoC to wake up USB equipment (slave). Its application scenario is that USB equipment needs to be slave, similar to USB equipment connecting PC as data transmission, or charging, to turn off USB controller to achieve a low-power state of USB. In the patent, when the host sends K or SE0 signal, the DP signal edge changes from high to low as an interrupt signal to make the processor exit sleep state, and send the control signal of switching switch within the longest response time of USB2.0 bus protocol, disconnect D+ and HSD2+, switch to D+ and HSD1+ connection, D- and HSD1- connection, and restore the USB bus between host and processor, and USB equipment resumes work. The USB2.0 bus protocol provides that 20ms should be responded after the host sends the wake-up signal, otherwise the host will clear the signal. After switching is completed, the whole system of USB equipment is woken up and powered on, then the clock and power of USB controller are configured, and then the state of USB controller needs to be stable before processing K state / SE0 signal sent by host. The above-mentioned patent converts the edge change of DP / DM into GPIO interrupt through off-chip double-pole double-throw switch to wake up MCU. But due to the time consumption of MCU re-powering and USB controller initialization, the current scheme is difficult to meet the 20ms Resume recovery time required by USB2.0 in actual test, so it cannot be widely applied. SUMMARY

[0008] The following presents a simplified summary of embodiments of the application in order to provide a basic understanding of some aspects of the application. This summary is not an extensive overview of the application. It is not intended to identify key or critical elements of the application or to delineate the scope of the application. Its sole purpose is to present some concepts of the application in a simplified form as a prelude to the more detailed description that is presented later.

[0009] In view of the deficiencies of the prior art, the present application improves the device-initiated remote wake-up mechanism, and proposes a hardware wake-up path for directly connecting a USB line state change signal to a system interrupt controller. In a suspend state, a USB controller can achieve a deep sleep state, and the system power consumption is significantly reduced.

[0010] According to a first aspect of the present application, a USB low-power wake-up system is provided, comprising: a USB physical layer interface (USB PHY) configured to receive differential signals DP / DM of a USB bus; a wake-up signal generation circuit coupled with the USB PHY and configured to generate a hardware wake-up signal when detecting that the bus changes from J state to K state in a USB low-power state; a system interrupt controller (INTC) directly connected with the wake-up signal generation circuit to receive the hardware wake-up signal and output a system wake-up interrupt; a USB controller coupled with the USB PHY, a main power supply of which is controlled by on-chip processing logic to enter or exit a USB low-power state; in the USB low-power state, the main clock and the main power supply of the USB controller are turned off, and the register context is saved by a chip always-on retention power domain; and the on-chip processing logic is responsive to the system wake-up interrupt to restore the main clock and the main power supply for the USB controller, so that the USB controller completes a bus wake-up sequence and enters a normal working state.

[0011] The chip always-on retention power domain and the on-chip processing logic are both internal modules of the SoC; the on-chip processing logic is powered by the retention power domain, used for processing interrupts, and controlling the power-on, power-off, clock gating, and wake-up sequence of each functional power domain in the SoC.

[0012] The wake-up signal generation circuit can be independently selected from the following two schemes according to the implementation: The first mode: the USB physical layer interface integrates a wake-up detection function, and directly outputs the hardware wake-up signal in a power supply domain; the USB physical layer interface is in a low-power monitoring mode in a USB low-power state, only maintains a bias current and a terminal resistance required for detecting DP / DM, and the rest of modules are powered off. At this time, the main power supply of the USB controller is turned off (the clock is kept), only the necessary power supply for keeping the subsequent USB controller and system functions normal is maintained, and the register context is saved by the chip always-on holding power supply domain. The USB controller works normally in full link, at this time, the system can ignore the USB controller entering a deep (deep sleep) state, and keeps the low-power scene of the whole system. The hardware wake-up signal is directly output by the USB physical layer interface, when there is a wake-up signal, the USB controller can directly receive the wake-up signal and send it to the on-chip processing logic for processing; the on-chip processing logic responds to the wake-up interrupt, and restores the main power supply of the USB controller.

[0013] The second mode: the USB physical layer interface only outputs a line state signal Linestate, the line state signal is sent to an external interrupt controller EIC (External Interrupt Controller) or a general-purpose input / output GPIO (General-Purpose Input / Output); the EIC or GPIO completes edge detection in a holding power supply domain and generates the hardware wake-up signal; the USB physical layer interface is completely powered off in the USB low-power state except for a terminal resistance and a Linestate buffer, and the main clock of the USB controller is turned off, only the necessary power supply for keeping the subsequent USB controller and system functions normal is maintained. This mode wakes up the whole system through the EIC and the GPIO, and then the system powers on and clocks the USB controller through the on-chip processing logic in the wake-up process, so that the USB controller can normally respond and complete the bus wake-up sequence.

[0014] The first mode is suitable for a USB physical layer interface with a "power-off wake-up" capability and a direct interrupt output. The second mode is a preferred mode, the hardware wake-up signal is an interrupt request signal generated by the EIC or the GPIO after the USB physical layer interface sends the current state of the USB data line to the EIC or the GPIO. This scheme has universality, the USB physical layer interface does not need to have a "power-off wake-up" capability, only needs to output a line state signal (Linestate), the wake-up capability is provided by the EIC / GPIO, the requirement for the USB physical layer interface is lower, the USB physical layer interface can be completely powered off except for a terminal resistance and a line state signal (Linestate) buffer, only the EIC / GPIO is kept monitoring, and the power consumption is lower. In addition, the GPIO / EIC should have a Schmitt trigger or a filter to prevent false triggering.

[0015] Further, the wake-up signal generating circuit comprises a line state detecting unit and an edge detecting unit; The line state detecting unit is used for converting the DP / DM differential signal output by the USB physical layer interface into a digital line state signal; The edge detecting unit, realized by the EIC / GPIO within the SoC, is used for generating a hardware wake-up signal when the line state signal is detected to jump from the J state to the K state.

[0016] The line state detecting unit is powered by the Always-On power domain, and the remaining analog and digital modules are powered off.

[0017] Further, the system interrupt controller is a programmable GPIO module or a dedicated external interrupt controller EIC, and the hardware wake-up signal is directly input to the GPIO module or the EIC through a chip pin without passing through the internal logic of the USB controller.

[0018] Further, the USB controller is a USB host controller or a USB device controller integrated in the SoC, and the register context thereof is kept in the Always-On power domain in the Suspend state, while the main clock and the main power are completely turned off.

[0019] According to a second aspect of the present application, a USB low-power wake-up method is provided, applied to the low-power wake-up system, which comprises the following steps: a) entering the USB low-power state: the on-chip processing logic turns off the main clock and the main power of the USB controller, and the register context of the USB controller is saved by the chip Always-On holding power domain; b) continuously monitoring the USB line state by the wake-up signal generating circuit; c) directly generating a hardware wake-up signal when the line state is detected to change from the J state to the K state; d) the system interrupt controller receives the hardware wake-up signal and sends a wake-up interrupt to the on-chip processing logic; e) the on-chip processing logic responds to the wake-up interrupt to restore the main clock and the main power of the USB controller; f) the USB controller restores the register context from the holding power domain, executes the wake-up sequence defined by the USB specification, and restores the normal data communication.

[0020] In the step c), the generation of the hardware wake-up signal is divided into the following two independently selectable schemes: a) The first solution: the USB physical layer interface integrates the wake-up detection function, and directly outputs the hardware wake-up signal in the power domain; the USB physical layer interface is in a low-power monitoring mode, only maintaining the bias current and terminal resistance required for detecting DP / DM, and the rest of the modules are powered off, that is, the USB physical layer interface maintains the lowest power consumption and directly outputs the line state change; b) The USB physical layer interface only outputs a line state signal, which is sent to an external interrupt controller EIC or a general-purpose input / output GPIO; the EIC or GPIO completes edge detection in the power domain and generates the hardware wake-up signal; the USB physical layer interface is completely powered off in the USB low-power state except for the terminal resistance and Linestate buffer; the USB controller main clock and main power are turned off, and the register context is saved by the power domain.

[0021] According to a third aspect of the present application, a chip is provided, which integrates the above-mentioned system on the same silicon chip.

[0022] According to a fourth aspect of the present application, a chip module is provided, which includes the chip and a USB connector.

[0023] According to a fifth aspect of the present application, a terminal is provided, which includes the chip module, and is configured to enter a Suspend state when the USB bus is idle, and to resume the USB communication when receiving a bus wake-up event.

[0024] The present application bypasses the USB controller in the power-off state through a hardware direct connection (SoC on-chip path), and directly connects to the interrupt pin (EIC / GPIO) of the chip, so that the system is first interrupted and then powered on / turned on, and the USB controller can be completely powered off and hibernated, thereby reducing the Suspend power consumption to the minimum, realizing micro-ampere-level suspension current, and being suitable for battery-powered USB devices, factory test fixtures and low-power terminals. BRIEF DESCRIPTION OF DRAWINGS

[0025] The present application can be better understood by reference to the following description taken in connection with the accompanying drawings, in which like reference numerals refer to like elements or features in the several views. The following description is included in order to provide a complete and enabling disclosure of the present application and is given in connection with the accompanying drawings. It is not intended to limit the scope of the application nor require the use of any particular design in practicing the present application. In the drawings: Figure 1 The wake-up path schematic diagram of embodiment 1 of the present application; Figure 2 The wake-up path schematic diagram of embodiment 2 of the present application; Figure 3Flow chart of low-power wake-up method for embodiment 2 of the present application. DETAILED DESCRIPTION

[0026] Embodiments of the present application will be described below with reference to the accompanying drawings. The elements and features described in one drawing or embodiment of the present application can be combined with the elements and features shown in one or more other drawings or embodiments. It should be noted that, for the purpose of clarity, the representation and description of components and processes unrelated to the present application, which are known to those of ordinary skill in the art, are omitted from the drawings and the description.

[0027] In the description of the present application, it should be understood that the terms "mounting", "connection", "coupling", "connecting", should be interpreted broadly, for example, they can be fixed connection, or detachable connection, or integral connection; they can be mechanical connection, or electrical connection; they can be direct connection, or indirect connection through an intermediate medium; they can be internal connection of two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0028] The terms used in the present application are explained as follows: IP: Intellectual Property, IP assets commonly used in the chip industry, also known as IP core (Intellectual Property Core), refers to a mature design of a circuit module with independent functions, which can be reused and has independent intellectual property rights. It is usually divided into soft core, hard core and fixed core.

[0029] USB low power state: refers to a mode in which the device enters a low power state to save battery life or reduce heat generation in USB communication.

[0030] Suspend state: the device enters a low-power suspend state, and the host also reduces the bus power consumption.

[0031] Resume state: the device recovers from the low-power state (Suspend State) and reenters the active state (Active State).

[0032] USB DP DM: in the USB interface, DP (Data Plus) and DM (Data Minus) are respectively the D- and D+ data lines of USB, which are two signal lines for data transmission, responsible for efficient communication between devices.

[0033] Line state: the current state of the USB data line, describing the different states of the connection between the device and the host, including SE0, J, K, etc. USB J state and K state: defined according to the differential signals under low speed and full speed / high speed, as shown in the following table:

[0034] Embodiment 1 Referring to Figure 1 The embodiment provides a USB low-power wake-up system, which comprises a USB physical layer interface, a wake-up signal generation circuit, a system interrupt controller, a USB controller and on-chip processing logic. The wake-up signal generation circuit generates a hardware wake-up signal when detecting that the bus changes from J state to K state, wakes up the whole system through the system interrupt controller, and then restores the USB controller and the on-chip processing logic. The hardware wake-up signal is generated internally by the USB physical layer interface, and after passing through the wake-up detection logic inside the USB controller, an interrupt request is output to the system interrupt controller.

[0035] The wake-up path of the embodiment is: wake-up signal passes through USB interface (USB INTERFACE) → USB physical layer interface USB PHY → USB controller USB Controller → system interrupt controller INTC → SoC in turn. In the embodiment, INTC_REQ is directly generated internally by the USB PHY, and the interrupt line is directly pulled to INTC. The path requires that the USB controller still maintains a certain clock during Suspend, and only retains the necessary power to maintain the normal functions of the subsequent USB controller and system, so as to detect the Resume (K state) signal at any time.

[0036] Embodiment 2 Referring to Figure 2 The embodiment provides a USB low-power wake-up system, which comprises a USB physical layer interface, a wake-up signal generation circuit, a system interrupt controller, a USB controller and on-chip processing logic. The USB physical layer interface receives the differential signals of USB DP / DM and outputs a line state signal. The wake-up signal generation circuit performs edge detection on the line state signal, and generates a hardware wake-up signal when detecting continuous K state. The hardware wake-up signal is directly input to the GPIO / EIC of the chip without passing through the USB controller. The GPIO / EIC generates a system interrupt, wakes up the on-chip processing logic, which immediately powers on the USB controller and restores the clock. The USB controller then performs the Resume sequence defined in the USB specification, completes the handshake with the host, and enters the normal transmission state. During Suspend, only a small amount of holding power is retained for the key modules of the USB controller to save the register context.

[0037] Unlike the embodiment 1, the wake-up signal generating circuit in this embodiment includes a line state detection unit and an edge detection unit. The line state detection unit is used to convert the DP / DM differential signal output by the USB PHY into a digital Linestate signal; the edge detection unit, implemented by the EIC / GPIO within the SoC, is used to generate a hardware wake-up signal when the Linestate signal is detected to jump from the J state to the K state.

[0038] When the USB changes from the Suspend state to the Active state, the linestate signal changes from the J state to the K state (Resume signal). The Resume signal is connected to the EIC or GPIO, which in turn wakes up the system. After the system is started, the power supply and clock of each module are restored, the USB Controller starts to work to process the Resume event, and then the next step of data processing is performed.

[0039] In the wake-up path of this embodiment, the USB PHY sends the Linestate to the EIC / GPIO, which in turn generates a wake-up interrupt. This embodiment is an improved scheme for the embodiment 1, in which the clock is further turned off. Compared with the embodiment 1, the USB PHY only needs to output the Linestate, and the wake-up capability is provided by the EIC / GPIO, so that the rest of the USB PHY is completely powered off (except for the terminal resistor and the Linestate output buffer), only the EIC / GPIO remains monitoring, and the power consumption is lower. The EIC / GPIO is the EIC / GPIO on the SoC side, no additional hardware is needed, and the implementation is an on-chip path of the SoC, which can respond to the wake-up signal faster and process the signal in time.

[0040] Embodiment 3 Referring to Figure 3 This embodiment provides a USB low-power wake-up method, which includes the steps of entering the Suspend, turning off the main clock and main power supply of the USB controller, monitoring the line state, generating a hardware wake-up signal, restoring the power supply, and executing a wake-up sequence. It includes the following steps: a) Enter the USB low-power state Suspend, turn off the main clock and main power supply of the USB controller, and save the register context of the USB controller by the chip always-on holding power domain, and enable the EIC / GPIO; b) Continuously monitor the USB line state signal Linestate by the EIC / GPIO; c) When the USB line state signal Linestate is detected to change from the J state to the K state, a hardware wake-up signal is directly generated; d) the system interrupt controller receives the hardware wake-up signal and issues a wake-up interrupt to the on-chip processing logic; e) the on-chip processing logic responds to the wake-up interrupt by restoring the master clock and the main power supply of the USB controller; f) the USB controller restores the register context from the retention power domain, executes the wake-up sequence defined by the USB specification, and resumes normal data communication.

[0041] Wherein, before step a), the USB controller sets a register by software to indicate that it is allowed to enter Suspend. The hardware wake-up signal in step c) always keeps the active level during the shutdown of the main power supply of the USB controller until the completion of the master clock and main power supply restoration in step e). After step f), the USB controller clears the register to exit the Suspend state.

[0042] Embodiment 4 The embodiment provides a chip implementation scheme, which integrates all or part of the functional modules of the low-power wake-up system in embodiment 1 or embodiment 2 in a single SoC.

[0043] Embodiment 5 The embodiment of the present application provides a chip module, which comprises the chip in embodiment 4 and a USB connector electrically coupled with the chip.

[0044] Embodiment 6 The embodiment of the present application provides a terminal, which comprises the chip module in embodiment 5, and the terminal is configured to enter the Suspend state when the USB bus is idle and to restore the USB communication when a bus wake-up event is received.

[0045] The person skilled in the art can determine whether the product of others adopts the technical solution of the present application by the following ways: 1. Measure the Suspend current of the chip in the suspended state of the USB bus, if it is significantly lower than the existing scheme, there is a possibility of adoption; 2. Use an oscilloscope to monitor the line state signal output by the USB PHY, if it is found that the signal is directly connected to the GPIO / EIC pin of the chip, and the main power supply of the USB controller is turned off, only a small amount of retention power is used to save the register context, it can be initially confirmed that the present scheme is used; 3. Through chip dissection and netlist analysis, if the wake-up signal generation circuit independent of the USB controller and the GPIO / EIC direct connection path are found, it can be directly proved that the infringement is committed.

[0046] In the above description of the specific embodiments of the present application, features described and / or shown for one implementation can be used in one or more other implementations in the same or similar manner, in combination with or in place of features in the other implementations.

[0047] It should be emphasized that the term "comprises / comprising" when used in this specification is taken to mean the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0048] Furthermore, the method of the present application is not limited to being performed in the time sequence described in the specification, but can also be performed in other time sequences, in parallel, or independently. Therefore, the order of execution of the method described in the specification does not constitute a limitation on the technical scope of the present application.

[0049] Although the present application has been disclosed by the above description of the specific embodiments of the present application, it should be understood that all of the above-described embodiments and examples are illustrative, and not restrictive. Those skilled in the art can design various modifications, improvements or equivalents of the present application within the spirit and scope of the appended claims. These modifications, improvements or equivalents should also be considered to be included in the scope of protection of the present application.

Claims

1. A USB low-power wake-up system, characterized by: include: A USB physical layer interface is configured to receive differential signals DP / DM of a USB bus; a wake-up signal generating circuit, coupled to the USB physical layer interface, and configured to generate a hardware wake-up signal in a USB low-power state; A system interrupt controller, directly connected to the wake-up signal generating circuit, to receive the hardware wake-up signal and output a system wake-up interrupt; A USB controller coupled to the USB physical layer interface, wherein the main power supply of the USB controller is controlled by on-chip processing logic to enter or exit a USB low-power state; in the USB low-power state, the main clock and main power supply of the USB controller are turned off, and the register context is saved by a normally-on hold power domain of the chip; as well as On-chip processing logic, in response to the system wake-up interrupt, restores the main clock and main power for the USB controller, so that the USB controller completes the bus wake-up sequence and enters a normal working state.

2. The USB low-power wake-up system according to claim 1, wherein: The wake-up signal generating circuit includes the following first implementation mode: The USB physical layer interface integrates a wake-up detection function and directly outputs the hardware wake-up signal within the power domain; the USB physical layer interface is in a low-power monitoring mode in the USB low-power state.

3. The USB low-power wake-up system according to claim 1, wherein: The wake-up signal generating circuit includes the following second implementation mode: The USB physical layer interface only outputs a line status signal, which is sent to an external interrupt controller EIC or a general-purpose input / output GPIO; the EIC or GPIO performs edge detection within the retention power domain and generates the hardware wake-up signal; at this time, the USB physical layer interface is completely powered off except for the terminal resistor and the line status signal buffer, and the main clock and main power of the USB controller are turned off, and the register context is saved by the retention power domain.

4. The USB low-power wake-up system according to claim 3, wherein: The hardware wake-up signal is directly input to the GPIO or EIC through a chip pin without passing through the internal logic of the USB controller.

5. The USB low-power wake-up system according to claim 3, wherein: The wake-up signal generating circuit includes a line state detection unit and an edge detection unit; The line status detection unit is used to convert the DP / DM differential signal output by the USB physical layer interface into a digital line status signal; The edge detection unit is implemented by the EIC / GPIO in the SoC and is used to generate a hardware wake-up signal when it detects that the line status signal jumps from the J state to the K state.

6. A USB low-power wake-up method, applied to the low-power wake-up system according to any one of claims 1 to 5, characterized in that: The following steps are involved: a) Entering the USB low-power state: On-chip processing logic turns off the USB controller's main clock and main power supply, and the USB controller's register context is preserved in the chip's normally-on hold power domain; b) The wake-up signal generating circuit continuously monitors the USB line status; c) When detecting that the line state changes from J state to K state, the wake-up signal generating circuit generates a hardware wake-up signal; d) the system interrupt controller receives the hardware wake-up signal and issues a wake-up interrupt to the on-chip processing logic; e) On-chip processing logic responds to the wake-up interrupt and restores the main clock and main power of the USB controller; f) The USB controller restores the register context from the retained power domain, performs the wake-up sequence defined by the USB specification, and resumes normal data communication.

7. The USB low-power wake-up method according to claim 6, wherein: The hardware wake-up signal in step c) is generated in a manner corresponding to the wake-up signal generating circuit defined in claim 2 or 3.

8. A chip, characterized in that: All or part of the functional modules of the low-power wake-up system according to any one of claims 1 to 5 are integrated on the same silicon chip.

9. A chip module, characterized in that: include: The chip according to claim 8; as well as A USB connector electrically coupled to the chip is used for docking with an external host or device.

10. A terminal, characterized in that: Including the chip module according to claim 9, the terminal is configured to enter a Suspend state when the USB bus is idle, and resume USB communication upon receiving a bus wake-up event.

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