System-on-chip, system-on-chip configuration method and electronic equipment

Abstract

The invention discloses a system-on-chip, a system-on-chip configuration method and electronic equipment. The system on chip comprises a multi-core RISC-V processor and a field programmable gate array (FPGA), the FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after the initial configuration is completed by power-on starting; the multi-core RISC-V processor is configured to start a bootloader according to the initial configuration completion signal, and the bootloader is configured to start the bootloader according to the initial configuration completion signal; under the condition that an FPGA reconfiguration event occurs, a reconfiguration request signal is sent to the FPGA; the FPGA is further configured to set a storage position to obtain new configuration data, and after reconfiguration is completed, a reconfiguration completion signal is sent to the multi-core RISC-V processor; the multi-core RISC-V processor is further configured to execute system interface reinitialization and / or configuration parameter updating according to the reconfiguration completion signal. According to the scheme of the invention, a bidirectional configuration mechanism between the FPGA and the RISC-V is realized based on the standardized interaction signal, and the dynamic configuration / upgrading requirements of system functions are fully met.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of chip technology, and in particular to a system-on-a-chip, a system-on-a-chip configuration method, and an electronic device. Background Technology

[0002] As electronic systems become increasingly integrated, SoC (System-on-Chip) platforms are evolving from single-processor systems to a deep integration of multi-core processors and programmable logic (FPGAs). This heterogeneous combination not only enables high-performance computing but also meets customized needs and adapts to diverse application scenarios. In practical applications, with the continuous addition of new features and increasing security requirements, system firmware and FPGA logic need to be updated regularly. Traditional static configuration methods often require system downtime or complex manual operations, making online upgrades and safe switchovers difficult. Dynamic configuration methods can smoothly update configurations during system operation, thereby reducing downtime and risks. Summary of the Invention

[0003] This application provides a system-on-a-chip (SoC), an SoC configuration method, and an electronic device. For heterogeneous SoCs built with multi-core RISC-V (Reduced Instruction Set Computer – V) processors and FPGAs, a bidirectional configuration mechanism between the FPGA and RISC-V is implemented based on standardized interaction signals. This mechanism allows the FPGA to guide the RISC-V startup during system boot, and the RISC-V to trigger FPGA reconfiguration during operation, fully meeting the dynamic configuration / upgrade requirements of the system.

[0004] This application provides a system-on-a-chip, including: a multi-core RISC-V processor and a field-programmable gate array (FPGA); The FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after power-on and initial configuration completion. The multi-core RISC-V processor is configured to, upon the initial configuration completion signal, start the bootloader; and, in the event of an FPGA reconfiguration event, send a reconfiguration request signal to the FPGA. The FPGA is also configured to set a storage location to obtain new configuration data, and after completing the reconfiguration, send a reconfiguration completion signal to the multi-core RISC-V processor. The multi-core RISC-V processor is also configured to perform system interface reinitialization and / or configuration parameter update based on the reconfiguration completion signal.

[0005] This application provides a method for configuring a system-on-a-chip, wherein the system-on-a-chip includes a multi-core RISC-V processor and a field-programmable gate array (FPGA), and the method includes: After the FPGA powers on and completes the initial configuration, it sends an initial configuration completion signal to the multi-core RISC-V processor. The multi-core RISC-V processor starts the bootloader based on the initial configuration completion signal; In the event of an FPGA reconfiguration event, the multi-core RISC-V processor sends a reconfiguration request signal to the FPGA; The FPGA retrieves new configuration data from a set storage location, completes the reconfiguration, and sends a reconfiguration completion signal to the multi-core RISC-V processor. The multi-core RISC-V processor performs system interface reinitialization and / or configuration parameter update based on the reconfiguration completion signal.

[0006] This application also provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the on-chip system configuration method as described in any embodiment of this disclosure.

[0007] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0009] Figure 1 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the structure of an FPGA configuration control module provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the structure of a RISC-V configuration management module provided in an embodiment of the present disclosure; Figure 4 A flowchart illustrating a system-on-chip configuration method provided in this embodiment of the disclosure; Figure 5 A flowchart of another system-on-chip configuration method provided in an embodiment of this disclosure. Detailed Implementation

[0010] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0011] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0012] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0013] SoC platforms are shifting from single-processor architectures to a deep integration of multi-core processors and programmable logic. Multi-core RISC-V (Fifth Generation Reduced Instruction Set Computer) processors offer advantages such as open source, flexibility, and low power consumption, while FPGAs provide high programmability and rapid prototyping capabilities. This heterogeneous combination of multi-core RISC-V processors and FPGAs not only enables high-performance computing but also meets customized needs and adapts to diverse application scenarios. Consequently, configuration update / upgrade solutions based on this heterogeneous SoC are becoming increasingly important. Providing chip configuration upgrade solutions without downtime can offer chip users a superior user experience.

[0014] In some feasible solutions, the FPGA completes the Bitstream configuration loading after power-on, and the processor also boots the firmware from the preset boot memory. If an FPGA configuration update or processor system update is required, it is often necessary to shut down and power on again. Dynamic reconfiguration or online reconfiguration cannot be achieved, which limits the system's flexibility in the face of function updates and performance optimizations.

[0015] In some feasible solutions, the FPGA primarily controls its own configuration, while the RISC-V core merely acts as a follow-up executor, lacking effective interaction between the two. Consequently, when switching functions or fixing firmware defects in certain application modes, the system needs to reconfigure the FPGA, and the reconfiguration results or status cannot be effectively transmitted. This limits the collaborative work between the two processing modules in the heterogeneous system and makes it difficult to fully meet the application requirements for automatic remote updates.

[0016] This disclosure provides a system-on-a-chip that establishes a bidirectional signaling mechanism between a multi-core RISC-V processor and an FPGA, enabling online dynamic configuration during runtime. Upon system power-up, the FPGA performs initial configuration and boots the RISC-V processor. During system operation, the RISC-V processor can proactively request reconfiguration of the FPGA, achieving flexible configuration and dynamic reconfiguration between the two components.

[0017] The system-on-a-chip (SoC) provided in this disclosure includes a multi-core RISC-V processor 110 and an FPGA 120, such as Figure 1 As shown, the FPGA120 is configured to send an initial configuration completion signal (init signal) to the multi-core RISC-V processor after power-on and initial configuration completion. The multi-core RISC-V processor 110 is configured to start the bootloader according to the initial configuration completion signal; and to send a reconfiguration request signal (program signal) to the FPGA 120 in the event of an FPGA reconfiguration event. The FPGA 120 is also configured to set a storage location to obtain new configuration data, and after completing the reconfiguration, send a reconfiguration completion signal (done signal) to the multi-core RISC-V processor 110. The multi-core RISC-V processor 110 is also configured to perform system interface reinitialization and / or configuration parameter update based on the reconfiguration completion signal.

[0018] As can be seen, the FPGA and the multi-core RISC-V processor, based on the aforementioned standard signals, implement configuration status feedback and command transmission for the FPGA, ensuring coordinated execution of the configuration processes of both parts. The multi-core RISC-V processor can proactively initiate configuration update requests as needed, instructing the FPGA to complete dynamic reconfiguration without stopping operation.

[0019] In some exemplary embodiments, the FPGA includes: an FPGA configuration control module 1210, which is a core control unit that realizes bidirectional configuration and dynamic reconfiguration between the RISC-V and FPGA systems.

[0020] In some exemplary embodiments, the FPGA further includes a data cache module and a decoding and verification module. The data cache module is used to store configuration data; the data cache module includes Flash memory or BRAM (Block Random Access Memory), but is not limited to any particular aspect and may also be other types of memory. In some exemplary embodiments, the configuration data includes a Bitstream. The decoding and verification module is used to decode the loaded configuration data and perform data verification. In some exemplary embodiments, the data verification includes CRC (Cyclic Redundancy Check) verification; other verification methods are not listed here.

[0021] Among them, such as Figure 2 As shown, the FPGA configuration control module 1210 includes: a state machine control unit 12110, a data loading unit 12120, and a state feedback unit 12130. Optionally, the FPGA configuration control module 1210 further includes: a storage interface unit 12140 and a configuration interface unit 12150.

[0022] The state machine control unit is configured to control the transitions between multiple states during the PFGA configuration process; the states include: idle, initial configuration completed, configuration in progress, reconfiguration completed, and configuration failed; the state feedback unit provides corresponding state signals based on the state.

[0023] The data loading unit is configured to read configuration data from the memory and load it into the FPGA configuration channel; The status feedback unit is configured to acquire status signals during the configuration process and feed them back to the multi-core RISC-V processor.

[0024] It is understood that the state machine control unit 12110 is used to control the state transitions at each stage of the entire FPGA configuration process, ensuring that the configuration process is orderly and controllable. In some exemplary embodiments, a hardware description language is used to implement the finite state machine. The state register is designed with 4-bit encoding, and the states include: Idle: In an idle state, waiting for configuration requests; Init: The FPGA completes its initial state and outputs the "init" signal. Programming: In the configuration state, the reconfiguration process is executed after responding to the "program" signal issued by RISC-V; Done: Reconfiguration complete, sending a "done" signal. Error: Configuration failed, error code is displayed.

[0025] The input signals that cause the transitions between multiple states of the state machine include one or more of the following: a reconfiguration request signal, from program information of a multi-core RISC-V processor; a configuration completion signal, from the data loading unit; and an error detection signal, from the decoding and verification module or the verification module in the data loading unit, or an error detection signal from other modules or units in the FPGA.

[0026] The data loading unit 12120 is used to read configuration data from the storage device and load it into the FPGA configuration channel, ensuring high-speed and complete transmission of configuration data. In some exemplary embodiments, the data loading unit has a built-in DMA (Direct Memory Access) controller, which supports automatic transfer of configuration data without CPU intervention.

[0027] The loaded configuration data includes a Bitstream, which can be stored in the BRAM integrated inside the FPGA or in the Flash memory outside the FPGA, and accessed via SPI / QSPI (Serial Peripheral Interface / Quad Serial Peripheral Interface).

[0028] In some exemplary embodiments, the data loading unit includes a FIFO (First-In-First-Out) buffer to prevent data transmission from being blocked by sudden bursts. In some exemplary embodiments, the data loading unit further includes a data verification module for verifying the integrity of configuration data. Data integrity verification is performed based on a checksum stored at the end of the BRAM or Flash memory. If verification fails, an error detection signal (Notify) is sent to the state machine.

[0029] The data transfer bandwidth of the data recording unit is 8-bit, 16-bit, 32-bit, 64-bit, or others, which can be determined according to the bandwidth requirements of different systems.

[0030] In some exemplary embodiments, the data loading unit 12120 is connected to a configuration data source via a storage interface unit 12140, including: FPGA internal memory and / or external memory. The internal BRAM memory is suitable for small-scale configuration files and offers low latency; the external memory includes Flash memory, which supports the storage and switching of multiple versions of configuration data.

[0031] In some exemplary embodiments, an SPI / QSPI controller is used to access the Flash memory, implementing the standard SPI / QSPI protocol and supporting command sequences (e.g., Read ID, Read Status, Read Data); it also has DMA read / write capabilities.

[0032] The status feedback unit 12130 is used to feed back the current status information and / or error information of the configuration control module to the RISC-V side, enabling the configuration process to be monitored and controlled. In some exemplary embodiments, the status feedback unit includes an 8-bit status register, with the status code defined as 0x00. Idle; 0x01 Init; 0x02 Programming; 0x03 Done; 0xFF Error.

[0033] In some exemplary embodiments, the error information includes an error code. The status feedback unit also includes an error code register for feeding back specific error information. For example, the error code is defined as: 0xE1. CRC check failed; 0xE2 Memory read timeout; 0xE3 The configuration interface is abnormal.

[0034] In some exemplary embodiments, the status feedback unit 12130 interacts with the multi-core RISC-V processor via a configuration interface unit 12150. The configuration interface unit 12150 is configured to interact with the multi-core RISC-V processor using an Advanced Extensible Interface (AXI); or, to interact with the multi-core RISC-V processor using a General Purpose Input / Output (GPIO) interface.

[0035] In some exemplary embodiments, the configuration interface unit 12150 is configured to use the AXI Lite protocol to interact with the multi-core RISC-V processor via registers in the FPGA. The registers include at least one of the following types: configuration status register, error code register, and configuration command register.

[0036] For example, the AXI Lite interface implementation uses a standard 64-bit register mapping; address space partitioning: 0x00 Configuration Request Register; 0x04 Status register; 0x08 Error code register; 0x0C Interrupt enable register.

[0037] In some exemplary embodiments, the configuration interface unit 12150 is configured to interact with the multi-core RISC-V processor using the following 4-wire GPIO interface: The system includes an initial configuration completion signal output, a reconfiguration completion signal output, a reconfiguration request signal input, and a configuration failure signal output.

[0038] In some exemplary embodiments, the multi-core RISC-V processor 110 includes a RISC-V configuration management module 1110.

[0039] like Figure 3 As shown, the RISC-V configuration management module 1110 includes the following sub-modules: configuration management driver unit 11110, system status detection unit 11120, configuration request generation unit 11130, and status receiving and processing unit 11140. The configuration management driver unit 11110 is configured to use an event-driven mode to schedule the operation of other sub-modules in the RISC-V configuration management module. The system status detection unit 11120 is configured to monitor the on-chip system operation status and determine whether an FPGA reconfiguration event has occurred. The configuration request generation unit 11130 is configured to generate a reconfiguration request signal when an FPGA reconfiguration event occurs, based on the judgment result of the system status detection unit. The status receiving and processing unit 11140 is configured to acquire status signals of the FPGA configuration process; and, if the acquired status signal indicates that the reconfiguration is complete, to perform system interface reinitialization and / or configuration parameter update.

[0040] In this context, the configuration management driver unit 11110 in the firmware of the multi-core RISC-V processor serves as the core of the upper-layer management logic, scheduling various sub-modules to complete configuration control tasks. In some exemplary embodiments, the configuration management driver (unit) is written in C language, runs in the RISC-V system firmware or RTOS operating system environment, and provides one or more of the following functional interfaces: The reconfiguration request API interface allows applications or system calls to initiate reconfiguration. Configuration status query API interface, used to obtain configuration status in real time; Configure the callback function; The Error Interrupt Service Routine (ISR) interface handles configuration failure status feedback from the FPGA side.

[0041] The configuration management driver (unit) adopts an event-driven model, which reduces CPU resource consumption and supports application layer instruction calls and automatic system scheduling.

[0042] As can be seen, the configuration management driver unit 11110 serves as the core of execution coordination for the entire RISC-V side configuration process. It operates in an event-driven mode, monitoring events or signals generated during configuration management, including any of the following: init signal, program signal, done signal, error signal, interrupt response event, and timeout event, thereby scheduling other functional units in the RISC-V configuration management module. The configuration management driver unit 11110 acts as the event scheduler for the entire configuration process, implementing event / signal management. Scheduling (Sub) Unit Call An automated configuration and execution mechanism for a closed-loop process.

[0043] In some exemplary embodiments, the configuration management driving unit 11110 triggers the execution of corresponding functional units based on the type of event or signal, including one or more of the following: The scheduling configuration interface unit 11160 completes the handshake and register operations for the program, init, and done signals; The scheduling system status detection unit 11120 performs configuration status polling to monitor the system's operating status; The scheduling configuration failure handling unit 11150 executes a rollback, reset, or reconfiguration process when an error or timeout event occurs.

[0044] The system status detection unit 11120 monitors the system operating status and determines whether the FPGA needs to be reconfigured. That is, it monitors the on-chip system operating status and determines whether an FPGA reconfiguration event has occurred. If it has, it sends a reconfiguration request signal to the FPGA.

[0045] In some exemplary embodiments, the system status detection unit 11120 monitors the following events: Changes in application layer functional requirements, such as user requests to switch application modes; System fault detection, such as CRC check errors and hardware malfunctions; Load monitoring allows for mode switching to optimize power consumption or improve performance. Firmware upgrade requirement.

[0046] An FPGA reconfiguration event is determined to have occurred when any of the above events is detected. It is understood that other events may also be monitored as needed for the application, and are not limited to the aspects described in this disclosure.

[0047] Based on the judgment result of the system status detection unit 11120, the configuration request generation unit 11130 generates a reconfiguration request signal and sends it to the FPGA when an FPGA reconfiguration event occurs.

[0048] In some exemplary embodiments, the configuration request generation unit 11130 uses an AXI interface to interact with the FPGA; or, it uses a GPIO interface to interact with the FPGA.

[0049] In some exemplary embodiments, the configuration request generation unit 11130 uses the AXI Lite interface to interact with the FPGA via registers. The RISC-V, acting as the AXI Lite Master, writes the "PROGRAM_REQ" flag to the configuration register (e.g., address 0x00, position 1) through register write operations, thus sending a reconfiguration request signal to the FPGA. In some exemplary embodiments, the reconfiguration request signal also includes additional parameters indicating a configuration file number or a mode identifier, to instruct the FPGA to load configuration data according to the configuration file number for reconfiguration; or, to load corresponding configuration data according to the mode identifier for reconfiguration.

[0050] In some exemplary embodiments, the configuration request generation unit 11130 uses a GPIO interface to interact with the FPGA, including controlling the GPIO signal line to send a high level as a configuration request signal. Optionally, a handshake mechanism is added to prevent signal loss.

[0051] As can be seen, after the configuration request generation unit 11130 generates and sends a reconfiguration request signal to the FPGA, the status receiving and processing unit 11140 waits for the feedback signal from the FPGA.

[0052] The status receiving and processing unit 11140 acquires status signals during the FPGA configuration process to determine whether the configuration was successful or failed. Similarly, this can be achieved using an AXI interface or a GPIO interface. For example, using the AXI Lite reading method, the status code in the FPGA-side status register (e.g., address 0x04) can be read; status code 0x03 indicates configuration completion, and 0xFF indicates configuration failure. Alternatively, the done signal and / or error signal can be received via GPIO.

[0053] In some exemplary embodiments, the status receiving and processing unit 11140 uses a GPIO interface to interact with FPGA and adds a dual-flip-flop synchronization and debouncing design to ensure signal stability.

[0054] In some exemplary embodiments, the status receiving and processing unit 11140 supports interrupt output, and the interrupt service routine reads the status register or GPIO signal to reduce polling.

[0055] In some exemplary embodiments, the RISC-V configuration management module 1110 further includes the following sub-module: a configuration interface unit 11160. This interface unit interfaces with the FPGA configuration interface unit 12150, using AXI or GPIO for signal interaction.

[0056] In some exemplary embodiments, the RISC-V configuration management module 1110 further includes the following sub-module: configuration failure handling unit 11150.

[0057] As can be seen, when the acquired status signal "done" indicates that the reconfiguration is complete, the status receiving and processing unit performs system interface reinitialization and / or configuration parameter update; If the status signal indicates a configuration failure, the configuration failure handling unit 11150 performs any of the following exception handling: The configuration request generation unit is invoked to generate a reconfiguration request signal again; Switch to the backup FPGA and power it on; Switch to backup configuration data; Start the system's fault protection function.

[0058] After successful FPGA reconfiguration, the multi-core RISC-V processor further completes system reinitialization and / or resource updates to ensure a smooth transition of the on-chip system to the new configuration. The on-chip system performs one or more of the following operations to achieve the overall configuration update: peripheral bus rescanning, interrupt vector table update, configuration parameter synchronization, FPGA memory mapping area reloading, current configuration version information update, logging, etc.

[0059] In the event of a configuration failure, corresponding exception handling and recovery are performed. In some exemplary embodiments, the error code register in the FPGA (e.g., address 0x08) is read to distinguish the error type, for example: 0xE1. CRC check failed; 0xE2 Storage read timeout; 0xE3 Configuration interface exceptions, etc. Depending on the error type indicated by the error code, one or more exception handling procedures will be executed.

[0060] In some exemplary embodiments, a reconfiguration request signal is sent to the FPGA again according to the set maximum number of retries; optionally, a set time interval is set between multiple requests. In some exemplary embodiments, exception handling includes: powering down the FPGA that failed to configure and powering on the backup FPGA to achieve backup FPGA switching. In some exemplary embodiments, exception handling includes: sending a reconfiguration request signal to instruct the FPGA to load backup configuration data, such as indicating a backup configuration file number.

[0061] In some exemplary embodiments, activating the system anomaly protection function includes one or more of the following: the on-chip system enters safe mode operation, or the set function module is turned off.

[0062] In some exemplary embodiments, when the status signal indicates a configuration failure, the configuration failure processing unit 11150 also performs a logging step to record failure-related information, including: time, error code, etc. Further details of the logging process are not discussed here.

[0063] As can be seen, the RISC-V architecture is open and customizable, allowing for configuration of the number of cores, privilege levels, and extended instruction sets (e.g., P extensions for low-power control) according to different scenarios. When a multi-core RISC-V is deployed in a SoC, each core can run independently or collaboratively execute different configuration tasks, allowing one core to act as the configuration control master core while other cores are in standby or task state. This architectural characteristic is highly compatible with the reconfigurability of FPGAs, enabling the configuration process to be more flexibly mapped to multi-threaded tasks, with tasks distributed among different cores, thereby improving overall configuration speed and reliability. This disclosure provides a system-on-a-chip based on a multi-core RISC-V processor and FPGA architecture, fully utilizing the customizability and adaptability of the RISC-V architecture, the programmability of the FPGA, and the bidirectional collaborative configuration mechanism proposed by the lock, resulting in stronger system compatibility and error recovery capabilities. A clear signal interface is defined between the FPGA and the multi-core RISC-V processor, supporting online reconfiguration during operation.

[0064] In some exemplary embodiments, the multi-core RISC-V processor can initiate the reconfiguration process based on operating system-level interrupts or timed triggering mechanisms, while the FPGA side uses a state machine to ensure strict state monitoring and response to the configuration process, thus guaranteeing the flexibility and reliability of the on-chip system reconfiguration scheme.

[0065] Employing a multi-core RISC-V processor, it supports customizable core functions, allowing the use of a minimum safe core as either a boot core or a configuration core. The bootloader is user-defined, and configuration tasks can be asynchronously and independently scheduled among multiple cores. Compared to traditional closed processor cores, such as ARM processors, the on-chip architecture based on the multi-core RISC-V processor clearly defines the configuration process, establishes smooth bidirectional configuration signal interaction, and complements the programmable characteristics of FPGAs.

[0066] This disclosure also provides a system-on-a-chip configuration method, wherein the system-on-a-chip includes: a multi-core RISC-V processor and a field-programmable gate array (FPGA), such as... Figure 4 As shown, the method includes: Step 410: After the FPGA powers on and completes the initial configuration, it sends an initial configuration completion signal (init signal) to the multi-core RISC-V processor. Step 420: The multi-core RISC-V processor starts the bootloader based on the initial configuration completion signal; Step 430: In the event of an FPGA reconfiguration event, the multi-core RISC-V processor sends a reconfiguration request signal (program signal) to the FPGA; Step 440: The FPGA retrieves new configuration data from the set storage location, completes the reconfiguration, and sends a reconfiguration completion signal (done signal) to the multi-core RISC-V processor. Step 450: Based on the reconfiguration completion signal, the multi-core RISC-V processor performs system interface reinitialization and / or configuration parameter update.

[0067] In some exemplary embodiments, such as Figure 5 As shown, it also includes: Step 460: If an exception occurs during the initial configuration or reconfiguration process, the FPGA sends a configuration failure signal (error signal) to the multi-core RISC-V processor. Step 470: Based on the configuration failure signal, the multi-core RISC-V processor performs any of the following exception handling: Send the reconfiguration request signal (program signal) to the FPGA again; Switch to the backup FPGA and power it on; Switch to backup configuration data; Start the system's fault protection function.

[0068] As can be seen, in step 410, the FPGA automatically loads configuration data after power-on. This process is called the initial configuration process, also known as the self-configuration process. Before step 410, there is also step 400, where the system powers on, initializes each power domain, and performs a global reset; that is, after the on-chip system powers on, the main DC-DC converter converts the input power to the voltage required by each module and triggers a global reset to ensure that all modules of the system are in the initial state.

[0069] In step 410, the Bitstream at the preset storage location is loaded to achieve self-configuration. After the configuration is completed, the FPGA configuration control module starts and detects the self-configuration status. It sends an initial configuration completion signal (init) to the multi-core RISC-V processor through the configuration interface unit 12150, indicating that the self-configuration is complete. In step 420, the RISC-V configuration management module starts the bootloader to complete system initialization based on the signal. Thus, the on-chip system begins normal operation. During operation, the RISC-V configuration management module detects an FPGA reconfiguration event, requiring the FPGA to be reconfigured, and then executes step 430. In step 430, the RISC-V configuration management module issues a reconfiguration request signal (program). In step 440, the FPGA configuration control module enters the reconfiguration process, loads new configuration data from memory, and executes the configuration. After the configuration is completed, the FPGA configuration control module sends back a reconfiguration completion signal (done). In step 450, after receiving the reconfiguration completion signal (done), the RISC-V configuration management module reinitializes some modules of the system to achieve configuration switching.

[0070] In some exemplary embodiments, the FPGA reconfiguration event includes any of the following events: FPGA application switching, FPGA configuration data upgrade, FPGA fault recovery, and FPGA power consumption optimization.

[0071] The occurrence of any of the above events signifies the need for FPGA reconfiguration. The RISC-V configuration management module then sends a reconfiguration request signal, triggering the FPGA to reload its configuration data for reconfiguration. Specifically, FPGA application switching refers to the need for the FPGA to be reconfigured to execute other application functions, or different modes of the same application function, based on the on-chip system's operational requirements. This is achieved by reloading different configuration data (Bitstream) onto the FPGA and coordinating with the multi-core RISC-V processor for reinitialization, enabling online switching without system downtime. FPGA configuration data upgrade refers to the need to reload new configuration data for application function upgrades or bug fixes. FPGA fault recovery refers to addressing system problems caused by FPGA malfunctions by loading new configuration data. FPGA power optimization refers to the need for the FPGA to enter a lower power consumption operating state in certain application scenarios during system operation, which can be achieved by modifying and reloading the configuration data. Optionally, other events requiring FPGA reconfiguration can be defined as needed, and the methods for monitoring these events are not particularly limited.

[0072] In the above process of some exemplary embodiments, the state transitions of the state machine in the FPGA configuration control module are as follows: After the system is powered on and the initial configuration is completed, the state machine enters the Init state and sends an init signal to the multi-core RISC-V side; The multi-core RISC-V processor has completed startup and issues program signals as needed during operation; When the FPGA receives the program signal, the state machine enters the Programming state and activates the data loading unit to perform reconfiguration. The data loading unit reads the configuration data through the storage interface unit, performs CRC verification, and moves it to the FPGA configuration path via DMA. Once configured, the state machine enters the done state and sends a done signal to the multi-core RISC-V processor through the state feedback unit.

[0073] During this process, the configuration interface unit in the FPGA configuration control module maintains continuous communication with the RISC-V side, and state changes can be fed back in real time via interrupt signals. If any abnormality occurs during the initial configuration and reconfiguration process, such as CRC check failure or read / write timeout, the state machine transitions to the error state and sends an error signal carrying failure information to the multi-core RISC-V processor for exception handling.

[0074] As can be seen, the on-chip system configuration scheme provided in this disclosure establishes a bidirectional configuration mechanism between the FPGA and the multi-core RISC-V processor. This allows the FPGA to boot the RISC-V system at system startup, and the RISC-V to trigger FPGA reconfiguration during operation, meeting the dynamic upgrade requirements of the system. During system operation, the configuration can be dynamically adjusted according to the system status, enabling on-demand reloading of configurations and avoiding unnecessary resource waste. Simultaneously, fault detection ensures a high configuration success rate. Based on a unified configuration interface and status feedback mechanism, system debugging, fault diagnosis, and parameter optimization are more convenient, facilitating future expansion to other configuration schemes or peripheral integration. A closed loop is formed between the RISC-V-side configuration management module and the FPGA configuration control module, providing real-time status feedback, supporting online configuration debugging and parameter updates, and improving the overall reliability of the on-chip system.

[0075] In some exemplary embodiments, the exceptions that occur when the FPGA performs the initial configuration or the reconfiguration include any of the following: configuration data verification failure, configuration data timing exception, memory read exception, and configuration interface exception.

[0076] As can be seen, during the FPGA's data configuration process, if any of the above-mentioned anomalies (failures / errors) are detected, the FPGA configuration control module sends a configuration failure signal (error signal) to the multi-core RISC-V processor, which then handles the corresponding anomaly. Thus, based on bidirectional dynamic configuration, a closed-loop feedback of the configuration status is formed, ensuring the reliability of dynamic configuration.

[0077] In some exemplary embodiments, the method further includes: after the multi-core RISC-V processor and FPGA are powered on, performing the following steps to complete the handshake: The multi-core RISC-V processor sends a reconfiguration request signal (program signal) to the FPGA; The FPGA sends a reconfiguration complete signal (done signal) to the multi-core RISC-V processor; The multi-core RISC-V processor sends a handshake acknowledgment signal (ack signal) to the FPGA.

[0078] Before executing step 410, the aforementioned handshake sequence protection mechanism is introduced to prevent the impact of accidental triggering, glitches, or unknown states during the initial power-on period on the configuration and reconfiguration process. Specifically, compared to step 430, the reconfiguration request signal and reconfiguration completion signal in step 440 can carry different signal parameters to indicate the currently executing handshake sequence.

[0079] It should be noted that the multi-core RISC-V processor and the FPGA use AXI or GPIO interfaces for signal interaction. For different signals, a unified interface method can be used, or different interface types can be used according to the characteristics of the signals, without being limited to a specific aspect.

[0080] This disclosure also provides an electronic device, including: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the on-chip system configuration method as described in any embodiment of this disclosure.

[0081] The on-chip configuration scheme provided in this disclosure fully demonstrates the design advantages of tight coupling between FPGA and RISC-V architecture in terms of multi-core scheduling cooperation, configuration flow control freedom, and module interface decoupling. A bidirectional interactive configuration mechanism between FPGA and RISC-V is established, enabling not only RISC-V to proactively initiate FPGA reconfiguration but also timely feedback of the configuration status to the main system, fully meeting the needs of dynamic on-chip applications and remote upgrades.

[0082] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0083] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A system-on-a-chip, characterized in that, include: Multi-core RISC-V processors and field-programmable gate arrays (FPGAs); The FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after power-on and initial configuration completion. The multi-core RISC-V processor is configured to, upon the initial configuration completion signal, start the bootloader; and, in the event of an FPGA reconfiguration event, send a reconfiguration request signal to the FPGA. The FPGA is also configured to set a storage location to obtain new configuration data, and after completing the reconfiguration, send a reconfiguration completion signal to the multi-core RISC-V processor. The multi-core RISC-V processor is also configured to perform system interface reinitialization and / or configuration parameter update based on the reconfiguration completion signal.

2. The system-on-a-chip according to claim 1, characterized in that, The FPGA includes: an FPGA configuration control module, which includes: a state machine control unit, a data loading unit, and a state feedback unit; The state machine control unit is configured to control the transitions between multiple states during the PFGA configuration process; the states include: idle, initial configuration completed, configuration in progress, reconfiguration completed, and configuration failed; The data loading unit is configured to read configuration data from the memory and load it into the FPGA configuration channel; The status feedback unit is configured to acquire status signals during the configuration process and feed them back to the multi-core RISC-V processor.

3. The system-on-a-chip according to claim 1 or 2, characterized in that, The multi-core RISC-V processor includes a RISC-V configuration management module; the RISC-V configuration management module includes the following sub-modules: a configuration management driver unit, a system status detection unit, a configuration request generation unit, and a status receiving and processing unit; The configuration management driver unit is configured to use an event-driven model to schedule the operation of other sub-modules in the RISC-V configuration management module; The system status detection unit is configured to monitor the on-chip system's operating status and determine whether an FPGA reconfiguration event has occurred. The configuration request generation unit is configured to generate a reconfiguration request signal when an FPGA reconfiguration event occurs, based on the judgment result of the system status detection unit. The status receiving and processing unit is configured to acquire status signals during the FPGA configuration process; and, if the acquired status signal indicates that reconfiguration is complete, to perform system interface reinitialization and / or configuration parameter update.

4. The system-on-a-chip according to claim 3, characterized in that, The RISC-V configuration management module also includes the following sub-module: a configuration failure handling unit; The configuration failure handling unit is configured to perform any of the following exception handling operations when the status signal indicates a configuration failure: The configuration request generation unit is invoked to generate a reconfiguration request signal again; Switch to the backup FPGA and power it on; Switch to backup configuration data; Start the system's fault protection function.

5. The system-on-a-chip according to claim 2, characterized in that, The FPGA configuration control module further includes: a configuration interface unit; The configuration interface unit is configured to interact with the multi-core RISC-V processor via the Advanced Extensible Interface (AXI); or, via the General Purpose Input / Output (GPIO) interface.

6. The system-on-a-chip according to claim 5, characterized in that, The configuration interface unit is configured to use the AXI Lite protocol to interact with the multi-core RISC-V processor via registers in the FPGA. The registers include at least one of the following types: configuration status register, error code register, and configuration command register.

7. The system-on-a-chip according to claim 5, characterized in that, The configuration interface unit is configured to interact with the multi-core RISC-V processor using the following 4-wire general purpose input / output (GPIO) interface: The system includes an initial configuration completion signal output, a reconfiguration completion signal output, a reconfiguration request signal input, and a configuration failure signal output.

8. A method for configuring an on-chip system, characterized in that, The system-on-a-chip includes a multi-core RISC-V processor and a field-programmable gate array (FPGA), and the method includes: After the FPGA powers on and completes the initial configuration, it sends an initial configuration completion signal to the multi-core RISC-V processor. The multi-core RISC-V processor starts the bootloader based on the initial configuration completion signal; In the event of an FPGA reconfiguration event, the multi-core RISC-V processor sends a reconfiguration request signal to the FPGA; The FPGA retrieves new configuration data from a set storage location, completes the reconfiguration, and sends a reconfiguration completion signal to the multi-core RISC-V processor. The multi-core RISC-V processor performs system interface reinitialization and / or configuration parameter update based on the reconfiguration completion signal.

9. The method according to claim 8, characterized in that, The method further includes: if the FPGA encounters an anomaly during the initial configuration or reconfiguration, it sends a configuration failure signal to the multi-core RISC-V processor; The multi-core RISC-V processor performs any of the following exception handling based on the configuration failure signal: Send a reconfiguration request signal to the FPGA again; Switch to the backup FPGA and power it on; Switch to backup configuration data; Start the system's fault protection function.

10. The method according to claim 8 or 9, characterized in that, The FPGA reconfiguration event includes any of the following events: FPGA application switching, FPGA configuration data upgrade, FPGA fault recovery, and FPGA power consumption optimization.

11. The method according to claim 9, characterized in that, The exception that occurs when the FPGA performs the initial configuration or the reconfiguration includes any of the following: Configuration data verification failed, configuration data timing error occurred, memory read error occurred, and configuration interface error occurred.

12. The method according to claim 8 or 9, characterized in that, The method further includes: after the multi-core RISC-V processor and FPGA are powered on, the following steps are performed to complete the handshake: The multi-core RISC-V processor sends a reconfiguration request signal to the FPGA; The FPGA sends a reconfiguration complete signal to the multi-core RISC-V processor; The multi-core RISC-V processor sends a handshake response signal to the FPGA.

13. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the on-chip system configuration method as described in any one of claims 8-12.

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