An adaptive conditional semiconductor chip array test system

Abstract

The application relates to the technical field of semiconductor chips, and discloses a self-adaptive semiconductor chip array test system, which comprises a PC end, a semiconductor device array and a control module, the PC end and the semiconductor device array are connected with the control module respectively, the control module comprises an acquisition unit, a gating array unit, an impedance adjustment unit and a test unit, the acquisition unit is used for acquiring semiconductor device signals and determining a gating mode according to the semiconductor device signals, the gating array unit is used for determining a switching speed and a conduction resistance according to the gating mode, the impedance adjustment unit is used for adjusting a channel resistance value to a target resistance value, and the test unit is used for applying excitation to a device to be tested of the semiconductor device array and controlling the acquisition unit to acquire a response signal of the device to be tested. The application remarkably improves the test efficiency and precision.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip technology, and more specifically, to an adaptive semiconductor chip array testing system. Background Technology

[0002] In the context of today's technological advancements, the fabrication and application of large-scale semiconductor devices are increasingly becoming a research hotspot. However, the testing and application of large-scale device arrays often require significant time and effort, and the experimental procedures are relatively cumbersome. For example, in the testing phase of semiconductor devices such as memristors and photodetectors, the limited number of devices that can be tested at one time due to equipment limitations results in a considerable time commitment to complete the entire testing task. Furthermore, because most semiconductor devices are relatively small, testing operations typically need to be performed under a microscope. If each test requires precise alignment of the device under a microscope, this undoubtedly reduces testing efficiency considerably, making the entire testing process more complex and time-consuming.

[0003] Therefore, it is necessary to design an adaptive semiconductor chip array testing system to address the problems existing in the current technology. Summary of the Invention

[0004] In view of this, the present invention proposes an adaptive condition semiconductor chip array test system, which aims to realize rapid switching between different devices in a semiconductor device array, simplify the test process, and improve test efficiency.

[0005] This invention proposes an adaptive condition semiconductor chip array testing system, comprising:

[0006] The system comprises a PC terminal, a semiconductor device array, and a control module, wherein the PC terminal and the semiconductor device array are respectively connected to the control module; the control module includes an acquisition unit, a gating array unit, an impedance adjustment unit, and a testing unit.

[0007] The acquisition unit is used to acquire signals from semiconductor devices and determine the gating mode based on the semiconductor device signals;

[0008] The gating array unit is used to determine the switching speed and on-resistance according to the gating mode;

[0009] The impedance adjustment unit is used to adjust the path resistance to the target resistance value;

[0010] The test unit is used to apply excitation to the device under test (DUT) of the semiconductor device array and control the acquisition unit to acquire the response signal of the DUT.

[0011] Further, determining the gating mode based on the semiconductor device signal includes:

[0012] The response signal voltage of the device under test is detected by an ADC and converted into a digital signal.

[0013] The digital signal is obtained by using a digital signal processing algorithm, and the gating mode is determined based on the feature data.

[0014] Furthermore, the gating modes include: sequential gating, reverse gating, cyclic gating, and random gating.

[0015] Furthermore, the gating array unit consists of five analog switch chips, which are high-speed, low-resistance analog switch chips.

[0016] Further, when determining the switching speed and on-resistance based on the gating mode, the following steps are included:

[0017] When the gating mode is sequential gating, the switching speed is determined to be the first switching speed, and the on-resistance is determined to be the first on-resistance;

[0018] When the gating mode is reverse gating, the switching speed is determined to be the second switching speed, and the on-resistance is determined to be the second on-resistance.

[0019] When the gating mode is cyclic gating or random gating, the switching speed is determined to be the third switching speed, and the on-resistance is determined to be the third on-resistance;

[0020] Wherein, the first switching speed is less than the second switching speed, and the second switching speed is less than the third switching speed; the first on-resistance is greater than or equal to the second on-resistance, and the second on-resistance is greater than the third on-resistance.

[0021] Furthermore, adjusting the path resistance to the target resistance includes:

[0022] The average resistance of the semiconductor device array is collected, the average resistance is compared with the average resistance threshold, and the resistance of the path is adjusted according to the comparison result.

[0023] When the average resistance is less than or equal to the average resistance threshold, the impedance adjustment unit increases the path resistance to the target resistance.

[0024] When the average resistance is greater than the average resistance threshold, the impedance adjustment unit lowers the path resistance to the target resistance.

[0025] Furthermore, the test unit includes several semiconductor test devices; the semiconductor test devices include one or more of the following: source meter, Keithley 4200, Agilent 4155b, oscilloscope, and signal generator.

[0026] Furthermore, the control module controls the test operation of the test unit through level triggering or interface communication.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] The semiconductor device array testing system proposed in this invention has excellent compatibility and can be adapted to a variety of semiconductor testing equipment.

[0029] This invention can employ either low-impedance analog switch chips to reduce interference with semiconductor device parameter testing, or high-speed analog switch chips to achieve rapid testing of semiconductor devices through quick switching of analog switches. Furthermore, this system also supports the use of high-speed, low-impedance analog switch chips to meet the needs of different application scenarios.

[0030] This invention introduces an impedance adjustment module, which can automatically adjust to the target impedance according to the actual needs of the semiconductor device through the control module, thereby regulating the current flowing through the semiconductor device, ensuring the stability of semiconductor device testing, and simplifying the data processing flow.

[0031] This invention employs a closed-loop control system, comprising PC software, a control unit, a gating circuit, and a semiconductor array. The PC software sends adjustment commands to the control unit based on the acquired semiconductor device test results. The control unit then further regulates the gating circuit and impedance adjustment unit, thereby altering the path of the semiconductor array (including signal impedance and signal channel), significantly improving testing efficiency and accuracy.

[0032] The design of this invention is simple and clear, with low cost, making it easy for designers to master and apply in practical design work. Attached Figure Description

[0033] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0034] Figure 1 This is a structural block diagram of an adaptive condition semiconductor chip array testing system provided in an embodiment of the present invention. Detailed Implementation

[0035] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, embodiments and features in the embodiments of the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] See Figure 1 As shown in some embodiments of this application, this embodiment provides an adaptive condition semiconductor chip array testing system, including:

[0037] The system comprises a PC terminal, a semiconductor device array, and a control module, wherein the PC terminal and the semiconductor device array are respectively connected to the control module; the control module includes an acquisition unit, a gating array unit, an impedance adjustment unit, and a testing unit.

[0038] The acquisition unit is used to acquire signals from semiconductor devices and determine the gating mode based on the semiconductor device signals;

[0039] The gating array unit is used to determine the switching speed and on-resistance according to the gating mode;

[0040] The impedance adjustment unit is used to adjust the path resistance to the target resistance value;

[0041] The test unit is used to apply excitation to the device under test (DUT) of the semiconductor device array and control the acquisition unit to acquire the response signal of the DUT.

[0042] In this embodiment, the analog switch strobe signals (specifically, the signals output by the 5-bit counter module) A4, A3, A2, A1, and A0 in the control module, as well as the chip strobe signal EN, are all generated by the STM32 system. These signals primarily perform the following five functions: First, they control the gating array unit, regulating the connection between semiconductor devices and test equipment according to specific rules to achieve signal acquisition or measurement; second, they acquire signals from semiconductor devices through the gating array unit and adjust the working mode of the gating array accordingly, including but not limited to gating speed, gating sequence, and gating of specific devices; third, they establish communication with test instruments, using serial interface communication (such as GPIB, UART, etc.) to remotely control the test operation of the test equipment, such as sending commands to start, stop, pause, and test simulation; fourth, they establish a communication bridge with the PC via the serial port, receiving control commands from the PC and setting control parameters, such as gating speed, gating sequence, gating count, and controlling the start, stop, and pause of gating, to achieve precise control of the gating array's operation; fifth, they also communicate with the PC via the serial port, feeding back the semiconductor device signals or scan status (such as current gating parameters) acquired by the control module to the PC, so as to facilitate real-time monitoring of the working status of the control unit, gating array, and semiconductor devices.

[0043] It is understood that the adaptive semiconductor chip array testing system provided in this embodiment can achieve efficient testing of semiconductor device arrays. During the testing process, the system can automatically select appropriate test modes and parameters according to the characteristics of the semiconductor devices, thereby ensuring the accuracy and repeatability of the test. In this way, the testing system of the present invention not only improves testing efficiency but also reduces testing costs, providing strong technical support for the mass production and quality control of semiconductor devices.

[0044] Specifically, determining the gating mode based on the semiconductor device signal includes:

[0045] The response signal voltage of the device under test is detected by an ADC and converted into a digital signal.

[0046] The digital signal is obtained by using a digital signal processing algorithm, and the gating mode is determined based on the feature data.

[0047] In this embodiment, the ADC is an analog-to-digital converter, used to convert analog signals into digital signals for computer processing. The conversion accuracy and speed of the ADC directly affect the performance of the test system. In this invention, the use of an ADC ensures high accuracy and efficiency in signal acquisition, thereby providing a reliable data foundation for subsequent digital signal processing.

[0048] In this embodiment, the feature data includes the amplitude, frequency, and phase information of the response signal. Using this feature data, the system can identify specific states and performance parameters of the semiconductor device, thereby selecting the most suitable test mode. For example, for high-speed switching devices, the system prioritizes the rise and fall times of the signal, while for low-noise amplifiers, it focuses more on the signal-to-noise ratio and linearity.

[0049] Specifically, the gating modes include: sequential gating, reverse gating, cyclic gating, and random gating.

[0050] In this embodiment, sequential gating refers to the sequential gating of devices 0 to n, reverse gating refers to the sequential gating of devices n to 0, cyclic gating refers to the cyclic gating of devices 0 to n to 0..., and random gating refers to the random gating of certain arrays for targeted testing, such as gating only devices 0, 8, 13, 25...

[0051] Specifically, the gating array unit consists of five analog switch chips, which are high-speed, low-resistance analog switch chips.

[0052] In this embodiment, in practical applications, the control module dynamically adjusts the operating mode of the gating array units according to the size of the semiconductor device array and the testing requirements. For example, when a full scan test of the entire array is required, the system will use a sequential gating mode; while when testing a specific area or a specific device, a reverse gating or cyclic gating mode may be used. The random gating mode is suitable for scenarios that require repeated testing or fault diagnosis of specific devices.

[0053] Specifically, determining the switching speed and on-resistance based on the gating mode includes:

[0054] When the gating mode is sequential gating, the switching speed is determined to be the first switching speed, and the on-resistance is determined to be the first on-resistance;

[0055] When the gating mode is reverse gating, the switching speed is determined to be the second switching speed, and the on-resistance is determined to be the second on-resistance.

[0056] When the gating mode is cyclic gating or random gating, the switching speed is determined to be the third switching speed, and the on-resistance is determined to be the third on-resistance;

[0057] Wherein, the first switching speed is less than the second switching speed, and the second switching speed is less than the third switching speed; the first on-resistance is greater than or equal to the second on-resistance, and the second on-resistance is greater than the third on-resistance.

[0058] In this embodiment, the first on-resistance is set to ensure the stability and accuracy of signal transmission in sequential gating mode, because the signal transmission path is longer in sequential gating mode, requiring a larger on-resistance to reduce signal attenuation. The second on-resistance is set in reverse gating mode, where the signal transmission path is shorter, allowing for a reduction in on-resistance to improve signal transmission speed. As for cyclic or random gating modes, since frequent switching may be involved, a suitable on-resistance and switching speed need to be set to balance signal transmission stability and speed.

[0059] Specifically, adjusting the path resistance to the target resistance includes:

[0060] The average resistance of the semiconductor device array is collected, the average resistance is compared with the average resistance threshold, and the resistance of the path is adjusted according to the comparison result.

[0061] When the average resistance is less than or equal to the average resistance threshold, the impedance adjustment unit increases the path resistance to the target resistance.

[0062] When the average resistance is greater than the average resistance threshold, the impedance adjustment unit lowers the path resistance to the target resistance.

[0063] In this embodiment, the resistance value of the path is manually or automatically adjusted by a resistance adjustment device such as a variable resistor or a digital potentiometer to adjust the path resistance value to the target resistance value.

[0064] In this embodiment, the impedance adjustment unit ensures that the resistance of the semiconductor device array can be precisely controlled during testing to adapt to different test conditions and requirements. By monitoring and adjusting the path resistance in real time, the system can maintain the stability and accuracy of the test signal, thereby improving the overall reliability of the test. For example, when the test environment or device characteristics change, the impedance adjustment unit can quickly respond and adjust the path resistance to adapt to the new test conditions. This dynamic adjustment mechanism is an important feature of the test system of this invention, enabling the test system to adapt to various complex and changing test scenarios and ensuring the consistency and repeatability of test results.

[0065] Specifically, the test unit includes several semiconductor test devices; the semiconductor test devices include one or more of the following: source meter, Keithley 4200, Agilent 4155b, oscilloscope, and signal generator.

[0066] In this embodiment, the configuration of the test unit can be flexibly adjusted according to different testing requirements. For example, for tests requiring precise current control, a source meter can be used; while for applications requiring high-speed signal measurement, the Keithley 4200 semiconductor parameter analyzer and the Agile 4155B semiconductor parameter analyzer provide high-speed and high-precision signal measurement capabilities. An oscilloscope is used to observe and record signal waveforms, while a signal generator is used to generate the specific signals required for the test. Through the combined use of these devices, the test unit can perform various complex test tasks, including DC parameter testing, AC parameter testing, transient analysis, and frequency response analysis.

[0067] Specifically, the control module controls the test operation of the test unit through level triggering or interface communication.

[0068] In this embodiment, the control module controls the test operation of the test unit via either level triggering or interface communication. Level triggering allows the test system to start or stop the test immediately upon receiving a specific level signal, which is suitable for test scenarios requiring rapid response. Interface communication, on the other hand, exchanges data with the test unit through an interface, enabling more complex control logic and test process management.

[0069] In summary, the adaptive semiconductor chip array testing system provided in this example can flexibly adjust test parameters and operating procedures according to different testing requirements, thereby achieving efficient and accurate testing of semiconductor chip arrays. This system not only adapts to various testing conditions but also provides customized testing solutions for specific testing needs, greatly improving testing flexibility and efficiency. Furthermore, the system design considers signal stability and accuracy, ensuring the reliability and repeatability of test results, which is of great significance for the research and development and production of semiconductor devices. Through this adaptive testing system, product development cycles can be effectively shortened, testing costs reduced, and product market competitiveness improved.

[0070] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program goods. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program goods embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0071] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program goods according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0072] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0073] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An adaptive-conditioned semiconductor chip array test system, characterized by, The application relates to a semiconductor device array test system, which comprises a PC terminal, a semiconductor device array and a control module, wherein the PC terminal and the semiconductor device array are connected with the control module respectively; the control module comprises a collection unit, a gating array unit, an impedance adjustment unit and a test unit; the collection unit is used for collecting semiconductor device signals and determining a gating mode according to the semiconductor device signals; the gating array unit is used for determining a switching speed and a conduction resistance according to the gating mode; the impedance adjustment unit is used for adjusting a channel resistance value to a target resistance value; and the test unit is used for applying excitation to a device to be tested in the semiconductor device array and controlling the collection unit to collect a response signal of the device to be tested. When the gating mode is determined according to the semiconductor device signals, the following steps are included: the response signal voltage of the device to be tested is detected by an ADC, and the response signal voltage is converted into a digital signal; a digital signal processing algorithm is adopted to obtain characteristic data of the digital signal, and the gating mode is determined according to the characteristic data. The gating mode includes sequential gating, reverse sequential gating, cyclic gating and random gating. The gating array unit is composed of five analog switch chips, and the analog switch chips are high-speed low-resistance analog switch chips. When the switching speed and the conduction resistance are determined according to the gating mode, the following steps are included: when the gating mode is sequential gating, the switching speed is determined as a first switching speed, and the conduction resistance is determined as a first conduction resistance; when the gating mode is reverse sequential gating, the switching speed is determined as a second switching speed, and the conduction resistance is determined as a second conduction resistance; and when the gating mode is cyclic gating or random gating, the switching speed is determined as a third switching speed, and the conduction resistance is determined as a third conduction resistance; wherein the first switching speed is smaller than the second switching speed, the second switching speed is smaller than the third switching speed, the first conduction resistance is greater than or equal to the second conduction resistance, and the second conduction resistance is greater than the third conduction resistance. When the channel resistance value is adjusted to the target resistance value, the following steps are included: the average resistance value of the semiconductor device array is collected, the average resistance value is compared with an average resistance value threshold, and the channel resistance value is adjusted according to the comparison result; when the average resistance value is smaller than or equal to the average resistance value threshold, the channel resistance value is adjusted to the target resistance value by the impedance adjustment unit; and when the average resistance value is greater than the average resistance value threshold, the channel resistance value is adjusted to the target resistance value by the impedance adjustment unit.

2. The adaptive conditional semiconductor chip array test system of claim 1, wherein, The test unit comprises a plurality of semiconductor test devices; the semiconductor test devices include one or more of a source table, a Keithley 4200, an Agilent 4155b, an oscilloscope and a signal generator. The control module controls the test operation of the test unit by a level triggering mode or an interface communication mode. ​ 3. The adaptive conditional semiconductor chip array test system of claim 2, wherein, ​ 4. The self-adapting conditional semiconductor chip array test system of claim 1, wherein, ​ 5. The self-adapting conditional semiconductor chip array test system of claim 1, wherein, ​ ​ ​ ​ ​ 6. The self-adapting conditional semiconductor chip array test system of claim 1, wherein, ​ ​ ​ ​ 7. The adaptive-conditional semiconductor-chip-array test system of claim 1, wherein, ​ 8. The adaptive, conditional semiconductor chip array test system of claim 1, wherein, ​

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