Control circuit for controlling a display panel

Abstract

The present disclosure provides a control circuit for controlling a display panel. The control circuit includes a first driving circuit and a second driving circuit for driving the display panel. The first driving circuit includes a first output terminal and a first input terminal. The first driving circuit sequentially outputs a plurality of test signals to the first output terminal during different periods in a diagnosis stage. The second driving circuit includes a second input terminal and a second output terminal. The second driving circuit receives the test signals through the second input terminal in the diagnosis stage, and sequentially outputs a plurality of response signals to the second output terminal during the different periods in response to the test signals. The first driving circuit receives the response signals through the first input terminal, and determines a connection state of the first driving circuit and the second driving circuit according to the response signals.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a control circuit, and more particularly, to a control circuit for controlling a display panel. BACKGROUND

[0002] Current displays are becoming more and more complicated. A display requires two or more driving circuits to drive a display panel of the display. If the number of driving circuits is large, the circuit connections between the driving circuits become more complicated. Generally, if a circuit connection is abnormal, an operator or a maintenance person manually checks the abnormal connection point of the driving circuit one by one. The above manual checking method consumes a large amount of time cost at least.

[0003] Therefore, how to provide an automatic checking mechanism for checking the circuit connections between the driving circuits is one of the research focuses of the person skilled in the art. SUMMARY

[0004] The present disclosure provides a control circuit for controlling a display panel. The control circuit provides an automatic diagnosis mechanism for checking circuit connections of driving circuits in the control circuit.

[0005] The control circuit includes a first driving circuit and a second driving circuit. The first driving circuit is connected to a first portion of the display panel. The first driving circuit drives the first portion in an operation phase. The first driving circuit includes a first output terminal and a first input terminal. The first driving circuit sequentially outputs a plurality of test signals to the first output terminal during different periods in a diagnosis phase. The second driving circuit is connected to a second portion of the display panel. The second driving circuit drives the second portion in the operation phase. The second driving circuit includes a second input terminal and a second output terminal. The second input terminal is connected to the first output terminal in a one-to-one manner. The second output terminal is connected to the first input terminal in a one-to-one manner. The second driving circuit receives the test signals through the second input terminal in the diagnosis phase, and sequentially outputs a plurality of response signals to the second output terminal during different periods in the diagnosis phase in response to the test signals. The first driving circuit receives the response signals through the first input terminal in the diagnosis phase, and determines a connection state of the first driving circuit and the second driving circuit according to the response signals.

[0006] Based on the above, in the diagnosis phase, the second driving circuit sequentially outputs the response signals to the second output terminal during different periods in response to the test signals. The first driving circuit receives the response signals through the first input terminal in the diagnosis phase, and determines the connection state of the first driving circuit and the second driving circuit. Therefore, the control circuit provides an automatic diagnosis mechanism for checking the circuit connections of the first driving circuit and the second driving circuit.

[0007] In order to make the above-mentioned content more easily understood, several embodiments accompanied by the drawings are set forth in detail below. BRIEF DESCRIPTION OF DRAWINGS

[0008] The present disclosure includes drawings to provide further understanding of the present disclosure, and the drawings are incorporated into the present specification and form a part of the present specification. The drawings show exemplary embodiments of the present disclosure and are used to explain the principles of the present disclosure together with the present specification.

[0009] Figure 1 A schematic diagram of a display according to an embodiment of the present disclosure is shown.

[0010] Figure 2 A timing diagram of a test signal and a completion signal according to an embodiment of the present disclosure is shown.

[0011] Figure 3 An operation schematic diagram of a control circuit in a diagnosis phase according to an embodiment of the present disclosure is shown.

[0012] Figure 4 An operation schematic diagram of a control circuit in a diagnosis phase according to an embodiment of the present disclosure is shown.

[0013] Figure 5 An operation schematic diagram of a control circuit in a diagnosis phase according to an embodiment of the present disclosure is shown.

[0014] Figure 6 An operation schematic diagram of a control circuit in a diagnosis phase according to an embodiment of the present disclosure is shown.

[0015] Figure 7 An operation schematic diagram of a control circuit in a diagnosis phase according to an embodiment of the present disclosure is shown.

[0016] Figure 8 An operation schematic diagram of a control circuit in a diagnosis phase according to an embodiment of the present disclosure is shown.

[0017] Figure 9 A schematic diagram of a control circuit according to an embodiment of the present disclosure is shown.

[0018] Figure 10 A flowchart of an operation of a control circuit in a diagnosis phase according to an embodiment of the present disclosure is shown.

[0019] Figure 11 A schematic diagram of a control circuit according to an embodiment of the present disclosure is shown.

[0020] REFERENCE NUMERALS

[0021] 10: display

[0022] 100, 200, 300, 400: control circuit

[0023] 110, 210, 310, 410: first drive circuit

[0024] 120, 220, 420_1, 420_2 to 420_m: second drive circuit

[0025] 211: test signal generator

[0026] 212: determination circuit

[0027] 221: determination circuit

[0028] 222: response signal generator

[0029] 320_1, 320_2: second drive circuit / drive circuit

[0030] BS: connection bus

[0031] CK: system clock

[0032] P1: first part

[0033] P2: second part

[0034] PL: display panel

[0035] PR1, PR1', PR2: period

[0036] S110, S120, S130, S140, S150, S160: step

[0037] SAN: abnormality notification signal

[0038] SC: completion signal

[0039] SR1, SR2, SR3, SR4, SR5, SR6, SR7, SR8 to SR(n-3), SR(n-2), SR(n-1), SRn: response signal

[0040] ST1, ST2: test signal

[0041] TI1_1, TI2_1, TI3_1, TI4_1: first input

[0042] TI1_2, TI2_2, TI3_2, TI4_2: second input

[0043] TO1_1, TO2_1, TO3_1, TO4_1: first output

[0044] TO1_2, TO2_2, TO3_2, TO4_2: second output

[0045] TT1_1, TT2_1, TT3_1, TT4_1: first transmission terminal

[0046] TT1_2, TT2_2, TT3_2, TT4_2: second transmission terminal DETAILED DESCRIPTION

[0047] The present disclosure can be understood, by referring to the following detailed description in conjunction with the drawings described below. It should be noted that the various drawings of the disclosure show portions of electronic devices for the purpose of clarity and ease of understanding by the reader, and certain elements in the various drawings can not be drawn to scale. In addition, the number and size of each device shown in the drawings is merely illustrative and is not intended to limit the scope of the disclosure.

[0048] Certain terminology is used in the description and in the appended claims to refer to particular components. As one skilled in the art will appreciate, electronic device manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" or "coupled" as used herein is intended to mean either an indirect or direct electrical connection. Accordingly, when the term "couple" or "coupled" is used in the following description, that term is intended to mean either an indirect or direct electrical connection between two components.

[0049] It should be understood that when an element is referred to as being "coupled to", "connected to", or "conducted to" another element, it can be directly connected to the other element or an intervening element can be present for relaying the electrical connection (indirect electrical connection). In contrast, when an element is referred to as being "directly coupled to", "directly conducted to", or "directly connected to" another element, then there is no intervening element.

[0050] Figure 1 A schematic diagram of a display according to an embodiment of the disclosure is shown. Figure 1A display 10 including a display panel PL and a control circuit 100 is shown. In this embodiment, the control circuit 100 is configured to control the display panel PL. The control circuit 100 is a driving device configured to drive the display panel PL. The control circuit 100 includes a first driving circuit 110 and a second driving circuit 120. The first driving circuit 110 is connected to a first portion P1 of the display panel PL. The first driving circuit 110 drives the first portion P1 of the display panel PL in an operation phase. The second driving circuit 120 is connected to a second portion P2 of the display panel PL. The second driving circuit drives the second portion P2 of the display panel PL in the operation phase.

[0051] In this embodiment, the first driving circuit 110 includes first output terminals TO1_1, TO2_1 and first input terminals TI1_1, TI2_1. The first driving circuit 110 sequentially outputs test signals ST1, ST2 to the first output terminals TO1_1, TO2_1 during different periods in the diagnosis phase. For example, during a first period, the first driving circuit 110 outputs the test signal ST1 to the first output terminal TO1_1. During a second period, the first driving circuit 110 outputs the test signal ST2 to the first output terminal TO2_1.

[0052] In this embodiment, the second driving circuit 120 includes second input terminals TI1_2, TI2_2 and second output terminals TO1_2, TO2_2. The second input terminals TI1_2, TI2_2 are connected to the first output terminals TO1_1, TO2_1 in a one-to-one manner. The second output terminals TO1_2, TO2_2 are connected to the first input terminals TI1_1, TI2_1 in a one-to-one manner. For example, the second input terminal TI1_2 is connected to the first output terminal TO1_1. The second input terminal TI2_2 is connected to the first output terminal TO2_1. The second output terminal TO1_2 is connected to the first input terminal TI1_1. The second output terminal TO2_2 is connected to the first input terminal TI2_1.

[0053] In this embodiment, the second driving circuit 120 receives the test signals ST1, ST2 through the second input terminals TI1_2, TI2_2 in the diagnosis phase. In the diagnosis phase, the second driving circuit 120 sequentially outputs the response signals SR1, SR2 to the second output terminals TO1_2, TO2_2 during different periods in response to the test signals ST1, ST2. For example, after receiving the test signals ST1, ST2, the second driving circuit 120 outputs the response signal SR1 to the second output terminal TO1_2 during a third period, and then outputs the response signal SR2 to the second output terminal TO2_2 during a fourth period. In this embodiment, the second driving circuit 120 can determine the test signals ST1, ST2. When at least one of the test signals ST1, ST2 is abnormal, the second driving circuit 120 generates the response signals SR1, SR2 including abnormal information.

[0054] In this embodiment, in the diagnosis phase, the first driving circuit 110 receives the response signals SR1, SR2 through the first input terminals TI1_1, TI2_1. The first driving circuit 110 determines the connection state of the first driving circuit 110 and the second driving circuit 120 according to the response signals SR1, SR2.

[0055] For example, when the response signals SR1, SR2 include abnormal information, the first driving circuit 110 determines that the connection state of the first input terminals TI1_1, TI2_1 and the second output terminals TO1_2, TO2_2 is abnormal. For example, when the timing of the response signal SR1 is similar to the timing of the response signal SR2, the first driving circuit 110 determines that the connection state of the first input terminals TI1_1, TI2_1 and the second output terminals TO1_2, TO2_2 is abnormal. For example, the first output terminals TO1_1 and TO2_1 can be shorted to each other. For example, the first input terminals TI1_1 and TI2_1 can be shorted to each other. Thus, the first driving circuit 110 determines at least the connection state of the first input terminals TI1_1, TI2_1 and the second output terminals TO1_2, TO2_2.

[0056] It should be noted that, in the diagnosis phase, the second driving circuit 120 sequentially outputs the response signals SR1, SR2 during different periods in response to the test signals ST1, ST2. The first driving circuit 110 determines the connection state of the first driving circuit 110 and the second driving circuit 120. Thus, the control circuit 100 provides an automatic diagnosis mechanism for checking the circuit connection of the first driving circuit 110 and the second driving circuit 120. The control circuit 100 also improves the speed of checking the circuit connection of the first driving circuit 110 and the second driving circuit 120.

[0057] The diagnostic stage can be a test stage before shipment of the display 10 or before shipment of the control circuit 100. The diagnostic stage can be a test stage when the display 10 is started up.

[0058] In this embodiment, the first output terminals TO1_1, TO2_1, the first input terminals TI1_1, TI2_1, the second input terminals TI1_2, TI2_2, and the second output terminals TO1_2, TO2_2 are used to transmit signals in the operation stage. For example, each of the signals can be one of a horizontal synchronization signal, a vertical synchronization signal, a gate drive signal, a reset signal, and a data signal.

[0059] In this embodiment, each of the first drive circuit 110 and the second drive circuit 120 can be a drive integrated circuit (IC).

[0060] Further, when the connection state is ended, the first drive circuit 110 provides a completion signal SC to the second drive circuit through at least one of the first output terminals TO1_1, TO2_1. The second drive circuit 120 ends the diagnostic stage in response to the completion signal SC. Thus, the control circuit 100 leaves the connection state.

[0061] In this embodiment, the first drive circuit 110 is referred to as a master drive circuit. The second drive circuit 120 is referred to as a slave drive circuit.

[0062] In some embodiments, the control circuit 100 includes the first drive circuit 110 and at least two second drive circuits for driving different parts of the display panel PL. The present disclosure is not limited to the number of the second drive circuits of this embodiment.

[0063] Figure 2 A timing chart of the test signal and the completion signal according to an embodiment of the present disclosure is shown. Figure 2 A timing chart of the test signal ST1 and the completion signal SC is shown. Please refer to Figure 1 and Figure 2 In this embodiment, the first drive circuit 110 sets the waveform of the test signal ST1 according to a first cycle number of the system clock CK and a second cycle number of the system clock CK. The first drive circuit 110 sets the length of time of the high level of the test signal ST1 according to the first cycle number of the system clock CK. For example, the first drive circuit 110 sets the first cycle number as “4”, but the present disclosure is not limited to this. Thus, the length of time of the high level of the test signal ST1 is equal to 4 cycles of the system clock CK. The high level can be a high voltage level, a high current level, or a high logic level.

[0064] The first driving circuit 110 sets the length of time of the low level of the test signal ST1 according to the second number of cycles of the system clock CK. For example, the first driving circuit 110 sets the second number of cycles to be "2", but the present disclosure is not limited thereto. Thus, the length of time of the low level of the test signal ST1 is equal to 2 cycles of the system clock CK. The low level can be a low voltage level, a low current level, or a low logic level.

[0065] The first driving circuit 110 also notifies the second driving circuit 120 of the waveform of the test signal ST1. Thus, the second driving circuit 120 can recognize the test signal ST1.

[0066] In the present embodiment, the first driving circuit 110 sets the waveform of the test signal ST2 according to the first number of cycles of the system clock CK and the second number of cycles of the system clock CK. The waveform of the test signal ST2 is equal to the waveform of the test signal ST1. In some embodiments, the waveform of the test signal ST2 is not equal to the waveform of the test signal ST1. The first driving circuit 110 outputs the test signals ST1, ST2 during different periods.

[0067] In addition, the first driving circuit 110 sets the test cycle number of the test signal ST1 and the test cycle number of the test signal ST2. In the present embodiment, the test cycle number of the test signal ST1 is equal to the test cycle number of the test signal ST2. In some embodiments, the test cycle number of the test signal ST1 is not equal to the test cycle number of the test signal ST2.

[0068] In the present embodiment, the first driving circuit 110 sets the waveform of the completion signal SC according to the third number of cycles of the system clock CK and the fourth number of cycles of the system clock CK.

[0069] The first driving circuit 110 sets the length of time of the high level of the completion signal SC according to the first number of cycles of the system clock CK. For example, the first driving circuit 110 sets the first number of cycles to be "6", but the present disclosure is not limited thereto. Thus, the length of time of the high level of the completion signal SC is equal to 6 cycles of the system clock CK. The high level can be a high voltage level, a high current level, or a high logic level.

[0070] The first driving circuit 110 sets the length of time of the low level of the completion signal SC according to the second number of cycles of the system clock CK. For example, the first driving circuit 110 sets the first number of cycles to be "3", but the present disclosure is not limited thereto. Thus, the length of time of the low level of the completion signal SC is equal to 3 cycles of the system clock CK. The low level can be a low voltage level, a low current level, or a low logic level. The first driving circuit 110 also notifies the second driving circuit 120 of the waveform of the completion signal SC. Thus, the second driving circuit 120 can recognize the completion signal SC.

[0071] Figure 3 An operation schematic diagram of the control circuit in the diagnosis stage according to an embodiment of the present disclosure is shown. Please refer to Figure 3 In this embodiment, the control circuit 200 includes a first driving circuit 210 and a second driving circuit 220. The first driving circuit 210 includes first output terminals TO1_1, TO2_1, first input terminals TI1_1, TI2_1, and first transmission terminals TT1_1, TT2_1. The second driving circuit 220 includes second input terminals TI1_2, TI2_2, second output terminals TO1_2, TO2_2, and second transmission terminals TT1_2, TT2_2. The second input terminals TI1_2, TI2_2 are connected to the first output terminals TO1_1, TO2_1 in a one-to-one manner. The second output terminals TO1_2, TO2_2 are connected to the first input terminals TI1_1, TI2_1 in a one-to-one manner. The second transmission terminals TT1_2, TT2_2 are connected to the first transmission terminals TT1_1, TT2_1 in a one-to-one manner. For example, the second transmission terminal TT1_2 is connected to the first output transmission terminal TT1_1. The second transmission terminal TT2_2 is connected to the first transmission terminal TT2_1.

[0072] In the diagnosis stage, the first driving circuit 210 sequentially outputs test signals ST1, ST2 during different periods. The second driving circuit 220 receives the test signals ST1, ST2. The second driving circuit 220 sequentially outputs response signals SR1 to SR4 to the second output terminals TO1_2, TO2_2 and the second transmission terminals TT1_2, TT2_2 during different periods in the diagnosis stage in response to the test signals ST1, ST2. The first driving circuit 210 receives the response signals SR1 to SR4 through the first input terminals TI1_1, TI2_1 and the first transmission terminals TT1_1, TT2_1. The first driving circuit 210 determines the connection state of the first driving circuit 210 and the second driving circuit 220 according to the response signals SR1 to SR4.

[0073] In this embodiment, when the test signals ST1, ST2 are received at different periods, the second driving circuit 220 generates the response signals SR1 to SR4 without abnormal information. Therefore, when the response signals SR1 to SR4 without abnormal information are received at different periods, the first driving circuit 210 determines that the connection state is normal.

[0074] For example, the number of test cycles is set to "3", but the present disclosure is not limited thereto. Thus, the first driving circuit 210 outputs 3 test cycles of the test signal ST1 in the period PR1, and outputs 3 test cycles of the test signal ST2 in the period PR2. After receiving 3 test cycles of the test signal ST1 in the period PR1, the second driving circuit 220 starts to sequentially output the response signals SR1 to SR4 during different periods. For example, the second driving circuit 220 outputs the response signal SR1 in the fourth test cycle of the test signal ST1, outputs the response signal SR2 in the fifth test cycle of the test signal ST1, and so on.

[0075] In the present embodiment, the first driving circuit 210 outputs 3 test cycles of the test signal ST1 in the period PR1, and then outputs 3 test cycles of the test signal ST1 again in the period PR1'. In some embodiments, the period PR1' can be skipped.

[0076] In the present embodiment, the first driving circuit 210 further includes a test signal generator 211 and a determination circuit 212. The test signal generator 211 is connected to the first output terminals TO1_1, TO2_1. The test signal generator 211 generates the test signals ST1, ST2, and sequentially outputs the test signals ST1, ST2 during different periods. The determination circuit 212 is connected to the first input terminals TI1_1, TI2_1 and the first transmission terminals TT1_1, TT2_1. The determination circuit 212 receives the response signals SR1 to SR4 through the first input terminals TI1_1, TI2_1 and the first transmission terminals TT1_1, TT2_1. The determination circuit 212 determines the connection state of the first driving circuit 210 and the second driving circuit 220 according to the response signals SR1 to SR4.

[0077] The second driving circuit 220 further includes a determination circuit 221 and a response signal generator 222. The determination circuit 221 is connected to the second input terminals TI1_2, TI2_2. The response signal generator 222 is connected to the second output terminals TO1_2, TO2_2, the second transmission terminals TT1_2, TT2_2, and the determination circuit 221. The determination circuit 221 controls the response signal generator 222 to generate the response signals SR1 to SR4 according to the test signals ST1, ST2 received by the receiving circuit. When the waveforms and the timing of the test signals ST1, ST2 are normal, the determination circuit 221 controls the response signal generator 222 to generate the response signals SR1, SR2 without abnormal information. The response signal generator 222 sequentially outputs the response signals SR1 to SR4 without abnormal information during different periods. The response signals SR1 to SR4 without abnormal information can be referred to as pass signals.

[0078] When at least one of the test signals ST1, ST2 is abnormal, the determination circuit 221 controls the response signal generator 222 to generate the response signals SR1 to SR4 including abnormal information. The response signal generator 222 sequentially outputs the response signals SR1 to SR4 including abnormal information during different periods. The response signals SR1 to SR4 including abnormal information can be referred to as failure signals.

[0079] In the present disclosure, the first drive circuit 210 includes two or more first output terminals. The second drive circuit 220 includes two or more second output terminals. In the present disclosure, the total number of the first input terminals and the first transmission terminals is greater than "1". The total number of the second input terminals and the second transmission terminals is greater than "1".

[0080] In the present embodiment, at least one of the test signal generator 211 and the determination circuit 212 can be embedded in the first timing controller of the first drive circuit 210. In other words, the first timing controller can perform at least one operation of the test signal generator 211 and the determination circuit 212.

[0081] In the present embodiment, at least one of the determination circuit 221 and the response signal generator 222 can be embedded in the second timing controller of the first drive circuit 210. In other words, the second timing controller can perform at least one operation of the determination circuit 221 and the response signal generator 222.

[0082] Figure 4 An operation schematic diagram of the control circuit in the diagnosis phase according to an embodiment of the present disclosure is shown. Please refer to Figure 4 In the present embodiment, the test signal generator 211 sequentially outputs the test signals ST1, ST2 during different periods. However, the determination circuit 221 determines that the test signals ST1 and ST2 received by the second drive circuit have the same timing. This abnormal state indicates an abnormal short-circuit connection between the first output terminals TO1_1 and TO2_1.

[0083] Therefore, when at least two of the test signals ST1, ST2 received by the second drive circuit 220 have the same timing, the second drive circuit 220 generates the response signals SR1 to SR4 including abnormal information during different periods in the diagnosis phase. In the present embodiment, the determination circuit 212 determines that the connection state is abnormal according to the response signals SR1 to SR4 including abnormal information. Therefore, the determination circuit 212 outputs an abnormal notification signal SAN corresponding to such an abnormal state.

[0084] Figure 5 An operation schematic diagram of the control circuit in the diagnosis phase according to an embodiment of the present disclosure is shown. Please refer to Figure 5In this embodiment, the response signal generator 222 sequentially outputs the response signals SR1 to SR4 during different periods. However, the response signals SR1 and SR4 received by the first driving circuit 210 have the same timing. Such an abnormal state indicates (1) an abnormal short-circuit connection between the first input terminal TI1_1 and the first transmission terminal TT2_1; and / or (2) an abnormal short-circuit connection between the second output terminal TO1_2 and the second transmission terminal TT2_2.

[0085] Therefore, when at least two of the response signals SR1 to SR4 received by the determination circuit 212 of the first driving circuit 210 have the same timing, the determination circuit 212 determines that the connection state of the first driving circuit 210 and the second driving circuit 220 is abnormal.

[0086] In this embodiment, the first driving circuit 210 determines that the connection state is abnormal according to the response signals SR1 to SR4. Therefore, the determination circuit 212 outputs an abnormal notification signal SAN corresponding to such an abnormal state.

[0087] Figure 6 An operation schematic diagram of the control circuit in the diagnosis stage according to an embodiment of the present disclosure is shown. Please refer to Figure 6 In this embodiment, the first driving circuit 210 detects the signals on the first output terminals TO1_1, TO2_1. When at least one of the response signals SR1 to SR4 is detected on at least one of the first output terminals TO1_1, TO2_1, the first driving circuit 210 determines that (1) at least one of the first output terminals TO1_1, TO2_1 and at least one of the first input terminals TI1_1, TI2_1 are short-circuited with each other; and / or (2) at least one of the first output terminals TO1_1, TO2_1 and at least one of the first transmission terminals TT1_1, TT2_1 are short-circuited with each other.

[0088] For example, the determination circuit 212 detects the signals on the first output terminals TO1_1, TO2_1. When the response signal SR1 is detected on the first output terminal TO2_1, the determination circuit 212 determines that the first output terminal TO2_1 and the first input terminal TI1_1 are short-circuited with each other. Therefore, the determination circuit 212 outputs an abnormal notification signal SAN corresponding to such an abnormal state.

[0089] Figure 7 An operation schematic diagram of the control circuit in the diagnosis stage according to an embodiment of the present disclosure is shown. Please refer to Figure 7In the present embodiment, the first drive circuit 210 cannot recognize the response signals SR1 to SR4 after the first drive circuit 210 outputs 3 test cycles of the test signal ST1. The first drive circuit 210 determines that the connection state is abnormal. For example, the number of test cycles is set to "3", but the present disclosure is not limited thereto.

[0090] For example, the number of test cycles is set to "3", but the present disclosure is not limited thereto. The determination circuit 212 cannot recognize all of the response signals SR1 to SR4 after the test signal generator 211 outputs 3 test cycles of the test signal ST1. The signal received by the determination circuit 212 can be a noise signal. Such an abnormal state indicates (1) an abnormal disconnection between the first output terminal TO1_1 and the test signal generator 211; (2) an abnormal disconnection between the first output terminal TO1_1 and the second input terminal TI1_2; (3) an abnormal disconnection between the second input terminal TI1_2 and the determination circuit 221 and / or (4) a failure of the second drive circuit 220. Therefore, the determination circuit 212 outputs an abnormal notification signal SAN corresponding to such an abnormal state.

[0091] Figure 8 An operation schematic diagram of the control circuit in the diagnosis phase according to an embodiment of the present disclosure is shown. Please refer to Figure 8 In the present embodiment, for example, the number of test cycles is set to "3", but the present disclosure is not limited thereto. The determination circuit 212 cannot recognize the response signal SR3 after the test signal generator 211 outputs 3 test cycles of the test signal ST1. The signal received by the determination circuit 212 through the first transmission terminal TT1_1 can be a noise signal.

[0092] Such an abnormal state indicates (1) an abnormal disconnection between the first transmission terminal TT1_1 and the determination circuit 212; (2) an abnormal disconnection between the first transmission terminal TT1_1 and the first transmission terminal TT1_2; and / or (3) an abnormal disconnection between the first transmission terminal TT1_2 and the response signal generator 222. Therefore, the determination circuit 212 outputs an abnormal notification signal SAN corresponding to such an abnormal state.

[0093] Based on Figure 7 and Figure 8 In the embodiment shown, the first drive circuit 210 determines that the connection state is abnormal when the first drive circuit 210 cannot recognize at least one of the response signals SR1 to SR4.

[0094] Figure 9A schematic diagram of a control circuit according to a third embodiment of the present disclosure is shown. In this embodiment, the control circuit 300 includes a first driving circuit 310 and second driving circuits 320_1 and 320_2. In an operation stage, the first driving circuit 310 drives a first portion (e.g., a first portion P1 of the display panel PL in Figure 1 ) of the display panel. The driving circuit 320_1 drives a second portion (e.g., a second portion P2 of the display panel PL in Figure 1 ) of the display panel. The driving circuit 320_2 drives a third portion of the display panel.

[0095] The first driving circuit 310 includes first output terminals TO1_1 to TO4_1, first input terminals TI1_1 to TI4_1, and first transmission terminals TT1_1 to TT4_1. The second driving circuit 320_1 includes second input terminals TI1_2, TI2_2, second output terminals TO1_2, TO2_2, and second transmission terminals TT1_2, TT2_2.

[0096] The second input terminals TI1_2, TI2_2 are connected to the first output terminals TO1_1, TO2_1 in a one-to-one manner.

[0097] The second output terminals TO1_2, TO2_2 are connected to the first input terminals TI1_1, TI2_1 in a one-to-one manner.

[0098] The second transmission terminals TT1_2, TT2_2 are connected to the first transmission terminals TT1_1, TT2_1 in a one-to-one manner. The connection between the first driving circuit 310 and the second driving circuit 320_1 is taught by the embodiment shown in Figure 3 .

[0099] The second driving circuit 320_2 includes second input terminals TI3_2, TI4_2, second output terminals TO3_2, TO4_2, and second transmission terminals TT3_2, TT4_2. The second input terminals TI3_2, TI4_2 are connected to the first output terminals TO3_1, TO4_1 in a one-to-one manner. The second output terminals TO3_2, TO4_2 are connected to the first input terminals TI3_1, TI4_1 in a one-to-one manner. The second transmission terminals TT3_2, TT4_2 are connected to the first transmission terminals TT3_1, TT4_1 in a one-to-one manner. The connection between the first driving circuit 310 and the second driving circuit 320_2 is similar to the connection between the first driving circuit 310 and the second driving circuit 320_1. For example, the second input terminal TI3_2 is connected to the first output terminal TO3_1. The second input terminal TI4_2 is connected to the first output terminal TO4_1. The second output terminal TO3_2 is connected to the first input terminal TI3_1. The second output terminal TO4_2 is connected to the first input terminal TI4_1. The second transmission terminal TT3_2 is connected to the first transmission terminal TT3_1. The second transmission terminal TT4_2 is connected to the first transmission terminal TT4_1.

[0100] Figure 10 A flowchart of the operation of the control circuit in the diagnosis stage according to an embodiment of the present disclosure is shown. Please refer to Figure 9 and Figure 10 In step S110, the first driving circuit 310 selects one of the second driving circuits 320_1 and 320_2 as a selected second driving circuit (or selected driving circuit). In step S120, the first driving circuit 310 sequentially outputs test signals ST1, ST2 to the selected second driving circuit during different periods.

[0101] For example, the first driving circuit 310 selects the second driving circuit 320_1 as the selected second driving circuit in step S110, and outputs the test signals ST1, ST2 to the first output terminals TO1_1, TO2_1 in step S120.

[0102] In step S130, the second driving circuit 320_1 receives the test signals ST1, ST2 through the second input terminals TI1_2, TI2_2. The second driving circuit 320_1 determines the test signals ST1, ST2, and sequentially outputs response signals SR1 to SR4 in response to the test signals ST1, ST2 during different periods.

[0103] For example, the number of the second input terminals is "Y". The number of the second transmission terminals for the output signal is "Z". The transmission cycle of each of the response signals SR1 to SR4 is "Q" cycles of the system clock. Therefore, in step S130, the second driving circuit 320_1 takes "Q(Y+Z)" cycles to output all of the response signals SR1 to SR4.

[0104] In detail, the second driving circuit 320_1 can check the transmission direction of the second transmission terminals TT1_2, TT2_2. If the transmission direction of the second transmission terminals TT1_2, TT2_2 is for the output signal, the second driving circuit 320_1 sequentially outputs the response signals SR1 to SR4 through the second output terminals TO1_2, TO2_2 and the second transmission terminals TT1_2, TT2_2 during different periods in response to the test signals ST1, ST2. If the second transmission terminals TT1_2, TT2_2 are for the input signal, the second driving circuit 320_1 sequentially outputs the response signals SR1, SR2 through the second output terminals TO1_2, TO2_2 during different periods in response to the test signals ST1, ST2.

[0105] For example, if both of the test signals ST1, ST2 are normal, the second driving circuit 320_1 outputs the response signals SR1 to SR4 without the abnormal information (i.e., a pass signal). In contrast, if at least one of the test signals ST1, ST2 is abnormal, the second driving circuit 320_1 outputs the response signals SR1 to SR4 including the abnormal information (i.e., a fail signal).

[0106] In some embodiments, the second driving circuit 320_1 can suspend outputting the response signals SR1 to SR4. Then, the second driving circuit 320_1 enters a waiting state. In the waiting state, the second driving circuit 320_1 counts the length of time of the waiting state. If the length of time reaches a default length of time, the second driving circuit 320_1 can leave the diagnosis phase.

[0107] In step S140, the first driving circuit 310 determines the connection state of the first driving circuit 310 and the second driving circuit 320_1 according to the response signals SR1 to SR4. The detailed operation of step S140 can be taught by the above-mentioned embodiments. Therefore, the detailed operation is not repeated here. Figure 3 to Figure 8 The detailed operation of step S140 can be taught by the above-mentioned embodiments. Therefore, the detailed operation is not repeated here.

[0108] For example, the number of the second input terminals is "Y". The number of the second transmission terminals for the output signal is "Z". The transmission cycle of each of the response signals SR1 to SR4 is "Q" cycles of the system clock. Therefore, the first driving circuit 310 takes at least "Q(Y+Z+1)" cycles to determine the connection state of the first driving circuit 310 and the second driving circuit 320_1.

[0109] In step S150, the first driving circuit 310 determines whether the second driving circuit 320_1 is the last second driving circuit. When the second driving circuit 320_1 is not the last second driving circuit, the first driving circuit 310 selects the next second driving circuit as the last second driving circuit, and returns to step S120.

[0110] For example, when the second driving circuit 320_1 is not the last second driving circuit, the first driving circuit 310 selects the second driving circuit 320_2 as the last second driving circuit. Therefore, in step S120, the first driving circuit 310 outputs the test signals ST1, ST2 to the first output terminals TO3_1, TO4_1.

[0111] In step S130, the second driving circuit 320_2 receives the test signals ST1, ST2 through the second input terminals TI3_2, TI4_2. The second driving circuit 320_2 determines the test signals ST1, ST2, and generates the response signals SR5 to SR8 in response to the test signals ST1, ST2. The second driving circuit 320_2 outputs the response signals SR1 to SR4 through the second output terminals TO3_2, TO4_2 and the second transmission terminals TT3_2, TT4_2 in sequence during different periods.

[0112] In step S140, the first driving circuit 310 determines the connection state of the first driving circuit 310 and the second driving circuit 320_2 according to the response signals SR5 to SR8.

[0113] In step S150, the first driving circuit 310 determines whether the second driving circuit 320_2 is the last second driving circuit. When the second driving circuit 320_2 is the last second driving circuit, the first driving circuit 310 ends the diagnosis phase in step S160. Therefore, the control circuit 300 exits the diagnosis phase.

[0114] In some embodiments, the control circuit 300 includes one second driving circuit. Therefore, steps S110, S150, S160 can be skipped.

[0115] Figure 11 A schematic diagram of a control circuit according to an embodiment of the present disclosure is shown. Please refer to Figure 10 and Figure 11In this embodiment, the control circuit 400 includes a first driving circuit 410 and second driving circuits 420_1 to 420_m. During the operation phase, each of the first driving circuit 410 and the second driving circuits 420_1 to 420_m drives the corresponding portion of the display panel PL.

[0116] Similar to Figure 3 The first driving circuit 310 and the second driving circuit 320_1 shown are illustrated. The first driving circuit 410 includes a first output terminal, a first input terminal, and a first transmission terminal. Figure 11 (Not shown in the diagram). Each of the second drive circuits 420_1 to 420_m includes a second output terminal, a second input terminal, and a second transmission terminal (not shown in the diagram). Figure 11 (Not shown in the image).

[0117] The second output terminals of the second drive circuits 420_1 to 420_m are connected to the first input terminal via the connection bus BS. The second input terminals of the second drive circuits 420_1 to 420_m are connected to the first output terminal via the connection bus BS. The second transmission terminals of the second drive circuits 420_1 to 420_m are connected to the first transmission terminal via the connection bus BS.

[0118] The first driving circuit 410 determines the connection status of the first driving circuit 410 and the second driving circuits 420_1 to 420_m during different time periods.

[0119] In step S110, the first driving circuit 410 selects the second driving circuit 420_1 as the selected second driving circuit in the first time period. In step S120, the first driving circuit 410 sequentially outputs test signals ST1 and ST2 to different first output terminals during different period periods. The second driving circuit 420_1 receives test signals ST1 and ST2 through its second input terminal. In step S130, the second driving circuit 420_1 determines the test signals ST1 and ST2 and, in response to the test signals ST1 and ST2, sequentially outputs response signals SR1 to SR4 during different period periods. In the first time period, in step S140, the first driving circuit 410 determines the connection state between the first driving circuit 410 and the second driving circuit 420_1 based on the response signals SR1 to SR4. Detailed operation of step S140 can be obtained through... Figure 3 to Figure 9 The illustrated embodiment is used for demonstration purposes. Therefore, detailed operations will not be repeated here.

[0120] In step S110, the first driving circuit 410 selects the second driving circuit 420_2 as the selected second driving circuit in the second time period, and in step S120, the first driving circuit 410 sequentially outputs the test signals ST1, ST2 to the different first output terminals during different periods. The second driving circuit 420_2 receives the test signals ST1, ST2 through the second input terminals. In step S130, the second driving circuit 420_2 determines the test signals ST1, ST2 and sequentially outputs the response signals SR5 to SR8 during different periods in response to the test signals ST1, ST2. In the second time period, in step S140, the first driving circuit 410 determines the connection state of the first driving circuit 410 and the second driving circuit 420_2 according to the response signals SR5 to SR8.

[0121] In step S110, the first driving circuit 410 selects the second driving circuit 420_m as the selected second driving circuit in the (m)th time period, and in step S120, the first driving circuit 410 sequentially outputs the test signals ST1, ST2 to the different first output terminals during different periods. The second driving circuit 420_m receives the test signals ST1, ST2 through the second input terminals. In step S130, the second driving circuit 420_m determines the test signals ST1, ST2 and sequentially outputs the response signals SR(n-3) to SRn during different periods in response to the test signals ST1, ST2. In step S140, in the (m)th time period, the first driving circuit 410 determines the connection state of the first driving circuit 410 and the second driving circuit 420_m according to the response signals SR5 to SR8.

[0122] In summary, the first driving circuit sequentially outputs the test signals to the first output terminals during different periods in the diagnosis stage. The second driving circuit sequentially outputs the response signals to the second output terminals during different periods in the diagnosis stage in response to the test signals. The first driving circuit determines the connection state of the first driving circuit and the second driving circuit. Therefore, in the diagnosis stage, the control circuit provides an automatic diagnosis mechanism for checking the circuit connection of the first driving circuit and the second driving circuit. The control circuit 100 also improves the speed of checking the circuit connection of the first driving circuit and the second driving circuit. In addition, the automatic diagnosis mechanism is also used for the control circuit including the first driving circuit and at least two second driving circuits.

[0123] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In summary, the present disclosure is intended to cover various modifications and variations, which fall within the scope of the appended claims and their equivalents.

Claims

1. A control circuit for controlling a display panel, comprising: a first driving circuit connected to a first portion of the display panel and configured to drive the first portion in an operation phase, wherein the first driving circuit comprises: a plurality of first output terminals, wherein the first driving circuit sequentially outputs a plurality of test signals to the plurality of first output terminals during different periods in a diagnosis phase; and a plurality of first input terminals; and a second driving circuit connected to a second portion of the display panel and configured to drive the second portion in the operation phase, wherein the second driving circuit comprises: a plurality of second input terminals connected to the plurality of first output terminals in a one-to-one manner; and a plurality of second output terminals connected to the plurality of first input terminals in a one-to-one manner, wherein the second driving circuit receives the plurality of test signals through the plurality of second input terminals in the diagnosis phase, and sequentially outputs a plurality of response signals to the plurality of second output terminals during different periods in the diagnosis phase in response to the plurality of test signals, and wherein the first driving circuit receives the plurality of response signals through the plurality of first input terminals in the diagnosis phase, and determines a connection state of the first driving circuit and the second driving circuit according to the plurality of response signals. 2.The control circuit of claim 1, wherein the first driving circuit sets waveforms of the plurality of test signals according to a first number of cycles of a system clock and a second number of cycles of the system clock. 3.The control circuit of claim 1, wherein: when determining the connection state is ended, the first driving circuit provides a completion signal to the second driving circuit through at least one of the plurality of first output terminals, and the second driving circuit ends the diagnosis phase in response to the completion signal. 4.The control circuit of claim 1, wherein when at least two of the plurality of test signals received by the second driving circuit have the same timing, the second driving circuit generates the plurality of response signals including abnormal information during different periods in the diagnosis phase. 5.The control circuit of claim 4, wherein the first driving circuit determines that the connection state is abnormal according to the plurality of response signals including the abnormal information. 6.The control circuit of claim 1, wherein when at least two of the plurality of response signals received by the first driving circuit have the same timing, the first driving circuit determines that the connection state is abnormal. 7.The control circuit of claim 1, wherein: the first driving circuit detects a plurality of signals on the plurality of first output terminals, and when at least one of the plurality of response signals is located on at least one of the plurality of first output terminals, the first driving circuit determines that the at least one of the plurality of first output terminals and at least one of the plurality of first input terminals are short-circuited to each other.

8. The control circuit according to claim 1, wherein when the first drive circuit fails to identify at least one of the plurality of response signals, the first drive circuit determines that the connection state is abnormal.

9. The control circuit according to claim 1, wherein: the first drive circuit further includes at least one first transmission terminal, the second drive circuit further includes at least one second transmission terminal, and the at least one second transmission terminal is connected to the at least one first transmission terminal in a one-to-one manner.

10. The control circuit according to claim 9, wherein: the second drive circuit sequentially outputs the plurality of response signals to the plurality of second output terminals and the at least one second transmission terminal during different periods in the diagnosis stage in response to the plurality of test signals, and the first drive circuit receives the plurality of response signals through the plurality of first input terminals and the at least one first transmission terminal in the diagnosis stage, and determines the connection state of the first drive circuit and the second drive circuit.

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