Refresh control circuit and memory

Abstract

The present application provides a refresh control circuit and memory, including: a refresh counter that counts pulses of a row activation window signal within the active level period of a refresh window signal and within the active level period of an enable signal, and outputs the count result; and performs a count reset in response to a period reset signal; a reset circuit for outputting a period reset signal when the count result currently output by the refresh counter reaches a preset number; and a control circuit for outputting a protection refresh window signal based on the count result currently output by the refresh counter; wherein, when the count result is within a preset range, the protection refresh window signal is at an active level. This solution can implement row hammer protection.

Description

Technical Field

[0001] The present application relates to memory technology, and in particular to a refresh control circuit and a memory. Background Art

[0002] With the development of memory technology, memory is widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] In practical applications, as memory devices become smaller and more integrated, interference between adjacent memory cells can lead to row hammer (RH) vulnerabilities. Specifically, RH vulnerabilities occur when a memory cell is repeatedly read and written, potentially causing data in other cells to flip. Therefore, an effective refresh control scheme is needed to control the execution of RH protection operations to prevent erroneous flips in memory cells. Summary of the Invention

[0004] Embodiments of the present application provide a refresh control circuit and a memory.

[0005] According to some embodiments, the first aspect of the present application provides a refresh control circuit, including: a refresh counter, which receives an activation command, a row activation window signal and a refresh window signal, and is used to count the pulses of the row activation window signal within the effective level period of the refresh window signal and within the effective level period of the enable signal, and output the counting result; and, in response to a periodic reset signal, performs a counting reset; wherein the enable signal is generated based on the activation command and the periodic reset signal; a reset circuit, wherein the input end of the reset circuit is connected to the output end of the refresh counter, and the output end of the reset circuit is connected to the reset end of the refresh counter, and is used to output a periodic reset signal when the counting result currently output by the refresh counter reaches a preset number; a control circuit, wherein the input end of the control circuit is connected to the output end of the refresh counter, and is used to output a protection refresh window signal according to the counting result currently output by the refresh counter; wherein, when the counting result is within a preset range, the protection refresh window signal is at a valid level.

[0006] In some embodiments, a refresh counter includes: an enable circuit, a detection circuit, a pulse generating circuit and a counter; the enable circuit receives an activation command and a periodic reset signal, and is used to generate an enable signal based on the activation command and the periodic reset signal; wherein the activation command controls the starting time of the effective level of the enable signal, and the periodic reset signal controls the ending time of the effective level of the enable signal; the detection circuit receives the enable signal, the row activation window signal and the refresh window signal, and is used to detect whether the pulse of the row activation window signal is within the effective level period of the refresh window signal and whether it is within the effective level period of the enable signal; if so, outputs the pulse of the row activation window signal; the pulse generating circuit is connected to the output end of the detection circuit, and is used to output a valid counting clock in response to the arrival of the pulse of the row activation window signal output by the detection circuit; the clock end of the counter is connected to the output end of the pulse generating circuit, and the reset end of the counter is connected to the reset circuit, and is used to accumulate counts in response to the effective counting clock and output the counting result; and, performs counting reset in response to the periodic reset signal.

[0007] In some embodiments, the detection circuit includes: a first AND gate; the first input end of the first AND gate receives a refresh window signal, the second input end of the first AND gate receives a row activation window signal, the third input end of the first AND gate is connected to the output end of the enable circuit, and the output end of the first AND gate is connected to the pulse generating circuit.

[0008] In some embodiments, the enabling circuit includes: a first NOT gate, a second NOT gate, a first NAND gate, and a second NAND gate; the input end of the first NOT gate receives an activation command, and the output end of the first NOT gate is connected to the first input end of the first NAND gate; the input end of the second NOT gate receives a periodic reset signal, and the output end of the second NOT gate is connected to the first input end of the second NAND gate; the second input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate is connected to the third input end of the first AND gate; the second input end of the second NAND gate is connected to the output end of the first NAND gate.

[0009] In some embodiments, the pulse generating circuit includes: a third NOT gate, a delay unit and a second AND gate; the first input end of the second AND gate is connected to the output end of the detection circuit, and the second input end of the second AND gate is connected to the output end of the delay unit; the input end of the third NOT gate is connected to the output end of the detection circuit, and the output end of the third NOT gate is connected to the input end of the delay unit, and the delay time of the delay unit is used to control the pulse width of the counting clock; the output end of the second AND gate is connected to the clock end of the counter as the output end of the pulse generating circuit.

[0010] In some embodiments, the counter includes: multiple levels of first triggers; the clock end of the first-level first trigger is connected to the output end of the pulse generating circuit, and the clock ends of other first triggers are connected to the inverting output end of the first trigger of the previous level; the input end of each first trigger is connected to the inverting output end of the first trigger, and the value output by the inverting output end of each level of the first trigger constitutes the output of the counter, which is a binary representation of the counting result; the reset end of each first trigger is connected to the output end of the reset circuit.

[0011] In some embodiments, the reset circuit includes: a reset generation circuit and an output circuit; the reset generation circuit is connected to the output end of the refresh counter and receives a period setting signal, and is used to output an initial reset signal to the output circuit when the counting result output by the refresh counter reaches a preset number of times corresponding to the period setting signal; the input end of the output circuit is connected to the output end of the reset generation circuit, and the output circuit is used to output the initial reset signal as a period reset signal in response to the end of the pulse of the row activation window signal within the effective level period of the refresh window signal.

[0012] In some embodiments, the period setting signal includes two bits, and the preset number includes four values, which are respectively recorded as the first number, the second number, the third number, and the fourth number.

[0013] In some embodiments, the reset generation circuit includes: a cycle decoding circuit, the cycle decoding circuit receives a cycle setting signal, and is used to output a selection signal for a first number, a selection signal for a second number, a selection signal for a third number, and a selection signal for a fourth number according to the cycle setting signal; a sub-decoder corresponding to each number; each sub-decoder receives at least one bit of a counting result, and is used to output a flag signal of the number when the value currently represented by the at least one received bit is consistent with the number corresponding to the sub-decoder; a third AND gate corresponding to each number; each third AND gate receives a selection signal for the corresponding number and a flag signal for the corresponding number; an OR operation unit, the input end of the OR operation unit is respectively connected to the output ends of all the third AND gates, and the output end of the OR operation unit is used to output an initial reset signal.

[0014] In some embodiments, the cycle decoding circuit includes: a first NOR gate, wherein a first input terminal of the first NOR gate receives one bit of a cycle setting signal, a second input terminal of the first NOR gate receives another bit of the cycle setting signal, and the first NOR gate is used to output a selection signal for a first number; a fourth NOR gate and a second NOR gate, wherein an input terminal of the fourth NOR gate is connected to the first input terminal of the first NOR gate, an output terminal of the fourth NOR gate is connected to the first input terminal of the second NOR gate, a second input terminal of the second NOR gate is connected to the second input terminal of the first NOR gate, and the second NOR gate is used to output a selection signal for a second number; a fifth NOR gate and a third NOR gate, the first input end of the third NOR gate is connected to the first input end of the first NOR gate, the input end of the fifth NOR gate is connected to the second input end of the first NOR gate, the output end of the fifth NOR gate is connected to the second input end of the third NOR gate, and the third NOR gate is used to output the selection signal for the third number; a third NAND gate and a sixth NOR gate, the first input end of the third NAND gate is connected to the first input end of the first NOR gate, the second input end of the third NAND gate is connected to the second input end of the first NOR gate, the output end of the third NAND gate is connected to the input end of the sixth NOR gate, and the sixth NOR gate is used to output the selection signal for the fourth number.

[0015] In some embodiments, the sub-decoder corresponding to the first number includes a fourth AND gate; the input ends of the fourth AND gate respectively receive the 3rd bit and the 2nd bit of the counting result, and the output end of the fourth AND gate is used to output the flag signal of the first number; the sub-decoder corresponding to the second number includes a fifth AND gate; the input ends of the fifth AND gate respectively receive the 4th bit and the 3rd bit of the counting result, and the output end of the fifth AND gate is used to output the flag signal of the second number; the sub-decoder corresponding to the third number includes a sixth AND gate; the input ends of the sixth AND gate respectively receive the 5th bit and the 2nd bit of the counting result, and the output end of the sixth AND gate is used to output the flag signal of the third number; the sub-decoder corresponding to the fourth number includes a seventh AND gate; the input ends of the seventh AND gate respectively receive the 5th bit and the 4th bit of the counting result, and the output end of the seventh AND gate is used to output the flag signal of the fourth number.

[0016] In some embodiments, the output circuit includes: a seventh NOT gate, an input end of the seventh NOT gate receiving a row activation window signal; an eighth AND gate, a first input end of the eighth AND gate receiving a refresh window signal, and a second input end of the eighth AND gate connected to an output end of the seventh NOT gate; a second flip-flop, an input end of the second flip-flop connected to an output end of a reset generation circuit, an output end of the second flip-flop connected to a reset end of a refresh counter, and a clock end of the second flip-flop connected to an output end of the eighth AND gate.

[0017] In some embodiments, the preset range is 4 to 6.

[0018] In some embodiments, the control circuit includes: a first multi-input AND gate, a second multi-input AND gate, a third multi-input AND gate, and a first multi-input OR gate; the first multi-input AND gate has multiple input terminals, and the multiple input terminals of the first multi-input AND gate respectively receive the inverted signal of the first bit, the inverted signal of the second bit, and the third bit of the counting result; the second multi-input AND gate has multiple input terminals, and the multiple input terminals of the second multi-input AND gate respectively receive the inverted signal of the first bit, the second bit, and the third bit of the counting result; the third multi-input AND gate has multiple input terminals, and the multiple input terminals of the third multi-input AND gate respectively receive the inverted signal of the first bit, the second bit, and the third bit of the counting result; the first input terminal of the first multi-input OR gate is connected to the output terminal of the first multi-input AND gate, the second input terminal of the first multi-input OR gate is connected to the output terminal of the second multi-input AND gate, the third input terminal of the first multi-input OR gate is connected to the output terminal of the third multi-input AND gate, and the output terminal of the first multi-input OR gate is used to output a protection refresh window signal.

[0019] According to some embodiments, the second aspect of the present application provides a memory, including: an instruction decoder, a refresh operation module, a storage block control module and a refresh control circuit as described above; the instruction decoder is used to parse and generate activation commands and refresh instructions according to external instructions; the refresh operation module is connected to the instruction decoder, and is used to output a refresh window signal and a row activation window signal in response to the refresh instruction; the refresh control circuit is connected to the instruction decoder, the refresh operation module and the storage block control module, and is used to output a protection refresh window signal according to the activation command, the refresh window signal and the row activation window signal; the storage block control module is connected to the refresh control circuit and the refresh operation module, and is used to perform refresh in response to the signal output by the refresh operation module, and to perform row hammer protection refresh in response to the protection refresh window signal.

[0020] The refresh control circuit and memory provided in the embodiments of the present application include a refresh counter, a reset circuit, and a control circuit. The refresh counter counts the pulses of the row activation window signal within the effective level period of the refresh window signal and the enable signal, and outputs the counting result. When the counting result reaches a preset number of times, the reset circuit instructs the refresh counter to reset. When the counting result is within a preset range, the control circuit outputs a valid protection refresh window signal to execute the row hammer protection refresh within the effective level period of the protection refresh window signal. The above scheme can realize row hammer protection refresh, and based on the support for setting a preset number of times and a preset range in this scheme, a certain number of refreshes can be selected in each round of the preset number of refreshes to execute row hammer protection refresh, so that while realizing row hammer protection refresh, the execution frequency of protection refresh can be adjusted, thereby improving the flexibility of row hammer protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, are used to explain the principles of the embodiments of the present application.

[0022] Figure 1 An example diagram of a memory architecture according to an embodiment is shown;

[0023] Figure 2 This is a structural diagram of a storage unit according to an embodiment;

[0024] Figure 3 This is an example of a hammering situation;

[0025] Figure 4 is a structural diagram of an exemplary refresh control circuit;

[0026] Figure 5 An example diagram of the timing of different signals of an example;

[0027] Figure 6 is a timing diagram of an example;

[0028] Figure 7 A schematic diagram of the structure of a refresh counter of an example;

[0029] Figure 8 A schematic diagram of the structure of a refresh counter of an example;

[0030] Figure 9 A schematic diagram of the structure of a refresh counter of an example;

[0031] Figure 10 is a timing diagram of an example;

[0032] Figure 11 A schematic diagram of the structure of a counter as an example;

[0033] Figure 12 This is an example diagram of the counting process;

[0034] Figure 13 is a schematic structural diagram of an exemplary reset circuit;

[0035] Figure 14 is a structural diagram of an exemplary periodic decoding circuit;

[0036] Figure 15 is a schematic structural diagram of an example sub-decoder;

[0037] Figure 16 is a structural diagram of an exemplary control circuit;

[0038] Figure 17 This is a diagram showing an example of the structure of a memory.

[0039] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0040] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present application.

[0041] The terms "including" and "having" in this application are intended to convey an open-ended, inclusive meaning and indicate that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first" and "second" are used solely for identification or distinction and do not limit the order or quantity of the elements and regions. Furthermore, the various elements and regions in the drawings are schematic illustrations only and are not limited to the sizes or distances shown.

[0042] The technical solution is described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0043] The technical solution is described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0044] Figure 1 FIG. 1 is an example diagram of a memory architecture shown in an embodiment, as shown in FIG. Figure 1 As shown in the figure, using DRAM as an example, it includes data input / output buffers, row decoders, column decoders, sense amplifiers, and a memory array. The data input / output buffers belong to the peripheral circuit area, while the sense amplifiers, row decoders, column decoders, and memory array belong to the array circuit area. The memory array is primarily composed of word lines, bit lines, and memory cells. Word lines in the memory array extend along the rows, while bit lines extend along the columns. The intersections of word lines and bit lines form the memory cells of the memory array.

[0045] Each storage unit is used to store one bit of data. Figure 2 As shown, Figure 2FIG1 is a structural diagram of a memory cell according to an embodiment. The memory cell is mainly composed of a transistor switch M and a capacitor C. The capacitor is used to store data, and the transistor switch is used to turn off or on according to the selected state.

[0046] A memory cell can be activated by controlling the word line and the bit line to achieve access to the memory cell. Take the read scenario as an example: when it is necessary to read the data in the memory cell, the word line of the row where the memory cell is located can be selected through the row decoder. Correspondingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the bit data stored in the memory cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the memory cell, and vice versa. In addition, take the write scenario as an example: when it is necessary to write bit data to a memory cell, such as writing 1. The word line of the row where the memory cell is located can be selected through the row decoder. The transistor M in the diagram is turned on accordingly, and by setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the memory cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the memory cell.

[0047] Based on the above, it can be seen that when the processor needs to read data from the memory, it will first activate the row address where the data is located, read the row of data under the row address into the sense amplifier, and then activate the column address where the data is located, read the data under the column address from the sense amplifier, and feed it back to the processor. At the same time, in order to ensure that data is not lost due to data reading, the data in the sense amplifier needs to be written back to the storage unit after reading the data. In recent years, with the higher demand for computer storage in production and life, equipment manufacturers hope to store more data without changing the size of the circuit board area. Therefore, the density of storage cells can only be increased, and the spacing between adjacent storage cells is getting smaller and smaller, which may cause mutual interference between them. For example, if the number of read and write times for the same address is large enough, it may cause the bits of adjacent rows to flip, that is, the originally stored 0 becomes 1, or the originally stored 1 becomes 0.

[0048] Further integration Figure 3 For example, Figure 3 For example, a hammer strike occurs when Figure 3As shown in the figure, when an attacker hammers a specific row of the memory, such as hammering the row filled with shade in the figure, the data in the memory cells near the row may be flipped. This is because, with the increasing manufacturing precision of DRAM, the components are getting smaller and smaller at the physical level, and electromagnetic interference is prone to occur between adjacent memory cells. This situation makes it possible for reading and writing a single area of ​​the memory to interfere with adjacent areas, causing current to flow into or out of adjacent memory cells. If a large number of reads and writes are repeated, the data in the adjacent memory cells may be changed. For example, in the adjacent row of the row filled with shade in the figure, that is, the affected row (Victim Row), part of the data in the adjacent row is flipped, such as the data in the third and fifth columns, which is flipped from 1 to 0.

[0049] In response to the above phenomenon, in some example solutions, in order to prevent RH attacks, the memory industry has deployed various solutions collectively referred to as target row refresh (TRR). The basic principle is to set a threshold for the number of activations of a memory row and refresh the detected target row when the number of activations exceeds the threshold. As an example, the specific approach is to embed the row address detected to have RH risk into the automatic refresh (Auto-Refresh). In some examples, RH protection refresh is embedded in each automatic refresh. In the above solution, since each automatic refresh requires the execution of RH protection refresh, it is not flexible enough, resulting in a significant increase in the number of commands and total time required to refresh the entire memory array, and higher requirements are placed on the data retention capability of the memory. Specifically, combined with the working principle of the aforementioned memory, it can be seen that data storage is actually achieved by storing a certain amount of charge in the capacitor in the memory cell. For example, a charge on the capacitor indicates that the stored data is 1, and no charge indicates that the stored data is 0. In actual applications, since the charge on the capacitor will be lost over time, the automatic refresh is precisely to retain the stored data. It is set to replenish the charge of the capacitor in each memory cell at intervals to maintain the charge on the capacitor in the state corresponding to the data stored in the memory cell. The specific process of refreshing includes reading out the stored data and rewriting it. The data retention capability of a memory is the ability of a memory cell to stably maintain a certain charge before replenishing the charge.

[0050] In practical applications, given the instability of the manufacturing process and the varying data retention and performance of memories, a more flexible and reliable RH protection solution is needed. Some aspects of the present application's embodiments address these considerations. The following describes the solution with examples in conjunction with some embodiments.

[0051] Figure 4 FIG. 1 is a structural diagram of an exemplary refresh control circuit, as shown in FIG. Figure 4As shown, the refresh control circuit includes: a refresh counter 11, a reset circuit 12 and a control circuit 13;

[0052] A refresh counter 11 receives an activation command ACT CMD, a row activation window signal tRAS window, and a refresh window signal tRFC window, and is configured to count pulses of the row activation window signal tRAS window within an active level period of the refresh window signal tRFC window and within an active level period of the enable signal, and output a counting result; and, in response to a period reset signal RST_D, to perform a counting reset; wherein the enable signal is generated based on the activation command ACT CMD and the period reset signal RST_D;

[0053] a reset circuit 12, wherein the input end of the reset circuit 12 is connected to the output end of the refresh counter 11, and the output end of the reset circuit 12 is connected to the reset end of the refresh counter 11, and is configured to output a periodic reset signal RST_D when the count result currently output by the refresh counter 11 reaches a preset number of times;

[0054] The control circuit 13 has an input end connected to the output end of the refresh counter 1 and is configured to output a protection refresh window signal RH window based on a count result currently output by the refresh counter 11. When the count result is within a preset range, the protection refresh window signal RH window is at a valid level.

[0055] In practical applications, the circuit provided in this embodiment can be applied to various memories. For example, it can be applied to, but not limited to, double data rate synchronous dynamic random access memory (DDR).

[0056] Specifically, the specific process of refreshing includes reading and writing data, and each refreshing process needs to be executed in conjunction with the corresponding instructions. As an example, Figure 5 This is an example diagram of the timing of different signals, such as Figure 5As shown, EN is the enable signal, ACT CMD is the activation command, PRE CMD is the precharge command, REF CMD is the refresh command, tRFC window is the refresh window signal, and tRAS window is the row activation window signal. Specifically, tRFC (Refresh Cycle Time) is the refresh time. Specifically, after the refresh command is issued, the memory will refresh all the storage cells in the storage array. The entire refresh process is carried out during the effective level period of the refresh window signal tRFC window. tRAS is the row activation time, and the pulse width of tRAS depends on the time between the activation operation and the precharge operation. In combination with the above, the specific processing of refresh includes reading and writing data, that is, each refresh requires row activation and precharge, so each pulse of tRASwindow in the effective level period of tRFC window represents a refresh. The figure takes the effective level as a high level as an example.

[0057] Among them, the enable signal responds to the arrival of the activation command and begins to enter the valid level period. In actual applications, there are many scenarios for performing row activation and pre-charging, such as but not limited to automatic refresh, self-refresh, and normal reading and writing, which all require row activation and pre-charging. Therefore, in order to improve the efficiency of row hammering protection and avoid unnecessary protection processing, in this embodiment, the pulses of the row activation window signal that are both in the valid level period of the refresh window signal and in the valid level period of the enable signal are specifically detected to filter out row activation operations that are obviously not row hammering situations. Figure 5 As shown in the figure, the first pulse in tRASwindow is not in the valid level period of tRFC window, so it is not counted. For example, a pulse of the row activation window signal is in the valid level period of the refresh window signal, but not in the valid level period of the enable signal. Since the valid level period of the enable signal has not yet begun, no activation command has been received before (usually obtained by decoding in response to an external instruction). The current row activation operation may be auto-refresh or self-refresh, not row hammering. Therefore, there is no need to perform protection refresh, so such pulses are not counted.

[0058] In this scenario example, for pulses in the row activation window signal tRAS window, the refresh counter 11 counts the pulses that are simultaneously within the active level period of the refresh window signal tRFC window and the active level period of the enable signal EN. When the number of such pulses reaches a certain number, a protective refresh process is executed. The objects and specific processing procedures of the protective refresh can be referred to in the relevant solutions and will not be described in detail here. Therefore, when the count result output by the refresh counter 11 falls within a preset range, the control circuit 13 outputs the protective refresh window signal RH window to promptly execute the row hammer protective refresh operation. In this embodiment, a reset circuit 12 is also provided to output a periodic reset signal to the refresh counter 11 when the count result output by the refresh counter 11 reaches a preset number, thereby resetting the refresh counter 11. That is, during the process of the refresh counter 11 counting the number of pulses of the tRAS window signal within the valid level period of the tRFC window signal and the EN signal, when the control circuit 13 detects that the current number of refreshes falls within the preset range, it switches a certain number of refreshes to protection refreshes by outputting a valid RH window signal until the number of refreshes counted by the refresh counter 11 reaches the preset number. Then, in response to the RST_D signal output by the reset circuit 12, it is reset to 0 and enters the next round of counting.

[0059] In combination with the above scheme, the frequency of row hammer protection refresh can be flexibly adjusted by setting the values ​​of the preset number and the preset range. For example, with every 6 as a counting cycle, the 5th and 6th refreshes in each cycle are set as protection refreshes, then the preset number can be set to 6, and the preset range can be set to 4 to 6, that is, in one example, the preset range is 4 to 6. Accordingly, when the counting result is 4 to 6, the control circuit 13 outputs a valid RH window signal, and when the counting result is 6, the reset circuit 12 outputs a RST_D signal, and the refresh counter 11 restarts counting. As an example, refer to Figure 5 The timing diagram shown in the figure uses six refreshes as a counting cycle, and the fifth and sixth refreshes in each counting cycle are protection refreshes as an example. Among them, CNT output is the counting result, and RST_D signal is the cycle reset signal.

[0060] For another example, it is also possible to set every 12 refreshes as a counting cycle, and similarly set the 5th and 6th refreshes in each cycle as protection refreshes, then the preset number can be set to 12, and the preset range can be set to 4 to 6. Accordingly, when the count result is 4 to 6, the control circuit 13 outputs a valid RH window signal, and when the count result is 12, the reset circuit 12 outputs a RST_D signal, and the refresh counter 11 restarts counting. As an example, Figure 6A timing diagram of an example is shown as follows: Figure 6 As shown in the figure, 12 refreshes are considered a counting cycle, and the fifth and sixth refreshes in each counting cycle are protection refreshes. Through the above examples and comparisons, it can be seen that based on the solution provided by this embodiment, the frequency of protection refreshes can be flexibly adjusted by setting a preset number and a preset range, thereby improving the flexibility and reliability of row hammer protection. It should be noted that the above is only an example. In actual applications, the preset number and preset range can be set according to the memory conditions and are not limited here.

[0061] Specifically, the refresh counter 11 is used to count the pulses of the tRAS window signal that are simultaneously within the valid level period of the tRFC window signal and the valid level period of the EN signal, and its implementation circuit is not limited. In one example, Figure 7 A structural diagram of a refresh counter is shown as follows: Figure 7 As shown, the refresh counter 11 includes: an enabling circuit 21, a detection circuit 22, a pulse generating circuit 23 and a counter 24;

[0062] An enable circuit 21 receives an activation command ACT CMD and a periodic reset signal RST_D, and is configured to generate an enable signal EN based on the activation command ACTCMD and the periodic reset signal RST_D; wherein the activation command ACT CMD controls the start time of the active level of the enable signal EN, and the periodic reset signal RST_D controls the end time of the active level of the enable signal EN;

[0063] The detection circuit 22 receives the enable signal EN, the row activation window signal tRAS window, and the refresh window signal tRFC window, and is used to detect whether the pulse of the row activation window signal tRAS window is within the valid level period of the refresh window signal tRFC window and the valid level period of the enable signal EN; if so, outputting the pulse of the row activation window signal tRAS window;

[0064] The pulse generating circuit 23 is connected to the output terminal of the detection circuit 22 and is used to output a valid counting clock CLK in response to the arrival of a pulse of the row activation window signal tRAS window output by the detection circuit 22;

[0065] The clock terminal of the counter 24 is connected to the output terminal of the pulse generating circuit 23, and the reset terminal of the counter 24 is connected to the reset circuit 12, for accumulating counts in response to the effective counting clock CLK and outputting the counting result; and performing count reset in response to the periodic reset signal RST_D.

[0066] Specifically, the enable circuit 21 outputs the EN signal based on the ACT CMD signal and the RST_D signal. In one example, the starting moment of the effective level period of the EN signal corresponds to the effective edge (such as the rising edge) of the ACT CMD signal, and the ending moment of the effective level period of the EN signal corresponds to the effective edge (such as the rising edge) of the RST_D signal. Optionally, before the RST_D signal arrives, if there are multiple ACT CMD signal pulses, the starting moment of the effective level period of the EN signal is controlled based on the effective edge of the first ACT CMD signal. The "corresponding" here refers to timing alignment, but the alignment here is not limited to complete alignment, because signal delay and timing error also need to be considered. Afterwards, the detection circuit 22 detects whether the pulse of the tRAS window signal is located both in the effective level period of the EN signal and in the effective level period of the tRFC window signal. If this condition is met, the pulse of the tRAS window signal is output. Accordingly, after the pulse generating circuit 23 receives the pulse output by the detection circuit 22, it generates a pulse of the counting clock CLK. Accordingly, the counter 24 accumulates 1 in response to the pulse of the counting clock CLK, thereby counting the number of refresh times corresponding to the pulse of the row activation window signal that is both within the valid level period of the refresh window signal and the valid level period of the enable signal.

[0067] The enabling circuit 21 is used to generate the enabling signal EN, and its implementation structure is not limited. In one example, Figure 8 A structural diagram of a refresh counter is shown as follows: Figure 8 As shown, the enabling circuit 21 includes: a first NOT gate 211, a second NOT gate 212, a first NAND gate 213 and a second NAND gate 214;

[0068] An input terminal of the first NOT gate 211 receives an activation command ACT CMD, and an output terminal of the first NOT gate 211 is connected to a first input terminal of the first NAND gate 213;

[0069] An input terminal of the second NOT gate 212 receives the periodic reset signal RST_D, and an output terminal of the second NOT gate 212 is connected to a first input terminal of the second NAND gate 214;

[0070] The second input of the first NAND gate 213 is connected to the output of the second NAND gate 214 . The output of the first NAND gate 213 is connected to the detection circuit 22 . The second input of the second NAND gate 214 is connected to the output of the first NAND gate 213 .

[0071] Specifically, the first NAND gate 213 and the second NAND gate 214 form a NAND-based SR flip-flop structure. The first input of the first NAND gate 213 serves as the set terminal of the SR flip-flop, and the second input of the second NAND gate serves as the reset terminal of the SR flip-flop. Both are active low. For example, when the pulse (high level) of the activation command ACT CMD arrives, the first NAND gate 211 outputs a low level signal via the inverting output. The set terminal of the SR flip-flop is 0 (active), and the SR flip-flop outputs a high level EN signal, indicating the start of the active level period of the EN signal. Next, the pulse of the activation command ACT CMD ends (flips to a low level), and the first NAND gate 212 inverts the set terminal of the SR flip-flop to 1 (inactive). At this point, the count result has not yet reached the preset number of times, so the periodic reset signal RST_D is low. The second NAND gate 212 outputs a high level signal via the inverting output. The reset terminal of the SR flip-flop is also 1 (inactive), and the SR flip-flop maintains the current output signal state, i.e., maintains the high level EN signal output. During the effective level period of the EN signal, the counter 24 counts the pulses of the tRAS window signal within the effective level period of the tRFC window signal until the counting result reaches a preset number, and the reset circuit 12 outputs a high-level RST_D signal. Accordingly, after the inversion of the second NOT gate 212, the reset terminal of the SR flip-flop is 0 (effective), and the SR flip-flop outputs a low-level EN signal, that is, the effective level period of the EN signal ends, thereby generating the enable signal EN.

[0072] It should be noted that the above example is only one possible implementation. In actual applications, the enabling circuit can also be implemented using other circuits. For example, an SR flip-flop structure based on a NOR gate can be used to generate an enable signal EN with the start time of the active level period corresponding to the ACT CMD signal and the end time corresponding to the RST_D signal. The specific implementation of the enabling circuit is not limited here.

[0073] In this example, the enable circuit is composed of conventional circuits such as a NOT gate and a NAND gate, thereby generating an enable signal to execute the subsequent refresh control scheme. Furthermore, the use of conventional circuits in this example facilitates process fabrication, further simplifies the circuit, and reduces costs.

[0074] Specifically, based on the EN signal, the tRAS window signal, and the tRFC window signal, the detection circuit 22 selects the pulses of the tRAS window signal that are simultaneously in the valid level period of the EN signal and the tRFC window signal for output, and its implementation structure is not limited. In one example, Figure 8 As shown, the detection circuit 22 includes: a first AND gate 221;

[0075] A first input terminal of the first AND gate 221 receives the refresh window signal tRFC window, a second input terminal of the first AND gate 221 receives the row activation window signal tRAS window, a third input terminal of the first AND gate 221 is connected to the output terminal of the enable circuit 21, and an output terminal of the first AND gate 221 is connected to the pulse generating circuit 23.

[0076] It should be noted that the figure only illustrates one example of a combined implementation, and other possible implementations are excluded. For example, when the enabling circuit 21 employs other implementation circuits, the illustrated implementation circuit of the detection circuit 22 can also be employed. As an example, taking the aforementioned example of a combined implementation of the enabling circuit 21 and the detection circuit 22 including the first AND gate 221, the third input terminal of the first AND gate 221 is connected to the output terminal of the first NAND gate 213 in the enabling circuit 21.

[0077] Specifically, first AND gate 221 outputs a high-level signal only when all inputs to first AND gate 221 are at a high level. For example, when the active levels of the EN signal and the tRFC window signal are high, when a high-level pulse of the tRAS window signal arrives, if both the EN signal and the tRFC window signal are at a high level, i.e., within the active level period of the EN signal and the tRFC window signal, first AND gate 221 outputs a high-level pulse, which is equivalent to outputting the pulse so that the pulse generation circuit 23 and counter 24 can count the pulse. If either the EN signal or the tRFC window signal is at a low level, first AND gate 221 always outputs a low-level signal, i.e., the pulse is ignored and not output, and counter 24 subsequently does not count the pulse.

[0078] In this example, the detection circuit is composed of AND gates, which select and output pulses within the row activation window signal that fall within the active level periods of both the enable signal and the refresh window signal, thereby executing the subsequent refresh control scheme. Furthermore, this example uses conventional circuitry, which facilitates process fabrication, further simplifies the circuit, and reduces costs.

[0079] Subsequently, in response to the pulse of the tRAS window signal output by the detection circuit 22, the pulse generating circuit 23 generates a counting clock pulse to instruct the counter 24 to accumulate the count. Specifically, the specific structure of the pulse generating circuit is not limited. In one example, Figure 9 A structural diagram of a refresh counter is shown as follows: Figure 9 As shown, the pulse generating circuit 23 includes: a third NOT gate 231, a delay unit 232 and a second AND gate 233;

[0080] A first input terminal of the second AND gate 233 is connected to the output terminal of the detection circuit 22 , and a second input terminal of the second AND gate 233 is connected to the output terminal of the delay unit 232 ;

[0081] The input end of the third NOT gate 231 is connected to the output end of the detection circuit 22, and the output end of the third NOT gate 231 is connected to the input end of the delay unit 232. The delay time of the delay unit 232 is used to control the pulse width of the counting clock CLK.

[0082] The output terminal of the second AND gate 233 , as the output terminal of the pulse generating circuit 23 , is connected to the clock terminal of the counter 24 .

[0083] Among them, the delay duration of the delay unit 232 can be set as needed, and accordingly, the pulse width of the pulse signal of the generated count clock CLK is consistent with the delay duration. In practical applications, the delay duration can be set to a smaller value to save power consumption. In conjunction with the circuit example, initially, the detection circuit 22 does not output a pulse of the tRAS window signal, that is, the detection circuit 22 continuously outputs a low level, and the first input end of the second AND gate 233 is 0. At this stage, the low level output by the detection circuit 22 is inverted and outputs a high level through the third NOT gate 231. This high level reaches the second input end of the second AND gate 233 after the delay of the delay unit 232. That is, the first input end of the second AND gate 233 is 0, the second input end of the second AND gate 233 is 1, and the second AND gate 233 outputs a low level.

[0084] Afterwards, when the detection circuit 22 detects a pulse of the row activation window signal that is simultaneously within the valid level period of the enable signal and the refresh window signal, the pulse is output. When outputting the pulse, the output of the detection circuit 22 flips from a low level to a high level. Accordingly, the first input terminal of the second AND gate 233 receives a high level signal. At this time, the third NOT gate 231 also receives the high level signal output by the detection circuit 22, and outputs a low level signal after inversion. However, the low level signal needs to be delayed by the delay unit 232 before it can reach the second AND gate 233. Therefore, before the low level output by the third NOT gate 231 reaches the second input terminal of the second AND gate 233, the first input terminal and the second input terminal of the second AND gate 233 are both 1, and the output of the second AND gate 233 flips to a high level until the low level output by the third NOT gate 231 reaches the second input terminal of the second AND gate 233. The output of the second AND gate 233 flips to a low level again, completing the output of a counting clock pulse. With reference to the example in the figure, Figure 10 is an example timing diagram, which shows the input terminal of the third NOT gate 231, as shown in FIG. Figure 9 Point A in the figure, and the output terminal of the third NOT gate 231, as shown in FIG. Figure 9 Point B in the figure, and the second input terminal of the second AND gate 233, that is, Figure 9Point C in FIG, and the timing waveform of the counting clock CLK. The specific structure of the delay unit is not limited, for example, it may include an even number of inverters connected in series.

[0085] In this example, the pulse generation circuit consists of an AND gate, a NOT gate, and a delay unit, thereby outputting a pulse count clock in response to the row activation window signal to execute the subsequent refresh control scheme. Furthermore, this example uses conventional circuitry, which facilitates process fabrication, further simplifies the circuit, and reduces costs.

[0086] In response to the counting clock output by the pulse generating circuit 23, the counter 24 counts once. The specific structure of the counter is not limited. In one example, Figure 11 A schematic diagram of the structure of a counter is shown as an example. Figure 11 As shown, the counter 24 includes: a multi-stage first trigger 241;

[0087] The clock end of the first-stage first trigger 241 is connected to the output end of the pulse generating circuit 23, and the clock ends of other first triggers 241 are connected to the inverting output end of the first trigger 241 of the previous stage; the input end of each first trigger 241 is connected to the inverting output end of the first trigger 241, and the value output by the inverting output end of each stage of the first trigger 241 constitutes the output CNT<…> of the counter, which is a binary representation of the counting result; the reset end of each first trigger 241 is connected to the output end of the reset circuit 12.

[0088] In order to facilitate the understanding of the scheme, Figure 12 For example: Figure 12 2 is an example diagram of the counting process. In practical applications, the number of first triggers can be determined as needed. For example, when the preset number is set to 12, five first triggers can be set. Figure 12 Taking the five-stage first trigger as an example, the output of the first trigger is the first bit CNT of the counting result. <0> The output of the first trigger of the second stage is the second bit CNT of the counting result. <1> The output of the first trigger of the third stage is the third bit CNT of the counting result. <2> The output of the first trigger of the fourth stage is the 4th bit CNT of the counting result. <3> The output of the first flip-flop of the fifth stage is the fifth bit CNT of the counting result. <4> .

[0089] Initially, the counting clock CLK is at a low level, and the in-phase output terminal of each first trigger 241 outputs 0, CNT <4> ~CNT <0> is 00000, indicating that the counting result is 0. At the same time, the inverting output terminal of each first flip-flop 241 outputs 1, and accordingly, the input terminal of each first flip-flop 241 is 1. Afterwards, when the first pulse of the counting clock CLK arrives, in response to the rising edge of the first counting clock pulse, the first-stage first flip-flop 241 outputs the signal at the input terminal (which is 1 at this time) to the non-inverting output terminal. At this time, the CNT output of the non-inverting output terminal of the first-stage first flip-flop 241 is <0> The output of the inverting output terminal is 0, and the input terminal is 0; the signal at the clock terminal of the second-stage first flip-flop 241 flips to 0 (falling edge), and the input and output states of the second-stage first flip-flop 241 are not updated. The output CNT of the entire counter 24 is <4> ~CNT <0> Updated to 00001, indicating that the count result is 1.

[0090] Afterwards, when the second pulse of the counting clock CLK arrives, in response to the rising edge of the second counting clock pulse, the first trigger 241 of the first stage outputs the signal of the input terminal (which is 0 at this time) to the in-phase output terminal. At this time, the CNT output of the in-phase output terminal of the first trigger 241 of the first stage is <0> The output of the inverting output terminal is updated to 0, and the output of the inverting output terminal is flipped to 1, generating a rising edge; the clock terminal of the second-stage first flip-flop 241 receives the rising edge, the output of the inverting output terminal of the second-stage first flip-flop 241 is updated to 1, and the inverting output terminal is flipped to 0, generating a falling edge; the input and output states of the third-stage first flip-flop 241 are not updated. The output CNT of the entire counter 24 <4> ~CNT <0> Updated to 0010, the characterization count result is 2.

[0091] Based on the above principle, multiple stages of first flip-flops are used to implement counting in response to pulses of the counting clock and output a binary representation of the counting result. This continues until the reset terminals of the first flip-flops 241 receive the periodic reset signal RST_D, resetting the outputs of all first flip-flops 241 to 0, returning to the initial state. The non-inverting output terminals of each stage of first flip-flops 241 all output 0, and the counter 24 restarts counting.

[0092] In this example, the counter is composed of multiple stages of first flip-flops, which enable counting and outputting the count result in response to a count clock to execute a subsequent refresh control scheme. Furthermore, this example uses conventional circuit implementation, which facilitates process fabrication, further simplifies the circuit, and reduces costs.

[0093] In this embodiment, the periodic reset signal RST_D is used to control the number of refreshes within a single counting cycle. The periodic reset signal RST_D is generated by the reset circuit 12, and the specific structure of the reset circuit is not limited. In one example, Figure 13FIG. 1 is a schematic diagram of a reset circuit as an example. Figure 13 As shown, the reset circuit 12 includes: a reset generation circuit 31 and an output circuit 32;

[0094] The reset generation circuit 31 is connected to the output terminal of the refresh counter 11 and receives the period setting signal TM<…>, and is configured to output an initial reset signal RST_T to the output circuit 32 when the count result output by the refresh counter 11 reaches a preset number of times corresponding to the period setting signal TM<…>;

[0095] The input end of the output circuit 32 is connected to the output end of the reset generation circuit 31. The output circuit 32 is configured to output the initial reset signal RST_T as the periodic reset signal RST_D in response to the end of the pulse of the row activation window signal tRAS window during the valid level period of the refresh window signal tRFC window.

[0096] In conjunction with the scenario example, when it is necessary to set a preset number of times, that is, the upper limit value of the count of a single counting cycle, a cycle setting signal TM<…> can be input to the refresh control circuit. The cycle setting signal may include at least one bit, and its data length may be determined as needed. For example, assuming that two counting cycles are provided, for example, 6 or 12, that is, the refresh control circuit supports every 6 refreshes as a counting cycle, or every 12 refreshes as a counting cycle, then the cycle setting signal may include one bit. Different counting cycles are represented by different values ​​based on this one bit. For example, when the cycle setting signal is 0, each counting cycle is set to include 6 refreshes, and when the cycle setting signal is 1, each counting cycle is set to include 12 refreshes.

[0097] Specifically, the reset generation circuit 31 determines the number of refresh cycles included in a corresponding single counting cycle based on the current cycle setting signal, namely the aforementioned preset number. When the count result output by the current refresh counter 11 reaches the preset number, it outputs the initial reset signal RST_T. Subsequently, upon receiving the initial reset signal RST_T, the output circuit 32 does not directly output the signal. Instead, it waits for the end of the last pulse of the row activation window signal tRAS window included in the current count result before outputting the received initial reset signal RST_T as the cycle reset signal RST_D, thereby resetting the refresh counter.

[0098] This design is intended to precisely control the active level period of the guard refresh window signal and improve the reliability of guard refreshes. For example, suppose a desired refresh count of six per count cycle is achieved, with RH guard refreshes performed at the fifth and sixth refreshes in each count cycle. Based on the previous example, the preset number is set to six, and the preset range is set to 4 to 6. Refresh counter 11 counts pulses of the tRAS window signal within the active level periods of both the tRFC window signal and the EN signal. In response to the clock pulse of count clock CLK corresponding to the fourth refresh, counter 24 outputs a count result of 4, which falls within the preset range. Accordingly, control circuit 13 begins outputting an active guard refresh window signal, and refreshes performed during the active level period of the guard refresh window signal are RH guard refreshes. That is, the fifth refresh is an RH guard refresh. The pulses of the tRAS window signal generated during the fifth refresh are again counted by refresh counter 11, and the output count result is updated to 5, still within the preset range. Control circuit 13 continues to output the active guard refresh window signal. By the sixth refresh, the state is still within the active level period of the protection refresh window signal, so the sixth refresh is also an RH protection refresh. Simultaneously, in response to the arrival of the pulse of the tRAS window signal corresponding to the sixth refresh, the refresh counter 11 updates its count result to 6. At this point, the count result reaches the preset number, and the reset generation circuit 31 generates an initial reset signal RST_T. However, to ensure that the sixth refresh is properly executed as a protection refresh (protection refresh must be performed within the active level period of the protection refresh window signal), the output circuit 32 does not initially output this initial reset signal RST_T. Instead, it waits until the current refresh stabilizes, that is, when the pulse of the tRAS window signal corresponding to the sixth refresh ends, before outputting it as a periodic reset signal RST_D to the refresh counter 11 for resetting, thereby ensuring that the RH protection refresh can be reliably executed.

[0099] In one example, the cycle setting signal includes two bits, and the preset number includes four values, which are recorded as the first number, the second number, the third number, and the fourth number. For example, the values ​​of the preset number can be 6, 12, 18, and 24. Specifically, the cycle setting device includes two bits, which can realize four values ​​00, 01, 10, and 11, corresponding to the four values ​​of the preset number. This example supports the selection and setting of the preset number through the cycle setting signal, thereby flexibly adjusting the refresh number of a single counting cycle to achieve flexible adjustment of the execution frequency of the RH protection refresh.

[0100] Specifically, for the case where a preset number of times is supported, the reset generation circuit needs to determine the current preset number of times according to the current cycle setting signal, so as to instruct the refresh counter to reset when the counting result reaches the preset number of times. Figure 13 As shown, the reset generation circuit 31 includes:

[0101] a period decoding circuit 311, which receives a period setting signal TM<…> and outputs a first-order selection signal RH_0, a second-order selection signal RH_1, a third-order selection signal RH_2, and a fourth-order selection signal RH_3 according to the period setting signal TM<…>;

[0102] A sub-decoder 312 corresponding to each number; each sub-decoder 312 receives at least one bit of the counting result and is configured to output a flag signal of the number when the value currently represented by the at least one received bit is consistent with the number corresponding to the sub-decoder 312;

[0103] A third AND gate 313 corresponding to each number; each third AND gate 313 receives a selection signal of a corresponding number and a flag signal of a corresponding number;

[0104] The OR operation unit 314 has an input terminal connected to the output terminals of all the third AND gates 313 , and an output terminal of the OR operation unit 314 is used to output the initial reset signal RST_T.

[0105] As an example, the flag signal for the first count in the figure is CNT_M, the flag signal for the second count is CNT_N, the flag signal for the third count is CNT_O, and the flag signal for the fourth count is CNT_P. The count flag signal effectively indicates that the current count result is consistent with that count, and the count selection signal effectively indicates that the count is currently selected. It can be understood that for any preset count, the count is reset only when that count is selected and the current count result reaches that count. That is, the reset generation circuit outputs the initial reset signal. For example, using an active-high level, a third AND gate is provided to detect whether the reset condition is currently met. In the example shown in the figure, a corresponding third AND gate 313 is set for each preset count. For example, taking the preset count as having four possible values, four third AND gates are provided. The third AND gate that receives the first count flag signal CNT_M and the select signal RH_0 corresponds to the first count, the third AND gate that receives the second count flag signal CNT_N and the select signal RH_1 corresponds to the second count, the third AND gate that receives the third count flag signal CNT_O and the select signal RH_2 corresponds to the third count, and the third AND gate that receives the fourth count flag signal CNT_P and the select signal RH_3 corresponds to the fourth count. By performing an AND logic operation on the flag signal and the select signal, it is detected whether the current count result has reached the currently selected count, thereby achieving accurate and timely reset.

[0106] For the OR operation unit, as long as any third AND gate outputs a valid level, an initial reset signal is output. Optionally, the OR operation unit is used to perform an OR logic operation on the output signals of the third AND gate corresponding to all times, and its specific structure is not limited. For example, the OR operation unit may include at least one OR gate, and the number of OR gates may be determined according to the number of third AND gates, that is, the number of preset times. For example, when the number of preset times is small, the OR operation unit may include a multi-input OR gate implementation. For example, if the preset number has two values, the OR operation unit may include one OR gate; if the preset number has three values, the OR operation unit may include a three-input OR gate. When the number of preset times is large, the OR operation unit may also be implemented by a multi-level OR gate unit. For example, as shown in the example, for the case where the above-mentioned preset number has four values, the OR operation unit 314 can be implemented as a two-level OR gate unit, and each level of the OR gate unit includes at least one OR gate 315. As Figure 13 As shown, the first-stage OR gate unit includes multiple (e.g., two) OR gates 315, whose inputs receive the outputs of the third AND gates 313, respectively. The second-stage OR gate unit includes one OR gate 315, which receives the outputs of the multiple OR gates in the previous-stage OR gate unit. The output of the OR gate in the second-stage OR gate unit is used to output the initial reset signal RST_T.

[0107] Specifically, the cycle decoding circuit is used to output a selection signal for each number of times. The selection signal for the number of times selected by the cycle setting signal is valid, and the selection signals for other numbers of times are invalid. In one example, Figure 14 FIG. 1 is a schematic diagram of a structure of an exemplary cycle decoding circuit, as shown in FIG. Figure 14 As shown, the cycle decoding circuit 311 includes:

[0108] A first NOR gate 41 has a first input terminal receiving one bit TM of a period setting signal. <0> The second input terminal of the first NOR gate 41 receives another bit TM of the cycle setting signal <1> , the first NOR gate 41 is used to output the first selection signal RH_0;

[0109] a fourth NOT gate 42 and a second NOR gate 43, wherein the input end of the fourth NOT gate 42 is connected to the first input end of the first NOR gate 41, the output end of the fourth NOT gate 42 is connected to the first input end of the second NOR gate 43, the second input end of the second NOR gate 43 is connected to the second input end of the first NOR gate 41, and the second NOR gate 43 is used to output the second selection signal RH_1;

[0110] a fifth NOT gate 44 and a third NOR gate 45, wherein a first input terminal of the third NOR gate 45 is connected to the first input terminal of the first NOR gate 41, an input terminal of the fifth NOT gate 44 is connected to the second input terminal of the first NOR gate 41, an output terminal of the fifth NOT gate 44 is connected to the second input terminal of the third NOR gate 45, and the third NOR gate 45 is used to output a third selection signal RH_2;

[0111] A third NAND gate 46 and a sixth NAND gate 47, wherein a first input terminal of the third NAND gate 46 is connected to a first input terminal of the first NOR gate 41, a second input terminal of the third NAND gate 46 is connected to a second input terminal of the first NOR gate 41, an output terminal of the third NAND gate 46 is connected to an input terminal of the sixth NAND gate 47, and the sixth NAND gate 47 is used to output a fourth selection signal RH_3.

[0112] It should be noted that the figure only shows the period setting signal including two bits TM <0> and TM <1> The preset times include four values ​​as examples. In actual applications, the specific structure of the cycle decoding circuit can be designed according to actual conditions and is not limited to the example in the figure. Specifically, a cycle setting signal of 00 indicates the selection of the first number, a cycle setting signal of 01 indicates the selection of the second number, a cycle setting signal of 10 indicates the selection of the third number, and a cycle setting signal of 11 indicates the selection of the fourth number.

[0113] Take the structure shown in the figure as an example: when the period setting signal TM<1:0> is 00, the TM received by the first NOR gate 41 is <0> and TM <1> are all 0, the first NOR gate 41 outputs 1, that is, the first selection signal is valid; in the signal received by the second NOR gate 43, TM <0> The inverted signal is 1, TM <1> is 0, so the second NOR gate outputs 0, that is, the selection signal of the second number is invalid; similarly, at this time, one input signal of the third NOR gate 45 is 1, so the third NOR gate 45 outputs 0, that is, the selection signal of the third number is invalid; the TM received by the third NAND gate 46 <0> and TM <1> are all 0, the third NAND gate 46 outputs 1, which is inverted by the sixth NOT gate 47 and outputs 0, that is, the fourth selection signal is invalid. When the cycle setting signal TM<1:0> is 10, the TM received by the first NOR gate 41 <0> is 0, TM <1> is 1, the first NOR gate 41 outputs 0, that is, the first selection signal is invalid; in the signal received by the second NOR gate 43, TM <0> The inverted signal is 1, TM <1> is 1, so the second NOR gate outputs 0, that is, the second number selection signal is invalid; in the signal received by the third NOR gate 45, TM <0> The inverted signal is 0, TM <1> The inverted signal of is 0, so the third NOR gate 45 outputs 1, that is, the selection signal of the third number is valid; the TM received by the third NAND gate 46 <0> Bit 0, TM <1> is 1, the third NAND gate 46 outputs 1, which is inverted by the sixth NOT gate 47 and outputs 0, that is, the fourth selection signal is invalid.

[0114] In this example, the cycle decoding circuit is composed of a NOT gate, a NOR gate, and a NAND gate. This circuit outputs a selection signal for each number of cycles based on a cycle setting signal, thereby executing the subsequent refresh control scheme. Furthermore, this example uses a conventional circuit implementation, which facilitates process fabrication, further simplifies the circuit, and reduces costs.

[0115] Each sub-decoder is used to output a flag signal of the preset number of times when the counting result reaches the corresponding preset number of times. In one example, Figure 15 A schematic diagram of the structure of a sub-decoder is shown as follows: Figure 15 As shown:

[0116] The sub-decoder corresponding to the first count includes a fourth AND gate 51; the input ends of the fourth AND gate 51 receive the third bit CNT of the counting result respectively. <2> and the second bit CNT <1> The output terminal of the fourth AND gate 51 is used to output the first count flag signal CNT_M;

[0117] The sub-decoder corresponding to the second number includes a fifth AND gate 52; the input terminals of the fifth AND gate 52 receive the fourth bit CNT of the counting result respectively. <3> and the third bit CNT <2> The output terminal of the fifth AND gate 52 is used to output the flag signal CNT_N of the second count;

[0118] The sub-decoder corresponding to the third number includes a sixth AND gate 53; the input terminals of the sixth AND gate 53 receive the fifth bit CNT of the counting result respectively. <4> and the second bit CNT <1> The output terminal of the sixth AND gate 53 is used to output the flag signal CNT_O of the third number;

[0119] The sub-decoder corresponding to the fourth number includes a seventh AND gate 54; the input terminals of the seventh AND gate 54 receive the fifth bit CNT of the counting result respectively. <4> and the 4th bit CNT <3> The output terminal of the seventh AND gate 54 is used to output the flag signal CNT_P of the fourth time.

[0120] It should be noted that the input signals of each sub-decoder in the figure are exemplified by the first number being 6, the second number being 12, the third number being 18, and the fourth number being 24. The figure is only an example and does not exclude other possible implementation methods. For example, the preset number of times may also be set to other values.

[0121] Combined with the example in the figure, the first digit of the counting result is CNT <0> , the second position is CNT <1> , the third position is CNT <2> , the 4th position is CNT <3> , the fifth is CNT <4> Taking the current count result as 5 as an example, the corresponding CNT<4:0> is 00101. Taking the high level as an example, the CNT<4:0> received by the fourth AND gate 51 is 00101. <2> 1. CNT <1> =0, so the fourth AND gate 51 outputs 0, and the first count flag signal CNT_M is invalid. <3> =0, so the fifth AND gate 52 outputs 0, and the second count flag signal CNT_N is invalid. Similarly, the sixth AND gate 53 and the seventh AND gate 54 both have an input CNT <4> It is 0, so both output 0, and the flag signals of the third and fourth times are also invalid.

[0122] Let's take the example of counting results reaching different preset times: for example, if the counting result is 6, the corresponding CNT <4> ~CNT <0> The CNT received by the fourth AND gate 51 is 00110. <2> 1. CNT <1> =1, so the fourth AND gate 51 outputs 1, and the first count flag signal CNT_M is valid. At the same time, the fifth AND gate 52 receives CNT <3> =0, so the fifth AND gate 52 outputs 0, and the second count flag signal CNT_N is invalid. Similarly, the sixth AND gate 53 and the seventh AND gate 54 both have an input CNT <4> is 0, so both output 0, and the flag signals of the third and fourth times are also invalid. In this example, the current counting result reaches the first number, but whether the reset generation circuit outputs the initial reset signal depends on whether the first number is the currently selected number. Assuming that the first number is the currently selected number, for example, the aforementioned cycle setting signal is 00, then the selection signal of the first number is also valid, then the reset generation circuit will output the initial reset signal, and the corresponding refresh counter will be reset to 0 at the end of the 6th pulse of the tRASwindow signal. Assuming that the currently selected preset number is 12, even if the flag signal of the first number is valid, since the selection signal of the first number is invalid, the reset generation circuit will not output the initial reset signal, the refresh counter will not be reset, and will continue counting.

[0123] For example, if the count result is 12, the corresponding CNT <4> ~CNT <0> The CNT received by the fourth AND gate 51 is 01100. <2> 1. CNT <1> =0, so the fourth AND gate 51 outputs 0, and the first count flag signal CNT_M is invalid. <3> =1, CNT <2> =1, so the fifth AND gate 52 outputs 1, and the second count flag signal CNT_N is valid. The sixth AND gate 53 and the seventh AND gate 54 both have an input CNT <4> =0, so both output 0, and the flag signals of the third and fourth times are invalid. Similarly, the reset generation circuit also needs to detect whether the selection signal of the second number is valid to decide whether to output the initial reset signal.

[0124] In this example, the sub-decoding circuit is composed of AND gates, which output a flag signal for each count based on the current count result to execute the subsequent refresh control scheme. Furthermore, this example uses conventional circuits for easy fabrication, further simplifying the circuit and reducing costs.

[0125] The reset generation circuit 31 of the above example can output the initial reset signal in a timely manner according to the counting result and the currently selected preset number of times. Subsequently, the output circuit 32 waits for the end of the current pulse of the tRAS window signal and outputs the initial reset signal as a periodic reset signal. In one example, Figure 13 As shown, the output circuit 32 includes:

[0126] a seventh NOT gate 321 , wherein an input terminal of the seventh NOT gate 321 receives a row activation window signal tRAS window;

[0127] an eighth AND gate 322 , wherein a first input terminal of the eighth AND gate 322 receives the refresh window signal tRFC window , and a second input terminal of the eighth AND gate 322 is connected to the output terminal of the seventh NOT gate 321 ;

[0128] The second trigger 323 has its input connected to the output of the reset generation circuit 31 , its output connected to the reset of the refresh counter 11 , and its clock connected to the output of the eighth AND gate 322 .

[0129] Specifically, the second flip-flop 323 responds to the rising edge, and the seventh NOT gate 321 is used to invert the tRAS window signal. It can be seen that the rising edge of a pulse in the row activation window signal tRAS window is inverted to obtain a falling edge, and the falling edge is inverted to obtain a rising edge. Therefore, it is assumed that when the reset generation circuit 31 responds to the arrival of the pulse (rising edge) of the tRAS window signal that meets the reset condition and outputs the initial reset signal RST_T, it is now within the valid level period of the tRFC window signal, so the first input terminal of the eighth AND gate 322 receives a high level, and the output signal of the eighth AND gate is consistent with the signal at the second input terminal. Therefore, at this time, the signal received at the clock terminal of the second flip-flop 323 is the falling edge of the rising edge of the pulse of the tRAS window signal after inversion, and the second flip-flop 323 does not output the periodic reset signal RST_D. Until the end of the pulse, that is, the tRASwindow signal has a falling edge, it is inverted by the seventh NOT gate 321 to obtain a rising edge, triggering the second flip-flop 323 to output the periodic reset signal RST_D. Refer to Figure 5 or Figure 6 The timing example shows that the count result is reset after the last pulse of the tRAS window signal in each counting cycle. Accordingly, if the count result after the reset falls outside the preset range, the valid period of the RHwindow signal ends. It should be noted that in practical applications, appropriate signal delays can be added to account for signal latency and circuit reliability. For example, in the figure, the periodic reset signal RST_D is output only after a certain period of time has passed after the sixth pulse of the tRAS window signal in the counting cycle.

[0130] In this example, the output circuit consists of a NOT gate, an AND gate, and a flip-flop. This circuit outputs a period reset signal at the end of the last pulse of the tRASwindow signal within the counting cycle, enabling subsequent refresh control. Furthermore, this example uses a conventional circuit implementation, which facilitates process fabrication, further simplifies the circuit, and reduces costs.

[0131] In this embodiment, the control circuit is used to output a protection refresh window signal when the counting result falls within a preset range, so as to perform RH protection refresh within the protection refresh window signal. In one example, Figure 16 FIG. 1 is a structural diagram of an exemplary control circuit, such as Figure 16 As shown, the control circuit 13 includes: a first multi-input AND gate 131, a second multi-input AND gate 132, a third multi-input AND gate 133 and a first multi-input OR gate 134;

[0132] The first multi-input AND gate 131 has a plurality of input terminals, and the plurality of input terminals of the first multi-input AND gate 131 respectively receive the inverted signal CNTB of the first bit of the counting result. <0> , the second bit inverted signal CNTB <1> And the third bit CNT <2> ;

[0133] The second multi-input AND gate 132 has a plurality of input terminals, and the plurality of input terminals of the second multi-input AND gate 132 respectively receive the first bit CNT of the counting result. <0> , the second bit inverted signal CNTB <1> And the third bit CNT <2> ;

[0134] The third multi-input AND gate 133 has a plurality of input terminals, and the plurality of input terminals of the third multi-input AND gate 133 respectively receive the inverted signal CNTB of the first bit of the counting result. <0> , the second bit CNT <1> And the third bit CNT <2> ;

[0135] A first input terminal of the first multi-input OR gate 134 is connected to the output terminal of the first multi-input AND gate 131, a second input terminal of the first multi-input OR gate 134 is connected to the output terminal of the second multi-input AND gate 132, a third input terminal of the first multi-input OR gate 134 is connected to the output terminal of the third multi-input AND gate 133, and an output terminal of the first multi-input OR gate 134 is used to output the protection refresh window signal RH window.

[0136] It should be noted that the situation shown in the figure is based on the preset range of 4 to 6 as an example, but other possible implementations are not excluded. For example, the preset range of other value intervals can also be set. Figure 5 or Figure 6In this example, the control circuit outputs a valid RH window signal in response to the count result being within a preset range. The illustrated timing sequence is merely an example; in actual applications, appropriate signal delays may be added to account for signal latency and circuit reliability. For example, the RH window signal's valid level period in the figure begins a certain period after the count result is updated to 4.

[0137] Combined with the example in the figure, the first digit of the counting result is CNT <0> , the second position is CNT <1> , the third position is CNT <2> , the 4th position is CNT <3> , the fifth is CNT <4> Taking the current count result as 3 as an example, the corresponding CNT <4> ~CNT <0> is 00011, accordingly, the CNTB received by the first multi-input AND gate 131 <0> 、CNTB <1> and CNT <2> are all 0, so the first multi-input AND gate 131 outputs 0. At the same time, among the input signals received by the second multi-input AND gate 132, CNTB <1> and CNT <2> is 0, so the second multi-input AND gate 132 outputs 0. Among the input signals received by the third multi-input AND gate 133, CNT <2> =0, so the third multi-input AND gate 133 outputs 0. Accordingly, the RH window signal output by the first multi-input OR gate 134 is 0, indicating that the RH window signal is invalid at this time, that is, RH protection refresh is not performed.

[0138] Let's take the counting result falling into the preset range as an example: for example, the counting result is 4, the corresponding CNT <4> ~CNT <0> is 00100. Accordingly, the CNTB received by the first multi-input AND gate 131 is <0> 、CNTB <1> and CNT <2> are both 1, so the first multi-input AND gate 131 outputs 1. At the same time, among the input signals received by the second multi-input AND gate 132, CNT <0> is 0, so the second multi-input AND gate 132 outputs 0. Among the input signals received by the third multi-input AND gate 133, CNT <1> =0, so the third multi-input AND gate 133 outputs 0. Correspondingly, the RH window signal output by the first multi-input OR gate 134 is 1, indicating that the RH window signal is valid at this time, and the RH protection refresh is performed during the valid period. For example, if the count result is 5, the corresponding CNT <4> ~CNT <0> The first multi-input AND gate 131 receives the CNTB <0> is 0, so the first multi-input AND gate 131 outputs 0. At the same time, among the input signals received by the second multi-input AND gate 132, CNT <0> 、CNTB <1> and CNT <2> are all 1, so the second multi-input AND gate 132 outputs 1. Among the input signals received by the third multi-input AND gate 133, CNTB <0> and CNT <1> =0, so the third multi-input AND gate 133 outputs 0. Correspondingly, the RH window signal output by the first multi-input OR gate 134 is still 1 and remains valid.

[0139] For example, if the count result is 6, the corresponding CNT <4> ~CNT <0> The first multi-input AND gate 131 receives the CNTB <1> is 0, so the first multi-input AND gate 131 outputs 0. At the same time, among the input signals received by the second multi-input AND gate 132, CNTB <1> is 0, so the second multi-input AND gate 132 outputs 0. Among the input signals received by the third multi-input AND gate 133, CNTB <0> 、CNT <1> and CNT <2> are all 1, so the third multi-input AND gate 133 outputs 1. Correspondingly, the RH window signal output by the first multi-input OR gate 134 remains 1 and remains valid. It should be noted that, in conjunction with the above example, when the count result is 6, the reset circuit 12 is also triggered to reset the count at the end of the pulse of the tRAS window signal of the current refresh (this is the sixth refresh in the current counting cycle). It can be understood that after the count result is reset to 00000, the control circuit 13 will output an invalid RH window signal, and the refresh counter 11 will restart counting.

[0140] The control circuit of the above example can output a valid RH window signal in a timely manner when the current counting result is within the preset range. Moreover, it is implemented by conventional devices such as AND gates and OR gates, which can further simplify the circuit and process and reduce costs.

[0141] The refresh control circuit provided in this embodiment includes a refresh counter, a reset circuit, and a control circuit. The refresh counter counts the pulses of the row activation window signal within the effective level period of the refresh window signal and the enable signal, and outputs the counting result. When the counting result reaches a preset number of times, the reset circuit instructs the refresh counter to reset. When the counting result is within a preset range, the control circuit outputs a valid protection refresh window signal to execute the row hammer protection refresh within the effective level period of the protection refresh window signal. The above scheme can realize row hammer protection refresh, and based on the support for setting a preset number of times and a preset range in this scheme, a certain number of refreshes can be selected in each round of the preset number of refreshes to execute row hammer protection refresh, so that while realizing row hammer protection refresh, the execution frequency of protection refresh can be adjusted, thereby improving the flexibility of row hammer protection.

[0142] Figure 17 This is an example diagram of the structure of an example memory, such as Figure 17 As shown, the memory includes: an instruction decoder 1, a refresh operation module 2, a storage block control module 3 and a refresh control circuit 4 as in any of the previous examples;

[0143] The instruction decoder 1 is used to parse and generate an activation command ACT CMD and a refresh command REF CMD according to an external instruction; the refresh operation module 2 is connected to the instruction decoder 1 and is used to output a refresh window signal tRFCwindow and a row activation window signal tRAS window in response to the refresh command REF CMD;

[0144] The refresh control circuit 4 is connected to the instruction decoder 1, the refresh operation module 2 and the storage block control module 3, and is used to output the protection refresh window signal RH window according to the activation command ACT CMD, the refresh window signal tRFC window and the row activation window signal tRAS window;

[0145] The memory block control module 3 is connected to the refresh control circuit 4 and the refresh operation module 2 , and is configured to execute refresh in response to a signal output by the refresh operation module 2 , and execute row hammer protection refresh in response to the protection refresh window signal RH window .

[0146] In combination with the solution of the aforementioned embodiment, taking DRAM as an example: Based on the aforementioned solution, the instruction decoder 1 parses the external instruction, such as the instruction issued by the processor, to obtain the activation command ACT CMD and the refresh instruction REF CMD. The refresh instruction is transmitted to the refresh operation module 2. At the same time, the instruction decoder 1 also transmits the activation command ACT CMD to the refresh control circuit 4. The refresh operation module 2 generates some window signals representing refresh parameters based on the refresh instruction REF CMD, such as the refresh window signal tRFC window and the row activation window signal tRAS window. The storage block control module 3 performs refresh based on the window signal output by the refresh operation module 2. During this period, when the refresh performed by the storage block control module 3 during the valid level period of the RH window signal output by the refresh control circuit 4 is switched to RH protection refresh. Among them, the refresh control circuit 4 includes a refresh counter, a reset circuit, and a control circuit.

[0147] The reset circuit is used to set the counting cycle. The refresh counter is used to count the number of refreshes performed during the valid period of the enable signal according to the counting cycle. A reset is performed at the end of each counting cycle. The control circuit outputs a valid RH window signal when the counting result reaches a preset range.

[0148] In the memory provided by this embodiment, the refresh control circuit includes a refresh counter, a reset circuit, and a control circuit. The refresh counter counts the pulses of the row activation window signal within the effective level period of the refresh window signal and the enable signal, and outputs the counting result. When the counting result reaches a preset number of times, the reset circuit instructs the refresh counter to reset. When the counting result is within a preset range, the control circuit outputs a valid protection refresh window signal to execute the row hammer protection refresh within the effective level period of the protection refresh window signal. The above scheme can realize row hammer protection refresh, and based on the support for setting a preset number of times and a preset range in this scheme, a certain number of refreshes can be selected in each round of the preset number of refreshes to execute row hammer protection refresh, so that while realizing row hammer protection refresh, the execution frequency of protection refresh can be adjusted, thereby improving the flexibility of row hammer protection.

[0149] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only.

[0150] It will be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A refresh control circuit, characterized in that: include: a refresh counter receiving an activation command, a row activation window signal, and a refresh window signal, for counting pulses of the row activation window signal within an effective level period of the refresh window signal and within an effective level period of the enable signal, outputting a counting result, and performing a count reset in response to a period reset signal; wherein the enable signal is generated based on the activation command and the periodic reset signal; a reset circuit, wherein an input end of the reset circuit is connected to an output end of the refresh counter, and an output end of the reset circuit is connected to a reset end of the refresh counter, and is configured to output the periodic reset signal when a count result currently output by the refresh counter reaches a preset number; A control circuit, wherein the input end of the control circuit is connected to the output end of the refresh counter, and is used to output a protection refresh window signal according to the counting result currently output by the refresh counter; wherein, when the counting result is within a preset range, the protection refresh window signal is at a valid level.

2. The refresh control circuit according to claim 1, wherein: The refresh counter includes: an enabling circuit, a detection circuit, a pulse generating circuit and a counter; The enabling circuit receives the activation command and the periodic reset signal, and is configured to generate the enabling signal based on the activation command and the periodic reset signal; wherein the activation command controls a starting time of an effective level of the enabling signal, and the periodic reset signal controls an ending time of an effective level of the enabling signal; The detection circuit receives the enable signal, the row activation window signal, and the refresh window signal, and is used to detect whether the pulse of the row activation window signal is located within the effective level period of the refresh window signal and the effective level period of the enable signal; if so, outputting the pulse of the row activation window signal; The pulse generating circuit is connected to the output terminal of the detection circuit and is used to output a valid counting clock in response to the arrival of the pulse of the row activation window signal output by the detection circuit; The clock end of the counter is connected to the output end of the pulse generating circuit, and the reset end of the counter is connected to the reset circuit, for accumulating counts in response to a valid counting clock and outputting counting results; and performing count reset in response to the periodic reset signal.

3. The refresh control circuit according to claim 2, wherein: The detection circuit includes: a first AND gate; The first input end of the first AND gate receives the refresh window signal, the second input end of the first AND gate receives the row activation window signal, the third input end of the first AND gate is connected to the output end of the enable circuit, and the output end of the first AND gate is connected to the pulse generating circuit.

4. The refresh control circuit according to claim 3, wherein: The enabling circuit includes: a first NOT gate, a second NOT gate, a first NAND gate and a second NAND gate; The input end of the first NOT gate receives the activation command, and the output end of the first NOT gate is connected to the first input end of the first NAND gate; The input end of the second NOT gate receives the periodic reset signal, and the output end of the second NOT gate is connected to the first input end of the second NAND gate; The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the output terminal of the first NAND gate is connected to the third input terminal of the first AND gate; the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate.

5. The refresh control circuit according to claim 2, wherein: The pulse generating circuit includes: a third NOT gate, a delay unit and a second AND gate; The first input terminal of the second AND gate is connected to the output terminal of the detection circuit, and the second input terminal of the second AND gate is connected to the output terminal of the delay unit; The input end of the third NOT gate is connected to the output end of the detection circuit, the output end of the third NOT gate is connected to the input end of the delay unit, and the delay time of the delay unit is used to control the pulse width of the counting clock; The output terminal of the second AND gate is connected to the clock terminal of the counter as the output terminal of the pulse generating circuit.

6. The refresh control circuit according to claim 2, wherein: The counter includes: a multi-stage first trigger; The clock end of the first trigger of the first stage is connected to the output end of the pulse generating circuit, and the clock ends of other first triggers are connected to the inverting output end of the first trigger of the previous stage; the input end of each first trigger is connected to the inverting output end of the first trigger, and the value output by the inverting output end of the first trigger of each stage constitutes the output of the counter, which is the binary representation of the counting result; the reset end of each first trigger is connected to the output end of the reset circuit.

7. The refresh control circuit according to claim 1, wherein: The reset circuit includes: a reset generation circuit and an output circuit; The reset generation circuit is connected to the output terminal of the refresh counter and receives a period setting signal, and is configured to output an initial reset signal to the output circuit when the count result output by the refresh counter reaches the preset number of times corresponding to the period setting signal; The input end of the output circuit is connected to the output end of the reset generation circuit, and the output circuit is used to output the initial reset signal as the periodic reset signal in response to the end of the pulse of the row activation window signal during the effective level period of the refresh window signal.

8. The refresh control circuit according to claim 7, wherein: The period setting signal includes two bits, and the preset number includes four values, which are respectively recorded as the first number, the second number, the third number and the fourth number.

9. The refresh control circuit according to claim 8, wherein: The reset generation circuit comprises: a period decoding circuit, the period decoding circuit receiving the period setting signal and configured to output a selection signal for the first number of times, a selection signal for the second number of times, a selection signal for the third number of times, and a selection signal for the fourth number of times according to the period setting signal; A sub-decoder corresponding to each number; each sub-decoder receives at least one bit of the counting result, and is configured to output a flag signal of the number when the value currently represented by the at least one received bit is consistent with the number corresponding to the sub-decoder; A third AND gate corresponding to each number; each third AND gate receives a selection signal corresponding to the number and a flag signal corresponding to the number; An OR operation unit, wherein the input end of the OR operation unit is respectively connected to the output ends of all the third AND gates, and the output end of the OR operation unit is used to output the initial reset signal.

10. The refresh control circuit according to claim 9, wherein: The cycle decoding circuit includes: a first NOR gate, wherein a first input terminal of the first NOR gate receives one bit of the period setting signal, a second input terminal of the first NOR gate receives another bit of the period setting signal, and the first NOR gate is configured to output a selection signal for the first number of times; a fourth NOT gate and a second NOR gate, wherein the input end of the fourth NOT gate is connected to the first input end of the first NOR gate, the output end of the fourth NOT gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate is connected to the second input end of the first NOR gate, and the second NOR gate is used to output the second-number selection signal; a fifth NOT gate and a third NOR gate, wherein a first input terminal of the third NOR gate is connected to the first input terminal of the first NOR gate, an input terminal of the fifth NOT gate is connected to the second input terminal of the first NOR gate, an output terminal of the fifth NOT gate is connected to the second input terminal of the third NOR gate, and the third NOR gate is used to output a selection signal for the third number; A third NAND gate and a sixth NAND gate, wherein the first input end of the third NAND gate is connected to the first input end of the first NOR gate, the second input end of the third NAND gate is connected to the second input end of the first NOR gate, the output end of the third NAND gate is connected to the input end of the sixth NAND gate, and the sixth NAND gate is used to output the selection signal of the fourth number of times.

11. The refresh control circuit according to claim 9, wherein: The sub-decoder corresponding to the first number includes a fourth AND gate; the input end of the fourth AND gate receives the third bit and the second bit of the counting result respectively, and the output end of the fourth AND gate is used to output a flag signal of the first number; The sub-decoder corresponding to the second number includes a fifth AND gate; the input ends of the fifth AND gate respectively receive the fourth bit and the third bit of the counting result, and the output end of the fifth AND gate is used to output a flag signal of the second number; The sub-decoder corresponding to the third number includes a sixth AND gate; the input ends of the sixth AND gate receive the 5th bit and the 2nd bit of the counting result respectively, and the output end of the sixth AND gate is used to output a flag signal of the third number; The sub-decoder corresponding to the fourth number includes a seventh AND gate; the input end of the seventh AND gate receives the 5th bit and the 4th bit of the counting result respectively, and the output end of the seventh AND gate is used to output the flag signal of the fourth number.

12. The refresh control circuit according to claim 7, wherein: The output circuit includes: a seventh NOT gate, wherein an input end of the seventh NOT gate receives the row activation window signal; an eighth AND gate, wherein a first input terminal of the eighth AND gate receives the refresh window signal, and a second input terminal of the eighth AND gate is connected to the output terminal of the seventh NOT gate; A second trigger, the input end of the second trigger is connected to the output end of the reset generation circuit, the output end of the second trigger is connected to the reset end of the refresh counter, and the clock end of the second trigger is connected to the output end of the eighth AND gate.

13. The refresh control circuit according to any one of claims 1 to 12, characterized in that: The preset range is 4 to 6.

14. The refresh control circuit according to claim 13, wherein: The control circuit includes: a first multi-input AND gate, a second multi-input AND gate, a third multi-input AND gate and a first multi-input OR gate; The first multi-input AND gate has a plurality of input terminals, and the plurality of input terminals of the first multi-input AND gate respectively receive the inverted signal of the first bit, the inverted signal of the second bit, and the third bit of the counting result; The second multi-input AND gate has a plurality of input terminals, and the plurality of input terminals of the second multi-input AND gate respectively receive the first bit, the inverted signal of the second bit, and the third bit of the counting result; The third multi-input AND gate has a plurality of input terminals, and the plurality of input terminals of the third multi-input AND gate respectively receive the inverted signal of the first bit, the second bit, and the third bit of the counting result; The first input end of the first multi-input OR gate is connected to the output end of the first multi-input AND gate, the second input end of the first multi-input OR gate is connected to the output end of the second multi-input AND gate, the third input end of the first multi-input OR gate is connected to the output end of the third multi-input AND gate, and the output end of the first multi-input OR gate is used to output the protection refresh window signal.

15. A memory, characterized in that: include: An instruction decoder, a refresh operation module, a storage block control module, and a refresh control circuit according to any one of claims 1 to 14; The instruction decoder is used to parse and generate an activation command and a refresh instruction according to an external instruction; the refresh operation module is connected to the instruction decoder and is used to output the refresh window signal and the row activation window signal in response to the refresh instruction; The refresh control circuit is connected to the instruction decoder, the refresh operation module and the storage block control module, and is used to output a protection refresh window signal according to the activation command, the refresh window signal and the row activation window signal; The memory block control module is connected to the refresh control circuit and the refresh operation module, and is configured to execute refresh in response to a signal output by the refresh operation module, and execute row hammer protection refresh in response to the protection refresh window signal.

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