Packaging structure and its preparation method

Abstract

This application provides a packaging structure including a first packaging unit, a second packaging unit, and an external component. The first packaging unit includes a first circuit unit, a first component, and a first packaging layer. The first circuit unit includes a first circuit region and a second circuit region. The first packaging layer covers the second circuit region, and the first component is embedded within the first packaging layer. The second packaging unit includes a second circuit unit, a second packaging layer, a second component, and a pad region. The second circuit unit includes a third circuit region and a fourth circuit region, with the third circuit region soldered to the first circuit region. The second packaging layer covers the fourth circuit region and includes a first surface. The second component is embedded within the second packaging layer. The pad region is electrically connected to the fourth circuit region and exposed on the first surface. The external component is fixed to the surface of the pad region facing away from the fourth circuit region. This packaging structure improves processing efficiency and facilitates the testing of the yield of each packaging unit. This application also provides a method for fabricating the packaging structure.

Description

Technical Field

[0001] This application relates to the field of circuit board packaging, specifically to a packaging structure and its fabrication method. Background Technology

[0002] Existing packaging structures typically involve soldering electronic components onto opposite surfaces of a circuit board, then using a packaging layer for double-sided encapsulation, and finally leading out a circuit layer on one surface and attaching test balls. However, this manufacturing process is relatively inefficient. Furthermore, electrical testing can only be performed after ball attachment, which hinders the monitoring of packaging yield during the packaging process, resulting in a relatively low overall packaging yield. Summary of the Invention

[0003] In view of this, this application provides a packaging structure that is beneficial for improving processing efficiency and facilitating the detection of the yield of each packaging unit.

[0004] This application also provides a method for preparing a packaging structure.

[0005] This application provides a packaging structure including a first packaging unit, a second packaging unit, and an external component. The first packaging unit includes a first circuit unit, a first component, and a first packaging layer. The first circuit unit includes a first circuit region and a second circuit region stacked and electrically connected along a first direction. The first packaging layer covers the second circuit region. The first component is embedded within the first packaging layer and electrically connected to the second circuit region. The second packaging unit includes a second circuit unit, a second packaging layer, a second component, and a pad region. The second circuit unit includes a third circuit region and a fourth circuit region stacked and electrically connected along the first direction. The third circuit region is soldered to the first circuit region. The second packaging layer covers the fourth circuit region and includes a first surface facing away from the fourth circuit region. The second component is embedded within the second packaging layer and electrically connected to the fourth circuit region. The pad region is electrically connected to the fourth circuit region and exposed on the first surface. The external component is fixed to the surface of the pad region facing away from the fourth circuit region.

[0006] This application also provides a method for fabricating a packaging structure, comprising the following steps: providing a first packaging unit, the first packaging unit including a first circuit unit, a first element, and a first packaging layer, the first circuit unit including a first circuit region and a second circuit region stacked and electrically connected along a first direction, the first packaging layer covering the second circuit region, the first element embedded in the first packaging layer and electrically connected to the second circuit region; providing a second packaging unit, the second packaging unit including a second circuit unit, a second packaging layer, a second element, and a pad area, the second circuit unit including a third circuit region and a fourth circuit region stacked and electrically connected along the first direction, the second packaging layer covering the fourth circuit region and including a first surface facing away from the fourth circuit region, the second element embedded in the second packaging layer and electrically connected to the fourth circuit region, the pad area electrically connected to the fourth circuit region and exposed on the first surface; stacking the first packaging unit and the second packaging unit along the first direction, and soldering the third circuit region to the first circuit region; forming an external component on the surface of the pad area facing away from the fourth circuit region, thereby obtaining the packaging structure.

[0007] In this application, the packaging structure includes a first packaging unit and a second packaging unit that are welded together. Before welding, the first packaging unit and the second packaging unit can be processed and electrically tested separately, which helps to improve the processing efficiency of the packaging structure and facilitates the detection of the yield of each packaging unit. Attached Figure Description

[0008] Figure 1 A cross-sectional view of a second substrate connected to a first element and a third element according to an embodiment of this application;

[0009] Figure 2 In order to be in Figure 1 The cross-sectional view shown is a second substrate after the first encapsulation layer has been formed.

[0010] Figure 3 To remove Figure 2 The diagram shown is a cross-sectional view of the portion behind the first encapsulation layer.

[0011] Figure 4 For separation Figure 3 A cross-sectional view of a single first packaging unit obtained after the first packaging layer and the second substrate shown.

[0012] Figure 5 This is a cross-sectional view of a first substrate connected to a second element according to an embodiment of this application;

[0013] Figure 6 In order to be in Figure 5 A cross-sectional view of the first substrate after the first package portion has been formed thereon;

[0014] Figure 7 To remove Figure 6 The diagram shows a cross-sectional view of the first package portion.

[0015] Figure 8 In order to be in Figure 7 The diagram shows a cross-sectional view of the first encapsulation portion after the first encapsulation area has been formed.

[0016] Figure 9 To form a through Figure 8 A cross-sectional view of the first through-hole of the first package portion and the first package area shown;

[0017] Figure 10 To form a through Figure 9 A cross-sectional view of the first package portion and the first patterned hole behind the first package area;

[0018] Figure 11 In order to be in Figure 10 The cross-sectional view shown is of the fifth circuit area formed inside the first graphic hole.

[0019] Figure 12 To form coverage Figure 11 A cross-sectional view of the second encapsulation area of ​​the fifth circuit region shown;

[0020] Figure 13 To form a through Figure 12 A cross-sectional view of the second patterned hole in the second encapsulation area shown;

[0021] Figure 14 In order to be in Figure 13 A cross-sectional view of multiple connected second package units is obtained after forming a pad area within the second patterned hole shown.

[0022] Figure 15 In order to be in Figure 14 The cross-sectional view shown is a second packaging unit after the first packaging unit has been formed on it.

[0023] Figure 16 In order to be in Figure 15 The diagram shows a cross-sectional view after a filler layer is formed between the first and second packaging units.

[0024] Figure 17 In order to be in Figure 16 The diagram shows a cross-sectional view of the second packaging unit after the external components have been formed.

[0025] Figure 18 This is a cross-sectional view of the packaging structure obtained in one embodiment of this application.

[0026] Explanation of main component symbols

[0027] Packaging structure 100 First packaging unit 10

[0028] First Line Unit 11, First Line Area 111

[0029] Second line zone 112 First dielectric layer 113

[0030] First weld resist layer 114 Second weld resist layer 115

[0031] First component 12 First encapsulation layer 13

[0032] Third element 14 Third surface 131

[0033] Second packaging unit 20 Second circuit unit 21

[0034] Third Line Section 211 Fourth Line Section 212

[0035] Second dielectric layer 213 Third solder resist layer 214

[0036] Fourth solder resist layer 215 Second encapsulation layer 22

[0037] First packaging section 221 Second packaging section 222

[0038] First packaging area 223 Second packaging area 224

[0039] Second surface 230 First surface 226

[0040] Second component 23, pad area 24

[0041] External component 30, Fifth line zone 26

[0042] Fill layer 40 Second pattern hole 201

[0043] Second through hole 202 First pattern hole 203

[0044] Second substrate 101 First substrate 204

[0045] First through hole 205, first direction X

[0046] Second direction Y

[0047] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0048] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0049] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. When a component is said to be "set on" another component, it can be directly set on the other component or there may be an intervening component.

[0050] Furthermore, the descriptions involving "first," "second," etc., in the embodiments of the present invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated.

[0051] Example 1:

[0052] This application provides a method for fabricating a packaging structure. Depending on different requirements, the order of steps in the fabrication method can be changed, and some steps can be omitted or combined. The fabrication method includes the following steps:

[0053] Step 1: Refer to Figure 1 A second substrate 101 is provided. The extending direction of the second substrate 101 is defined as the second direction Y. The second substrate 101 includes a plurality of first line units 11 arranged and interconnected along the second direction Y. Each first line unit 11 includes a first line region 111 and a second line region 112 stacked and electrically connected along a first direction X. The first direction X is perpendicular to the second direction Y. The material of the first line region 111 and the second line region 112 can both be copper. In this embodiment, the second substrate 101 includes two first line units 11 arranged along the second direction Y. In some embodiments, the first line unit 11 further includes a first dielectric layer 113, a first solder resist layer 114, and a second solder resist layer 115. The first dielectric layer 113 is disposed in the first direction X between the first line region 111 and the second line region 112. The first solder resist layer 114 and the first line region 111 together cover one surface of the first dielectric layer 113. The second solder resist layer 115 and the second line region 112 together cover the other opposite surface of the first dielectric layer 113. For example, the material of the first dielectric layer 113 can be one of a liquid crystal polymer, polyethylene terephthalate, or polyimide. For example, the first solder resist layer 114 and the second solder resist layer 115 can be formed by spraying solder resist ink.

[0054] Then, a first element 12 is mounted on the second line area 112 of each first line unit 11. The first element 12 is electrically connected to the second line area 112. Exemplarily, the first element 12 can be an active element, such as a chip. The first element 12 can be soldered to the second line area 112 using conductive paste, such as solder paste.

[0055] In some embodiments, a third element 14 is also mounted on each of the second line areas 112. Exemplarily, the third element 14 may be a passive component, such as a resistor or inductor. The third element 14 can also be soldered to the second line area 112 using conductive paste, such as solder paste or copper paste.

[0056] Step Two: Refer to Figure 2 A first encapsulation layer 13 is formed on each first circuit unit 11 to cover the first element 12, such that the first element 12 is embedded within the first encapsulation layer 13. The first encapsulation layer 13 includes a third surface 131 facing away from the second circuit region 112, and the third surface 131 is higher than the upper surface of the first element 12 in a first direction X. For example, the material of the first encapsulation layer 13 may be epoxy resin or silicone resin.

[0057] In some embodiments, the first encapsulation layer 13 further covers the third element 14, and the third surface 131 is higher than the upper surface of the third element 14 in the first direction X. In some embodiments, the upper surface of the first element 12 is higher than the upper surface of the third element 14 in the first direction X.

[0058] Step 3: Refer to Figure 2 and Figure 3 A portion of the thickness of the first encapsulation layer 13 is removed along the first direction X, exposing the first element 12 on the third surface 131, resulting in a plurality of interconnected first encapsulation units 10. In some embodiments, the third element 14 is spaced apart from the third surface 131 in the first direction X.

[0059] The first packaging unit 10 includes a first element 12, a first circuit unit 11, a first packaging layer 13, and a third element 14. For example, a portion of the first packaging layer 13 can be removed by grinding. The first element 12 is embedded in the first packaging layer 13 while being exposed on the third surface 131, which facilitates heat dissipation of the first element 12.

[0060] In another embodiment, step three can be omitted, such that the first element 12 is spaced apart from the third surface 131 in the first direction X.

[0061] Step Four: Refer to Figure 3 and Figure 4 Multiple interconnected first packaging units 10 are separated. For example, multiple interconnected first packaging units 10 can be separated by dicing to obtain multiple independent first packaging units 10. The method of forming multiple first packaging units 10 from a whole board and then cutting them to obtain independent first packaging units 10 is beneficial to improving the production efficiency of the first packaging units 10.

[0062] In another embodiment, the second substrate 101 may include only one first line unit 11, in which case step four can be omitted.

[0063] In another embodiment, a first packaging unit 10 may be provided directly. The first packaging unit 10 includes a first circuit unit 11, a first element 12, and a first packaging layer 13. The first circuit unit 11 includes a first circuit region 111 and a second circuit region 112 stacked and electrically connected along a first direction X. The first packaging layer 13 covers the second circuit region 112. The first element 12 is embedded in the first packaging layer 13 and electrically connected to the second circuit region 112.

[0064] Step 5: Refer to Figure 5 A first substrate 204 is provided. The first substrate 204 includes a plurality of second line units 21 arranged along a second direction Y. The second line units 21 include a third line region 211 and a fourth line region 212 stacked and electrically connected along a first direction X. In this embodiment, the first substrate 204 includes two second line units 21 arranged along the second direction Y.

[0065] In some embodiments, the second circuit unit 21 further includes a second dielectric layer 213, a third solder resist layer 214, and a fourth solder resist layer 215. The second dielectric layer 213 is disposed in a first direction X between the third circuit region 211 and the fourth circuit region 212. The third circuit region 211 and the third solder resist layer 214 together cover one surface of the second dielectric layer 213. The fourth circuit region 212 and the fourth solder resist layer 215 together cover the other opposite surface of the second dielectric layer 213.

[0066] For example, the material of the second dielectric layer 213 can be a liquid crystal polymer, polyethylene terephthalate, or polyimide. The materials of the third circuit region 211 and the fourth circuit region 212 can both be copper. The third solder resist layer 214 and the fourth solder resist layer 215 can be formed by spraying solder resist ink.

[0067] Then, a second element 23 is mounted on the fourth line area 212 of each second line unit 21. For example, the second element 23 can be an active element, such as a chip. The second element 23 can be soldered to the fourth line area 212 using conductive paste, such as solder paste or copper paste, so that the second element 23 is electrically connected to the fourth line area 212.

[0068] For example, both the first substrate 204 and the second substrate 101 can be obtained by performing operations such as opening holes, electroplating, exposure and development, etching, and forming a solder resist layer on a double-sided copper-clad substrate.

[0069] Step Six: Refer to Figure 6A first encapsulation portion 221 is formed on each second circuit unit 21 to cover the second element 23, such that the second element 23 is embedded within the first encapsulation portion 221. For example, the material of the first encapsulation portion 221 may be epoxy resin or silicone resin. The first encapsulation portion 221 includes a second surface 230 facing away from the fourth circuit region 212, and the second surface 230 is higher than the upper surface of the second element 23 in the first direction X.

[0070] Step Seven: Refer to Figure 6 and Figure 7 A portion of the thickness of the first encapsulation portion 221 is removed along the first direction X, exposing the second element 23 on the second surface 230. The second element 23 is embedded in the first encapsulation portion 221 while being exposed on the second surface 230, which facilitates heat dissipation of the second element 23. For example, the portion of the thickness of the first encapsulation portion 221 can be removed by grinding.

[0071] Step 8: Refer to Figure 8 A first encapsulation region 223 is formed on the second surface 230. Exemplarily, the material of the first encapsulation region 223 may be polyimide or polyethylene terephthalate. The first encapsulation region 223 also covers the second element 23.

[0072] Step Nine: Refer to Figure 9 A plurality of first through holes 205 are formed along the first direction X, penetrating the first packaging area 223 and the first packaging part 221. Each first through hole 205 is spaced apart from the second element 23 in the second direction Y. For example, the first through holes 205 can be formed by laser drilling.

[0073] Step 10: Refer to Figure 9 and Figure 10 A second through-hole 202 is formed along the first direction X, penetrating the first packaging region 223 and connecting each of the first through-holes 205. Each second through-hole is spaced apart from the second element 23 in the second direction Y. The second through-hole 202 is disposed around the outer periphery of a portion of the first through-holes 205 located within the first packaging region 223, such that the first through-holes 205 and the second through-hole 202 together form a second patterned hole 201. A second surface 230 is exposed in the portion of the second patterned hole 201 located within the first packaging region 223. For example, the second through-hole 202 can be formed by laser drilling.

[0074] In another embodiment, a through hole penetrating the first encapsulation region 223 along the first direction X can be formed first, and then a through hole penetrating the first encapsulation portion 221 along the first direction X can be formed to obtain the second patterned hole 201.

[0075] Step Eleven: Refer to Figure 11A fifth line region 26, electrically connected to the fourth line region 212, is formed within the second patterned hole 201. The fifth line region 26 is located within a portion of the second patterned hole 201 within the first package region 223 and is spaced apart from the second element 23 in the second direction Y. Exemplarily, the fifth line region 26 can be formed by electroplating or chemical plating. The material of the fifth line region 26 can be copper. This application uses a method of opening holes in the first package region 223 and the first package portion 221 and forming the fifth line region 26 within the second patterned hole 201, eliminating the need for additional exposure, development, and etching steps, thus simplifying the formation process of the fifth line region 26.

[0076] Step Twelve: Refer to Figure 12 A second encapsulation region 224 is formed on the first encapsulation region 223, covering the fifth circuit region 26. The second encapsulation region 224 covers the fifth circuit region 26 and the second element 23. The second encapsulation region 224 and the first encapsulation region 223 together form a second encapsulation portion 222. The second encapsulation portion 222 and the first encapsulation portion 221 together form a second encapsulation layer 22. The second encapsulation layer 22 includes a first surface 226 facing away from the fourth circuit region 212. At this time, the second encapsulation region 224 includes the first surface 226. The second element 23 is embedded in the second encapsulation layer 22 and spaced apart from the first surface 226 in the first direction X. For example, the material of the second encapsulation region 224 can be polyimide or polyethylene terephthalate.

[0077] In another embodiment, a through-hole penetrating the first package portion 221 can be formed first, and then a plating layer can be formed inside the through-hole and on the second surface 230. The fifth circuit region 26 can then be obtained through exposure, development, and etching. Finally, the second package layer 22 is laminated onto the fifth circuit region 26.

[0078] Step Thirteen: Refer to Figure 13 A first patterned hole 203 is formed within the second packaging region 224, penetrating the first surface 226. The first patterned hole 203 is stacked on the same side of the second component 23 and the fifth circuit region 26. Exemplarily, the first patterned hole 203 can be formed by laser drilling. In some embodiments, the fifth circuit region 26 can form the bottom wall of a portion of the holes in the first patterned hole 203. The remaining holes in the first patterned hole 203 can be spaced apart from the fifth circuit region 26 in the first direction X, thereby facilitating flexible adjustment of the distribution of the first patterned holes 203 and enabling subsequent increases in the number of solder pads.

[0079] In another embodiment, the fifth line area 26 may form the bottom wall of all the holes in the first patterned hole 203.

[0080] In another embodiment, a second encapsulation layer 22 covering the second element 23 can be formed directly on each second circuit unit 21. A first patterned hole 203 penetrating the first surface 226 is formed within the second encapsulation layer 22.

[0081] Step Fourteen: Refer to Figure 14 A pad area 24 electrically connected to the fifth circuit area 26 is formed within the first pattern hole 203, resulting in multiple interconnected second package units 20. At this time, the pad area 24 is stacked on the same side of the second component 23 and the fifth circuit area 26 and electrically connected to the fourth circuit area 212 through the fifth circuit area 26. The pad area 24 is exposed on the first surface 226. The second component 23 is located between the fourth circuit area 212 and the pad area 24. Introducing the fifth circuit area 26 and then rearranging the pad area 24 helps to increase the number of pads in the pad area 24. Furthermore, forming the pad area 24 within the first pattern hole 203 helps to improve the connection stability of the pad area 24 and simplify the formation process of the pad area 24.

[0082] In another embodiment, the second element 23 may be exposed on the first surface 226, thereby improving the heat dissipation of the second element 23 within the precursor 207.

[0083] In another embodiment, the first patterned hole 203 may not be formed, and the pad area 24 may be formed directly on the first surface 226 by selective printing.

[0084] In another embodiment, a second packaging unit 20 may be provided directly. The second packaging unit 20 includes a second circuit unit 21, a second packaging layer 22, a second element 23, and a pad area 24. The second circuit unit 21 includes a third circuit area 211 and a fourth circuit area 212 stacked and electrically connected along a first direction X. The second packaging layer 22 covers the fourth circuit area 212 and includes a first surface 226 facing away from the fourth circuit area 212. The pad area 24 is electrically connected to the fourth circuit area 212 and exposed on the first surface 226. The second element 23 is embedded within the second packaging layer 22 and electrically connected to the fourth circuit area 212.

[0085] Step 15: Refer to Figure 15 The first packaging unit 10 and the second packaging unit 20 are stacked along the first direction X, and the third circuit region 211 is soldered to the first circuit region 111. For example, the third circuit region 211 and the first circuit region 111 can be soldered using conductive paste, such as solder paste or copper paste.

[0086] In this embodiment, the first packaging units 10 connected to different second packaging units 20 are arranged at intervals in the second direction Y.

[0087] Step Sixteen: Refer to Figure 16A filler layer 40 is formed between the first circuit unit 11 of the first encapsulation unit 10 and the second circuit unit 21 of the second encapsulation unit 20. For example, the filler layer 40 may be epoxy resin. The filler layer 40 helps to improve the connection stability between the first encapsulation unit 10 and the second encapsulation unit 20.

[0088] In this embodiment, the filling layers 40 connected to different second packaging units 20 are arranged at intervals in the second direction Y.

[0089] In another embodiment, step sixteen can be omitted.

[0090] Step Seventeen: Refer to Figure 16 and Figure 17 An external component 30 is formed on the surface of the pad area 24 opposite to the fourth circuit area 212. Exemplarily, the external component 30 can be a solder ball. The external component 30 can also be a lead. This application does not impose specific limitations on the shape and material of the external component 30.

[0091] Step 18: Refer to Figure 17 and Figure 18 At least a plurality of interconnected second packaging units 20 are separated to obtain a packaging structure 100. The packaging structure 100 includes only one first packaging unit 10 and one second packaging unit 20. For example, at least a plurality of interconnected second packaging units 20 can be separated by dicing or laser cutting.

[0092] When the filler layers 40 connected to different second packaging units 20 are interconnected, and the first packaging units 10 connected to different second packaging units 20 are interconnected, it is also necessary to cut and separate multiple first packaging units 10 and multiple filler layers 40.

[0093] In another embodiment, step eighteen can be omitted. In this case, the packaging structure 100 may include a plurality of second packaging units 20 and a plurality of first packaging units 10.

[0094] In another embodiment, the first substrate 204 may include only one second circuit unit 21. In this case, step eighteen can also be omitted, so that the packaging structure 100 includes a second packaging unit 20 and a first packaging unit 10.

[0095] Example 2:

[0096] Reference Figure 18This application provides an embodiment of a packaging structure 100. The packaging structure 100 includes a first packaging unit 10, a second packaging unit 20, and an external component 30. The packaging structure 100 may include one or more first packaging units 10. The packaging structure 100 may also include one or more second packaging units 20. In this embodiment, the packaging structure 100 includes one first packaging unit 10 and one second packaging unit 20.

[0097] The first packaging unit 10 includes a first circuit unit 11, a first element 12, and a first packaging layer 13. The first circuit unit 11 includes a first circuit region 111 and a second circuit region 112 that are stacked and electrically connected along a first direction. The first packaging layer 13 covers the second circuit region 112. The first element 12 is embedded in the first packaging layer 13 and electrically connected to the second circuit region 112.

[0098] The second packaging unit 20 includes a second circuit unit 21, a second packaging layer 22, a second component 23, and a pad area 24. The second circuit unit 21 includes a third circuit area 211 and a fourth circuit area 212 stacked and electrically connected along a first direction. The third circuit area 211 is soldered to the first circuit area 111. The second packaging layer 22 covers the fourth circuit area 212 and includes a first surface 226 facing away from the fourth circuit area 212. The pad area 24 is electrically connected to the fourth circuit area 212 and exposed on the first surface 226. The second component 23 is embedded within the second packaging layer 22 and electrically connected to the fourth circuit area 212. An external component 30 is fixed to the surface of the pad area 24 facing away from the fourth circuit area 212.

[0099] In this application, the packaging structure 100 includes a first packaging unit 10 and a second packaging unit 20 that are soldered together. Before soldering, the first packaging unit 10 and the second packaging unit 20 can be processed and electrically tested separately, which helps to improve the processing efficiency of the packaging structure 100 and facilitates the detection of the yield of each unit.

[0100] In some embodiments, the first encapsulation layer 13 includes a third surface 131 facing away from the second circuit region 112. The first element 12 is exposed on the third surface 131, such that the surface of the first element 12 facing away from the second circuit region 112 is not covered by the first encapsulation layer 13, thereby facilitating heat dissipation of the first element 12.

[0101] In another embodiment, the first element 12 may be spaced apart from the third surface 131 in the first direction X, such that the first element 12 is completely encapsulated within the first encapsulation layer 13.

[0102] In some embodiments, the first packaging unit 10 may further include a third element 14. The third element 14 is embedded in the first packaging layer 13 and may be spaced apart from the third surface 131 in the first direction X.

[0103] In some embodiments, the first circuit unit 11 further includes a first dielectric layer 113, a first solder resist layer 114, and a second solder resist layer 115. The first solder resist layer 114 and the first circuit region 111 together cover one surface of the first dielectric layer 113. The second solder resist layer 115 and the second circuit region 112 together cover the other surface of the first dielectric layer 113 opposite to it. Providing solder resist layers can prevent short circuits from occurring in the circuit regions on the same surface.

[0104] In some embodiments, the second circuit unit 21 further includes a second dielectric layer 213, a third solder resist layer 214, and a fourth solder resist layer 215. The third circuit region 211 and the third solder resist layer 214 together cover one surface of the second dielectric layer 213. The fourth circuit region 212 and the fourth solder resist layer 215 together cover the opposite surface of the second dielectric layer 213. Providing solder resist layers can prevent short circuits from occurring in the circuit regions on the same surface.

[0105] In some embodiments, the second packaging unit 20 further includes a fifth packaging region 26 electrically connected between the fourth packaging region 212 and the pad region 24. The second packaging layer 22 includes a first packaging portion 221 and a second packaging portion 222 stacked along a first direction X. The first packaging portion 221 covers the fourth packaging region 212 and includes a second surface 230 facing the second packaging portion 222. The fifth packaging region 26 is disposed on the second surface 230 and is spaced apart from the second element 23 in a second direction Y perpendicular to the first direction X. The pad region 24 is stacked on the same side of the second element 23 and the fifth packaging region 26, such that the second element 23 is located between the pad region 24 and the fourth packaging region 212, thereby facilitating an increase in the number of pads in the pad region 24.

[0106] In some embodiments, the second element 23 is exposed on the second surface 230, which facilitates heat dissipation of the second packaging unit 20 during the manufacturing process.

[0107] In another embodiment, the second element 23 may be spaced apart from the second surface 230 in the first direction X, such that the second element 23 is completely enclosed inside the first package portion 221.

[0108] In some embodiments, the second encapsulation portion 222 includes a first encapsulation region 223 and a second encapsulation region 224 stacked together. The first encapsulation region 223 is disposed on the second surface 230 and connected between the second encapsulation region 224 and the first encapsulation portion 221. The second encapsulation region 224 includes a first surface 226. The second encapsulation layer 22 is provided with a second patterned hole 201 penetrating the first encapsulation portion 221 and the first encapsulation region 223 outside the region of the second element 23. The second surface 230 is exposed in a portion of the second patterned hole 201 located within the first encapsulation region 223. The fifth circuit region 26 is located within a portion of the second patterned hole 201 within the first encapsulation region 223. This allows the fifth circuit region 26 to be fabricated without additional exposure, development, and etching steps, simplifying the molding process of the fifth circuit region 26.

[0109] In some embodiments, the second encapsulation layer 22 is provided with a first patterned hole 203 penetrating the first surface 226 and located within the second encapsulation region 224. The pad region 24 is fixed within the first patterned hole 203. Forming the pad region 24 within the first patterned hole 203 simplifies the formation process of the pad region 24 and improves the connection stability of the pad region 24.

[0110] In some embodiments, the encapsulation structure 100 further includes a filler layer 40. The filler layer 40 is disposed between the first line unit 11 and the second line unit 21.

[0111] The materials of the components in Example 2 are the same as those of the corresponding components in Example 1, so they will not be described again.

[0112] The above description is merely an optimized implementation of this application, and its application should not be limited to this specific implementation. Other modifications and alterations made by those skilled in the art based on the technical concept of this application should fall within the protection scope of this application.

Claims

1. A packaging structure, characterized in that, include: The first packaging unit includes a first circuit unit, a first element, and a first packaging layer. The first circuit unit includes a first circuit area and a second circuit area stacked and electrically connected along a first direction. The first packaging layer covers the second circuit area. The first element is embedded in the first packaging layer and electrically connected to the second circuit area. The second packaging unit includes a second circuit unit, a second packaging layer, a second component, and a pad area. The second circuit unit includes a third circuit area and a fourth circuit area stacked and electrically connected along the first direction. The third circuit area is soldered to the first circuit area. The second packaging layer covers the fourth circuit area and includes a first surface facing away from the fourth circuit area. The second component is embedded in the second packaging layer and electrically connected to the fourth circuit area. The pad area is electrically connected to the fourth circuit area and exposed on the first surface. as well as An external component is fixed to the surface of the pad area opposite to the fourth circuit area; The second packaging unit further includes a fifth packaging area electrically connected between the fourth packaging area and the pad area. The second packaging layer includes a first packaging portion and a second packaging portion stacked along the first direction. The first packaging portion covers the fourth packaging area and includes a second surface facing the second packaging portion. The fifth packaging area is disposed on the second surface and is spaced apart from the second element in a second direction perpendicular to the first direction. The pad area is stacked on the same side of the second element and the fifth packaging area. The second element is exposed on the second surface; The second element is located on the fourth line area.

2. The packaging structure as described in claim 1, characterized in that, The first encapsulation layer includes a third surface facing away from the second circuit area, and the first element is exposed on the third surface.

3. The packaging structure as described in claim 1 or 2, characterized in that, The encapsulation structure further includes a filler layer disposed between the first circuit unit and the second circuit unit.

4. A method for preparing a packaging structure, characterized in that, Includes the following steps: A first packaging unit is provided, the first packaging unit includes a first circuit unit, a first element and a first packaging layer, the first circuit unit includes a first circuit area and a second circuit area stacked and electrically connected along a first direction, the first packaging layer covers the second circuit area, and the first element is embedded in the first packaging layer and electrically connected to the second circuit area; A second packaging unit is provided, the second packaging unit including a second circuit unit, a second packaging layer, a second component and a pad area, the second circuit unit including a third circuit area and a fourth circuit area stacked and electrically connected along the first direction, the second packaging layer covering the fourth circuit area and including a first surface facing away from the fourth circuit area, the second component being embedded in the second packaging layer and electrically connected to the fourth circuit area, and the pad area being electrically connected to the fourth circuit area and exposed on the first surface; The first packaging unit and the second packaging unit are stacked along the first direction, and the third circuit area is soldered to the first circuit area; An external component is formed on the surface of the pad area opposite to the fourth circuit area, thereby obtaining the package structure; The method for preparing the second packaging unit includes: A first substrate is provided, the first substrate including a plurality of second line units arranged along a second direction perpendicular to the first direction, and the fourth line area of ​​each second line unit is provided with the second element; A second encapsulation layer covering the second element is formed on each of the second line units; and A first patterned hole penetrating the first surface is formed within the second encapsulation layer, and the pad area is formed within the first patterned hole to obtain a plurality of interconnected second encapsulation units; After forming the external component, the preparation method further includes: Separate at least a plurality of interconnected second packaging units such that the packaging structure includes a first packaging unit and a second packaging unit; Forming the second encapsulation layer specifically includes: A first package portion covering the second element is formed on each of the second line units, the first package portion including a second surface facing away from the fourth line area; A first encapsulation region is formed on the second surface; A second patterned hole is formed along the first direction, penetrating the first packaging area and the first packaging part. The second surface is exposed in a portion of the second patterned hole located in the first packaging area. A fifth circuit area electrically connected to the fourth circuit area is formed in the second patterned hole. The fifth circuit area is located in a portion of the second patterned hole in the first packaging area and is spaced apart from the second element in the second direction. A second encapsulation area is formed on the first encapsulation area, covering the fifth circuit area. The second encapsulation area includes the first surface. The second encapsulation area and the first encapsulation area together form a second encapsulation part. The first encapsulation part and the second encapsulation part together form the second encapsulation layer.

5. The preparation method according to claim 4, characterized in that, After forming the first encapsulation portion, the preparation method further includes: Remove a portion of the thickness of the first package portion along the first direction, so that the second element is exposed on the second surface; The first encapsulation area also covers the second element.

6. The preparation method according to claim 4, characterized in that, The fabrication of the first packaging unit includes: A second substrate is provided, the second substrate including a plurality of first line units arranged and interconnected along a second direction perpendicular to the first direction, and the first element is provided on the second line area of ​​each first line unit; A first encapsulation layer covering the first element is formed on each of the first line units, the first encapsulation layer including a third surface facing away from the second line area; A portion of the thickness of the first encapsulation layer is removed along the first direction, exposing the first element on the third surface, resulting in a plurality of interconnected first encapsulation units. Separate multiple interconnected first packaging units.

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