A semiconductor package structure and a forming method thereof

Abstract

The application provides a semiconductor package structure and a forming method thereof. The package structure comprises a semiconductor substrate, the semiconductor substrate comprises a core area, a protection area and a cutting path area, and an interlayer dielectric layer is formed on the surface of the semiconductor substrate; a first passivation layer is located on the surface of the interlayer dielectric layer, and a plurality of first openings exposing the interlayer dielectric layer are formed in the first passivation layer; a first pad, a second pad and a third pad are respectively located in the first openings of the core area, the protection area and the cutting path area and on the surface of the first passivation layer, and the surface of the second pad is higher than the surfaces of the first pad and the third pad; and a substrate is used for packaging the semiconductor substrate, and the first pad and the substrate are connected by a bonding wire. The application provides a semiconductor package structure and a forming method thereof, which can avoid short circuit between the bonding wire and a test structure and improve the reliability of a device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a method for forming the same. Background Technology

[0002] As the integration of circuits in terminal devices continues to increase, the demand for smaller chip sizes is growing. To reduce chip height, low-arc, high-bonding wire packaging will be the future trend, especially for advanced 14nm functional products.

[0003] However, low-arc high-bonding leads can easily cause the wire to come into contact with the chip edge, and there are often exposed test structures left on the dicing track. When the lead comes into contact with the test structure during the bonding process, it will inevitably cause a short circuit, thus causing the chip to fail.

[0004] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the Invention

[0005] This application provides a semiconductor packaging structure and a method for forming the same, which can avoid short circuits between bonding wires and test structures and improve device reliability.

[0006] One aspect of this application provides a method for forming a semiconductor package structure, comprising: providing a semiconductor substrate, the semiconductor substrate including a core region, a protection region, and a dicing region, an interlayer dielectric layer formed on the surface of the semiconductor substrate, and a first protection ring and a second protection ring formed in the interlayer dielectric layer of the protection region; forming a first passivation layer on the surface of the interlayer dielectric layer, the first passivation layer including a plurality of first openings of the interlayer dielectric layer respectively exposing the core region, the protection region, and the dicing region; forming a first bonding pad, a second bonding pad, and a third bonding pad that are not connected to each other in the first openings of the core region, the protection region, and the dicing region and on the surface of the first passivation layer, wherein the surface of the second bonding pad is higher than the surface of the first bonding pad and the third bonding pad; forming a second passivation layer on the sidewalls and surface of the second bonding pad; providing a substrate, and encapsulating the semiconductor substrate on the substrate, wherein the first bonding pad and the substrate are connected by bonding wires.

[0007] In some embodiments of this application, the first protection ring and the second protection ring are electrically connected by a connection structure.

[0008] In some embodiments of this application, the first protective ring includes several first metal layers and a first through-hole located between adjacent first metal layers and electrically connected to the adjacent first metal layers; the second protective ring includes several second metal layers and a second through-hole located between adjacent second metal layers and electrically connected to the adjacent second metal layers; wherein each first metal layer and each second metal layer are electrically connected through the connection structure.

[0009] In some embodiments of this application, the extension direction of the connection structure is the same as the extension direction of the bonding wire.

[0010] In some embodiments of this application, the width of the projection of the connection structure in the vertical direction is greater than the width of the projection of the bonding line in the vertical direction.

[0011] In some embodiments of this application, the surface of the second pad is 0.5 micrometers to 2 micrometers higher than the surfaces of the first and third pads.

[0012] In some embodiments of this application, the ratio of the distance between the upper surface of the second passivation layer and the upper surface of the third pad to the distance between the second passivation layer on the sidewall of the second pad and the bond line flush with the upper surface of the third pad is less than 20%.

[0013] In some embodiments of this application, the method for forming the first, second, and third solder pads includes: forming a first metal material layer in the first opening and on the surface of the first passivation layer; etching away the first metal material layer above the surface of the first passivation layer in the core region and the cut-out region; forming a second metal material layer on the surface of the first passivation layer and the surface of the first metal material layer; etching away the second metal material layer located adjacent to the core region, the protection zone, and the cut-out region, wherein the first and second metal material layers located in the core region constitute the first solder pad, the first and second metal material layers located in the protection zone constitute the second solder pad, and the first and second metal material layers located in the cut-out region constitute the third solder pad.

[0014] Another aspect of this application provides a semiconductor package structure, comprising: a semiconductor substrate, the semiconductor substrate including a core region, a protection region, and a dicing region, an interlayer dielectric layer formed on the surface of the semiconductor substrate, and a first protection ring and a second protection ring formed in the interlayer dielectric layer of the protection region; a first passivation layer located on the surface of the interlayer dielectric layer, the first passivation layer including a plurality of first openings of the interlayer dielectric layer respectively exposing the core region, the protection region, and the dicing region; a first bonding pad, a second bonding pad, and a third bonding pad located in the first openings of the core region, the protection region, and the dicing region and on the surface of the first passivation layer, respectively, and not connected thereto, wherein the surface of the second bonding pad is higher than the surface of the first bonding pad and the third bonding pad; a second passivation layer located on the sidewall and surface of the second bonding pad; and a substrate, the semiconductor substrate being packaged on the substrate, the first bonding pad and the substrate being connected by bonding wires.

[0015] In some embodiments of this application, the first protection ring and the second protection ring are electrically connected by a connection structure.

[0016] In some embodiments of this application, the first protective ring includes several first metal layers and a first through-hole located between adjacent first metal layers and electrically connected to the adjacent first metal layers; the second protective ring includes several second metal layers and a second through-hole located between adjacent second metal layers and electrically connected to the adjacent second metal layers; wherein each first metal layer and each second metal layer are electrically connected through the connection structure.

[0017] In some embodiments of this application, the extension direction of the connection structure is the same as the extension direction of the bonding wire.

[0018] In some embodiments of this application, the width of the projection of the connection structure in the vertical direction is greater than the width of the projection of the bonding line in the vertical direction.

[0019] In some embodiments of this application, the surface of the second pad is 0.5 micrometers to 2 micrometers higher than the surfaces of the first and third pads.

[0020] In some embodiments of this application, the ratio of the distance between the upper surface of the second passivation layer and the upper surface of the third pad to the distance between the second passivation layer on the sidewall of the second pad and the bond line flush with the upper surface of the third pad is less than 20%.

[0021] This application provides a semiconductor packaging structure and a method for forming the same. The surface of the second pad is higher than the surfaces of the first and third pads, which can prevent the bonding wire from contacting the third pad and causing a short circuit between the bonding wire and the test structure, thereby improving device reliability. Attached Figure Description

[0022] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0023] in:

[0024] Figure 1 This is a schematic diagram of a semiconductor packaging structure;

[0025] Figures 2 to 10 This is a schematic diagram of each step in the method for forming a semiconductor packaging structure according to an embodiment of this application. Detailed Implementation

[0026] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0027] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0028] Figure 1 This is a schematic diagram of a semiconductor packaging structure.

[0029] refer to Figure 1 As shown, the semiconductor package structure includes: a substrate 100; a semiconductor substrate 200 packaged on the substrate 100, the semiconductor substrate 200 including a core region 201, a protection zone 202, and a dicing zone 203, an interlayer dielectric layer 210 formed on the surface of the semiconductor substrate 200, the interlayer dielectric layer 210 having metal interconnect structures 211, a first protection ring 212, a second protection ring 213, and a test structure 214 respectively located in the core region 201, the protection zone 202, and the dicing zone 203; a first passivation layer 220 located on the surface of the interlayer dielectric layer 210; and metal interconnect structures 211, a first protection ring 212, a second protection ring 213, and a test structure 214 respectively located in the core region 201, the protection zone 202, and the dicing zone 203. The first passivation layer has four unconnected pads: a first pad 221, a second pad 222, a third pad 223, and a fourth pad 224. The first pad 221 penetrates the first passivation layer 220 and is electrically connected to the metal interconnect structure 211. The second pad 222 penetrates the first passivation layer 220 and is electrically connected to the first guard ring 212. The third pad 223 penetrates the first passivation layer 220 and is electrically connected to the second guard ring 223. The fourth pad 224 penetrates the first passivation layer 220 and is electrically connected to the test structure 214. The second passivation layer 240 is located on the sidewalls and surface of the second pad 222 and the third pad 223.

[0030] Continue to refer to Figure 1 As shown, the first solder pad 221 is connected to the substrate 100 via solder balls 230 and bonding wires 250 formed on the surface of the first solder pad 221.

[0031] However, in Figure 1The structure shown still has the following drawbacks. First, because the advanced process uses a low-arc, high-bonding wire structure, the bonding wire 250 is prone to contact with the fourth pad 224 located at the chip edge, causing a short circuit between the bonding wire 250 and the test structure 214. Second, although the dual protection ring structure improves protection capability, the dual protection rings are separate. As the overall chip size decreases, the manufacturing process becomes much more difficult, and the contact interface area ratio between the metal material and the dielectric material increases, leading to unstable stress and overall structural instability, making it prone to cracking.

[0032] To address the aforementioned issues, this application provides a semiconductor packaging structure and its formation method. On one hand, the surface of the second bonding pad is higher than the surfaces of the first and third bonding pads, which can prevent the bonding wire from contacting the third bonding pad and causing a short circuit between the bonding wire and the test structure. On the other hand, the dual protection ring structure is combined to improve its stability, thereby improving the reliability of the device.

[0033] Figures 2 to 10 This is a schematic diagram of each step in the method for forming a semiconductor package structure according to an embodiment of this application. The method for forming a semiconductor package structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0034] refer to Figure 2 As shown, a semiconductor substrate 300 is provided, the semiconductor substrate 300 includes a core region 301, a protection region 302 and a dicing region 303, an interlayer dielectric layer 310 is formed on the surface of the semiconductor substrate 300, and a first protection ring 312 and a second protection ring 313 are formed in the interlayer dielectric layer 310 of the protection region 302.

[0035] In some embodiments of this application, the material of the semiconductor substrate 300 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations of the above.

[0036] In some embodiments of this application, the core region 301 is a region for forming active devices (e.g., transistors, capacitors, memories, etc.); the protection region 302 is a region for forming a seal ring; and the cut channel region 303 is a region for forming a cut channel.

[0037] In some embodiments of this application, the material of the interlayer dielectric layer 310 includes silicon oxide or silicon nitride, etc. The method for forming the interlayer dielectric layer 310 includes chemical vapor deposition (CVD) or physical vapor deposition (PVD), etc.

[0038] In some embodiments of this application, a metal interconnect structure 311 is further formed in the interlayer dielectric layer 310 of the core region 301. The metal interconnect structure 311 is used, for example, for electrically connecting active devices in the semiconductor substrate 300.

[0039] In some embodiments of this application, a test structure 314 is also formed in the interlayer dielectric layer 310 of the cutting channel region 303.

[0040] In some embodiments of this application, the first protection ring 312 and the second protection ring 313 are electrically connected via a connection structure 320. The first protection ring 312, the second protection ring 313, and the connection structure 320 can be integrally connected and can be formed simultaneously.

[0041] In some embodiments of this application, the first protective ring 312 includes a plurality of first metal layers and a first through-hole located between adjacent first metal layers and electrically connected to the adjacent first metal layers; the second protective ring includes a plurality of second metal layers and a second through-hole located between adjacent second metal layers and electrically connected to the adjacent second metal layers; wherein each first metal layer and each second metal layer are electrically connected through the connection structure 320.

[0042] In some embodiments of this application, the extension direction of the connection structure 320 is the same as the extension direction of the bonding wire. Since the bonding wire is formed in a subsequent process, the positional relationship between the connection structure 320 and the bonding wire will be shown when the bonding wire is formed (see reference). Figure 10 ).

[0043] In some embodiments of this application, the width of the projection of the connection structure 320 in the vertical direction is greater than the width of the projection of the bonding line in the vertical direction.

[0044] In the technical solution of this application, each metal layer from top to bottom in the traditional double-ring protection ring structure (i.e., the first protection ring 312 and the second protection ring 313) is connected together, thus merging into a single-ring protection ring structure. The merging reduces the manufacturing difficulty and decreases the contact area ratio between the metal and dielectric materials, resulting in more stable stress between them. Combined with the robust and stable characteristics of the protection ring stack structure, the merging increases the support force of the protection ring structure, thus better protecting the chip.

[0045] In the technical solution of this application, the connecting structure 320 is located directly below the path of the bond wire, and the extension direction of the connecting structure 320 is consistent with the pulling direction of each bond wire. The size of the connecting structure is slightly larger than the size of the bond wire. By associating the guard ring structure with the bond wire, the guard ring can be modified and changed according to the size, direction, and number of the bond wire, giving full play to its characteristics and providing multiple protective functions.

[0046] refer to Figure 3 As shown, a first passivation layer 330 is formed on the surfaces of the interlayer dielectric layer 310, the metal interconnect structure 311, the first guard ring 312, the second guard ring 213, and the test structure 314. The first passivation layer 330 includes a plurality of first openings 331 in the interlayer dielectric layer 310 that respectively expose the core region 301, the protection zone 302, and the cut channel region 303. Specifically, the plurality of first openings 331 expose the metal interconnect structure 311, the first guard ring 312, the second guard ring 313, and the test structure 314. The first openings 331 may also expose the connection structure 320.

[0047] In some embodiments of this application, the material of the first passivation layer 330 includes silicon oxide or silicon nitride, etc. The method for forming the first passivation layer 330 includes chemical vapor deposition or physical vapor deposition, etc.

[0048] In some embodiments of this application, the method for forming the plurality of first openings 331 includes: forming a patterned photoresist layer on the surface of the first passivation layer 330, the patterned photoresist layer defining the positions of the plurality of first openings; etching the first passivation layer 330 using the patterned photoresist layer as a mask to form the plurality of first openings 331; and removing the patterned photoresist layer.

[0049] refer to Figures 4 to 7 As shown, a first solder pad 341, a second solder pad 342, and a third solder pad 343 that are not connected are formed in the first opening 331 of the core area 301, the protection area 302, and the cutting channel area 303, respectively, and on the surface of the first passivation layer 330. The surface of the second solder pad 342 is higher than the surfaces of the first solder pad 341 and the third solder pad 343.

[0050] In some embodiments of this application, the surface of the second pad 342 is 0.5 micrometers to 2 micrometers higher than the surfaces of the first pad 341 and the third pad 343.

[0051] refer to Figure 4 As shown, a first metal material layer 340a is formed in the first opening 331 and on the surface of the first passivation layer 330.

[0052] refer to Figure 5 As shown, the first metal material layer 340a above the surface of the first passivation layer 330 in the core region 301 and the cutting channel region 303 is etched away. A portion of the first metal material layer 340a located at the edge of the protection zone 302 is also etched away.

[0053] refer to Figure 6As shown, a second metal material layer 340b is formed on the surface of the first passivation layer 330 and the surface of the first metal material layer 340a. The material of the second metal material layer 340b is the same as the material of the first metal material layer 340a.

[0054] refer to Figure 7 As shown, etching removes the second metal material layer 340b located adjacent to the core region 301, the protection zone 302, and the cut channel region 303. The first metal material layer 340a and the second metal material layer 340b located in the core region 301 form the first solder pad 341. The first metal material layer 340a and the second metal material layer 340b located in the protection zone 302 form the second solder pad 342. The first metal material layer 340a and the second metal material layer 340b located in the cut channel region 303 form the third solder pad 343.

[0055] It should be noted that only the thickness of the metal solder pads above the protective ring structure is relative to... Figure 1 The structure is increased. The thicknesses of the first solder pad 341 and the third solder pad 343 are relative to... Figure 1 The structure was not increased.

[0056] In some embodiments of this application, the thickness of the metal pads above the guard ring structure is increased, making the surface of the second pad 342 higher than the surfaces of the first pad 341 and the third pad 343, thereby elevating the bonding wires and preventing short circuits. Furthermore, the vertical compressive stress exerted by the bonding wires is more easily resisted and released by the guard ring structure and the second pad 342, preventing chip damage. And this increase in the thickness of the metal pads is only localized above the guard ring structure, without adding any additional stress burden to the chip.

[0057] refer to Figure 8 As shown, a second passivation layer 350 is formed on the sidewall and surface of the second pad 342.

[0058] In some embodiments of this application, the material of the second passivation layer 350 includes silicon oxide or silicon nitride. Methods for forming the second passivation layer 350 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0059] In some embodiments of this application, the method of forming the second passivation layer 350 includes: forming a second passivation layer on the surfaces of the first pad 341, the second pad 342, the third pad 343 and the first passivation layer 330; and removing the second passivation layer located on the surfaces of the first pad 341 and the third pad 343.

[0060] refer to Figure 9As shown, a substrate 400 is provided, and the semiconductor substrate 300 is packaged on the substrate 400. The first solder pad 341 and the substrate 400 are connected by a bonding wire 370. Specifically, a solder ball 360 is also formed on the surface of the first solder pad 341. The first solder pad 341 is connected to the substrate 400 through the solder ball 360 and the bonding wire 370.

[0061] Because of the increased thickness of the second pad 342, the bonding wire 370 can be raised, thus preventing the bonding wire 370 from contacting the third pad 343 and causing a short circuit between the bonding wire 370 and the test structure 314.

[0062] In some embodiments of this application, the ratio of the distance H between the upper surface of the second passivation layer 350 and the upper surface of the third pad 343 to the distance L between the second passivation layer 350 on the sidewall of the second pad 342 and the bonding line 370 flush with the upper surface of the third pad 343 is less than 20%, for example, less than 15%, less than 10%, less than 5%, less than 1%, etc. Specifically, the ratio of the distance H between the upper surface of the second passivation layer 350 and the upper surface of the third pad 343 to the distance L between the second passivation layer 350 on the sidewall of the second pad 342 and the bonding line 370 flush with the upper surface of the third pad 343 is less than the ratio of the distance H between the upper surface of the second passivation layer 350 and the upper surface of the third pad 343 to the distance M between the second passivation layer 350 on the sidewall of the second pad 342 and the outer sidewall of the third pad 343. That is, H / L is less than H / M. Wherein, H ranges from 0.5 micrometers to 2 micrometers, M ranges from 10 micrometers to 50 micrometers, and H / M ranges from 1% to 20%. The values ​​of H and M are determined by the specific process.

[0063] Figure 10 This is a top view of the semiconductor package structure.

[0064] refer to Figure 10 As shown, the core region 301 is located at the center of the semiconductor substrate, the protection zone 302 surrounds the core region 301, and the dicing zone 303 surrounds the protection zone 302. The substrate 400 is connected to the first bonding pad 341 via the bonding wire 370. The connection structure 320 is located directly below the bonding wire 370, and the extension direction of the connection structure 320 is the same as the direction of the bonding wire 370. The width of the vertical projection of the connection structure 320 is greater than the width of the vertical projection of the bonding wire.

[0065] This application provides a semiconductor packaging structure and a method for forming the same. The surface of the second pad is higher than the surfaces of the first and third pads, which can prevent the bonding wire from contacting the third pad and causing a short circuit between the bonding wire and the test structure, thereby improving device reliability.

[0066] Embodiments of this application also provide a semiconductor packaging structure, see reference. Figure 9 As shown, it includes: a semiconductor substrate 300, the semiconductor substrate 300 including a core region 301, a protection region 302 and a dicing region 303, an interlayer dielectric layer 310 formed on the surface of the semiconductor substrate 300, a first protection ring 312 and a second protection ring 313 formed in the interlayer dielectric layer 310 of the protection region 302; and a first passivation layer 330 located on the surface of the interlayer dielectric layer 310, the first passivation layer 330 including a plurality of first openings in the interlayer dielectric layer 310 that respectively expose the core region 301, the protection region 302 and the dicing region 303; A first solder pad 341, a second solder pad 342, and a third solder pad 343, which are not connected, are located in the first opening of the core region 301, the protection region 302, and the dicing region 303, and on the surface of the first passivation layer 330, respectively, wherein the surface of the second solder pad 342 is higher than the surfaces of the first solder pad 341 and the third solder pad 343; a second passivation layer 350 is located on the sidewall and surface of the second solder pad 342; a substrate 400 is on which the semiconductor substrate 300 is packaged, and the first solder pad 341 and the substrate 400 are connected by a bonding wire 370.

[0067] refer to Figure 9 As shown, in some embodiments of this application, the material of the semiconductor substrate 300 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations of the above.

[0068] In some embodiments of this application, the core region 301 is a region for forming active devices (e.g., transistors, capacitors, memories, etc.); the protection region 302 is a region for forming a seal ring; and the cut channel region 303 is a region for forming a cut channel.

[0069] In some embodiments of this application, the material of the interlayer dielectric layer 310 includes silicon oxide or silicon nitride, etc.

[0070] In some embodiments of this application, a metal interconnect structure 311 is further formed in the interlayer dielectric layer 310 of the core region 301. The metal interconnect structure 311 is used, for example, for electrically connecting active devices in the semiconductor substrate 300.

[0071] In some embodiments of this application, a test structure 314 is also formed in the interlayer dielectric layer 310 of the cutting channel region 303.

[0072] In some embodiments of this application, the first protection ring 312 and the second protection ring 313 are electrically connected via a connection structure 320. The first protection ring 312, the second protection ring 313, and the connection structure 320 can be integrally connected.

[0073] In some embodiments of this application, the first protective ring 312 includes a plurality of first metal layers and a first through-hole located between adjacent first metal layers and electrically connected to the adjacent first metal layers; the second protective ring includes a plurality of second metal layers and a second through-hole located between adjacent second metal layers and electrically connected to the adjacent second metal layers; wherein each first metal layer and each second metal layer are electrically connected through the connection structure 320.

[0074] In some embodiments of this application, the extension direction of the connection structure 320 is the same as the extension direction of the bonding wire.

[0075] In some embodiments of this application, the width of the projection of the connection structure 320 in the vertical direction is greater than the width of the projection of the bonding line in the vertical direction.

[0076] In some embodiments of this application, the ratio of the distance H between the upper surface of the second passivation layer 350 and the upper surface of the third pad 343 to the distance L between the second passivation layer 350 on the sidewall of the second pad 342 and the bonding line 370 flush with the upper surface of the third pad 343 is less than 20%, for example, less than 15%, less than 10%, less than 5%, less than 1%, etc. Specifically, the ratio of the distance H between the upper surface of the second passivation layer 350 and the upper surface of the third pad 343 to the distance L between the second passivation layer 350 on the sidewall of the second pad 342 and the bonding line 370 flush with the upper surface of the third pad 343 is less than the ratio of the distance H between the upper surface of the second passivation layer 350 and the upper surface of the third pad 343 to the distance M between the second passivation layer 350 on the sidewall of the second pad 342 and the outer sidewall of the third pad 343. That is, H / L is less than H / M. Wherein, H ranges from 0.5 micrometers to 2 micrometers, M ranges from 10 micrometers to 50 micrometers, and H / M ranges from 1% to 20%. The values ​​of H and M are determined by the specific process.

[0077] refer to Figure 10 As shown, the core region 301 is located at the center of the semiconductor substrate, the protection zone 302 surrounds the core region 301, and the dicing zone 303 surrounds the protection zone 302. The substrate 400 is connected to the first bonding pad 341 via the bonding wire 370. The connection structure 320 is located directly below the bonding wire 370, and the extension direction of the connection structure 320 is the same as the direction of the bonding wire 370. The width of the vertical projection of the connection structure 320 is greater than the width of the vertical projection of the bonding wire.

[0078] In the technical solution of this application, each metal layer from top to bottom in the traditional double-ring protection ring structure (i.e., the first protection ring 312 and the second protection ring 313) is connected together, thus merging into a single-ring protection ring structure. The merging reduces the manufacturing difficulty and decreases the contact area ratio between the metal and dielectric materials, resulting in more stable stress between them. Combined with the robust and stable characteristics of the protection ring stack structure, the merging increases the support force of the protection ring structure, thus better protecting the chip.

[0079] In the technical solution of this application, the connecting structure 320 is located directly below the path of the bond wire, and the extension direction of the connecting structure 320 is consistent with the pulling direction of each bond wire. The size of the connecting structure is slightly larger than the size of the bond wire. By associating the guard ring structure with the bond wire, the guard ring can be modified and changed according to the size, direction, and number of the bond wire, giving full play to its characteristics and providing multiple protective functions.

[0080] refer to Figure 3 As shown, in some embodiments of this application, the material of the first passivation layer 330 includes silicon oxide or silicon nitride. The plurality of first openings 331 respectively expose the metal interconnect structure 311, the first guard ring 312, the second guard ring 313, and the test structure 314. The first openings 331 may also expose the connection structure 320.

[0081] In some embodiments of this application, the surface of the second pad 342 is 0.5 micrometers to 2 micrometers higher than the surfaces of the first pad 341 and the third pad 343.

[0082] It should be noted that only the thickness of the metal solder pads above the protective ring structure is relative to... Figure 1 The structure is increased. The thicknesses of the first solder pad 341 and the third solder pad 343 are relative to... Figure 1 The structure was not increased.

[0083] In this application's technical solution, the thickness of the metal pads above the guard ring structure is increased, making the surface of the second pad 342 higher than the surfaces of the first pad 341 and the third pad 343. This elevates the bonding wires, preventing short circuits. Furthermore, the vertical compressive stress exerted by the bonding wires is more easily resisted and released by the guard ring structure and the second pad 342, preventing chip damage. Moreover, the increase in the thickness of the metal pads is only a localized increase above the guard ring structure, without adding any additional stress burden to the chip.

[0084] In some embodiments of this application, the material of the second passivation layer 350 includes silicon oxide or silicon nitride.

[0085] In some embodiments of this application, the surface of the first solder pad 341 is further formed with solder balls 360. The first solder pad 341 is connected to the substrate 400 through the solder balls 360 and the bonding wires 370.

[0086] Because of the increased thickness of the second pad 342, the bonding wire 370 can be raised, thus preventing the bonding wire 370 from contacting the third pad 343 and causing a short circuit between the bonding wire 370 and the test structure 314.

[0087] This application provides a semiconductor packaging structure and a method for forming the same. The surface of the second pad is higher than the surfaces of the first and third pads, which can prevent the bonding wire from contacting the third pad and causing a short circuit between the bonding wire and the test structure, thereby improving device reliability.

[0088] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0089] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0090] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0091] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0092] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor package structure, characterized in that, include: A semiconductor substrate is provided, comprising a core region, a protection region, and a dicing region. An interlayer dielectric layer is formed on the surface of the semiconductor substrate. A first protection ring and a second protection ring are formed in the interlayer dielectric layer of the protection region. The first protection ring and the second protection ring are electrically connected by a connection structure. The first protection ring comprises a plurality of first metal layers and a first via located between adjacent first metal layers and electrically connected to the adjacent first metal layers. The second protection ring comprises a plurality of second metal layers and a second via located between adjacent second metal layers and electrically connected to the adjacent second metal layers. Each first metal layer and each second metal layer are electrically connected by the connection structure. A first passivation layer is formed on the surface of the interlayer dielectric layer, the first passivation layer including a plurality of first openings in the interlayer dielectric layer that respectively expose the core region, the protection region and the cut channel region; A first, second, and third non-connected solder pads are formed in the first openings of the core area, the protection area, and the cutting channel area, respectively, and on the surface of the first passivation layer, wherein the surface of the second solder pad is higher than the surfaces of the first and third solder pads. A second passivation layer is formed on the sidewalls and surface of the second pad; A substrate is provided, and the semiconductor substrate is packaged on the substrate, wherein the first bonding pad and the substrate are connected by bonding wires.

2. The method for forming a semiconductor package structure as described in claim 1, characterized in that, The extension direction of the connection structure is the same as the extension direction of the bonding wire.

3. The method for forming a semiconductor package structure as described in claim 1, characterized in that, The width of the vertical projection of the connection structure is greater than the width of the vertical projection of the bonding line.

4. The method for forming a semiconductor package structure as described in claim 1, characterized in that, The surface of the second pad is 0.5 to 2 micrometers higher than the surfaces of the first and third pads.

5. The method for forming a semiconductor package structure as described in claim 1, characterized in that, The ratio of the distance between the upper surface of the second passivation layer and the upper surface of the third pad to the distance between the second passivation layer on the sidewall of the second pad and the bond line flush with the upper surface of the third pad is less than 20%.

6. The method for forming a semiconductor package structure as described in claim 1, characterized in that, The method for forming the first solder pad, the second solder pad, and the third solder pad includes: A first metallic material layer is formed in the first opening and on the surface of the first passivation layer; Etching removes the first metal material layer above the surface of the first passivation layer in the core region and the cut channel region; A second metal material layer is formed on the surface of the first passivation layer and the surface of the first metal material layer; The second metal material layer located adjacent to the core area, the protection area, and the cut channel area is etched away. The first metal material layer and the second metal material layer located in the core area constitute the first solder pad. The first metal material layer and the second metal material layer located in the protection area constitute the second solder pad. The first metal material layer and the second metal material layer located in the cut channel area constitute the third solder pad.

7. A semiconductor packaging structure, characterized in that, include: A semiconductor substrate includes a core region, a protection region, and a dicing region. An interlayer dielectric layer is formed on the surface of the semiconductor substrate. A first protection ring and a second protection ring are formed in the interlayer dielectric layer of the protection region. The first protection ring and the second protection ring are electrically connected by a connection structure. The first protection ring includes several first metal layers and a first via located between adjacent first metal layers and electrically connected to the adjacent first metal layers. The second protection ring includes several second metal layers and a second via located between adjacent second metal layers and electrically connected to the adjacent second metal layers. Each first metal layer and each second metal layer are electrically connected by the connection structure. A first passivation layer is located on the surface of the interlayer dielectric layer, and the first passivation layer includes a plurality of first openings in the interlayer dielectric layer that expose the core region, the protection region and the cut channel region respectively; The first, second, and third solder pads, which are not connected, are located in the first opening in the core area, the protection area, and the cutting channel area, respectively, and on the surface of the first passivation layer, wherein the surface of the second solder pad is higher than the surfaces of the first and third solder pads. The second passivation layer is located on the sidewall and surface of the second pad; A substrate, wherein the semiconductor substrate is packaged on the substrate, and the first bonding pad and the substrate are connected by bonding wires.

8. The semiconductor packaging structure as described in claim 7, characterized in that, The extension direction of the connection structure is the same as the extension direction of the bonding wire.

9. The semiconductor packaging structure as described in claim 7, characterized in that, The width of the vertical projection of the connection structure is greater than the width of the vertical projection of the bonding line.

10. The semiconductor packaging structure as described in claim 7, characterized in that, The surface of the second pad is 0.5 to 2 micrometers higher than the surfaces of the first and third pads.

11. The semiconductor packaging structure as described in claim 7, characterized in that, The ratio of the distance between the upper surface of the second passivation layer and the upper surface of the third pad to the distance between the second passivation layer on the sidewall of the second pad and the bond line flush with the upper surface of the third pad is less than 20%.

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