Semiconductor device, manufacturing method, power module, conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. The semiconductor device includes: a substrate, including a first region extending along a first direction and a second region located on opposite sides of the first region; a semiconductor epitaxial layer, the semiconductor epitaxial layer located in the second region includes a drift region, a body region and a first doping type contact region that are sequentially away from the substrate; the semiconductor epitaxial layer located in the first region includes a drift region and a second doping type contact region that are sequentially away from the substrate; a gate trench, located on a surface of the semiconductor epitaxial layer away from the substrate and extending along a second direction, with a trench gate structure located in the trench; a shielding layer, located at the bottom of the trench gate structure; a connecting column, located on at least one side of the trench gate structure and used to connect the shielding layer and the second doping type contact region; a first electrode, in contact with the first and second doping type contact regions; the technical solution provided by the present invention reduces the on-resistance and volume of the device and improves the breakdown voltage of the device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle. Background Art

[0002] SiC MOSFET has undergone a process from planar type to trench type. By improving the gate structure, the direction of current flow on the gate has changed from planar to vertical. Compared with planar semiconductor devices, trench semiconductor devices have the advantages of small cell size and high current density.

[0003] Figure 1 This is a schematic diagram of the structure of a trench-type semiconductor device provided in the related art, referring to Figure 1 The current trench-type semiconductor device includes a substrate 1 and a semiconductor epitaxial layer 2 made of SiC located on one side of the substrate, wherein the semiconductor epitaxial layer 2 includes an N-drift region, a P-body region (P-body) and a contact region that are sequentially away from the substrate 1; wherein the P+ contact region is implanted in the gap between the N+ contact regions, and the N+ contact region and the P+ contact region are simultaneously connected to the source; however, due to the adjacent layout of the N+ contact region, the P+ contact region, and the N+ contact region, the gate G spacing is large, resulting in the problem that the size of the unit cell is still too large, and the area utilization efficiency is low, resulting in high cost and on-resistance of the semiconductor device; in addition, in the trench-type semiconductor device, the high electric field at the bottom and corner of the gate trench will increase the electric field on the gate insulating layer, thereby making the gate insulating layer easily broken down; in the related art, a P+ region can be formed at the bottom of the gate trench as an electric field shielding structure (not shown) by ion implantation, but the P+ region at the gate bottom is prone to degradation of the shielding effect and failure due to accumulated charge. Therefore, how to reduce the on-resistance and volume of semiconductor devices while increasing the breakdown voltage of the devices is a technical problem that needs to be solved urgently by people in this field. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle, so as to reduce the on-resistance and volume of the semiconductor device while increasing the breakdown voltage of the device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0006] substrate;

[0007] a semiconductor epitaxial layer located on one side of the substrate; wherein the substrate includes a first region extending along a first direction and second regions located on opposite sides of the first region; the semiconductor epitaxial layer located in the second region includes a drift region, a body region, and a first doping type contact region sequentially away from the substrate; and the semiconductor epitaxial layer located in the first region includes a drift region and a second doping type contact region sequentially away from the substrate;

[0008] A gate trench and a trench gate structure; the gate trench is located on a surface of the semiconductor epitaxial layer away from the substrate and extends along a second direction; the trench gate structure is located in the gate trench; the second direction intersects the first direction;

[0009] a shielding layer, located in the semiconductor epitaxial layer and at the bottom of the trench gate structure;

[0010] a connecting column located in the semiconductor epitaxial layer and located on at least one side of the trench gate structure, the connecting column being used to connect the shielding layer and the second doping type contact region;

[0011] a first electrode, located on a side of the substrate away from the semiconductor epitaxial layer and in contact with the first doping type contact region and the second doping type contact region;

[0012] The second electrode is located on a surface of the semiconductor epitaxial layer away from the substrate.

[0013] Optionally, the shielding layer extends along the second direction; in a plane perpendicular to the second direction, the shielding layer is in a concave shape;

[0014] The shielding layer includes a first sidewall, a second sidewall and a bottom layer located between the first sidewall and the second sidewall; the bottom layer is located between the bottom of the trench gate structure and the substrate; the first sidewall and the second sidewall are respectively located on opposite sides of the bottom of the trench gate structure.

[0015] Optionally, the connecting column extends along the second direction;

[0016] The connecting column located in the second region is columnar in a plane perpendicular to the second direction, with a top in contact with the body region and spaced apart from the shielding layer in the first direction;

[0017] The connecting column located in the first region is in an inverted T-shape in a plane perpendicular to the second direction, with a top in contact with the second doping type contact region and a bottom including an extension portion connected to the adjacent shielding layer.

[0018] Optionally, a surface of the semiconductor epitaxial layer away from the substrate includes a plurality of gate trenches extending along the second direction and arranged at intervals along the first direction, and a trench gate structure is correspondingly provided in each of the gate trenches;

[0019] The connecting pillar is located between two adjacent trench gate structures.

[0020] Optionally, in the first region, the second doping type contact regions are continuously arranged in the first direction between two adjacent trench gate structures; and the connecting pillar is arranged between every two adjacent trench gate structures;

[0021] Alternatively, in the first region, the second doping type contact region is arranged between two adjacent trench gate structures at intervals in the first direction; the connecting column is located between two adjacent trench gate structures in the sandwiched area containing the second doping type contact region; wherein, the two adjacent second doping type contact regions include a body region and a first doping type contact region that are sequentially away from the substrate.

[0022] Optionally, in the second region, a distance between the top of the first sidewall and the body region is greater than zero, and a distance between the top of the second sidewall and the body region is greater than zero;

[0023] In the first region, a distance from the top of the first sidewall to the second doping type contact region is greater than or equal to zero; a distance from the top of the second sidewall to the second doping type contact region is greater than or equal to zero.

[0024] Optionally, in a direction perpendicular to the substrate, the thickness of the shielding layer is greater than a first preset value, and the height of the connecting column is greater than a second preset value.

[0025] Optionally, the shielding layer, the connecting pillar and the body region are all doped with ions of the second doping type, and the doping concentration of the shielding layer and the connecting pillar are both greater than the doping concentration of the body region;

[0026] The drift region is doped with ions of a first doping type.

[0027] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, which is used to manufacture the semiconductor device according to any embodiment of the present invention, comprising:

[0028] Providing a substrate; the substrate comprising a first region extending along a first direction and second regions located on opposite sides of the first region;

[0029] forming a semiconductor epitaxial layer on one side of the substrate;

[0030] Performing ion implantation on the semiconductor epitaxial layer to form a drift region, a body region, and a first doping type contact region sequentially away from the substrate in the semiconductor epitaxial layer located in the second region, forming a drift region and a second doping type contact region sequentially away from the substrate in the semiconductor epitaxial layer located in the first region, and forming a connecting column extending along a second direction in the drift region;

[0031] forming a gate trench extending along the second direction on a surface of the semiconductor epitaxial layer away from the substrate;

[0032] Performing ion implantation at the bottom of the gate trench to form a shielding layer;

[0033] forming a trench gate structure in the gate trench; wherein the connecting column is located on at least one side of the trench gate structure, and the connecting column is used to connect the shielding layer and the second doping type contact area;

[0034] A first electrode is formed on a side of the semiconductor epitaxial layer away from the substrate, and a second electrode is formed on a side of the substrate away from the semiconductor epitaxial layer; wherein the first electrode contacts the first doping type contact region and the second doping type contact region.

[0035] Optionally, before performing ion implantation at the bottom of the gate trench to form a shielding layer, the method further includes:

[0036] forming a first sacrificial oxide layer on a surface of the semiconductor epitaxial layer away from the substrate, and on the sidewalls and bottom of the gate trench;

[0037] The first sacrificial oxide layer at the bottom of the gate trench is removed.

[0038] Optionally, after ion implantation is performed at the bottom of the gate trench to form a shielding layer, the method further includes:

[0039] A carbon film is formed on the surface of the semiconductor epitaxial layer away from the substrate, the sidewalls and the bottom of the gate trench, and the gate trench wall is passivated with argon gas and subjected to high-temperature annealing treatment, and then the carbon film is removed.

[0040] Optionally, after removing the carbon film, the method further includes:

[0041] A second sacrificial oxide layer is formed on the surface of the semiconductor epitaxial layer away from the substrate, the sidewall and the bottom of the gate trench, and the second sacrificial oxide layer and the first sacrificial oxide layer are removed in sequence.

[0042] Optionally, forming a second doping type contact region in the semiconductor epitaxial layer located in the first region includes:

[0043] forming second doping type contact regions continuously arranged in the first direction in the semiconductor epitaxial layer located in the first region;

[0044] forming a connecting column extending along a second direction in the drift region, comprising:

[0045] forming a connecting column extending along the second direction between every two adjacent trench gate structures;

[0046] Alternatively, forming a second doping type contact region in the semiconductor epitaxial layer located in the first region comprises:

[0047] forming a plurality of second doping type contact regions spaced apart in the first direction in the semiconductor epitaxial layer located in the first region;

[0048] forming a connecting column extending along a second direction in the drift region, comprising:

[0049] The connecting pillar is formed between two adjacent trench gate structures including the second doping type contact region in the sandwiched area.

[0050] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device according to any one of the embodiments of the present invention, wherein the substrate is configured to support a dual-gate semiconductor device.

[0051] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0052] The power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0053] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is configured to convert alternating current (AC) into direct current (DC), convert DC into DC, or convert DC into AC, and then input the converted DC into AC, and then input the converted DC into the load.

[0054] The technical solution provided by the embodiment of the present invention is to sequentially arrange the first doping type contact area and the second doping type contact area in the direction in which the trench gate structure extends (the second direction), so that the contact area between the two adjacent trench gate structures has only the first doping type contact area, or only the second doping type contact area; instead of sequentially arranging the first doping type contact area and the second doping type contact area in the direction in which the trench gate structure is arranged (the first direction) in the related art, therefore, compared with the method of sequentially arranging the first doping type contact area and the second doping type contact area between the two adjacent trench gate structures in the related art, the embodiment of the present invention can reduce the contact area between the two adjacent trench gate structures. The gate spacing between the trench gate structures can reduce the volume of the unit cell, improve the device area utilization efficiency and reduce the on-resistance; in addition, a shielding layer is set at the bottom of the trench gate structure, and a connecting column is set on at least one side of the trench gate structure. The shielding layer and the second doping type contact area are connected through the connecting column, thereby realizing conduction between the shielding layer and the first electrode, preventing the shielding layer at the bottom of the gate from experiencing a decrease in shielding effect and failure due to accumulated charge, thereby ensuring the breakdown voltage of the device; in addition, the connecting column can generate a lateral electric field similar to a super junction when the device is turned off, protecting the prone collapse points on both sides of the device gate bottom, thereby further improving the breakdown voltage of the device.

[0055] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 This is a schematic structural diagram of a trench-type semiconductor device provided in the prior art;

[0058] Figure 2 is a three-dimensional diagram of a semiconductor device provided by an embodiment of the present invention;

[0059] Figure 3 yes Figure 2 Schematic diagram of the cross-section structure along section line AA1;

[0060] Figure 4 yes Figure 2 Schematic diagram of the cross-sectional structure along section line BB1;

[0061] Figure 5is a top view of a substrate provided by an embodiment of the present invention;

[0062] Figure 6 yes Figure 2 Another schematic cross-sectional view along section line BB1;

[0063] Figure 7 is a three-dimensional diagram of another semiconductor device provided by an embodiment of the present invention;

[0064] Figure 8 yes Figure 7 Schematic diagram of the cross-sectional structure along section line CC1;

[0065] Figure 9 yes Figure 7 Another cross-sectional structural diagram along section line CC1;

[0066] Figure 10 is a schematic cross-sectional structural diagram of another semiconductor device located in the second region provided by an embodiment of the present invention;

[0067] Figure 11 is a schematic cross-sectional structural diagram of another semiconductor device located in the second region provided by an embodiment of the present invention;

[0068] Figure 12 1 is a schematic structural diagram corresponding to step S110 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0069] Figure 13 1 is a schematic structural diagram corresponding to step S120 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0070] Figures 14 and 15 1 is a schematic structural diagram corresponding to step S130 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0071] Figures 16 and 17 1 is a schematic structural diagram corresponding to step S140 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0072] Figures 18-19 1 is a schematic structural diagram corresponding to step S150 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0073] Figure 20 is a top view of a semiconductor epitaxial layer provided by an embodiment of the present invention;

[0074] Figure 21 It is a top view of another semiconductor epitaxial layer provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0075] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0076] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0077] An embodiment of the present invention provides a semiconductor device, Figure 2 is a three-dimensional diagram of a semiconductor device provided by an embodiment of the present invention, Figure 3 yes Figure 2 Schematic diagram of the cross-section structure along the section line AA1 ( Figure 3 The first electrode 70 and the passivation layer 90 are not shown. Figure 4 yes Figure 2 Schematic diagram of the cross-sectional structure along the section line BB1, where Figure 2 The diagram in the left area shows an example of the external structure of a semiconductor device. Figure 2 The diagram in the middle right area exemplarily shows the internal structure of the semiconductor device; Figures 2 to 4 , semiconductor devices include:

[0078] substrate 10;

[0079] A semiconductor epitaxial layer 20 is located on one side of a substrate 10. The substrate 10 includes a first region extending along a first direction X and second regions located on opposite sides of the first region. The semiconductor epitaxial layer 20 located in the second region includes a drift region 21, a body region 22, and a first doping type contact region 23, which are sequentially farther away from the substrate 10. The semiconductor epitaxial layer 20 located in the first region Q1 includes the drift region 21 and the second doping type contact region 24, which are sequentially farther away from the substrate 10.

[0080] A gate trench and a trench gate structure 50; the gate trench is located on a surface of the semiconductor epitaxial layer 20 away from the substrate 10 and extends along a second direction Y; the trench gate structure 50 is located in the gate trench; the second direction Y intersects the first direction X;

[0081] The shielding layer 30 is located in the semiconductor epitaxial layer 20 and at the bottom of the trench gate structure 50;

[0082] a connecting pillar 40 , located in the semiconductor epitaxial layer 20 and at least on one side of the trench gate structure 50 , the connecting pillar 40 being used to connect the shielding layer 30 and the second doping type contact region 24 ;

[0083] A first electrode 70 is located on a side of the substrate 10 away from the semiconductor epitaxial layer 20 and is in contact with the first doping type contact region 23 and the second doping type contact region 24;

[0084] The second electrode is located on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 .

[0085] Specifically, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 may be the same or different. In an embodiment of the present invention, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 are the same, and both may be SiC. That is, the trench power device in the embodiment of the present invention may be a trench SiC power device. SiC has excellent physical and electrical properties. Compared with silicon, SiC has a larger bandgap and has advantages such as a high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios. In some embodiments of the present invention, the substrate 10 and the semiconductor epitaxial layer 20 can be provided integrally. The substrate 10 and the semiconductor epitaxial layer 20 being provided integrally can be understood as the substrate 10 and the semiconductor epitaxial layer 20 being a single SiC film structure formed in the same manufacturing process. After the front surface of the entire SiC film structure is processed, the back surface of the SiC film structure is thinned and heavily ion doped to form the substrate 10.

[0086] The surface of the semiconductor epitaxial layer 20 facing away from the substrate 10 includes at least one gate trench. The gate trench extends along a second direction Y, which intersects the first direction X. In one embodiment of the present invention, the second direction Y and the first direction X are perpendicular to each other. A third direction Z is perpendicular to both the second direction Y and the first direction X. The gate trench can be formed by sequentially etching the contact region, the body region 22, and the partial thickness of the drift region 21 from the surface of the semiconductor epitaxial layer 20 facing away from the substrate 10. Figure 5 is a top view of a substrate provided by an embodiment of the present invention, with reference to Figure 5The substrate 10 includes a first region Q1 extending along a first direction X and a second region Q2 located on opposite sides of the first region Q1 in a second direction Y. The drift region 21 located in the second region Q2 can have the same thickness as the drift region 21 located in the first region Q1. The sum of the thicknesses of the body region 22 and the first type contact region located in the second region Q2 can be the same as the thickness of the second doping type contact region 24 located in the second region Q2, thereby ensuring that the second doping type contact region 24 contacts at least a portion of the body region 22. A trench gate structure 50 is disposed in a gate trench. The trench gate structure 50 includes a polysilicon gate 51 and a gate insulating layer 52 located between the polysilicon gate 51 and the gate trench. The material of the gate insulating layer 52 can include at least one of aluminum oxide and silicon oxide.

[0087] The semiconductor epitaxial layer 20 is also provided with a shielding layer 30 and a connecting pillar 40. The shielding layer 30 and the connecting pillar 40 can be formed by implanting dopant ions of the second doping type into the semiconductor epitaxial layer 20. The connecting pillar 40 is located on at least one side of the trench gate structure 50 and extends along the direction in which the trench gate structure 50 extends. During the extension process, the top of the connecting pillar 40 contacts the second doping type contact region 24, thereby achieving electrical connection with the second doping type contact region 24. The shielding layer 30 is located at the bottom of the trench gate structure 50 and contacts the adjacent connecting pillar 40, thereby achieving electrical connection between the shielding layer 30 and the second doping type contact region 24 through the connecting pillar 40. The second doping type contact region 24 contacts the first electrode 70, thereby realizing electrical connection between the shielding layer 30 and the first electrode 70, preventing the shielding effect of the gate bottom shielding layer 30 from being reduced and failing due to accumulated charge, thereby ensuring the breakdown voltage of the device; moreover, the connecting column 40 can generate a lateral electric field similar to a superjunction when the device is turned off, protecting the vulnerable points on both sides of the gate bottom of the device, and also improving the breakdown voltage of the device. Among them, the materials of the first electrode 70 and the second electrode can both include metal materials. The first electrode 70 can be a drain electrode, and the second electrode can be a source electrode; or, the first electrode 70 can be a source electrode, and the second electrode can be a drain electrode. In an embodiment of the present invention, the first electrode 70 is a source electrode, and the second electrode is a drain electrode.

[0088] In addition, compared Figure 3 and Figure 1In the embodiment of the present invention, the first doping type contact region 23 and the second doping type contact region 24 are sequentially arranged in the direction in which the trench gate structure 50 extends (the second direction Y), so that the contact region between two adjacent trench gate structures 50 has only the first doping type contact region 23 or only the second doping type contact region 24. This replaces the method of sequentially arranging the first doping type contact region (N+ contact region) and the second doping type contact region (P+ contact region) in the direction in which the trench gate structure (gate G) is arranged (the first direction X) as in the related art. Compared to the method of sequentially arranging the first doping type contact region and the second doping type contact region between two adjacent trench gate structures in the related art, the embodiment of the present invention can reduce the gate spacing between two adjacent trench gate structures, thereby reducing the volume of the unit cell, improving the device area utilization efficiency, and reducing the on-resistance; thereby reducing the volume of the unit cell, improving the device area utilization efficiency, and reducing the on-resistance.

[0089] The above is the core inventive concept of the present invention. The semiconductor device is described in detail below with reference to the accompanying drawings.

[0090] refer to Figures 2 to 5 Optionally, the shielding layer 30, the connecting column 40 and the body region 22 are all doped with ions of the second doping type, and the doping concentration of the shielding layer 30 and the connecting column 40 are both greater than the doping concentration of the body region 22; the drift region 21 is doped with ions of the first doping type.

[0091] Specifically, the doping type of the shielding layer 30, the doping type of the connecting pillar 40, and the doping type of the body region 22 are all the same as the doping type of the second-doping-type contact region 24. The doping type of the substrate 10 and the doping type of the drift region 21 are all the same as the doping type of the first-doping-type contact region 23. The doping type of the first-doping-type contact region 23 can be N-type, and the doping type of the second-doping-type contact region 24 can be P-type. Alternatively, the doping type of the first-doping-type contact region 23 can be P-type, and the doping type of the second-doping-type contact region 24 can be N-type. Figure 4 , the first-doping type contact region 23 and the drift region 21 are exemplarily shown to be doped with N-type dopant ions; the second-doping type contact region 24, the body region 22, the shielding layer 30, and the connecting pillar 40 are doped with P-type dopant ions. The P+ and N+ shown in the figure indicate a high ion doping concentration in that region, while the P- and N- indicate a low ion doping concentration in that region. The N-type dopant ions may be P (phosphorus) or N (nitrogen) ions, and the P-type dopant ions may be Al (aluminum) ions or B (boron) ions.

[0092] Based on the above embodiments, please continue to refer to Figures 2 to 5 Optionally, the shielding layer 30 extends along the second direction Y; in a plane perpendicular to the second direction Y, the shielding layer 30 is concave in shape.

[0093] Specifically, the shielding layer 30 extends along the direction in which the trench gate structure 50 extends, so that the entire bottom of the trench gate structure 50 is protected by the shielding layer 30. The shielding layer 30 includes a first sidewall 32, a second sidewall 33, and a bottom layer 31 located between the first sidewall 32 and the second sidewall 33; the bottom layer 31 is located between the bottom of the trench gate structure 50 and the substrate 10; the first sidewall 32 and the second sidewall 33 are respectively located on opposite sides of the bottom of the trench gate structure 50. In a plane perpendicular to the second direction Y, the shielding layer 30 is concave in shape, forming a cap-shaped shielding layer, which can effectively enhance the shielding layer 30's protective effect on the bottom surface and bottom corners of the trench gate structure 50, reduce the risk of electric field breakdown at the bottom surface and bottom corners of the trench gate structure 50, and thus further improve the breakdown voltage of the semiconductor device.

[0094] Based on the above embodiments, please continue to refer to Figure 2 and Figure 3 Optionally, in the second region Q2, the distance between the top of the first side wall 32 and the body region 22 is greater than zero, and the distance between the top of the second side wall 33 and the body region 22 is greater than zero; that is, there is a gap between the shielding layer 30 located in the second region Q2 and the body region 22, thereby ensuring that electrons flowing in from the second electrode can flow from the drift region 21 at the gap along the side wall of the gate trench into the channel in the body region 22.

[0095] refer to Figure 4 and Figure 6 , and combined with Figure 2 In the first region Q1, the distance from the top of the first sidewall 32 to the second doping type contact region 24 is greater than or equal to zero; the distance from the top of the second sidewall 33 to the second doping type contact region 24 is greater than or equal to zero. That is, the shielding layer 30 in the first region Q1 can contact the second doping type contact region 24 (e.g., Figure 4 As shown), or without contact (as shown Figure 6 When the shielding layer 30 contacts the second doping type contact region 24 , the shielding layer 30 can be directly connected to the second doping type contact region 24 , thereby achieving conduction with the first electrode 70 .

[0096] Based on the above embodiments, please continue to refer to Figures 2 to 6 , Optionally, the connecting column 40 extends along the second direction Y;

[0097] The connecting column 40 located in the second region Q2 is columnar in a plane perpendicular to the second direction Y, with the top in contact with the body region 22 and spaced apart from the shielding layer 30 in the first direction X (refer to FIG. Figure 2 and Figure 3 );

[0098] The connecting column 40 located in the first region Q1 is in an inverted T-shape in a plane perpendicular to the second direction Y, with the top in contact with the second doping type contact region 24 and the bottom including an extension portion connected to the adjacent shielding layer 30 (refer to FIG. Figure 2 、 Figure 4 and Figure 6 ).

[0099] Specifically, the connecting pillar 40 extends along the second direction Y, that is, the connecting pillar 40 extends along the direction in which the trench gate structure 50 extends. During the extension process, the top of the connecting pillar 40 contacts the second doping type contact region 24 located in the first region Q1, and contacts the first doping type contact region 23 located in the second region Q2. The connecting pillar 40 is formed by implanting dopant ions of the second doping type into the semiconductor epitaxial layer 20. Therefore, the connecting pillar 40 in the second region Q2 can be used as the second doping type contact region in the second region Q2 and contact the body region 22, so that the body region 22 in the second region Q2 can also be connected to the second doping type contact region 24 located in the first region Q1 through the connecting pillar 40 in the second region Q2, and then connected to the first electrode 70, which can further reduce the on-resistance of the semiconductor device.

[0100] The connecting pillar 40 located in the second region Q2 is columnar in a plane perpendicular to the second direction Y and is spaced apart from the shielding layer 30 in the first direction X. This ensures that electrons flowing from the second electrode can flow from the drift region 21 between the shielding layer 30 and the connecting pillar 40 to the body region 22. The connecting pillar 40 located in the first region Q1 is in an inverted T-shape in a plane perpendicular to the second direction Y, with an extension at its bottom that contacts the adjacent shielding layer 30, thereby achieving electrical connection between the connecting pillar 40 and the shielding layer 30.

[0101] Based on the above embodiments, optionally, the surface of the semiconductor epitaxial layer 20 away from the substrate 10 includes a plurality of gate trenches extending along the second direction Y and arranged at intervals along the first direction X, and a trench gate structure 50 is correspondingly arranged in each gate trench; the connecting column 40 is located between two adjacent trench gate structures 50.

[0102] Based on the above embodiments, please continue to refer to Figures 2 to 6 Optionally, in the first region Q1, the second doping type contact region 24 is continuously arranged between adjacent trench gate structures 50 in the first direction X; if there is a second doping type contact region 24 between each adjacent trench gate structure 50, a connecting column 40 can be arranged between each two adjacent trench gate structures 50.

[0103] or, Figure 7 is a three-dimensional diagram of another semiconductor device provided by an embodiment of the present invention, Figure 8 yes Figure 7Schematic diagram of the cross-section structure along the section line CC1, Figure 9 yes Figure 7 Another cross-sectional structure diagram along the section line CC1, refer to Figures 7 to 9 In the first region Q1, the second doping type contact regions 24 are spaced apart between adjacent trench gate structures 50 in the first direction X. Some adjacent trench gate structures 50 include the second doping type contact regions 24. The connecting pillar 40 is located between two adjacent trench gate structures 50 that include the second doping type contact regions 24 in the sandwiched region. Figure 9 , between two adjacent second doping type contact regions 24 are a body region 22 and a first doping type contact region 23 that are sequentially away from the substrate 10. In the embodiment of the present invention, P+ ions are selectively doped between the continuously arranged gates, thereby reducing the space occupied by the P+ region.

[0104] Figure 7 In the semiconductor device shown, the structure of the semiconductor device located in the second region Q1 can refer to Figure 3 shown. Figure 8 and Figure 9 The structures shown are all structures of semiconductor devices located in the first region Q2 (the first electrode 70 and the passivation layer 90 are not shown). Figure 8 and Figure 9 The structure shown differs in that Figure 8 The middle shielding layer 30 contacts the second doping type contact region 24. Figure 9 The middle shielding layer 30 is not in contact with the second doping type contact region 24 .

[0105] Based on the above embodiments, Figure 10 is a schematic cross-sectional structural diagram of another semiconductor device located in the second region provided by an embodiment of the present invention. Figure 11 is a schematic cross-sectional view of another semiconductor device located in the second region provided by an embodiment of the present invention, with reference to Figure 10 and Figure 11 Optionally, in a direction perpendicular to the substrate 10 , the thickness of the shielding layer 30 is greater than a first preset value, and / or the height of the connecting pillar 40 is greater than a second preset value.

[0106] in, Figure 10 In the structure shown, in the direction perpendicular to the substrate 10 , the height of the connecting pillar 40 is greater than a second preset value. Figure 11 In the structure shown, in a direction perpendicular to the substrate 10 , the thickness of the shielding layer 30 is greater than a first preset value, and the height of the connecting pillar 40 is greater than a second preset value.

[0107] Specifically, the first preset value and the second preset value can be set according to actual needs. The P+ connecting column 40, in addition to connecting the p-body to the source ground, also generates a lateral electric field similar to a superjunction when the device is turned off to protect the device from breakdown points on both sides of the gate bottom, thereby increasing the breakdown voltage. Setting the thickness of the shielding layer 30 to be greater than the first preset value and the height of the connecting column 40 to be greater than the second preset value can be understood as deepening the P+ connecting column 40 and the P+ shielding layer 30, thereby improving the electric field shielding effect on the bottom of the trench gate structure 50.

[0108] An embodiment of the present invention further provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device according to any embodiment of the present invention. The method for preparing the semiconductor device includes:

[0109] S110 , providing a substrate; the substrate includes a first region extending along a first direction and second regions located on opposite sides of the first region.

[0110] Specifically, refer to Figure 12 , the material of the substrate 10 can be SiC. Figure 5 The substrate 10 includes a first region Q1 extending along a first direction X and second regions Q2 located at opposite sides of the first region Q1.

[0111] S120 , forming a semiconductor epitaxial layer on one side of the substrate.

[0112] Specifically, refer to Figure 13 , the material of the semiconductor epitaxial layer 20 may be the same as or different from the material of the substrate 10. In an embodiment of the present invention, the material of the substrate 10 is the same as the material of the semiconductor epitaxial layer 20, and both may be SiC. That is, the trench power device in the embodiment of the present invention may be a trench SiC power device. In some embodiments of the present invention, the substrate 10 and the semiconductor epitaxial layer 20 may be integrally provided. The integral provision of the substrate 10 and the semiconductor epitaxial layer 20 can be understood as the substrate 10 and the semiconductor epitaxial layer 20 being a whole SiC film layer structure formed in the same preparation process.

[0113] S130. Perform ion implantation on the semiconductor epitaxial layer to form a drift region, a body region, and a first doping type contact region that are sequentially away from the substrate in the semiconductor epitaxial layer located in the second region, form a drift region and a second doping type contact region that are sequentially away from the substrate in the semiconductor epitaxial layer located in the first region, and form a connecting column extending along the second direction in the drift region.

[0114] Specifically, the PECVD and photolithography techniques can be used to transfer the pattern of the mask to the SiO2 mask layer, and then the semiconductor epitaxial layer 20 is frontally ion-implanted based on the patterned mask layer to form a drift region 21, a body region 22, and a first doping type contact region 23 that are sequentially away from the substrate 10 in the semiconductor epitaxial layer 20 located in the second region Q2 (refer to FIG. Figure 14 ), a drift region 21 and a second doping type contact region 24 are formed in the semiconductor epitaxial layer 20 located in the first region Q1, which are sequentially away from the substrate 10 (refer to Figure 15 ), and forming a connection column 40 extending along the second direction Y in the drift region 21 (refer to Figure 14 and Figure 15 ). The mask layer is then removed. Mask layers with different patterns can be used when ion implantation is performed on different areas.

[0115] Figure 14 and Figure 15 In the embodiment, the first doping type contact region 23 and the drift region 21 are doped with N-type dopant ions; the second doping type contact region 24, the body region 22, and the connecting pillar 40 are doped with P-type dopant ions. The P-type dopant ion implantation can be performed in batches, and a deeper P+ connecting pillar 40 can be formed first (high energy implantation allows for deeper implantation); then, P-type dopant ions are implanted upwards in the second region Q2 to form a P-body region 22 with a lower concentration of P-type dopant ions; and then, N-type dopant ions are implanted upwards to form an N+ contact region (first doping type contact region 23) above the P-body region 22. P-type dopant ions are implanted in the first region Q1 to form a P+ contact region (second doping type contact region 24).

[0116] S140 , forming a gate trench extending along a second direction on a surface of the semiconductor epitaxial layer away from the substrate.

[0117] Specifically, Figure 16 is a schematic diagram of forming a gate trench in the second region Q2 corresponding to step S140, Figure 17 is a schematic diagram of forming a gate trench in the first region Q1 corresponding to step S140, referring to Figure 16 and Figure 17, a gate trench 01 extending along the second direction Y can be formed on the side of the semiconductor epitaxial layer 20 away from the substrate 10 by a photolithography process. Specific steps may include: depositing SiO2 as a mask layer on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 by a deposition process such as CVD, spin-coating a photoresist PR on the mask layer surface, forming the photoresist PR of the desired pattern by exposure and development, and then etching the mask layer based on the patterned photoresist PR to pattern the mask layer. The patterned mask layer exposes the preset position of the gate trench. Based on the patterned mask layer, the semiconductor epitaxial layer 20 is etched to form the gate trench 01. The etching process can be a plasma dry etching process, such as RIE or ICP etching process. The gate trench 01 extends along the second direction Y, and the number of gate trenches 01 can be set according to actual needs. In one embodiment of the present invention, a plurality of gate trenches 01 extending along the second direction Y and spaced apart along the first direction X are formed on the surface of the semiconductor.

[0118] Furthermore, before ion implantation is performed at the bottom of the gate trench 01 to form the shielding layer 30, it also includes: forming a first sacrificial oxide layer on the surface of the semiconductor epitaxial layer 20 away from the substrate 10, the sidewalls and bottom of the gate trench 01, and removing the first sacrificial oxide layer at the bottom of the gate trench.

[0119] Specifically, a first sacrificial oxide layer is formed on the sidewalls and bottom of the gate trench 01 to repair damage caused by etching. The first sacrificial oxide layer at the bottom of the gate trench is removed, while the first sacrificial oxide layer at the sidewalls is retained. The patterned first sacrificial oxide layer can be used as a mask layer for ion implantation to form the shielding layer 30, thereby simplifying the semiconductor device fabrication process. The first sacrificial oxide layer at the bottom of the gate trench 01 can be removed by BOE cleaning.

[0120] S150 , performing ion implantation at the bottom of the gate trench to form a shielding layer.

[0121] Specifically, Figure 18 is a schematic diagram of forming a shielding layer 30 in the second region Q2 corresponding to step S150, Figure 19 is a schematic diagram of forming the shielding layer 30 in the first region Q1 corresponding to step S150, referring to Figure 18 and Figure 19, with a patterned first sacrificial oxide layer, ion implantation is performed at the bottom of the gate trench 01 to form a shielding layer 30 extending along the second direction Y. The shielding layer 30 may include a first sidewall 32, a second sidewall 33, and a bottom layer 31 located between the first sidewall 32 and the second sidewall 33; the bottom layer 31 is located at the bottom of the gate trench; the first sidewall 32 and the second sidewall 33 are located on opposite sides of the gate trench. In a plane perpendicular to the second direction Y, the shielding layer 30 is concave in shape, forming a cap-shaped shielding layer, which can effectively enhance the shielding layer 30's protective effect on the bottom surface and bottom corners of the trench gate structure 50.

[0122] Furthermore, after ion implantation is performed at the bottom of the gate trench to form a shielding layer, the method further includes:

[0123] A carbon film is formed on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 and the sidewalls and bottom of the gate trench 01 . The walls of the gate trench 01 are passivated with argon gas and subjected to high-temperature annealing treatment, and then the carbon film is removed.

[0124] Specifically, to activate the implanted dopant ions and eliminate lattice damage defects caused by the implanted dopant ions, the semiconductor epitaxial layer 20 needs to be activated and annealed at a high temperature, typically as high as 1600°C to 1800°C. However, at such a high activation annealing temperature, since the semiconductor epitaxial layer 20 is made of silicon carbide, Si on the silicon carbide surface easily sublimates from the SiC surface and redeposits on the wafer surface in the form of Si, Si2C, SiC2, etc., forming step clusters. This increases the surface roughness of the SiC wafer and the interface state density, seriously affecting device performance. A commonly used method for high-temperature annealing is the carbon film protection method, which is generally produced by sputtering a carbon film protective layer or by baking and curing a photoresist to form a carbon film protective layer. After the high-temperature annealing is completed, the carbon film used to protect the silicon carbide surface needs to be removed. If the carbon film is not removed cleanly, it will affect the ohmic contact and seriously affect the device's switching characteristics, conductivity, withstand voltage characteristics, and other performance. The carbon film can be removed by immersion in a chemical solution, which is usually a certain concentration of hydrochloric acid with a certain amount of nitric acid as a catalyst.

[0125] Furthermore, after removing the carbon film, the process further includes forming a second sacrificial oxide layer on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 and on the sidewalls and bottom of the gate trench 01, and sequentially removing the second sacrificial oxide layer and the first sacrificial oxide layer. Specifically, after removing the carbon film from the surface of the semiconductor epitaxial layer 20, a second sacrificial oxide layer is formed on the surface of the semiconductor epitaxial layer 20 through a thermal oxidation process to repair the crystal lattice of the semiconductor epitaxial layer 20; then, the second sacrificial oxide layer and the first sacrificial oxide layer are removed. The surface sacrificial oxide layer can be removed by BOE cleaning.

[0126] S160, forming a trench gate structure in the gate trench; wherein a connecting column is located on at least one side of the trench gate structure, and the connecting column is used to connect the shielding layer and the second doping type contact area.

[0127] Specifically, refer to Figure 3 and Figure 4 A gate insulating layer 52 is formed on the walls of the gate trench; and a polysilicon material is filled in the gate trench to form a polysilicon gate 51. The trench gate structure 50 includes a polysilicon gate 51 and a gate insulating layer 52 surrounding the polysilicon gate 51. The material of the gate insulating layer 52 can include at least one of SiO2 and Al2O3, and the gate insulating layer 52 can be prepared by at least one of ALD, thermal oxidation, and wet processing.

[0128] S170, forming a first electrode on a side of the semiconductor epitaxial layer away from the substrate, and forming a second electrode on a side of the substrate away from the semiconductor epitaxial layer; wherein the first electrode is in contact with the first doping type contact region and the second doping type contact region.

[0129] Specifically, after forming the first electrode 70 on the side of the semiconductor epitaxial layer 20 away from the substrate 10, the second electrode may be formed on the side of the substrate 10 away from the semiconductor epitaxial layer 20. It should be noted that before forming the second electrode on the surface of the substrate 10 away from the semiconductor epitaxial layer 20, the substrate 10 may be thinned from the side of the substrate 10 away from the semiconductor epitaxial layer 20, and the substrate 10 may be heavily doped with the first dopant ions, so that the doping concentration of the first dopant ions in the substrate 10 is greater than the doping concentration of the first dopant ions in the drift region 21.

[0130] Before forming the first electrode 70 on the side of the semiconductor epitaxial layer 20 away from the substrate 10, a passivation layer 90 can be formed on the side of the semiconductor epitaxial layer 20 away from the substrate 10, and then an opening is formed in the passivation layer 90, and then the first electrode 70 is formed, so that the first electrode 70 and the trench gate structure 50 can be isolated by the passivation layer 90.

[0131] Based on the above embodiments, Figure 20 Optionally, forming a second doping type contact region 24 in the semiconductor epitaxial layer 20 located in the first region Q1 includes: forming the second doping type contact region 24 continuously arranged in the first direction X in the semiconductor epitaxial layer 20 located in the first region Q1. Then forming a connecting column 40 extending along the second direction Y in the drift region 21 includes: forming a connecting column 40 extending along the second direction Y between each two adjacent trench gate structures 50, thereby forming the following Figure 2 The arrangement of the second doping type contact region 24 and the connecting column 40 in FIG.

[0132] Based on the above embodiments, Figure 21 Optionally, forming a second doping type contact region 24 in the semiconductor epitaxial layer 20 located in the first region Q1 includes forming a plurality of second doping type contact regions 24 spaced apart in the first direction X in the semiconductor epitaxial layer 20 located in the first region Q1. Then forming a connecting column 40 extending along the second direction Y in the drift region 21 includes forming a connecting column 40 between two adjacent trench gate structures 50 containing the second doping type contact regions 24 in the sandwiched region. Thus, the following can be formed: Figure 7 The arrangement of the second doping type contact region 24 and the connecting column 40 in FIG.

[0133] An embodiment of the present invention further provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to support the semiconductor device. The power module has the same technical effects and will not be described in detail here.

[0134] An embodiment of the present invention further provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, the semiconductor device being electrically connected to the circuit board. The circuit has the same technical effects and is not further described here.

[0135] An embodiment of the present invention further provides a vehicle including a load and a power conversion circuit according to any embodiment of the present invention, wherein the power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. The embodiments have the same technical effects and are not further described here.

[0136] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a semiconductor epitaxial layer located on one side of the substrate; wherein the substrate includes a first region extending along a first direction and second regions located on opposite sides of the first region; the semiconductor epitaxial layer located in the second region includes a drift region, a body region, and a first doping type contact region sequentially away from the substrate; and the semiconductor epitaxial layer located in the first region includes a drift region and a second doping type contact region sequentially away from the substrate; A gate trench and a trench gate structure; the gate trench is located on a surface of the semiconductor epitaxial layer away from the substrate and extends along a second direction; the trench gate structure is located in the gate trench; the second direction intersects the first direction; a shielding layer, located in the semiconductor epitaxial layer and at the bottom of the trench gate structure; a connecting column located in the semiconductor epitaxial layer and on at least one side of the trench gate structure, the connecting column being used to connect the shielding layer and the second doping type contact region; the connecting column extending along the second direction; the connecting column located in the second region being columnar in a plane perpendicular to the second direction, with a top in contact with the body region and spaced apart from the shielding layer in the first direction; the connecting column located in the first region being in an inverted T-shape in a plane perpendicular to the second direction, with a top in contact with the second doping type contact region and a bottom including an extension portion connected to the adjacent shielding layer; a first electrode, located on a side of the substrate away from the semiconductor epitaxial layer and in contact with the first doping type contact region and the second doping type contact region; The second electrode is located on a surface of the semiconductor epitaxial layer away from the substrate.

2. The semiconductor device according to claim 1, wherein The shielding layer extends along the second direction; in a plane perpendicular to the second direction, the shielding layer is in a concave shape; The shielding layer includes a first sidewall, a second sidewall and a bottom layer located between the first sidewall and the second sidewall; the bottom layer is located between the bottom of the trench gate structure and the substrate; the first sidewall and the second sidewall are respectively located on opposite sides of the bottom of the trench gate structure.

3. The semiconductor device according to claim 1, wherein The surface of the semiconductor epitaxial layer away from the substrate includes a plurality of gate trenches extending along the second direction and spaced apart along the first direction, wherein each gate trench is correspondingly provided with a trench gate structure; The connecting pillar is located between two adjacent trench gate structures.

4. The semiconductor device according to claim 3, wherein In the first region, the second doping type contact region is continuously arranged between two adjacent trench gate structures in the first direction; and the connecting pillar is arranged between every two adjacent trench gate structures; Alternatively, in the first region, the second doping type contact region is arranged between two adjacent trench gate structures at intervals in the first direction; the connecting column is located between two adjacent trench gate structures in the sandwiched area containing the second doping type contact region; wherein, the two adjacent second doping type contact regions include a body region and a first doping type contact region that are sequentially away from the substrate.

5. The semiconductor device according to claim 2, wherein In the second region, a distance between the top of the first sidewall and the body region is greater than zero, and a distance between the top of the second sidewall and the body region is greater than zero; In the first region, a distance from the top of the first sidewall to the second doping type contact region is greater than or equal to zero; a distance from the top of the second sidewall to the second doping type contact region is greater than or equal to zero. The semiconductor device according to claim 1 , wherein: In a direction perpendicular to the substrate, the thickness of the shielding layer is greater than a first preset value, and the height of the connecting pillar is greater than a second preset value.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The shielding layer, the connecting pillar and the body region are all doped with ions of the second doping type, and the doping concentration of the shielding layer and the connecting pillar are both greater than the doping concentration of the body region; The drift region is doped with ions of a first doping type.

8. A method for preparing a semiconductor device, characterized in that: Used to prepare the semiconductor device according to any one of claims 1 to 7, comprising: Providing a substrate; the substrate comprising a first region extending along a first direction and second regions located on opposite sides of the first region; forming a semiconductor epitaxial layer on one side of the substrate; Performing ion implantation on the semiconductor epitaxial layer to form a drift region, a body region, and a first doping type contact region sequentially away from the substrate in the semiconductor epitaxial layer located in the second region, forming a drift region and a second doping type contact region sequentially away from the substrate in the semiconductor epitaxial layer located in the first region, and forming a connecting column extending along a second direction in the drift region; forming a gate trench extending along the second direction on a surface of the semiconductor epitaxial layer away from the substrate; Performing ion implantation at the bottom of the gate trench to form a shielding layer; forming a trench gate structure in the gate trench; wherein the connecting column is located on at least one side of the trench gate structure, and the connecting column is used to connect the shielding layer and the second doping type contact area; A first electrode is formed on a side of the semiconductor epitaxial layer away from the substrate, and a second electrode is formed on a side of the substrate away from the semiconductor epitaxial layer; wherein the first electrode contacts the first doping type contact region and the second doping type contact region.

9. The method for preparing a semiconductor device according to claim 8, wherein: Before ion implantation is performed at the bottom of the gate trench to form a shielding layer, the method further includes: forming a first sacrificial oxide layer on a surface of the semiconductor epitaxial layer away from the substrate, and on the sidewalls and bottom of the gate trench; The first sacrificial oxide layer at the bottom of the gate trench is removed.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: After ion implantation is performed at the bottom of the gate trench to form a shielding layer, the method further includes: A carbon film is formed on the surface of the semiconductor epitaxial layer away from the substrate, the sidewalls and the bottom of the gate trench, and the gate trench wall is passivated with argon gas and subjected to high-temperature annealing treatment, and then the carbon film is removed.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: After removing the carbon film, the method further comprises: A second sacrificial oxide layer is formed on the surface of the semiconductor epitaxial layer away from the substrate, the sidewall and the bottom of the gate trench, and the second sacrificial oxide layer and the first sacrificial oxide layer are removed in sequence.

12. The method for preparing a semiconductor device according to claim 8, wherein: Forming a second doping type contact region in the semiconductor epitaxial layer located in the first region, comprising: forming second doping type contact regions continuously arranged in the first direction in the semiconductor epitaxial layer located in the first region; forming a connecting column extending along a second direction in the drift region, comprising: forming a connecting column extending along the second direction between every two adjacent trench gate structures; Alternatively, forming a second doping type contact region in the semiconductor epitaxial layer located in the first region comprises: forming a plurality of second doping type contact regions spaced apart in the first direction in the semiconductor epitaxial layer located in the first region; forming a connecting column extending along a second direction in the drift region, comprising: The connecting pillar is formed between two adjacent trench gate structures including the second doping type contact region in the sandwiched area.

13. A power module, characterized in that: The method comprises a substrate and at least one semiconductor device according to any one of claims 1 to 7, wherein the substrate is used to carry the semiconductor device.

14. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

15. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 14, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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