Control method, device, circuit and chip of switching converter

Abstract

The present application discloses a control method, device, circuit and chip for a switching converter, which relates to the field of switching power supplies. The method comprises obtaining a first PFM time control curve PFML and a second PFM time control curve PFMR; the curve PFMR is a hysteresis curve of the curve PFML, and the same V FB The PFM time corresponding to the voltage on the curve PFMR is greater than the PFM time corresponding to the voltage on the curve PFML; based on the curve PFMR and the curve PFML, according to the current V FB and valley signal, to determine whether the first restriction condition or the second restriction condition is met, the first restriction condition being the judgment condition for the converter to switch from the QR mode to the CCM mode; the second restriction condition being the judgment condition for the converter to switch from the CCM mode to the QR mode; when the first restriction condition or the second restriction condition is met, the corresponding working mode switching is performed.

Description

Technical Field

[0001] The present application relates to the field of switching power supplies, and in particular to a control method, device, circuit and chip for a switching converter. Background Art

[0002] like Figure 1 As shown, according to the waveform characteristics of the primary current IPRI and the secondary current ISEC of the isolation transformer of the switching converter, its operating mode is divided into continuous conduction mode (CCM), critical conduction mode (BCM) and discontinuous conduction mode (DCM). In the DCM mode, the operating mode in which the switching converter is turned on at the resonance valley is called quasi-resonant mode (QR). The control loop controls the operating mode of the switching converter according to the feedback voltage of the switching converter.

[0003] Under low input voltage and heavy load conditions, the input voltage fluctuates greatly, resulting in large fluctuations in the feedback voltage. This in turn causes the converter that switches modes based on the feedback voltage to easily switch repeatedly between CCM mode and QR mode, affecting the stability of the switching converter. Summary of the invention

[0004] The purpose of the present application is to provide a control method, device, circuit and chip for a switching converter to solve the problem that the switching converter repeatedly switches between CCM mode and QR mode under low input voltage and heavy load conditions, affecting the stability of the switching converter.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] In a first aspect, the present application provides a control method for a switching converter, comprising:

[0007] Obtain a first PFM time control curve PFML and a second PFM time control curve PFMR, wherein the curve PFML is a feedback voltage V FB With the first PFM time T PFML The relationship curve of PFMR is the feedback voltage V FB The second PFM time T PFMR The curve PFMR is the hysteresis curve of the curve PFML, the same V FB The PFM time T corresponding to the voltage on the PFMR curve PFMR Greater than the corresponding PFM time T on the PFML curve PFML ;

[0008] Based on the curve PFMR and the curve PFML, according to the current V FBand valley signal, to determine whether the switching converter satisfies a first restriction condition or a second restriction condition; the first restriction condition is used as a determination condition for the converter to switch from the QR mode to the CCM mode; the second restriction condition is used as a determination condition for the converter to switch from the CCM mode to the QR mode;

[0009] When the first restriction condition or the second restriction condition is met, the corresponding working mode is switched.

[0010] Optionally, when the first restriction condition or the second restriction condition is met, performing corresponding working mode switching includes:

[0011] When the first restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFMR PFMR , controls the end position of the current switching cycle of the switching converter to switch from the first valley of the current switching cycle to the PFM time T PFMR When the time after △t time is reached, the next switching cycle is entered to switch from QR mode to CCM mode;

[0012] When the second restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFML PFML , controlling the switch of the switching converter to be turned on at the first valley bottom of the current switching cycle, thereby switching from the CCM mode to the QR mode.

[0013] Optionally, before determining whether the first restriction condition is met, the method further includes:

[0014] Based on the curve PFMR and the curve PFML, determine the current V FB The corresponding PFM time T PFML and T PFMR At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR Perform timing, and detect the valley signal during the timing period;

[0015] The first restriction condition includes at least one of a first condition and a second condition;

[0016] The first condition includes: at the current V FB The corresponding T PFMR No valley signal is detected within the △t time after the timing is reached, where △t is greater than 1 / 2 of the free resonance period;

[0017] The second condition includes: the current V FB Greater than the feedback voltage threshold Vth , V th Greater than the critical feedback voltage of CCM mode and QR mode.

[0018] Optionally, before determining whether the second restriction condition is met, the method further includes:

[0019] Based on the curve PFMR and the curve PFML, determine the current V FB The corresponding PFM time T PFML and T PFMR At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR Perform timing, and detect the valley signal during the timing period; when the switching converter switches from the QR mode to the CCM mode, it is necessary to time the time after switching to the CCM mode;

[0020] The second restriction condition includes the third condition and the fourth condition;

[0021] The third condition includes: at the current V FB The corresponding PFM time T PFML After the timing is reached and the PFM time T PFMR Before the timing is reached, the valley signal is detected;

[0022] The fourth condition includes: the switching converter switches from QR mode to CCM mode after T blank Switching to QR mode is not allowed within the time threshold.

[0023] Optionally, at the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR When timing, the same timer is used to measure the current V FB The corresponding PFM time T PFML and T PFMR Keep timing.

[0024] In a second aspect, the present application provides a control device for a switching converter, comprising:

[0025] The control curve module obtains the first PFM time control curve PFML and the second PFM time control curve PFMR, wherein the curve PFML is the feedback voltage V FB With the first PFM time T PFML The relationship curve of PFMR is the feedback voltage V FB The second PFM time T PFMR The curve PFMR is the hysteresis curve of the curve PFML, the same VFB The PFM time T corresponding to the voltage on the PFMR curve PFMR Greater than the corresponding PFM time T on the PFML curve PFML ;

[0026] A judgment module is used to determine the current V FB voltage and valley signal, to determine whether the switching converter satisfies a first restriction condition or a second restriction condition; the first restriction condition is used as a determination condition for the converter to switch from the QR mode to the CCM mode; the second restriction condition is used as a determination condition for the converter to switch from the CCM mode to the QR mode;

[0027] The switching module is used to switch the working mode accordingly when the first restriction condition or the second restriction condition is met.

[0028] In a third aspect, the present application provides a control circuit for a switching converter, comprising:

[0029] A timer is used to feedback the switching converter voltage V at the beginning of each switching cycle. FB The first PFM time T corresponding to the first PFM time control curve PFML and the second PFM time control curve PFMR PFML and the second PFM time T PFMR The curve PFML is the feedback voltage V FB With the first PFM time T PFML The relationship curve of PFMR is the feedback voltage V FB The second PFM time T PFMR The curve PFMR is the hysteresis curve of the curve PFML, the same V FB The PFM time T corresponding to the voltage on the PFMR curve PFMR Greater than the corresponding PFM time T on the PFML curve PFML ;

[0030] A first logic gate combination circuit, used for judging whether a first restriction condition is met, and when the first restriction condition is met, the output logic value is flipped;

[0031] A second logic gate combination circuit, used for judging whether a second restriction condition is met, and when the second restriction condition is met, the output logic value is flipped;

[0032] A mode determination circuit is used to output a first mode control signal when the output logic value of the first logic gate combination circuit is flipped, and output a second mode control signal when the output logic value of the second logic gate combination circuit is flipped, the first mode control signal is used to control the switching converter to switch from the QR mode to the CCM mode, and the second mode control signal is used to control the switching converter to switch from the CCM mode to the QR mode.

[0033] Optionally, the first logic gate combination circuit includes:

[0034] The comparator has its non-inverting input connected to the feedback voltage V FB , the reverse input terminal is connected to the feedback threshold voltage V th , V th Greater than the critical feedback voltage of CCM mode and QR mode; when V FB >V th When , the logic signal FB_OK output by the comparator is set to 1;

[0035] A first edge pulse module, wherein the input terminal of the first edge pulse module is connected to a timer at a PFM time T PFMR The logic signal pfmr is output when the timing is completed. When the rising edge of the logic signal pfmr arrives, the first edge pulse module generates a pulse signal PFMR_Pulse. The pulse width of the pulse signal PFMR_Pulse should be greater than the transmission delay from the delay pulse module to the mode determination circuit.

[0036] A delayed pulse module, wherein the input terminal of the delayed pulse module is connected to the pulse signal PFMR_Pulse and the valley signal Valley_Pluse, and the delayed pulse module starts timing from the rising edge of the pulse signal PFMR_Pulse, and if the valley signal Valley_Pulse is not received during the timing period △t, a narrow pulse signal QR_Timeout is output, wherein △t is greater than 1 / 2 of the free resonance period;

[0037] A first AND gate, wherein the input end of the first AND gate is connected to a narrow pulse signal QR_Timeout and a logic signal FB_OK. When the narrow pulse signal QR_Timeout is received and the logic signal FB_OK is set to 1, the logic signal Set output by the first AND gate is set to 1; otherwise, the logic signal Set is set to 0. The logic signal Set is connected to a mode determination circuit.

[0038] Optionally, the second logic gate combination circuit includes:

[0039] A second AND gate, wherein the input terminal of the second AND gate is connected to the valley bottom signal Valley_Pluse and the timer at the PFM time T PFMLThe logic signal pfml output when the timing is completed, when the logic signal pfml is set to 1 and the valley signal Valley_Pluse is received, the logic signal QR_Set output by the second AND gate is set to 1, otherwise, the logic signal QR_Set is set to 0;

[0040] The edge negative pulse module, the input terminal mode of the edge negative pulse module determines the logic signal CCM output by the circuit when the output logic value of the first logic gate combination circuit is flipped, when the rising edge of the logic signal CCM arrives, the second edge negative pulse module outputs a pulse width of the time threshold T blank Negative pulse signal CCM_Blank;

[0041] A third AND gate, wherein the input end of the third AND gate is connected to a negative pulse signal CCM_Blank and a logic signal QR_Set. When the falling edge of the negative pulse signal CCM_Blank arrives and the logic signal QR_Set is set to 1, the logic signal Rst output by the third AND gate is set to 1; otherwise, the logic signal Rst output by the third AND gate is set to 0, and the logic signal Rst is connected to a mode determination circuit.

[0042] In a fourth aspect, the present application provides a chip, comprising: a processor and a communication interface, wherein the communication interface is coupled to the processor, and wherein the processor is used to run a program or instruction, and when the processor executes the program or instruction, the steps of the control method of the switching converter described in any one of the above are implemented.

[0043] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0044] The present application provides a control method, device, circuit and chip for a switching converter. In the present application, the curve PFMR is a hysteresis curve of the curve PFML: for the same V FB The second PFM time corresponding to the value on the curve PFMR is greater than the first PFM time corresponding to the value on the curve PFML; the curve PFMR controls the switching from the QR mode to the CCM mode, and the curve PFML controls the switching from the CCM mode to the QR mode. Therefore, based on the curve PFMR and the curve PFML, according to the current V FBand valley signal, to determine whether the switching converter meets the first restriction condition or the second restriction condition, the first restriction condition being used as the determination condition for the converter to switch from the QR mode to the CCM mode, and the second restriction condition being used as the determination condition for the converter to switch from the CCM mode to the QR mode; when the first restriction condition or the second restriction condition is met, the corresponding working mode switching is performed to ensure the reliability of the switching between the QR mode and the CCM mode, and to avoid the problem of repeated switching between the QR mode and the CCM mode when the first restriction condition or the second restriction condition is not met.

[0045] In addition, the present application uses the same timer to calculate the current V based on the curve PFMR and the curve PFML. FB The corresponding PFM time T PFML and T PFMR For timing, that is, using one hardware to implement the curve PFMR and the curve PFML, the problem of difficulty in ensuring the deviation consistency of using two hardware modules is avoided, making the logic implementation simpler and simplifying the circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 This is a schematic diagram of a working mode of a switching converter in one embodiment of the present application;

[0048] Figure 2 This is a schematic diagram of the structure of a control system of a switching converter in one embodiment of the present application;

[0049] Figure 3 A schematic flow chart of a control method for a switching converter provided in one embodiment of the present application;

[0050] Figure 4 A schematic diagram of a PFM time control curve provided in an embodiment of the present application;

[0051] Figure 5 A schematic diagram of functional modules of a control device for a switching converter provided in another embodiment of the present application;

[0052] Figure 6 A schematic diagram of functional modules of a control circuit of a switching converter provided by another embodiment of the present application;

[0053] Figure 7A circuit connection diagram of a control circuit of a switching converter provided in another embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] Figure 2 The schematic diagram of the structure of a control system of a switching converter provided in an embodiment of the present application is shown. The control system of the switching converter includes: an input voltage V connected in sequence in an energy transmission loop in , filter 1, rectifier circuit 2, transformer 3, freewheeling circuit 4, output capacitor C1, feedback network 5 connected to the secondary side of the transformer 3, controller 6 connected to the feedback network 5 and the filter 1, auxiliary winding network 7 connected to the controller 6 after being coupled to the secondary side of the transformer 3, switch Q1 connected to the controller 6 and the primary side of the transformer 3, current sampler 8 connected between the switch Q1 and the controller 6, and high-voltage starting circuit 9 connected between the filter 1 and the controller 6.

[0056] The controller 6 is used to execute the steps of a control method for a switching converter provided in some embodiments of the present application. in After filtering by filter 1, rectification by rectifier circuit 2, conversion by transformer 3, freewheeling circuit 4, and processing by output capacitor C1, the output voltage V is obtained. out , output voltage V out The output feedback voltage V is processed by the feedback network 5. FB Give the controller 6, V FB Feedback V out The error from the expected value. The input voltage V in After passing through the filter 1 and the high-voltage startup circuit 9, the startup current is provided to the controller 6. The auxiliary winding network 7 supplies power to the VDD of the controller 6, and provides output voltage information, valley information, secondary demagnetization of the transformer 3 and other information to the controller 6. The current sampler 8 samples the primary current I of the transformer 3. PRI to the controller 6, and the controller 6 generates a voltage V according to the feedback voltage V FB and a valley signal, and adopting a control method for a switching converter provided in an embodiment of the present application to control the switching converter to switch between a CCM mode and a QR mode.

[0057] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0058] In an exemplary embodiment, Figure 3 As shown, a control method for a switching converter is provided, comprising the following steps 201 to 203. Among them:

[0059] Step 201, obtaining a first PFM time control curve PFML and a second PFM time control curve PFMR, wherein the curve PFML is a feedback voltage V FB With the first PFM time T PFML The relationship curve of PFMR is the feedback voltage V FB The second PFM time T PFML The curve PFMR is the hysteresis curve of the curve PFML, that is, the same V FB The PFM time T corresponding to the value on the PFMR curve PFMR Greater than the corresponding PFM time T on the PFML curve PFML .

[0060] In the embodiment of the present application, the curve PFMR is used to control the switch from QR mode to CCM mode, and the curve PFML is used to control the switch from CCM mode to QR mode. The QR mode is an operating mode in which the switching converter is turned on at the resonance valley of the drain-source voltage of the switch Q1 connected to the primary side of the transformer. When the CCM mode is switched to the QR mode, the valley pulse of the first valley will be detected. Specifically, the first half of the curve PFMR is used in the QR mode and V FB In [V B ,V A ] range, the number of conduction valleys is reduced and the switching frequency is increased. B is the minimum feedback voltage in QR mode, V A is the PFM time T on the PFMR curve PFMR = ... FB Greater than V A The first half of the curve PFML is used for the QR mode and V FB In [V B ,V A ] range, the number of conduction valleys increases, the switching period increases, and the switching frequency decreases, thereby realizing the switching frequency reduction control in the QR mode. In the second half of the curve PFML, as VFB Further increase, PFM time T PFML Maintain T Lmin , used to coordinate the fixed switching frequency control in CCM mode. The critical point AL between the first half and the second half of the curve PFML is used to control the switch from CCM mode to QR mode. The feedback voltage V on the curve PFML FB The corresponding PFM time starts from the switch-on moment (the start of the switching cycle), and the timing duration is the current feedback voltage V FB The corresponding PFM time T on the curve PFML PFML , the curve PFMR feedback voltage V FB The corresponding PFM time starts from the switch-on moment (the start of the switching cycle), and the timing duration is the current feedback voltage V FB The corresponding PFM time T on the PFMR curve PFMR Each V FB The corresponding PFM time T PFML , T PFMR Can be built on simulation software Figure 2 The control system of the switching converter shown is confirmed by simulation iterations.

[0061] like Figure 4 As shown, the slope of each point in the first half of the curve PFML and the curve PFMR is negative, and the corresponding V FB In [V B ,V A ]. FB Less than V B When the switching converter enters the burst mode, T PFML and T PFMR The longest, to achieve the burst mode fixed frequency switching action control. FB Greater than V B Enter QR mode, T PFML and T PFMR becomes shorter, according to V FB The corresponding T PFML or T PFMR Control the switching frequency to achieve the variable frequency switching action control of QR mode. FB As V FB The corresponding T PFMR The number of conduction valleys of the control switch converter is reduced, and the switching frequency is increased in the QR mode. FB When it continues to decrease, according to V FB The corresponding T PFMLThe number of conduction valleys of the control switch converter is increased to achieve the switching frequency reduction control in the QR mode. The second half of the curves PFML and PFMR is a straight line segment with a slope of zero. The inflection point between the first half and the second half of the curve PFML is the first critical point AL, and the voltage corresponding to the first critical point AL is V A , the corresponding T PFML is the first minimum time T Lmin The inflection point between the first half and the second half of the curve PFMR is the second critical point AR, and the voltage corresponding to the second critical point AR is V A , the corresponding T PFMR The second minimum time T Rmin .

[0062] Step 202: Based on the curve PFMR or the curve PFML, according to the current V FB and a valley signal to determine whether the switching converter satisfies the first restriction condition or the second restriction condition; the first restriction condition is the judgment condition for the converter to switch from the QR mode to the CCM mode, that is, whether the actual working state of the switching converter satisfies the judgment condition for reliable switching into the CCM mode; the second restriction condition is the judgment condition for the converter to switch from the CCM mode to the QR mode, that is, whether the actual working state of the switching converter satisfies the judgment condition for reliable switching into the QR mode; the valley signal refers to the valley detection signal correspondingly generated when the drain-source voltage of the switch Q1 of the switching converter oscillates to the valley during the free resonance period.

[0063] Step 203: When the first restriction condition or the second restriction condition is met, corresponding working mode switching is implemented.

[0064] In the embodiment of the present application, when the first restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFMR PFMR , controls the end position change of the current switching cycle of the switching converter, that is, the start time change of the next switching cycle (that is, switching from the first valley of the current switching cycle to the PFM time T PFMR When the time after △t time is reached, the next switching cycle is entered), thereby switching from QR mode to CCM mode. After entering CCM mode, compared with QR mode, the switching cycle is reduced and the switching frequency is increased. After switching to CCM mode, every PFM time T PFMR (T Rmin ) timing arrives, the switching converter immediately enters the next switching cycle, thereby realizing the fixed-frequency switching action. When the second restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFML PFML, control the switch Q1 of the switching converter to turn on at the first valley bottom of the current switching cycle, realize the end position change of the current switching cycle (i.e., the start position change of the next switching cycle), and switch the switching converter from CCM mode to QR mode. After entering the QR mode, compared with the CCM mode, the switching cycle increases and the switching frequency decreases. The first valley bottom refers to the first valley bottom of the drain-source terminal voltage of the switching converter Q1.

[0065] By implementing the above-mentioned steps 201 to 203, the corresponding working mode switching is performed only when the first restriction condition or the second restriction condition is met, so as to ensure the reliability of the switching between the QR mode and the CCM mode and avoid the problem of repeated switching between the QR mode and the CCM mode when the first restriction condition or the second restriction condition is not met.

[0066] As an optional implementation, in order to avoid the problem of repeatedly entering and exiting the CCM mode, the step 202, before determining whether the first restriction condition is met, further includes:

[0067] Based on the curve PFMR and the curve PFML, determine the current V FB The corresponding PFM time T PFML and T PFMR At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR Timing is performed and a valley signal is detected during the timing period.

[0068] As an optional implementation, the first restriction condition includes at least one of a first condition and a second condition. The first condition includes: FB The corresponding T PFMR After the timing reaches △t, the valley signal is still not detected, and △t is greater than 1 / 2 free resonance period. The second condition includes: the current V FB Greater than the feedback voltage threshold V th , V th Greater than the critical feedback voltage V in CCM and QR modes A +△V FB , where the feedback voltage V A The corresponding PFM time T on the PFMR curve PFMR It is exactly equal to the transformer demagnetization time plus 1 / 2 free resonance cycle time, △V FB The feedback voltage is V A When the transformer demagnetization time continues to increase, the feedback voltage change caused by 1 / 2 free oscillation period.

[0069] In the embodiment of the present application, when V FBIncrease to V A When the PFM time on the PFMR curve decreases to the minimum value T Rmin ; The corresponding PFM time on the PFML curve decreases to the minimum value T Lmin At this time, the first valley of the system is just at T Rmin When the timing reaches the arrival time, the switching cycle includes 1 / 2 of the free resonance cycle. Therefore, on this basis, the first and second conditions are defined to effectively reduce the repeated switching between modes. And the larger the △t time, the deeper the CCM depth when the switching converter switches into the CCM mode, and the feedback voltage V FB The larger the value, the higher the resistance of V FB The stronger the jitter capability. FB The larger the switch, the deeper the CCM depth when the converter switches to CCM mode. At this time, the system switches to CCM and resists V FB The stronger the jitter capability.

[0070] In the embodiment of the present application, satisfying at least one of the first condition and the second condition means satisfying the first restriction condition.

[0071] As an optional implementation, in order to further avoid the problem of repeatedly entering and exiting the CCM mode, the step 202, before determining whether the second restriction condition is met, further includes:

[0072] Based on the curve PFMR and the curve PFML, determine the current V FB The corresponding PFM time T PFML and T PFMR At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR Timing is performed, and the valley signal is detected during the timing period; when the switching converter switches from the QR mode to the CCM mode, the time after switching to the CCM mode needs to be timed.

[0073] In the embodiment of the present application, the second limiting condition includes a third condition and a fourth condition. The third condition includes: FB The corresponding PFM time T PFML After the timing is reached and the PFM time T PFMR Before the timing is reached, the valley signal is detected to ensure that the actual working state of the switching converter meets the requirements for reliable switching into the QR mode. The fourth condition includes: T after the switching converter switches to the CCM mode blank The system is not allowed to switch to QR mode within the time threshold.

[0074] In the embodiment of the present application, when V FB Reduce to V AWhen the system's first valley is at T Rmin When the timing reaches the arrival time, the switching cycle contains 1 / 2 free resonance cycle, and the system is in DCM state. FB Continue to decrease until it is less than V A , then the third condition makes the switch converter detect the valley signal after the PFML timing is reached but before the PFMR timing is reached, and the switch converter can be switched to the QR mode naturally. The first condition for the switch converter to enter the CCM mode includes the first condition, that is, T PFMR If the valley signal is not detected within the △t time after the timing is reached, the condition for exiting the CCM mode is the third condition, that is, T PFML After the timing is reached and T PFMR The valley signal is detected before the timing is reached, so there is at least a time delay of △t when entering and exiting the CCM mode, which ensures that the system smoothly transitions from the CCM mode to the QR mode, further reducing the repeated switching between modes. In addition, when the switching converter just switches to the CCM mode, there is a sudden change in the switching cycle, and the system transfer energy increases stepwise, resulting in V FB The system then exits the CCM mode. In the embodiment of the present application, after the switching converter switches to the CCM mode, the T blank The system is not allowed to switch to QR mode within the time limit, so as to avoid the phenomenon of repeatedly entering and exiting CCM mode caused by the above factors. Therefore, after entering CCM mode, blank The judgment result of the third condition is shielded within the time period, so that the switching converter is always maintained in the CCM mode.

[0075] from Figure 4 It can be seen from the PFML curve that when V FB Reduce to V A , the system will transition from CCM state to QR state. The specific control process is: as the load decreases, V FB Gradually decreases, when V FB Reduce to V A When the system's first valley is at T Rmin When the timing arrives, the switching cycle contains 1 / 2 free resonance cycle, and the system is in DCM state. FB Continue to decrease until it is less than V A , the switching converter will detect the valley signal Valley_Pulse after the PFML timing is reached but before the PFMR timing is reached. At this time, the switching converter naturally switches to the QR mode by combining the PFML logic signal and the ValleyPulse signal.

[0076] Assuming that the system initially operates in QR mode (first valley conduction mode), the valley pulse signal of the first valley of the system will arrive before the PFMR timing arrives. As the system load increases, the feedback voltage V FB As the voltage increases, the transformer needs longer time to demagnetize. Then the valley pulse of the first valley of the system will move backward compared to the starting point of the switching cycle. Figure 4 It can be seen from the PFMR curve that as V FB The increase of PFMR time decreases, that is, the time when PFMR timing arrives will move forward compared to the starting point of the switching cycle. FB Increase to V FB =V A When the system is in DCM mode, the arrival time of the valley signal ValleyPulse of the first valley is exactly the same as the arrival time of the PFMR time. When the feedback voltage further increases to V FB >V A , the demagnetization end time required by the transformer will be further increased, and the PFMR time will be further reduced. Then, the valley pulse signal of the first valley will not be detected before the PFMR time is reached, which means that the system is about to enter the CCM state. However, if the system immediately switches to the CCM mode at this time, the system is likely to repeatedly enter and exit the CCM mode due to feedback voltage fluctuations. Based on this, the present application sets the first condition and the second condition to avoid the problem of the system repeatedly entering and exiting the CCM mode.

[0077] As an optional implementation, in order to improve the control effect, at the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR When timing, the same timer is used to measure the current V FB The corresponding PFM time T PFML and T PFMR Keep timing.

[0078] The traditional technology uses the PFM time control curve of the switching converter as the first curve, the first curve realizes the variable frequency control of the QR mode, and designs a second curve independent of the PFM time control curve, the second curve realizes the fixed frequency control of the CCM mode, and uses two relatively independent hardware to realize the first curve and the second curve. However, since the deviation consistency of the two hardware is difficult to ensure, the deviation consistency of the first curve and the second curve is difficult to ensure, which leads to unsatisfactory switching control effect between the CCM mode and the QR mode. The present application uses the same timer to control the current V FB The corresponding PFM time T PFML and TPFMR For timing, that is, using one hardware to implement the curve PFMR and the curve PFML, the problem of difficulty in ensuring the deviation consistency of using two hardware modules is avoided, making the logic implementation simpler and simplifying the circuit design.

[0079] As an optional implementation, when the first restriction condition and the second restriction condition are not satisfied at the same time, based on the curve PFMR or the curve PFML, according to the current V FB and valley signal, to control the switching converter to maintain in the corresponding working mode, the specific control process is:

[0080] When the first valley is turned on in the QR mode and the first restriction condition is not met, if V FB Increase, at this time the converter balances the energy demand of the system output by increasing the excitation current of the transformer. FB Increase, corresponding to T PFMR The voltage decreases, but the switch Q1 of the switching converter is still turned on at the first valley bottom, that is, the QR mode is maintained;

[0081] When the first valley is turned on in the QR mode and the first restriction condition is not met, if V FB Reduced, at this time the converter balances the energy demand of the system output by reducing the excitation current of the transformer. FB decreases, the corresponding T PFMR Increases, but the switch Q1 of the switching converter is still turned on at the first valley bottom, that is, the QR mode is maintained;

[0082] In CCM mode, when the second restriction condition is not met, T Rmin That is the current switching cycle. When T Rmin When the timing is reached, the switching converter is controlled to immediately enter the next switching cycle, so that the switching converter maintains a fixed-frequency working mode in the CCM mode.

[0083] Based on the same inventive concept, the embodiment of the present application also provides a control device for a switching converter for implementing the control method for the switching converter involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the control device for one or more switching converters provided below can refer to the limitations of the control method for the switching converter above, and will not be repeated here.

[0084] In an exemplary embodiment, Figure 5 As shown, a control device 30 of a switching converter is provided, comprising:

[0085] The control curve module 301 is used to obtain a first PFM time control curve PFML and a second PFM time control curve PFMR, wherein the curve PFML is a feedback voltage V FB With the first PFM time T PFML The relationship curve of PFMR is the feedback voltage V FB The second PFM time T PFMR The curve PFMR is the hysteresis curve of the curve PFML, and the same V FB The corresponding PFM time T on the PFMR curve PFMR Greater than the corresponding PFM time T on the PFML curve PFML ; The curve PFMR is used to coordinate the control of switching from the QR mode to the CCM mode, and the curve PFML is used to coordinate the control of switching from the CCM mode to the QR mode;

[0086] The judgment module 302 is used to determine the current V FB and valley signal, to determine whether the first restriction condition or the second restriction condition is satisfied; the first restriction condition is a determination condition for the converter to switch from the QR mode to the CCM mode; the second restriction condition is a determination condition for the converter to switch from the CCM mode to the QR mode;

[0087] The switching module 303 is used to switch the corresponding working mode when the first restriction condition or the second restriction condition is met.

[0088] As an optional implementation manner, the judging module 302 is further configured to:

[0089] Before determining whether the first restriction condition is met, the method further includes:

[0090] Based on the curve PFMR and the curve PFML, determine the current V FB The corresponding PFM time T PFML and T PFMR At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR Timing is performed and a valley signal is detected during the timing period.

[0091] The first limiting condition includes at least one of a first condition and a second condition. The first condition includes: FB The corresponding T PFMR After the timing reaches △t, no valley signal is detected, where △t is greater than 1 / 2 of the free resonance period. The second condition includes: the current V FBGreater than the feedback voltage threshold V th , V th The critical feedback voltage of the CCM mode and the QR mode is greater than the critical feedback voltage of the CCM mode and the QR mode. The relevant introduction of the critical feedback voltage of the CCM mode and the QR mode is described in the above method embodiment, which will not be repeated here. The time △t is the set delay, and the feedback voltage threshold V th is the set threshold value, which can be iteratively designed through simulation and other methods to obtain the time △t and / or feedback voltage threshold V corresponding to the optimal control effect under different operating frequency, input voltage, output voltage and output power. th .

[0092] In the embodiment of the present application, satisfying at least one of the first condition and the second condition means satisfying the first restriction condition.

[0093] As an optional implementation manner, the judging module 302 is further configured to:

[0094] Before determining whether the second restriction condition is met, based on the curve PFMR and the curve PFML, determine the current V FB The corresponding PFM time T PFML and T PFMR At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR The timing is performed, and the valley signal is detected during the timing. When the switching converter switches from the QR mode to the CCM mode, it is necessary to time the time after switching to the CCM mode. The second restriction condition includes the third condition and the fourth condition. The third condition includes: at the current V FB The corresponding PFM time T PFML After the timing is reached and the PFM time T PFMR Before the timing is reached, a valley signal is detected. The fourth condition includes: after the switching converter switches to the CCM mode, T blank The system is not allowed to switch to QR mode within the time threshold.

[0095] As an optional implementation manner, the switching module 303 is further configured to:

[0096] When the first restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFMR PFMR , controls the end position change of the current switching cycle of the switching converter, that is, the start time change of the next switching cycle (that is, switching from the first valley of the current switching cycle to the PFM time T PFMRWhen the time after △t time is reached, the next switching cycle is entered), thereby switching from QR mode to CCM mode. When the second restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFML PFML , control the switch Q1 of the switching converter to turn on at the first valley bottom of the current switching cycle, realize the end position change of the current switching cycle (that is, the start position change of the next switching cycle), and switch the switching converter from CCM mode to QR mode.

[0097] As an optional implementation, the control device 30 of the switching converter further includes:

[0098] The transmission control module 304 is used to, when the first restriction condition and the second restriction condition are not satisfied at the same time, based on the curve PFMR or the curve PFML according to the current V FB and valley signal, to control the switching converter to maintain in the corresponding working mode, the specific control process is:

[0099] When the first valley is turned on in the QR mode and the first restriction condition is not met, if V FB Increase, at this time the converter balances the energy demand of the system output by increasing the excitation current of the transformer. FB Increase, corresponding to T PFMR The voltage decreases, but the switch Q1 of the switching converter is still turned on at the first valley bottom, that is, the QR mode is maintained;

[0100] When the first valley is turned on in the QR mode and the first restriction condition is not met, if V FB Reduced, at this time the converter balances the energy demand of the system output by reducing the excitation current of the transformer. FB decreases, the corresponding T PFMR Increases, but the switch Q1 of the switching converter is still turned on at the first valley bottom, that is, the QR mode is maintained;

[0101] In CCM mode, when the second restriction condition is not met, T Rmin That is the current switching cycle. When T Rmin When the timing is reached, the switching converter is controlled to immediately enter the next switching cycle, so that the switching converter maintains a fixed-frequency working mode in the CCM mode.

[0102] Based on the same inventive concept, the embodiment of the present application also provides a control circuit of a switching converter for implementing the control method of the switching converter involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the control circuit embodiments of one or more switching converters provided below can refer to the limitations of the control method of the switching converter above, and will not be repeated here.

[0103] In an exemplary embodiment, a control circuit of a switching converter is provided, such as Figure 6 As shown, including:

[0104] The timer 401 is used to check the feedback voltage V of the switching converter at the beginning of each switching cycle (the switch is turned on). FB The first PFM time T corresponding to the first PFM time control curve PFML and the second PFM time control curve PFMR PFML and the second PFM time T PFMR Timing is performed; the relevant introduction of the curve PFMR and the curve PFML can be found in the records of the above embodiment, which will not be repeated here;

[0105] The first logic gate combination circuit 402 is used to determine whether the first restriction condition is met, and the first restriction condition is a determination condition for the converter to switch from the QR mode to the CCM mode; when the first restriction condition is met, the output logic value is flipped; for example, when the first restriction condition is not met, the output logic value of the first logic gate combination circuit 402 is 0, and flips to 1 after the first restriction condition is met; for another example, when the first restriction condition is not met, the output logic value of the first logic gate combination circuit 402 is 1, and flips to 0 after the first restriction condition is met; no specific limitation is made here, and it can be set according to actual needs;

[0106] The second logic gate combination circuit 403 is used to determine whether the second restriction condition is met, and the second restriction condition is a determination condition for the converter to switch from the CCM mode to the QR mode; when the second restriction condition is met, the output logic value is flipped; for example, when the first restriction condition is not met, the output logic value of the second logic gate combination circuit 403 is 0, and flips to 1 after the first restriction condition is met; for example, when the first restriction condition is not met, the output logic value of the second logic gate combination circuit 403 is 1, and flips to 0 after the first restriction condition is met; no specific limitation is made here, and it can be set according to actual needs;

[0107] The mode determination circuit 404 is used to output a first mode control signal when the output logic value of the first logic gate combination circuit is flipped, and output a second mode control signal when the output logic value of the second logic gate combination circuit is flipped, wherein the first mode control signal is used to control the switching converter to switch from the QR mode to the CCM mode, and the second mode control signal is used to control the switching converter to switch from the CCM mode to the QR mode.

[0108] In the embodiment of the present application, when the first restriction condition is met in the QR mode, the switching converter is controlled to switch from the QR mode to the CCM mode, and according to the current V FB The corresponding T on the PFMR curve PFMR The switching frequency of the switching converter is controlled to increase, so that the switching converter performs a fixed-frequency switching operation at the increased switching frequency in the CCM mode. When the second restriction condition is met in the CCM mode, the switching converter is controlled to turn on at the first valley bottom and enter the next switching cycle, so as to realize a reliable switch from the CCM mode to the QR mode.

[0109] As an optional implementation manner, the mode determination circuit 404 is further configured to:

[0110] When the first restriction condition and the second restriction condition are not satisfied at the same time, the output remains unchanged to control the switching converter to maintain the corresponding working mode.

[0111] In the embodiment of the present application, when the first valley is turned on in the QR mode and the first restriction condition is not met, if V FB When V increases, the converter balances the energy demand of the system input and output by increasing the excitation current of the transformer. FB Increase, corresponding to T PFMR The system still maintains conduction at the first valley bottom, i.e., QR mode. FB The corresponding T on the PFMR curve PFMR The switching frequency of the switching converter is controlled to increase, and the switch of the switching converter is controlled to be turned on at the first valley bottom, so that the switching converter continues to use the increased switching frequency to transfer energy in the QR mode. When the first valley bottom is turned on in the QR mode, and the first restriction condition is not met, if V FB When V FB decreases, the corresponding T PFMR increases, but the system still maintains conduction at the first valley bottom, that is, QR mode. FB The corresponding T on the PFML curve PFMLThe switching frequency of the switching converter is controlled to decrease, and the switch of the switching converter is controlled to be turned on at the first valley bottom, so that the switching converter continues to use the reduced switching frequency to perform energy transmission in the QR mode. In the CCM mode, when the second restriction condition is not met, T Rmin That is the current switching cycle. When T Rmin When the timing is reached, the switching converter is controlled to immediately enter the next switching cycle, so that the switching converter maintains a fixed-frequency working mode in the CCM mode.

[0112] As an optional implementation, the input terminal of the timer 401 is connected to V FB and a pulse signal DRV_Set for triggering the switch Q1 of the switching converter to turn on, the timer 401 is pressed Figure 4 The middle curve PFML and curve PFMR are V FB The corresponding T PFML 、T PFMR Keep timing.

[0113] In the embodiment of the present application, in T PFMR When the timing is completed, the logic signal pfmr output by the timer 401 is set to 1, and when the rising edge of the pulse signal DRV_Set arrives, the logic signal pfmr output by the timer 401 is set to 0. PFML When the timing is completed, the logic signal pfml output by the timer 401 is set to 1, and when the rising edge of the pulse signal DRV_Set arrives, the logic signal pfml output by the timer 401 is set to 0.

[0114] As an optional implementation, the first restriction condition includes a first condition. The first logic gate combination circuit 402 includes:

[0115] A first edge pulse module, wherein an input terminal of the first edge pulse module is connected to a logic signal pfmr, and when a rising edge of the logic signal pfmr arrives, the first edge pulse module generates a pulse signal PFMR_Pulse, and a pulse width of the pulse signal PFMR_Pulse should be greater than a transmission delay from the delay pulse module to the mode determination circuit;

[0116] A delayed pulse module, the input end of which is connected to the pulse signal PFMR_Pulse and the valley signal Valley_Pluse. The delayed pulse module starts timing from the rising edge of the pulse signal PFMR_Pulse, and if the valley signal Valley_Pulse is not received during the timing period △t, a narrow pulse signal QR_Timeout is output. The pulse signal QR_Timeout is connected to the mode determination circuit 404.

[0117] As an optional implementation, the first restriction condition includes the second condition. The first logic gate combination circuit 402 includes:

[0118] The comparator has its non-inverting input connected to the feedback voltage V FB , the reverse input terminal is connected to a comparison power supply, the voltage of the comparison power supply is equal to the feedback voltage threshold V th , V th is greater than the critical feedback voltage of the CCM mode and the QR mode. The relevant introduction of the critical feedback voltage of the CCM mode and the QR mode is described in detail in the above method embodiment, which will not be repeated here; when V FB >V th When the comparator outputs the logic signal FB_OK, the comparator outputs the logic signal FB_OK set to 1; otherwise, the comparator outputs the logic signal FB_OK set to 0.

[0119] As an optional implementation manner, the first mode condition includes a first condition and a second condition, and the first logic gate combination circuit 402 includes:

[0120] The comparator has its non-inverting input connected to the feedback voltage V FB , the reverse input terminal is connected to the feedback threshold voltage V th ; When V FB >V th When the comparator outputs a logic signal FB_OK, the comparator outputs a logic signal FB_OK set to 1; otherwise, the comparator outputs a logic signal FB_OK set to 0;

[0121] A first edge pulse module, wherein an input terminal of the first edge pulse module is connected to a logic signal pfmr, and when a rising edge of the logic signal pfmr arrives, the first edge pulse module generates a pulse signal PFMR_Pulse, and a pulse width of the pulse signal PFMR_Pulse should be greater than a transmission delay from the delay pulse module to the mode determination circuit;

[0122] A delayed pulse module, wherein the input terminal of the delayed pulse module is connected to the pulse signal PFMR_Pulse and the valley signal Valley_Pluse, and the delayed pulse module starts timing from the rising edge of the pulse signal PFMR_Pulse, and if the valley signal Valley_Pulse is not received during the timing period △t, the delayed pulse module outputs a narrow pulse signal QR_Timeout;

[0123] A first AND gate, wherein the input end of the first AND gate is connected to the narrow pulse signal QR_Timeout and the logic signal FB_OK. When the narrow pulse signal QR_Timeout is received and the logic signal FB_OK is set to 1, the logic signal Set output by the first AND gate is set to 1, otherwise, the logic signal Set is set to 0, and the logic signal Set is connected to the mode determination circuit 404.

[0124] As an optional implementation, the second logic gate combination circuit 403 includes:

[0125] a second AND gate, wherein an input terminal of the second AND gate is connected to the logic signal pfml and the valley signal Valley_Pluse, and when the logic signal pfml is set to 1 and the valley signal Valley_Pluse is received, the logic signal QR_Set output by the second AND gate is set to 1, otherwise, the logic signal QR_Set is set to 0;

[0126] The edge negative pulse module, the input terminal mode of the edge negative pulse module determines the logic signal CCM output by the circuit when the output logic value of the first logic gate combination circuit is flipped, when the rising edge of the logic signal CCM arrives, the second edge negative pulse module outputs a pulse width of the time threshold T blank Negative pulse signal CCM_Blank;

[0127] A third AND gate, wherein the input end of the third AND gate is connected to the negative pulse signal CCM_Blank and the logic signal QR_Set. When the falling edge of the negative pulse signal CCM_Blank arrives and the logic signal QR_Set is set to 1, the logic signal Rst output by the third AND gate is set to 1; otherwise, the logic signal Rst output by the third AND gate is set to 0, and the logic signal Rst is connected to the mode determination circuit 404.

[0128] As an optional implementation, the mode determination circuit 404 includes:

[0129] An SR trigger, wherein the S input terminal of the SR trigger is connected to the output signal of the first logic gate combination circuit, the R input terminal of the SR trigger is connected to the output signal of the second logic gate combination circuit, the Q terminal of the SR trigger is connected to the first mode control circuit, and the QN terminal of the SR trigger is connected to the second mode control circuit. When the output signal of the first logic gate combination circuit is set to 1 and the output signal of the second logic gate combination circuit is set to 0, the logic signal CCM output from the Q terminal of the SR trigger is set to 1, and the logic signal QR output from the QN terminal of the SR trigger is set to 0. When the logic signal CCM is set to 1, a corresponding pulse signal DRV_Set is generated, so that the switching converter switches from the QR mode to the CCM mode. When the logic signal QR is set to 1, a corresponding pulse signal DRV_Set is generated, so that the switching converter switches from the CCM mode to the QR mode. When the output signal of the first logic gate combination circuit is set to 0 and the output signal of the second logic gate combination circuit is set to 1, the logic signal CCM output from the Q terminal of the SR trigger is set to 0, and the logic signal QR output from the QN terminal of the SR trigger is set to 1. When the output signal of the first logic gate combination circuit is set to 0 and the output signal of the second logic gate combination circuit is set to 0, the output of the SR flip-flop remains unchanged.

[0130] As an optional implementation, the first limiting condition includes a first condition and a second condition, and the second limiting condition includes a third condition and a fourth condition. The first logic gate combination circuit 402 includes a comparator, a first edge pulse module, a delay pulse module and a first AND gate, the second logic gate combination circuit 403 includes a second AND gate, an edge negative pulse module and a third AND gate, and the mode determination circuit 404 includes an SR trigger. Figure 7 As shown, the input terminal of the timer 401 is connected to V FB and a pulse signal DRV_Set for triggering the switch Q1 of the switching converter to turn on, the timer 401 is pressed Figure 3 The middle curve PFML and curve PFMR are V FB The corresponding T PFML 、T PFMR Timing. PFMR When the timing is completed, the logic signal pfmr output by the timer 401 is set to 1, and when the rising edge of the pulse signal DRV_Set arrives, the logic signal pfmr output by the timer 401 is set to 0. PFML When the timing is completed, the logic signal pfml output by the timer 401 is set to 1, and when the rising edge of the pulse signal DRV_Set arrives, the logic signal pfml output by the timer 401 is set to 0. The same-direction input terminal of the comparator is connected to the feedback voltage V FB , the reverse input terminal is connected to the feedback threshold voltage V th ; When V FB >V thWhen the rising edge of the logic signal pfmr arrives, the logic signal FB_OK output by the comparator is set to 1; otherwise, the logic signal FB_OK output by the comparator is set to 0. The input terminal of the first edge pulse module is connected to the logic signal pfmr. When the rising edge of the logic signal pfmr arrives, the first edge pulse module generates a pulse signal PFMR_Pulse. The pulse width of the pulse signal PFMR_Pulse should be greater than the transmission delay from the delay pulse module input to the mode determination circuit. The input terminal of the delay pulse module is connected to the pulse signal PFMR_Pulse and the valley signal Valley_Pluse. The delay pulse module starts timing from the rising edge of the pulse signal PFMR_Pulse. If the timing is △t and the valley signal Valley_Pulse is not received during the timing, the narrow pulse signal QR_Timeout is output. The input terminal of the first AND gate is connected to the narrow pulse signal QR_Timeout and the logic signal FB_OK. When the narrow pulse signal QR_Timeout is received and the logic signal FB_OK is set to 1, the logic signal Set output by the second AND gate is set to 1, otherwise, the logic signal Set output by the first AND gate is set to 0. The input terminal of the second AND gate is connected to the logic signal pfml and the valley signal Valley_Pluse. When the logic signal pfml is set to 1 and the valley signal Valley_Pluse is received, the logic signal QR_Set output by the second AND gate is set to 1, otherwise, the logic signal QR_Set output by the second AND gate is set to 0. The input terminal of the edge negative pulse module is connected to the logic signal CCM. When the rising edge of the logic signal CCM arrives, the second edge negative pulse module outputs a negative pulse signal CCM_Blank with a pulse width of Tblank. The input terminal of the third AND gate is connected to the negative pulse signal CCM_Blank and the logic signal QR_Set. When the falling edge of the negative pulse signal CCM_Blank arrives and the logic signal QR_Set is set to 1, the logic signal Rst output by the third AND gate is set to 1, otherwise, the logic signal Rst output by the third AND gate is set to 0. The S input terminal of the SR trigger is connected to the logic signal Set, the R input terminal of the SR trigger is connected to the logic signal Rst, the Q terminal of the SR trigger is connected to the fourth AND gate, and the QN terminal of the SR trigger is connected to the valley lock control logic circuit. When the logic signal Set is set to 1 and the logic signal Rst is set to 0, the logic signal CCM output by the Q terminal of the SR trigger is set to 1, and the logic signal QR output by the QN terminal of the SR trigger is set to 0. When the logic signal Set is set to 0 and the logic signal Rst is set to 1, the logic signal CCM output by the Q terminal of the SR trigger is set to 0, and the logic signal QR output by the QN terminal of the SR trigger is set to 1. When the logic signal Set is set to 0 and the logic signal Rst is set to 0, the output of the SR trigger remains unchanged.

[0131] As an optional implementation manner, the control circuit of the switching converter further includes:

[0132] The first mode control circuit 405 is used for, upon receiving the first mode control signal, controlling the current V FB and valley signal, controlling the change in the starting time of the next switching cycle of the switching converter, so that the switching converter switches from the QR mode to the CCM mode.

[0133] As an optional implementation, Figure 7 As shown, the first mode control circuit 405 includes:

[0134] a second edge pulse module, wherein an input terminal of the second edge pulse module is connected to a logic signal CCM, and when a rising edge of the logic signal CCM arrives, the first edge pulse module generates a pulse signal CCM_ENT;

[0135] a fourth AND gate, wherein an input terminal of the fourth AND gate is connected to the logic signal CCM and the output signal of the first logic gate combination circuit, and when the logic signal CCM and the output signal of the first logic gate combination circuit are both set to 1, the fourth AND gate outputs the logic signal PEMR_INT;

[0136] An OR gate, wherein the input terminal of the OR gate is connected to the logic signal PEMR_INT and the logic signal PEMR_INT, and when at least one of the logic signal PEMR_INT and the logic signal PEMR_INT is set to 1, the OR gate outputs a pulse signal DRV_Set.

[0137] In an exemplary embodiment, a control chip of a switching converter is provided, and the control chip of the switching converter includes a processor, a memory, an input / output interface (I / O for short) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the control chip of the switching converter is used to provide computing and control capabilities. The memory of the control chip of the switching converter includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the control chip of the switching converter is used to store video tag processing data. The input / output interface of the control chip of the switching converter is used to exchange information between the processor and an external device. The communication interface of the control chip of the switching converter is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a control method of a switching converter is implemented.

[0138] Those skilled in the art will understand that the above-described structure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the control chip of the switching converter to which the scheme of the present application is applied. The specific control chip of the switching converter may include more or fewer components than those described above, or combine certain components, or have a different arrangement of components.

[0139] In an exemplary embodiment, a chip is also provided, including: a processor and a communication interface, wherein the communication interface is coupled to the processor, and wherein the processor is used to run a program or instruction, and the processor implements the steps of the above-mentioned method embodiments when executing the program or instruction.

[0140] In an exemplary embodiment, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0141] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0142] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0143] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0144] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0145] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A control method for a switching converter, characterized in that: The control method of the switching converter comprises: Obtain a first PFM time control curve PFML and a second PFM time control curve PFMR, wherein the curve PFML is a feedback voltage V FB With the first PFM time T PFML The relationship curve of PFMR is the feedback voltage V FB The second PFM time T PFMR The curve PFMR is the hysteresis curve of the curve PFML, the same V FB The PFM time T corresponding to the voltage on the PFMR curve PFMR Greater than the corresponding PFM time T on the PFML curve PFML ; Based on the curve PFMR and the curve PFML, according to the current V FB and valley signal, to determine whether the switching converter satisfies a first restriction condition or a second restriction condition; the first restriction condition is used as a determination condition for the converter to switch from the QR mode to the CCM mode; the second restriction condition is used as a determination condition for the converter to switch from the CCM mode to the QR mode; When the first restriction condition or the second restriction condition is met, the corresponding working mode switching is performed, specifically including: When the first restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFMR PFMR , controls the end position of the current switching cycle of the switching converter to switch from the first valley of the current switching cycle to the PFM time T PFMR When the time after △t time is reached, the next switching cycle is entered to switch from QR mode to CCM mode; When the second restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFML PFML , controlling the switch of the switching converter to be turned on at the first valley bottom of the current switching cycle, thereby switching from the CCM mode to the QR mode.

2. The control method of the switching converter according to claim 1, characterized in that: Before determining whether the first restriction condition is met, the method further includes: Based on the curve PFMR and the curve PFML, determine the current V FB The corresponding PFM time T PFML and T PFMR At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR Perform timing, and detect the valley bottom signal during the timing period; The first restriction condition includes at least one of a first condition and a second condition; The first condition includes: at the current V FB The corresponding T PFMR No valley signal is detected within the △t time after the timing is reached, where △t is greater than 1 / 2 of the free resonance period; The second condition includes: the current V FB Greater than the feedback voltage threshold V th , V th Greater than the critical feedback voltage of CCM mode and QR mode.

3. The control method of the switching converter according to claim 1 or 2, characterized in that: Before determining whether the second restriction condition is met, the method further includes: Based on the curve PFMR and the curve PFML, determine the current V FB The corresponding PFM time T PFML and T PFMR At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR Perform timing, and detect the valley signal during the timing period; when the switching converter switches from the QR mode to the CCM mode, it is necessary to time the time after switching to the CCM mode; The second restriction condition includes the third condition and the fourth condition; The third condition includes: at the current V FB The corresponding T PFML After the timing is reached and T PFMR Before the timing is reached, the valley signal is detected; The fourth condition includes: after the switching converter switches from the QR mode to the CCM mode, T blank Switching to QR mode is not allowed within the time threshold.

4. The control method of the switching converter according to claim 3, characterized in that: At the beginning of each switching cycle, the current V FB The corresponding PFM time T PFML and T PFMR When timing, the same timer is used to measure the current V FB The corresponding PFM time T PFML and T PFMR Keep timing.

5. A control device for a switching converter, characterized in that: The control device of the switching converter comprises: The control curve module obtains the first PFM time control curve PFML and the second PFM time control curve PFMR, wherein the curve PFML is the feedback voltage V FB With the first PFM time T PFML The relationship curve of PFMR is the feedback voltage V FB The second PFM time T PFMR The curve PFMR is the hysteresis curve of the curve PFML, the same V FB The PFM time T corresponding to the voltage on the PFMR curve PFMR Greater than the corresponding PFM time T on the PFML curve PFML ; A judgment module is used to determine the current V FB and valley signal, to determine whether the switching converter satisfies a first restriction condition or a second restriction condition; the first restriction condition is used as a determination condition for the converter to switch from the QR mode to the CCM mode; the second restriction condition is used as a determination condition for the converter to switch from the CCM mode to the QR mode; A switching module, used to switch the corresponding working mode when the first restriction condition or the second restriction condition is met, includes: When the first restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFMR PFMR , controls the end position of the current switching cycle of the switching converter to switch from the first valley of the current switching cycle to the PFM time T PFMR When the time after △t time is reached, the next switching cycle is entered to switch from QR mode to CCM mode; When the second restriction condition is met, according to the current V FB The PFM time T corresponding to the curve PFML PFML , controlling the switch of the switching converter to be turned on at the first valley bottom of the current switching cycle, thereby switching from the CCM mode to the QR mode.

6. A control circuit for a switching converter, characterized in that: The control circuit of the switching converter comprises: The timer is used to monitor the feedback voltage V of the switching converter at the beginning of each switching cycle. FB The first PFM time T corresponding to the first PFM time control curve PFML and the second PFM time control curve PFMR PFML and the second PFM time T PFMR The curve PFML is the feedback voltage V FB With the first PFM time T PFML The relationship curve of PFMR is the feedback voltage V FB The second PFM time T PFMR The curve PFMR is the hysteresis curve of the curve PFML, the same V FB The PFM time T corresponding to the voltage on the PFMR curve PFMR Greater than the corresponding PFM time T on the PFML curve PFML ; A first logic gate combination circuit, used for judging whether a first restriction condition is satisfied, wherein the first restriction condition is used as a judgment condition for the converter to switch from the QR mode to the CCM mode, and when the first restriction condition is satisfied, the output logic value is flipped; A second logic gate combination circuit is used to determine whether a second restriction condition is met, wherein the second restriction condition is used as a determination condition for the converter to switch from the CCM mode to the QR mode, and when the second restriction condition is met, the output logic value is flipped; A mode determination circuit, configured to output a first mode control signal when the output logic value of the first logic gate combination circuit is flipped, and to output a second mode control signal when the output logic value of the second logic gate combination circuit is flipped; wherein the first mode control signal is used to control the switching converter to switch from the QR mode to the CCM mode, specifically comprising: According to the current V FB The PFM time T corresponding to the curve PFMR PFMR , controls the end position of the current switching cycle of the switching converter to switch from the first valley bottom of the current switching cycle to T PFMR When the time after △t time is reached, the next switching cycle is entered to switch from QR mode to CCM mode; The second mode control signal is used to control the switching converter to switch from the CCM mode to the QR mode, specifically including: According to the current V FB The PFM time T corresponding to the curve PFML PFML , controlling the switch of the switching converter to be turned on at the first valley bottom of the current switching cycle, thereby switching from the CCM mode to the QR mode.

7. The control circuit of the switching converter according to claim 6, characterized in that: The first logic gate combination circuit comprises: The comparator has its non-inverting input connected to the feedback voltage V FB , the reverse input terminal is connected to the feedback threshold voltage V th , V th Greater than the critical feedback voltage of CCM mode and QR mode; when V FB >V th When , the logic signal FB_OK output by the comparator is set to 1; A first edge pulse module, wherein the input terminal of the first edge pulse module is connected to a timer at a PFM time T PFMR The logic signal pfmr is output when the timing is completed. When the rising edge of the logic signal pfmr arrives, the first edge pulse module generates a pulse signal PFMR_Pulse. The pulse width of the pulse signal PFMR_Pulse should be greater than the transmission delay from the delay pulse module to the mode determination circuit. A delayed pulse module, wherein the input terminal of the delayed pulse module is connected to the pulse signal PFMR_Pulse and the valley signal Valley_Pluse, and the delayed pulse module starts timing from the rising edge of the pulse signal PFMR_Pulse, and if the valley signal Valley_Pulse is not received during the timing period △t, a narrow pulse signal QR_Timeout is output, wherein △t is greater than 1 / 2 of the free resonance period; A first AND gate, wherein the input end of the first AND gate is connected to a narrow pulse signal QR_Timeout and a logic signal FB_OK. When the narrow pulse signal QR_Timeout is received and the logic signal FB_OK is set to 1, the logic signal Set output by the first AND gate is set to 1; otherwise, the logic signal Set is set to 0. The logic signal Set is connected to a mode determination circuit.

8. The control circuit of the switching converter according to claim 6, characterized in that: The second logic gate combination circuit comprises: A second AND gate, wherein the input terminal of the second AND gate is connected to the valley bottom signal Valley_Pluse and the timer at the PFM time T PFML The logic signal pfml output when the timing is completed, when the logic signal pfml is set to 1 and the valley signal Valley_Pluse is received, the logic signal QR_Set output by the second AND gate is set to 1, otherwise, the logic signal QR_Set is set to 0; The edge negative pulse module, the input terminal mode of the edge negative pulse module determines the logic signal CCM output by the circuit when the output logic value of the first logic gate combination circuit is flipped, and when the rising edge of the logic signal CCM arrives, the edge negative pulse module outputs a pulse width of the time threshold T blank Negative pulse signal CCM_Blank; A third AND gate, wherein the input end of the third AND gate is connected to a negative pulse signal CCM_Blank and a logic signal QR_Set. When the falling edge of the negative pulse signal CCM_Blank arrives and the logic signal QR_Set is set to 1, the logic signal Rst output by the third AND gate is set to 1; otherwise, the logic signal Rst output by the third AND gate is set to 0, and the logic signal Rst is connected to a mode determination circuit.

9. A chip, comprising: A processor and a communication interface, wherein the communication interface is coupled to the processor, and wherein the processor is used to run a program or an instruction, and when the processor executes the program or the instruction, the steps of the control method of the switching converter according to any one of claims 1 to 4 are implemented.

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