Negative pressure detection circuit

Abstract

The present invention discloses a negative voltage detection circuit, which includes: an enabling module, including a logic unit and a switch unit, wherein the logic unit is used to generate a first control signal and a second control signal based on a first input signal and a second input signal to control the switch unit to be in a first state or a second state; a comparison module, connected between a power supply voltage and a reference potential, and connected to the input voltage and the switch unit. When the switch unit is in a first state, the comparison module is not working; when the switch unit is in a second state, the comparison module compares the input voltage and the reference potential to generate a comparison signal. The present invention improves the accuracy of negative voltage detection through the logic unit, consumes no static current when negative voltage detection is not performed, and reduces the overall power consumption of the chip; the comparison module is almost unaffected by process angle and temperature, and completes fast transient response detection.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a negative voltage detection circuit. Background Art

[0002] With the rapid development of power devices in the field of integrated circuits, the design of switching circuits is increasingly moving towards high robustness, low power consumption and fast response.

[0003] In switching circuits, the gate of a power tube sometimes requires negative voltage to operate. To ensure sufficient drive capability without affecting the overall performance of the circuit, it is necessary to detect the gate voltage. To reduce costs and the chip's overall operating current, the static power consumption of this detection circuit must be as low as possible. Furthermore, some LDO chips also detect negative input voltage to enter special test modes for chip testing or other functional operations. During normal operation of some low-power LDOs, it is desirable for this detection circuit to consume no current.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a negative pressure detection circuit. Summary of the Invention

[0005] The purpose of the present invention is to provide a negative pressure detection circuit, which can solve the problems of low negative pressure detection accuracy, high static power consumption of the detection circuit, slow detection speed and large circuit area.

[0006] In order to achieve the above-mentioned purpose, the technical solution provided by one embodiment of the present invention is as follows:

[0007] A negative pressure detection circuit, comprising an enabling module, a comparing module and a shaping module; wherein,

[0008] an enabling module, comprising a logic unit and a switch unit, wherein the logic unit is configured to generate a first control signal and a second control signal according to a first input signal and a second input signal to control the switch unit to be in a first state or a second state;

[0009] The comparison module is connected between the power supply voltage and the reference potential, and is connected to the input voltage and the switch unit. When the switch unit is in a first state, the comparison module does not work. When the switch unit is in a second state, the comparison module compares the input voltage and the reference potential to generate a comparison signal.

[0010] In one or more embodiments of the present invention, the comparison module includes a first branch and a second branch; wherein,

[0011] The first branch includes a voltage dividing unit and a third transistor, the voltage dividing unit is connected between the input voltage and the power supply voltage, the voltage dividing unit includes a first voltage dividing node, a first end of the third transistor is connected to the first voltage dividing node, and a second end of the third transistor is connected to the voltage dividing unit;

[0012] The second branch includes a fourth transistor, a first terminal of the fourth transistor is connected to the reference potential, a control terminal of the fourth transistor is connected to the control terminal of the third transistor, and a second terminal of the fourth transistor is indirectly connected to the power supply voltage;

[0013] The comparison module generates a comparison signal by comparing the voltage of the first voltage-dividing node with a reference potential.

[0014] In one or more embodiments of the present invention, the voltage dividing unit includes a first resistor and a third resistor, wherein the first end of the first resistor is connected to the power supply voltage, the second end of the first resistor is connected to the second end of the third transistor, the first end of the third resistor and the first end of the third transistor are both connected to the first voltage dividing node, and the second end of the third resistor is used to receive the input voltage; the second branch includes a second resistor, the first end of the second resistor is connected to the power supply voltage, and the second end of the second resistor is connected to the second end of the fourth transistor; or,

[0015] The voltage dividing unit includes a first current source and a third resistor, wherein the first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the second end of the third transistor, the first end of the third resistor and the first end of the third transistor are both connected to the first voltage dividing node, and the second end of the third resistor is used to receive the input voltage; the second branch includes a second current source, the first end of the second current source is connected to the power supply voltage, and the second end of the second current source is connected to the second end of the fourth transistor.

[0016] In one or more embodiments of the present invention, the switch unit includes a first transistor and a second transistor; wherein,

[0017] The first end of the first transistor is connected to the control end of the fourth transistor, the second end of the first transistor is connected to the second end of the fourth transistor, and the control end of the first transistor receives a first control signal;

[0018] A first terminal of the second transistor is connected to a reference potential, a second terminal of the second transistor is connected to a control terminal of the fourth transistor, and the control terminal of the second transistor receives a second control signal.

[0019] In one or more embodiments of the present invention, the comparison module further includes a third branch, the third branch including a fifth transistor, a first end of the fifth transistor being connected to the first voltage divider node, a second end of the fifth transistor being indirectly connected to the power supply voltage, and a control end of the fifth transistor being connected to the second end of the fourth transistor.

[0020] In one or more embodiments of the present invention, the voltage dividing unit includes a third resistor and a sixth resistor, a first end of the sixth resistor is connected to the power supply voltage, a second end of the sixth resistor is connected to the second end of the third transistor, the first end of the third resistor and the first end of the third transistor are both connected to the first voltage dividing node, and the second end of the third resistor is used to receive the input voltage; the second branch includes a fifth resistor, a first end of the fifth resistor is connected to the power supply voltage, and a second end of the fifth resistor is connected to the second end of the fourth transistor; the third branch includes a fourth resistor, a first end of the fourth resistor is connected to the power supply voltage, and a second end of the fourth resistor is connected to the second end of the fifth transistor; or,

[0021] The voltage dividing unit includes a third current source and a third resistor, the first end of the third current source is connected to the power supply voltage, the second end of the third current source is connected to the second end of the third transistor, the first end of the third resistor and the first end of the third transistor are both connected to the first voltage dividing node, and the second end of the third resistor is used to receive the input voltage. The second branch includes a fourth current source, the first end of the fourth current source is connected to the power supply voltage, and the second end of the fourth current source is connected to the second end of the fourth transistor; the third branch includes a fourth resistor and a fifth current source, the first end of the fourth resistor and the first end of the fifth current source are connected to the power supply voltage, and the second end of the fourth resistor and the second end of the fifth current source are connected to the second end of the fifth transistor.

[0022] In one or more embodiments of the present invention, the switch unit includes a sixth transistor, a seventh transistor, and an eighth transistor; wherein,

[0023] A first terminal of the sixth transistor is connected to the control terminal of the third transistor, a second terminal of the sixth transistor is connected to the second terminal of the third transistor, and the control terminal of the sixth transistor is used to receive a first control signal;

[0024] A first terminal of the seventh transistor is connected to a reference potential, a second terminal of the seventh transistor is connected to a control terminal of the fourth transistor, and the control terminal of the seventh transistor is used to receive a second control signal;

[0025] The first end of the eighth transistor is connected to the first end of the fifth transistor, the second end of the eighth transistor is connected to the control end of the fifth transistor, and the control end of the eighth transistor receives a second control signal.

[0026] In one or more embodiments of the present invention, the second input signal is a delayed signal of the first input signal;

[0027] During a first period, the first input signal is at a low level, the second input signal is at a low level, the first control signal is at a low level, the second control signal is at a high level, the switch unit is in a first state, and the comparison module does not operate;

[0028] During the second period, the first input signal is at a high level, the second input signal is at a low level, the first control signal is at a high level, the second control signal is at a low level, the switch unit is in the second state, and the comparison module compares the input voltage with the reference potential to generate a comparison signal;

[0029] In the third period, the first input signal is high, the second input signal is high, the first control signal is low, the second control signal is high, the switch unit is in the first state, and the comparison module does not work.

[0030] In one or more embodiments of the present invention, the logic unit includes a first NOT gate, a first NAND gate, a second NAND gate, and a second NOT gate; wherein,

[0031] The input end of the first NOT gate is used to receive a second input signal, and the output end of the first NOT gate is connected to the first input end of the first NAND gate and the first input end of the second NAND gate;

[0032] The second input terminal of the first NAND gate is used to receive a first input signal, the output terminal of the first NAND gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to the comparison module and generates a first control signal;

[0033] The second input end of the second NAND gate is used to receive the first input signal, and the output end of the second NAND gate is connected to the comparison module and generates a second control signal;

[0034] The second input signal is a delayed signal of the first input signal.

[0035] In one or more embodiments of the present invention, the negative pressure detection circuit further includes a shaping module, which is connected to the comparison module and is configured to shape the comparison signal and generate an output signal.

[0036] In one or more embodiments of the present invention, the shaping module includes a Schmitt trigger and an inverter, the first end of the Schmitt trigger receives the comparison signal, the second end of the Schmitt trigger is connected to the first end of the inverter, and the second end of the inverter is used to generate an output signal.

[0037] Compared with the prior art, the negative voltage detection circuit of the present invention realizes accurate detection and rapid response of the input voltage negative voltage through the comparison module and the enable module. When negative voltage detection is not performed, the enable module can control the comparison module to not consume static current.

[0038] The accuracy of negative pressure detection is improved through digital logic gates. At the same time, zero static operating current can be achieved when no negative pressure detection is performed, reducing the overall power consumption of the chip.

[0039] The use of a comparison module in the form of a resistor divider makes the detection circuit almost unaffected by process angle and temperature, and completes fast transient response detection; the present invention uses fewer devices, saves circuit area, reduces circuit design complexity, and improves circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 1 is a circuit structure diagram of a negative pressure detection circuit in Example 1 of the present invention;

[0042] Figure 2 1 is a signal waveform diagram of the negative pressure detection circuit in Example 1 of the present invention;

[0043] Figure 3 2 is a circuit structure diagram of a negative pressure detection circuit in Example 2 of the present invention;

[0044] Figure 4 4 is a circuit structure diagram of a negative pressure detection circuit in Example 3 of the present invention;

[0045] Figure 5 4 is a circuit structure diagram of a negative pressure detection circuit in Example 4 of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0047] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices to achieve the same or similar functional purpose, such as a connection through circuits or components such as switches and follower circuits. Furthermore, in the present invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0048] Example 1:

[0049] like Figure 1 As shown, a negative pressure detection circuit in one embodiment includes: an enabling module, a comparing module 20 and a shaping module 30 .

[0050] Specifically, the enabling module includes a logic unit 11 and a switch unit 12. The logic unit 11 is configured to generate a first control signal S1 and a second control signal S2 according to a first input signal EN and a second input signal END to control the switch unit 12 to be in the first state or the second state.

[0051] The comparison module 20 is connected between the power supply voltage AVDD and the reference potential AVSS, and is connected to the input voltage INPUT and the switch unit 12. When the switch unit 12 is in a first state, the comparison module 20 is inoperative. When the switch unit 12 is in a second state, the comparison module compares the input voltage INPUT with the reference potential AVSS to generate a comparison signal Vm.

[0052] The shaping module 30 is connected to the comparing module 20 and is used to shape the comparison signal Vm and generate an output signal OUTPUT.

[0053] like Figure 1 As shown, the comparison module 20 in one embodiment includes a first branch and a second branch. The first branch includes a voltage divider unit and a third transistor M3. The voltage divider unit is connected between the input voltage INPUT and the power supply voltage AVDD. The voltage divider unit includes a first voltage divider node n. The first end of the third transistor M3 is connected to the first voltage divider node n, and the second end of the third transistor M3 is connected to the voltage divider unit.

[0054] Specifically, in one embodiment, the voltage divider unit includes a first resistor R1 and a third resistor R3. A first end of the first resistor R1 is connected to the power supply voltage AVDD, a second end of the first resistor R1 is connected to the second end of the third transistor M3, a first end of the third resistor R3 and a first end of the third transistor M3 are both connected to a first voltage dividing node n, and a second end of the third resistor R3 is configured to receive an input voltage INPUT.

[0055] The second branch includes a fourth transistor M4 and a second resistor R2. A first terminal of the fourth transistor M4 is connected to a reference potential AVSS, a control terminal of the fourth transistor M4 is connected to a control terminal of the third transistor M3, a second terminal of the fourth transistor M4 is connected to a second terminal of the second resistor R2, and a first terminal of the second resistor R2 is connected to a power supply voltage AVDD. The comparison module 20 generates a comparison signal Vm by comparing the voltage of the first voltage-dividing node with the reference potential AVSS.

[0056] like Figure 1 As shown, the switch unit 12 in one embodiment includes a first transistor M1 and a second transistor M2. The first end of the first transistor M1 is connected to the control end of the fourth transistor M4, the second end of the first transistor M1 is connected to the second end of the fourth transistor M4, and the control end of the first transistor M1 receives a first control signal S1.

[0057] A first end of the second transistor M2 is connected to the reference potential AVSS, a second end of the second transistor M2 is connected to the control end of the fourth transistor M4, and the control end of the second transistor M2 receives a second control signal S2.

[0058] like Figure 2 As shown, in one embodiment, the second input signal END is a delayed signal of the first input signal EN.

[0059] In the first period, the first input signal EN is at a low level, the second input signal END is at a low level, the first control signal S1 is at a low level, so the first transistor M1 is turned off, the second control signal S2 is at a high level, so the second transistor M2 is turned on, the switch unit 12 is in the first state, and the comparison module 20 does not work.

[0060] In the second period, the first input signal EN is at a high level, the second input signal END is at a low level, the first control signal S1 is at a high level, so the first transistor M1 is turned on, the second control signal S2 is at a low level, so the second transistor M2 is turned off, the switch unit 12 is in the second state, the comparison module 20 divides the input voltage INPUT, and compares the voltage of the first divided node with the reference potential AVSS to generate a comparison signal Vm.

[0061] In the third period, the first input signal EN is at a high level, the second input signal END is at a high level, the first control signal S1 is at a low level, so the first transistor M1 is turned off, the second control signal S2 is at a high level, so the second transistor M2 is turned on, the switch unit 12 is in the first state, and the comparison module 20 does not work.

[0062] It can be understood that the logic unit 11 can adopt a patrol mechanism, that is, the first input signal EN periodically jumps from a low level to a high level and then to a low level, thereby controlling the comparison module 20 to periodically detect the input voltage INPUT, which neither consumes static current nor can achieve accurate monitoring of the input voltage INPUT.

[0063] like Figure 1 As shown, the enabling module in one embodiment includes a first NOT gate U1 , a first NAND gate U3 , a second NAND gate U2 , and a second NOT gate U4 .

[0064] Specifically, the input end of the first NOT gate U1 is used to receive the second input signal END, the output end of the first NOT gate U1 is connected to the first input end of the first NAND gate U3 and the first input end of the second NAND gate U2. The second input end of the first NAND gate U3 and the second input end of the second NAND gate U2 are used to receive the first input signal EN, the output end of the first NAND gate U3 is connected to the input end of the second NAND gate U4, the output end of the second NAND gate U4 is connected to the comparison module 20 and generates the first control signal S1, and the output end of the second NAND gate U2 is connected to the comparison module 20 and generates the second control signal S2.

[0065] like Figure 1 As shown, the shaping module 20 in one embodiment includes a Schmitt trigger U5 and an inverter U6. A first terminal of the Schmitt trigger U5 is connected to the second terminal of the third transistor M3 to receive the comparison signal Vm. A second terminal of the Schmitt trigger U5 is connected to a first terminal of the inverter U6. A second terminal of the inverter U6 generates an output signal OUTPUT.

[0066] The Schmitt trigger U5 itself has a hysteresis interval, and will flip only when the comparison signal Vm is higher than a certain value or lower than a lower value, to ensure that the output signal OUTPUT does not oscillate back and forth.

[0067] Combine Figure 2 and Figure 1It can be seen that when the first input signal EN is at a high level and the second input signal END is at a low level, the first control signal S1 is at a high level and the second control signal S2 is at a low level. At this time, the first transistor M1 is turned on and the second transistor M2 is turned off, so the comparison module 20 is turned on, and the first resistor R1 and the third resistor R3 form a resistor divider. At this time, the voltage of the first voltage divider node = (AVDD-INPUT)*R3 / (R1+R3). Since the first resistor R1 and the third resistor R3 are resistors of the same type, the voltage of the first voltage divider node is only proportional to the difference between the power supply voltage AVDD and the input voltage INPUT, and is not related to the process corner temperature, etc., thereby achieving accurate negative pressure detection and fast response.

[0068] The comparison module 20 compares the voltage at the first voltage-dividing node with a reference potential AVSS. In one embodiment, the reference potential AVSS is ground potential. When the voltage at the first voltage-dividing node is greater than the reference potential AVSS, the comparison signal Vm (the potential at the second terminal of the third transistor M3) is pulled high. After passing through the shaping circuit 30, a high-level output signal OUTPUT is output. When the voltage at the first voltage-dividing node is less than the reference potential AVSS, the comparison signal Vm is pulled low. After passing through the shaping circuit 30, a low-level output signal OUTPUT is output.

[0069] Example 2:

[0070] like Figure 3 The negative voltage detection circuit of the embodiment shown differs from that of Embodiment 1 in that: the voltage divider unit includes a first current source I1 and a third resistor R3, the first end of the first current source I1 is connected to the power supply voltage AVDD, the second end of the first current source I1 is connected to the second end of the third transistor M3, the first end of the third resistor R3 and the first end of the third transistor M3 are both connected to the first voltage divider node n, and the second end of the third resistor R3 is used to receive the input voltage INPUT.

[0071] In one embodiment, the second branch includes a fourth transistor M4 and a second current source I2. A first terminal of the fourth transistor M4 is connected to a reference potential AVSS, a second terminal of the fourth transistor M4 is connected to a second terminal of the second current source I2, a control terminal of the fourth transistor M4 is connected to a control terminal of the third transistor M3, and a first terminal of the second current source I2 is connected to a power supply voltage AVDD.

[0072] In one embodiment, the resistors at the sources of the first current source I1 and the second current source I2 are of the same type as the third resistor R3. Therefore, the voltage at the first voltage dividing node is only proportional to the difference between the power supply voltage AVDD and the input voltage INPUT, and is independent of the process corner temperature, etc., thereby achieving accurate negative pressure detection and fast response.

[0073] Combine Figure 2 and Figure 1 It can be seen that when the first input signal EN is at a high level and the second input signal END is at a low level, the first control signal S1 is at a high level and the second control signal S2 is at a low level. At this time, the switch unit 12 is in the second state, that is, the first transistor M1 is turned on and the second transistor M2 is turned off, so the comparison module 20 is turned on, and the comparison module 20 compares the voltage of the first voltage dividing node with the reference potential AVSS. The reference potential AVSS in one embodiment is the ground potential.

[0074] When the voltage at the first voltage-dividing node is greater than the reference potential AVSS, the comparison signal Vm (the potential at the second terminal of the third transistor M3) is pulled high and, after passing through the shaping circuit 30, outputs a high-level output signal OUTPUT. When the voltage at the first voltage-dividing node is less than the reference potential AVSS, the comparison signal Vm is pulled low and, after passing through the shaping circuit 30, outputs a low-level output signal OUTPUT.

[0075] Example 3:

[0076] like Figure 4 As shown, the difference from embodiment 1 is that the comparison module 20 in one embodiment includes a first branch, a second branch and a third branch.

[0077] The first branch includes a voltage divider unit and a third transistor M3. The voltage divider unit is connected between the input voltage INPUT and the power supply voltage AVDD. The voltage divider unit includes a first voltage divider node n. The first end of the third transistor M3 is connected to the first voltage divider node n, and the second end of the third transistor M3 is connected to the voltage divider unit. In one embodiment, the voltage divider unit includes a third resistor R3 and a sixth resistor R6. The first end of the sixth resistor R6 is connected to the power supply voltage AVDD, the second end of the sixth resistor R6 is connected to the second end of the third transistor M3, the first end of the third resistor R3 and the first end of the third transistor M3 are both connected to the first voltage divider node n, and the second end of the third resistor R3 is used to receive the input voltage INPUT.

[0078] The second branch includes a fourth transistor M4 and a fifth resistor R5. A first terminal of the fourth transistor M4 is connected to the reference potential AVSS, a control terminal of the fourth transistor M4 is connected to the control terminal of the third transistor M3, a second terminal of the fourth transistor M4 is connected to the second terminal of the fifth resistor R5, and a first terminal of the fifth resistor R5 is connected to the power supply voltage AVDD.

[0079] The third branch includes a fifth transistor M5 and a fourth resistor R4. A first end of the fifth transistor M5 is connected to the first voltage dividing node n, a second end of the fifth transistor M5 is connected to the second end of the fourth resistor R4, a control end of the fifth transistor M5 is connected to the second end of the fourth transistor M4, and a first end of the fourth resistor R4 is connected to the power supply voltage AVDD.

[0080] The comparison module 20 generates a comparison signal Vm by comparing the voltage of the first voltage-dividing node with a reference potential AVSS.

[0081] In one embodiment, the third resistor R3, the fourth resistor R4, and the sixth resistor R6 are of the same type. Therefore, the voltage at the first voltage-dividing node is proportional only to the difference between the power supply voltage AVDD and the input voltage INPUT, and is independent of the process corner temperature, etc., thereby achieving accurate negative pressure detection and fast response.

[0082] like Figure 4 As shown, the switch unit 12 in one embodiment includes a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8.

[0083] The first terminal of the sixth transistor M6 is connected to the control terminal of the third transistor M3, the second terminal of the sixth transistor M6 is connected to the second terminal of the third transistor M3, and the control terminal of the sixth transistor M6 is configured to receive the first control signal S1. The first terminal of the seventh transistor M7 is connected to the reference potential AVSS, the second terminal of the seventh transistor M7 is connected to the control terminal of the fourth transistor M4, and the control terminal of the seventh transistor M7 is configured to receive the second control signal S2. The first terminal of the eighth transistor M8 is connected to the first terminal of the fifth transistor M5, the second terminal of the eighth transistor M8 is connected to the control terminal of the fifth transistor M5, and the control terminal of the eighth transistor M8 receives the second control signal S2.

[0084] like Figure 2 As shown, in the first time period, the first input signal EN is at a low level, the second input signal END is at a low level, the first control signal S1 is at a low level, so the sixth transistor M6 is turned off, the second control signal S2 is at a high level, so the seventh transistor M7 and the eighth transistor M8 are turned on, the switch unit 12 is in the first state, and the comparison module 20 does not work.

[0085] During the second period, the first input signal EN is at a high level, the second input signal END is at a low level, the first control signal S1 is at a high level, so the sixth transistor M6 is turned on, the second control signal S2 is at a low level, so the seventh transistor M7 and the eighth transistor M8 are turned off, the switch unit 12 is in the second state, and the comparison module 20 compares the input voltage INPUT with the reference potential AVSS to generate a comparison signal Vm.

[0086] In the third period, the first input signal EN is at a high level, the second input signal END is at a high level, the first control signal S1 is at a low level, so the sixth transistor M6 is turned off, the second control signal S2 is at a high level, so the seventh transistor M7 and the eighth transistor M8 are turned on, the switch unit 12 is in the first state, and the comparison module 20 does not work.

[0087] When the voltage at the first voltage-dividing node is greater than the reference potential AVSS, the comparison signal Vm (the potential at the second terminal of the fifth transistor M5) is pulled high and, after passing through the shaping circuit 30, outputs a high-level output signal OUTPUT. When the voltage at the first voltage-dividing node is less than the reference potential AVSS, the comparison signal Vm is pulled low and, after passing through the shaping circuit 30, outputs a low-level output signal OUTPUT.

[0088] like Figure 4 As shown, the shaping module 20 in one embodiment includes a Schmitt trigger U5 and an inverter U6. A first terminal of the Schmitt trigger U5 is connected to the second terminal of the third transistor M3 to receive the comparison signal Vm. A second terminal of the Schmitt trigger U5 is connected to a first terminal of the inverter U6. A second terminal of the inverter U6 generates an output signal OUTPUT.

[0089] The comparison module 20 in one embodiment adopts a common-gate amplifier structure, which reduces the random mismatch error of the input transistor pair (the third transistor M3 and the fourth transistor M4).

[0090] Example 4:

[0091] like Figure 5 As shown, the difference between an embodiment and embodiment 1 is that the comparison module in an embodiment includes a first branch, a second branch and a third branch.

[0092] The first branch includes a voltage divider unit and a third transistor M3. The voltage divider unit is connected between the input voltage INPUT and the power supply voltage AVDD. The voltage divider unit includes a first voltage divider node n. The first end of the third transistor M3 is connected to the first voltage divider node n, and the second end of the third transistor M3 is connected to the voltage divider unit. The voltage divider unit includes a third resistor R3 and a third current source I3. The first end of the third current source I3 is connected to the power supply voltage AVDD, the second end of the third current source I3 is connected to the second end of the third transistor M3, the first end of the third resistor R3 and the first end of the third transistor M3 are both connected to the first voltage divider node n, and the second end of the third resistor R3 is used to receive the input voltage INPUT.

[0093] The second branch includes a fourth transistor M4 and a fourth current source I4. A first terminal of the fourth transistor M4 is connected to the reference potential AVSS, a control terminal of the fourth transistor M4 is connected to the control terminal of the third transistor M3, a second terminal of the fourth transistor M4 is connected to the second terminal of the fourth current source I4, and a first terminal of the fourth current source I4 is connected to the power supply voltage AVDD.

[0094] The third branch includes a fifth transistor M5, a fourth resistor R4, and a fifth current source I5. A first end of the fifth transistor M5 is connected to the first voltage dividing node n, a second end of the fifth transistor M5 is connected to the second end of the fourth resistor R4, a control end of the fifth transistor M5 is connected to the second end of the fourth transistor M4, and a first end of the fourth resistor R4 is connected to the power supply voltage AVDD. A first end of the fifth current source I5 is connected to the power supply voltage AVDD, and a second end of the fifth current source I5 is connected to the second end of the fifth transistor M5.

[0095] The comparison module generates a comparison signal Vm by comparing the voltage of the first voltage-dividing node with a reference potential AVSS.

[0096] In one embodiment, the third current source I3, the fourth current source I4, and the fifth current source I5 are current sources of the same source, and the currents generated by the third current source I3, the fourth current source I4, and the fifth current source I5 are equal. Furthermore, the resistors at the sources of the third current source I3, the fourth current source I4, and the fifth current source I5 are of the same type as the third resistor R3 and the fourth resistor R4. Therefore, the voltage at the first voltage-dividing node is proportional only to the difference between the power supply voltage AVDD and the input voltage INPUT, and is independent of the process corner temperature, thereby achieving accurate negative pressure detection and rapid response.

[0097] like Figure 5 As shown, in one embodiment, the switch unit 12 includes a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8.

[0098] The first terminal of the sixth transistor M6 is connected to the control terminal of the third transistor M3, the second terminal of the sixth transistor M6 is connected to the second terminal of the third transistor M3, and the control terminal of the sixth transistor M6 is configured to receive the first control signal S1. The first terminal of the seventh transistor M7 is connected to the reference potential AVSS, the second terminal of the seventh transistor M7 is connected to the control terminal of the fourth transistor M4, and the control terminal of the seventh transistor M7 is configured to receive the second control signal S2. The first terminal of the eighth transistor M8 is connected to the first terminal of the fifth transistor M5 and the first voltage dividing node n, the second terminal of the eighth transistor M8 is connected to the control terminal of the fifth transistor M5, and the control terminal of the eighth transistor M8 receives the second control signal S2.

[0099] like Figure 2As shown, in the first time period, the first input signal EN is at a low level, the second input signal END is at a low level, the first control signal S1 is at a low level, so the sixth transistor M6 is turned off, the second control signal S2 is at a high level, so the seventh transistor M7 and the eighth transistor M8 are turned on, the switch unit 12 is in the first state, and the comparison module 20 does not work.

[0100] In the second period, the first input signal EN is at a high level, the second input signal END is at a low level, the first control signal S1 is at a high level, so the sixth transistor M6 is turned on, the second control signal S2 is at a low level, so the seventh transistor M7 and the eighth transistor M8 are turned off, the switch unit 12 is in the second state, and the comparison module 20 compares the input voltage INPUT with the reference potential AVSS to generate a comparison signal Vm.

[0101] In the third period, the first input signal EN is at a high level, the second input signal END is at a high level, the first control signal S1 is at a low level, so the sixth transistor M6 is turned off, the second control signal S2 is at a high level, so the seventh transistor M7 and the eighth transistor M8 are turned on, the switch unit 12 is in the first state, and the comparison module 20 does not work.

[0102] When the voltage at the first voltage-dividing node is greater than the reference potential AVSS, the comparison signal Vm (the potential at the second terminal of the fifth transistor M5) is pulled high and, after passing through the shaping circuit 30, outputs a high-level output signal OUTPUT. When the voltage at the first voltage-dividing node is less than the reference potential AVSS, the comparison signal Vm is pulled low and, after passing through the shaping circuit 30, outputs a low-level output signal OUTPUT.

[0103] like Figure 5 As shown, the shaping module includes a Schmitt trigger U5 and an inverter U6. The first end of the Schmitt trigger U5 is connected to the second end of the fifth transistor M5 to receive the comparison signal Vm, the second end of the Schmitt trigger U5 is connected to the first end of the inverter U6, and the second end of the inverter U6 is used to generate the output signal OUTPUT.

[0104] It is also worth noting that in the above embodiment, the first terminal of the transistor is the source, the second terminal is the drain, and the control terminal is the gate. In other optional embodiments, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 in the above embodiment can all be BJT transistors or MOS transistors.

[0105] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0106] The negative voltage detection circuit of the present invention realizes accurate detection and rapid response of the negative voltage of the input voltage through the comparison module and the enable module. When negative voltage detection is not performed, the enable module can control the comparison module not to consume static current.

[0107] The present invention uses digital logic gates to improve the accuracy of negative pressure detection, and can also achieve zero static operating current when no negative pressure detection is performed, thereby reducing the overall power consumption of the chip.

[0108] The present invention uses a comparison module in the form of a resistor voltage divider to make the detection circuit almost unaffected by process angle and temperature, and complete fast transient response detection; the present invention uses fewer devices, saves the area of ​​the circuit chip, reduces the complexity of the chip circuit design, and improves the reliability of the circuit.

[0109] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0110] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A negative pressure detection circuit, characterized in that: The circuit includes an enabling module, a comparing module and a shaping module; wherein, an enabling module, comprising a logic unit and a switch unit, wherein the logic unit is configured to generate a first control signal and a second control signal according to a first input signal and a second input signal to control the switch unit to be in a first state or a second state; a comparison module connected between the power supply voltage and the reference potential, and connected to the input voltage and the switch unit, wherein when the switch unit is in a first state, the comparison module does not operate, and when the switch unit is in a second state, the comparison module compares the input voltage and the reference potential to generate a comparison signal; The comparison module includes a first branch and a second branch; wherein, The first branch includes a voltage dividing unit and a third transistor, the voltage dividing unit is connected between the input voltage and the power supply voltage, the voltage dividing unit includes a first voltage dividing node, a first end of the third transistor is connected to the first voltage dividing node, and a second end of the third transistor is connected to the voltage dividing unit; The second branch includes a fourth transistor, a first terminal of the fourth transistor is connected to the reference potential and the switch unit, a control terminal of the fourth transistor is connected to the control terminal of the third transistor and the switch unit, a second terminal of the fourth transistor is indirectly connected to the power supply voltage, and a second terminal of the fourth transistor is connected to the switch unit; The comparison module generates a comparison signal by comparing the voltage of the first voltage-dividing node with a reference potential.

2. The negative pressure detection circuit according to claim 1, characterized in that: The voltage dividing unit includes a first resistor and a third resistor, wherein the first end of the first resistor is connected to the power supply voltage, the second end of the first resistor is connected to the second end of the third transistor, the first end of the third resistor and the first end of the third transistor are both connected to the first voltage dividing node, and the second end of the third resistor is used to receive the input voltage; the second branch includes a second resistor, the first end of the second resistor is connected to the power supply voltage, and the second end of the second resistor is connected to the second end of the fourth transistor; or, The voltage dividing unit includes a first current source and a third resistor, wherein the first end of the first current source is connected to the power supply voltage, the second end of the first current source is connected to the second end of the third transistor, the first end of the third resistor and the first end of the third transistor are both connected to the first voltage dividing node, and the second end of the third resistor is used to receive the input voltage; the second branch includes a second current source, the first end of the second current source is connected to the power supply voltage, and the second end of the second current source is connected to the second end of the fourth transistor.

3. The negative pressure detection circuit according to claim 1, wherein: The switch unit includes a first transistor and a second transistor; wherein, The first end of the first transistor is connected to the control end of the fourth transistor, the second end of the first transistor is connected to the second end of the fourth transistor, and the control end of the first transistor receives a first control signal; A first terminal of the second transistor is connected to a reference potential, a second terminal of the second transistor is connected to a control terminal of the fourth transistor, and the control terminal of the second transistor receives a second control signal.

4. The negative pressure detection circuit according to claim 1, wherein: The comparison module also includes a third branch, which includes a fifth transistor, a first end of the fifth transistor is connected to the first voltage dividing node, a second end of the fifth transistor is indirectly connected to the power supply voltage, and a control end of the fifth transistor is connected to the second end of the fourth transistor.

5. The negative pressure detection circuit according to claim 4, characterized in that: The voltage dividing unit includes a third resistor and a sixth resistor, wherein a first end of the sixth resistor is connected to the power supply voltage, a second end of the sixth resistor is connected to the second end of the third transistor, a first end of the third resistor and a first end of the third transistor are both connected to a first voltage dividing node, and a second end of the third resistor is used to receive an input voltage; the second branch includes a fifth resistor, wherein a first end of the fifth resistor is connected to the power supply voltage, and a second end of the fifth resistor is connected to the second end of the fourth transistor; the third branch includes a fourth resistor, wherein a first end of the fourth resistor is connected to the power supply voltage, and a second end of the fourth resistor is connected to the second end of the fifth transistor; or, The voltage dividing unit includes a third current source and a third resistor, the first end of the third current source is connected to the power supply voltage, the second end of the third current source is connected to the second end of the third transistor, the first end of the third resistor and the first end of the third transistor are both connected to the first voltage dividing node, and the second end of the third resistor is used to receive the input voltage. The second branch includes a fourth current source, the first end of the fourth current source is connected to the power supply voltage, and the second end of the fourth current source is connected to the second end of the fourth transistor; the third branch includes a fourth resistor and a fifth current source, the first end of the fourth resistor and the first end of the fifth current source are connected to the power supply voltage, and the second end of the fourth resistor and the second end of the fifth current source are connected to the second end of the fifth transistor.

6. The negative pressure detection circuit according to claim 4, characterized in that: The switch unit includes a sixth transistor, a seventh transistor and an eighth transistor; wherein, A first terminal of the sixth transistor is connected to the control terminal of the third transistor, a second terminal of the sixth transistor is connected to the second terminal of the third transistor, and the control terminal of the sixth transistor is used to receive a first control signal; A first terminal of the seventh transistor is connected to a reference potential, a second terminal of the seventh transistor is connected to a control terminal of the fourth transistor, and the control terminal of the seventh transistor is used to receive a second control signal; The first end of the eighth transistor is connected to the first end of the fifth transistor, the second end of the eighth transistor is connected to the control end of the fifth transistor, and the control end of the eighth transistor receives a second control signal.

7. The negative pressure detection circuit according to claim 1, wherein: The second input signal is a delayed signal of the first input signal; During a first period, the first input signal is at a low level, the second input signal is at a low level, the first control signal is at a low level, the second control signal is at a high level, the switch unit is in a first state, and the comparison module does not operate; During the second period, the first input signal is at a high level, the second input signal is at a low level, the first control signal is at a high level, the second control signal is at a low level, the switch unit is in the second state, and the comparison module compares the input voltage with the reference potential to generate a comparison signal; In the third period, the first input signal is high, the second input signal is high, the first control signal is low, the second control signal is high, the switch unit is in the first state, and the comparison module does not work.

8. The negative pressure detection circuit according to claim 1, wherein: The logic unit includes a first NOT gate, a first NAND gate, a second NAND gate and a second NOT gate; wherein, The input end of the first NOT gate is used to receive a second input signal, and the output end of the first NOT gate is connected to the first input end of the first NAND gate and the first input end of the second NAND gate; The second input terminal of the first NAND gate is used to receive a first input signal, the output terminal of the first NAND gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to the comparison module and generates a first control signal; The second input end of the second NAND gate is used to receive the first input signal, and the output end of the second NAND gate is connected to the comparison module and generates a second control signal; The second input signal is a delayed signal of the first input signal.

9. The negative pressure detection circuit according to claim 1, wherein: The negative pressure detection circuit further includes a shaping module, which is connected to the comparison module and is used to shape the comparison signal and generate an output signal.

10. The negative pressure detection circuit according to claim 9, characterized in that: The shaping module includes a Schmitt trigger and an inverter, a first end of the Schmitt trigger receives a comparison signal, a second end of the Schmitt trigger is connected to the first end of the inverter, and the second end of the inverter is used to generate an output signal.

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