Substrate management controller communication method and apparatus, computer device, and storage medium

Abstract

This invention relates to the field of server technology, and discloses a communication method, apparatus, computer device, and storage medium for a baseboard management controller. The method includes: after the server is powered on, controlling a first power module to output a first power supply to power the flash memory of the baseboard management controller, wherein the baseboard management controller boots up by loading firmware in the flash memory; if the baseboard management controller fails to boot normally, controlling the first power module to output a second power supply to power the flash memory; if the baseboard management controller boots normally, controlling the second power module to output a first bus level to provide a first reference voltage for the bus, so that the bus operates based on the first reference voltage; monitoring the bus's operating status information; if the operating status information indicates that the bus is malfunctioning, controlling the second power module to output a second bus level to provide a second reference voltage for the bus, so that the bus operates based on the second reference voltage. This invention saves on the investment cost of management board design.

Description

Technical Field

[0001] This invention relates to the field of server technology, and more specifically to a baseboard management controller communication method, apparatus, computer equipment, and storage medium. Background Technology

[0002] With the adoption of modular server designs, the reusability of the management board has become increasingly important. The management board houses the Baseboard Management Controller (BMC) and management-related main control chips. The server motherboard houses the Central Processing Unit (CPU) and control timing-related main control chips. The management board and the server motherboard communicate via a bus.

[0003] In related technologies, different server motherboards may communicate with the baseboard management controller via different buses, and these buses use different voltage levels. Therefore, different management boards need to be designed for different server motherboards. Furthermore, since the power supply requirements of the BMC flash memory may differ, different management boards need to be designed for the varying power supply requirements of the BMC flash memory.

[0004] Different server motherboards and different BMC flash memory power supply requirements result in many different management board designs, leading to high design strength and high design costs. Summary of the Invention

[0005] In view of this, the present invention provides a baseboard management controller communication method, apparatus, computer equipment and storage medium to solve the problem that the management board design is strong and costly due to the many different management board designs in the related art.

[0006] In a first aspect, the present invention provides a baseboard management controller communication method, the method comprising:

[0007] After the server is powered on, the first power module is controlled to output the first power supply to power the flash memory of the baseboard management controller, wherein the baseboard management controller is started by loading the firmware in the flash memory;

[0008] If the baseboard management controller fails to start normally, the first power module is controlled to output a second power supply to power the flash memory of the baseboard management controller.

[0009] When the baseboard management controller is started normally, the second power module is controlled to output a first bus level to provide a first reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the first reference voltage;

[0010] Monitor the operating status information of the bus under the first reference voltage;

[0011] If the working status information indicates that the bus is malfunctioning, it is determined that the baseboard management controller and the server motherboard cannot communicate normally. The second power module is then controlled to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the second reference voltage.

[0012] The baseboard management controller communication method provided in this embodiment sets a target logic device in the management board. After the server powers on, the target logic device controls the first power module to output a first power supply to power the flash memory of the baseboard management controller. If the baseboard management controller fails to start normally, the first power module outputs a second power supply to power the flash memory, achieving adaptive switching of the power required by the flash memory. When the baseboard management controller starts normally, the second power module outputs a first bus level by default to provide a first reference voltage for the bus, enabling the bus to operate based on the first reference voltage. If the bus malfunctions, the second power module outputs a second bus level to provide a second reference voltage for the bus, enabling the bus to operate based on the second reference voltage, thus achieving adaptive switching of the required bus level. This allows the same management board to be compatible with different server motherboards, reducing the design complexity and investment cost of the management board.

[0013] In one optional implementation, after controlling the first power module to output a first power supply to power the flash memory of the substrate management controller and after controlling the first power module to output a second power supply to power the flash memory of the substrate management controller, the method further includes:

[0014] Monitor the watchdog signal of the baseboard management controller;

[0015] If the watchdog signal outputs a square wave within a preset time period, it is determined that the baseboard management controller has started normally.

[0016] If the watchdog signal does not output a square wave within a preset time period, it is determined that the baseboard management controller has not started normally.

[0017] The communication method for the baseboard management controller provided in this embodiment can detect startup faults of the baseboard management controller in a timely manner by listening to the watchdog signal of the baseboard management controller and judging whether it outputs a square wave normally within a preset time period, thus ensuring the accuracy of the startup status of the baseboard management controller.

[0018] In one optional implementation, while controlling the first power module to output a second power supply to power the flash memory of the substrate management controller, the method further includes:

[0019] Pull the reset signal of the substrate management controller low to cause the substrate management controller to reload the firmware in the flash memory.

[0020] The substrate management controller communication method provided in this embodiment can ensure that the firmware used by the substrate management controller is obtained from the flash memory after the second power supply powers the flash memory of the substrate management controller.

[0021] In an optional implementation, the method further includes:

[0022] When the operating status information indicates that the bus is working normally, the normal operating voltage of the bus is determined to be the first reference voltage provided by the first bus level, and the baseboard management controller communicates normally with the server motherboard.

[0023] The baseboard management controller communication method provided in this embodiment accurately identifies and sets the normal operating voltage of the current bus to the first reference voltage provided by the first bus level, enabling the baseboard management controller to communicate normally with the server motherboard.

[0024] In an optional implementation, the method further includes:

[0025] In the event of a server motherboard malfunction, the baseboard management controller is controlled to record an error log, enabling the user to handle the server motherboard malfunction based on the error log.

[0026] The baseboard management controller communication method provided in this embodiment records error logs for server motherboard anomalies, which helps technicians quickly locate the cause of the problem and speeds up the repair process.

[0027] In one optional implementation, while controlling the second power module to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, the method further includes:

[0028] The power-on signal of the server motherboard is pulled low so that the bus between the baseboard management controller and the server motherboard operates based on a second reference voltage provided by a second bus level.

[0029] The baseboard management controller communication method provided in this embodiment provides a second reference voltage for the bus between the baseboard management controller and the server motherboard by controlling the second power module to output a second bus level, while simultaneously lowering the power-on signal of the server motherboard. This avoids circuit damage or data corruption during voltage adjustment, enabling the bus between the baseboard management controller and the server motherboard to smoothly transition between different reference voltages and increasing operational safety.

[0030] In one optional implementation, monitoring the operating status information of the bus under the first reference voltage includes:

[0031] Monitor the data path of the bus under the first reference voltage;

[0032] If there is no data transmission interruption in the data path, it is determined that the bus has a continuous data path under the first reference voltage;

[0033] In the event of a data transmission interruption in the data path, it is determined that the bus has no continuous data path under the first reference voltage;

[0034] When the bus has a continuous data path under the first reference voltage, the data transmitted on the bus is parsed to determine whether the data transmitted on the bus meets the bus protocol.

[0035] If the bus has a continuous data path under the first reference voltage and the data transmitted by the bus meets the bus protocol, it is determined that the bus is working normally.

[0036] In the case that there is no continuous data path on the bus under the first reference voltage, the data transmitted on the bus is parsed to determine whether the data transmitted on the bus meets the bus protocol;

[0037] If there is no continuous data path on the bus under the first reference voltage and the data transmitted on the bus does not meet the bus protocol, determine whether the server motherboard reset signal is in a high state.

[0038] If the server motherboard reset signal is high, it is determined that the server motherboard is malfunctioning.

[0039] If the server motherboard reset signal is in a normal state, it is determined that the bus is malfunctioning.

[0040] The board management controller communication method provided in this embodiment determines whether the bus is working normally or abnormally by continuously monitoring the data path of the bus under a specific voltage and analyzing data transmission interruptions and protocol compliance, thereby accurately identifying and setting the normal operating voltage of the current bus.

[0041] It can also determine whether the problem is with the server motherboard or the bus based on the status of the server motherboard reset signal, thus enabling users to perform corresponding repairs based on different anomalies, greatly improving maintenance efficiency.

[0042] In a second aspect, the present invention provides a baseboard management controller communication device, the device comprising:

[0043] The first control module is used to control the first power module to output the first power supply to power the flash memory of the baseboard management controller after the server is powered on, wherein the baseboard management controller is started by loading the firmware in the flash memory;

[0044] The second control module is used to control the first power module to output a second power supply to power the flash memory of the baseboard management controller when the baseboard management controller fails to start normally.

[0045] The third control module is used to control the second power module to output a first bus level to provide a first reference voltage for the bus between the baseboard management controller and the server motherboard when the baseboard management controller is started normally, so that the bus operates based on the first reference voltage.

[0046] The monitoring module is used to monitor the operating status information of the bus under the first reference voltage;

[0047] The first determining module is configured to determine that the baseboard management controller and the server motherboard cannot communicate normally when the working status information indicates that the bus is malfunctioning, and control the second power module to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the second reference voltage.

[0048] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the board management controller communication method of the first aspect or any corresponding embodiment described above.

[0049] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the board management controller communication method of the first aspect or any corresponding embodiment thereof.

[0050] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the baseboard management controller communication method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0052] Figure 1 (a) is a schematic diagram of a server architecture in related technologies;

[0053] Figure 1 (b) is a schematic diagram of another server architecture in related technologies;

[0054] Figure 2 This is a flowchart illustrating the communication method of the baseboard management controller according to an embodiment of the present invention;

[0055] Figure 3 This is a schematic diagram of the structure for implementing power switching of the first power module according to an embodiment of the present invention;

[0056] Figure 4 This is a schematic diagram illustrating the process of automatic switching of the BMC Flash power supply by the management board CPLD according to an embodiment of the present invention;

[0057] Figure 5 This is a schematic diagram of the structure of the management board according to an embodiment of the present invention;

[0058] Figure 6 This is a schematic diagram illustrating the process by which the management board CPLD automatically determines whether the BMC and the server motherboard have successfully completed a handshake, according to an embodiment of the present invention.

[0059] Figure 7 This is a flowchart illustrating another baseboard management controller communication method according to an embodiment of the present invention;

[0060] Figure 8 This is a structural block diagram of a baseboard management controller communication device according to an embodiment of the present invention;

[0061] Figure 9 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] As server panel design becomes mainstream, ease of operation, ease of maintenance, and reusability of management boards are increasingly becoming development trends.

[0064] Figure 1 Image (a) is a schematic diagram of a server architecture in related technologies. For example... Figure 1 As shown in (a), the server architecture includes a server motherboard and a management board. The server motherboard, by default, houses the CPUs (exemplarily CPU1 and CPU0), the Platform Controller Hub (PCH), and the Complex Programmable Logic Device (CPLD) associated with control timing. The PCH serves as the master controller for the enhanced Serial Peripheral Interface (eSPI) in this server architecture, initiating communication and configuring slave devices. The CPLD associated with control timing is called CPLD for Sequence. A CPLD is a digital integrated circuit whose logic functions are custom-designed by the user according to their needs.

[0065] In this server architecture, the management board houses the BMC, the BMC & Basic Input Output System (BIOS) flash memory (only the BMC Flash is shown in the diagram), and the CPLD for management. The BMC is the eSPI slave device, and its flash memory includes 3.3V BMC Flash1 and 3.3V BMC Flash0. It should be noted that 3.3V is equivalent to 3V3.

[0066] Furthermore, in this server architecture, the BMC interacts with the PCH on the server motherboard via the eSPI bus, thereby enabling communication between the BMC and the server motherboard.

[0067] Figure 1 Figure (b) is a schematic diagram of a server architecture in related technologies. For example... Figure 1 As shown in (b), the server architecture includes a server motherboard and a management board. Figure 1 The server motherboard and management board in (a) are similar in design, and the similarities will not be repeated here. The difference is that the server motherboard does not include a PCH; the CPU on the server motherboard interacts with the BMC via a low pin count (LPC) bus. The BMC's flash memory includes 1.8V BMC Flash1 and 1.8V BMC Flash0. It should be noted that 1.8V is equivalent to 1V8.

[0068] The management board, in accordance with the protocol requirements, houses the BMC and the CPLD main control chip related to management. The BMC and BIOS images are stored in Flash and the back window input / output (I / O) ports.

[0069] Although eSPI and LPC are multiplexed buses under the BMC in the two server architectures described above, the different voltage levels used by these two buses (eSPI uses 1.8V, and LPC uses 3.3V) mean that the management boards used in these two server architectures cannot be the same. This means that each project must design its own separate management board during the actual design process.

[0070] Accordingly, BMC Flash chips are also divided into chips with different power supplies depending on the project and customer requirements, such as 1.8V BMC Flash and 3.3V BMC Flash as shown in the figure. That is to say, even if the server motherboard is the same, it is still necessary to distinguish between management boards designed for 1.8V power supply BMC Flash and management boards designed for 3.3V power supply BMC Flash.

[0071] For different server motherboards, as long as the pin order of the control board interface is consistent, a management board that can adapt to different server motherboards can be designed. However, due to the combination of bus requirements of server motherboards and power supply requirements of BMC memory in related technologies, the design of management boards with the same function will become increasingly common. In other words, due to design inconsistencies in different projects and customer needs, management boards with different designs will be further subdivided, resulting in high design complexity and cost for management boards, placing a significant burden on management and R&D personnel. Furthermore, developing the same management board for every server motherboard will also lead to duplication and waste of manpower and resources, making the R&D investment disproportionate to the output.

[0072] Therefore, a management board that can be compatible with the power supply requirements of various server motherboard buses and BMC memory is needed to reduce the design complexity and cost of the management board.

[0073] This invention provides a communication method for a baseboard management controller. By setting a target logic unit in the management board, the target logic unit controls a first power module to output a first power supply to power the flash memory of the baseboard management controller after the server powers on. If the baseboard management controller fails to start normally, the first power module outputs a second power supply to power the flash memory, achieving adaptive switching of the power required by the flash memory. When the baseboard management controller starts normally, the second power module outputs a first bus level by default to provide a first reference voltage for the bus, enabling the bus to operate based on the first reference voltage. If the bus malfunctions, the second power module outputs a second bus level to provide a second reference voltage for the bus, enabling the bus to operate based on the second reference voltage, thus achieving adaptive switching of the required bus level. The same management board can be compatible with different server motherboards, reducing the design complexity and cost of the management board.

[0074] According to an embodiment of the present invention, a communication method for a baseboard management controller is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0075] This embodiment provides a baseboard management controller communication method, which can be used to manage target logic devices in the board. Figure 2 This is a flowchart of a baseboard management controller communication method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0076] Step S201: After the server is powered on, the first power module is controlled to output the first power supply to power the flash memory of the baseboard management controller. The baseboard management controller is started by loading the firmware in the flash memory.

[0077] The target logic device is a CPLD. The management board in this embodiment includes a first power management IC (PMIC) that powers the flash memory of the baseboard management controller.

[0078] Figure 3 This is a schematic diagram illustrating the structure for power switching of the first power module according to an embodiment of the present invention. Figure 3As shown, the first power module is PMIC1. After the server is powered on, the management board CPLD controls the enable signal (FLASH_PWR_EN) of the first power module, causing the first power module to output the first power supply and the second power supply.

[0079] The first power module also includes a multiplexer (MUX). The CPLD is used to control the enable (MUX_EN) of this multiplexer, enabling signal path selection and flexible configuration. The first power module provides two power supplies to the MUX (P3V3_STBY and P1V8_STBY), namely 3V3 and 1V8 power supplies. Under the control of the CPLD, the MUX outputs one of these power supplies to power the BMC flash memory.

[0080] It should be noted that the BMC flash memory connects to the FWSPI (Firmware Serial Peripheral Interface) within the BMC via a Serial Peripheral Interface (SPI) to allow the BMC to access the firmware (FW) stored in the BMC flash memory. The BMC flash memory is used to store an image of the BMC firmware.

[0081] Figure 4 This is a flowchart illustrating the automatic switching of the BMC Flash power supply by the management board CPLD according to an embodiment of the present invention. Figure 4 As shown, after the server is powered on by Alternating Current (AC), the management board CPLD controls MUX_EN and outputs P3V3_STBY power to the FLASH by default.

[0082] In other words, the first power supply is 3V3.

[0083] Understandably, after powering the flash memory of the baseboard management controller, the baseboard management controller will load the firmware in the flash memory to boot.

[0084] Step S202: If the substrate management controller fails to start normally, control the first power module to output the second power supply to power the flash memory of the substrate management controller.

[0085] If the baseboard management controller fails to start normally, it indicates that the power supply required for the flash memory of the baseboard management controller is not the primary power supply. In this case, the management board CPLD controls MUX_EN to switch the power supply output of P1V8_STBY to the flash memory. It is understandable that if the flash power supply does not meet the flash requirements, the baseboard management controller (BMC) cannot start.

[0086] In other words, the second power supply is 1V8.

[0087] Understandably, after the power switch is completed, the flash memory of the baseboard management controller operates based on the second power supply. At this time, the baseboard management controller reloads the firmware in the flash memory to start up.

[0088] Step S203: When the baseboard management controller is started normally, control the second power module to output the first bus level to provide the first reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the first reference voltage.

[0089] in, Figure 5 This is a schematic diagram of the structure of the management board according to an embodiment of the present invention. Figure 5 As shown, the management board includes: BMC, management board CPLD, second power module PMIC2, and third power module PMIC3. It should be noted that the management board also includes... Figure 3 The structure shown is not shown in this figure.

[0090] The BMC has four signal lines. The CLK_ESPI_LPC, IO[3:0]_ESPI_LPC, CS_ESPI_LPC, and ALERT_ESPI_LPC signal lines are shared by the ESPI and LPC buses. The order of these signal lines may differ on the connectors between the management board and the server motherboard. The CLK_ESPI_LPC signal line is the clock signal line; the IO[3:0]_ESPI_LPC signal lines are four general-purpose I / O signal lines used for data transmission, control signals, or other signal transmission; the CS_ESPI_LPC signal line is the chip select signal line used to control and select a specific device for communication. In other words, the server motherboard communicates with the BMC by pulling this chip select signal line low; the ALERT_ESPI_LPC signal line is the interrupt or error signal notification line. It can be understood that in this embodiment, the management board combines the same function signal lines of the ESPI and LPC buses into a single signal line, i.e., a multiplexed signal line design.

[0091] The BMC is equipped with interfaces for connecting signal lines. The CLK_ESPI_LPC signal line is connected to the CLK interface, the IO[3:0]_ESPI_LPC signal line is connected to the IO[3:0] interface, the CS_ESPI_LPC signal line is connected to the CS0_N interface, and the ALERT_ESPI_LPC signal line is connected to the ALERT0_N interface.

[0092] In this embodiment, to achieve the function of adaptively identifying the reference voltage required by the bus, the ESPI bus / LPC bus on the link is additionally connected to the management board CPLD for monitoring. That is, by adding line ①, additional mounting chips are added to the management board CPLD for the ESPI bus and LPC bus. This allows the management board CPLD to also connect to the four signal lines connected to the BMC. This enables the management board CPLD to automatically identify the eSPI bus and LPC bus and wake up the management engine (ME) mechanism, adaptively switching between the 3.3V reference voltage required by the LPC bus and the 1.8V reference voltage required by the eSPI bus. Here, ME is the server motherboard, and the wake-up mechanism realizes that the server motherboard and BMC have successfully handshaked, enabling normal communication between the server motherboard and BMC.

[0093] After the server is powered on, it provides a 12V DC power supply (P12V_PSU) to the management board. This DC power supply powers the second power module through line ②, and can also power the third power module.

[0094] It should be noted that the ESPI_LPC_PWR_EN signal is controlled by the CPLD on the management board and is used to send control signals to the second power module, drive the second power module to output bus level, and provide a reference voltage (ESPI_LPC_PWR_REF) to the bus.

[0095] The second power module, under the control of the management board CPLD, provides the reference voltage required for the CPLD and BMC to the ESPI bus or LPC bus.

[0096] It should be noted that the third power module is used to power the management board CPLD and BMC.

[0097] In related technologies, different server motherboards use eSPI / LPC for communication with the BMC. While the BMC chip design uses a multiplexed bus, the different bus levels used by the master and slave chips, as well as the different BMC reference voltages, prevent them from sharing the same management board. This embodiment utilizes a multiplexed circuit and power supply design for the ESPI and LPC buses. The power supply enable of the power module is controlled by the management board's CPLD, supplying power to the bus and the BMC reference voltage respectively.

[0098] Figure 6 This is a flowchart illustrating how the management board CPLD automatically determines whether the BMC and the server motherboard have successfully completed a handshake, according to an embodiment of the present invention. Figure 6As shown, when the baseboard management controller is started normally, the management board CPLD controls the second power module PMIC2 to output P3V3_STBY by default, with the first bus level being 3.3V, which corresponds to the LPC bus level. This ensures that the bus between the baseboard management controller and the server motherboard operates based on the first reference voltage of 3.3V.

[0099] Step S204: Monitor the operating status information of the bus under the first reference voltage.

[0100] like Figure 6 As shown, the management board CPLD monitors the operating status information of the bus under the first reference voltage to determine whether the BMC and the server motherboard have successfully handshaked. It can be understood that this bus can be either an eSPI bus or an LPC bus.

[0101] Step S205: If the working status information indicates that the bus is malfunctioning, it is determined that the baseboard management controller and the server motherboard cannot communicate normally. The second power module is controlled to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the second reference voltage.

[0102] The bus's operating status information under the first reference voltage indicates a bus malfunction. If this indicates an abnormality, it means the bus is not an LPC bus, and the baseboard management controller cannot communicate normally with the server motherboard. The management board's CPLD then switches its output to P1V8_STBY, corresponding to the second bus level (1.8V, the eSPI bus level). This ensures the bus between the baseboard management controller and the server motherboard operates based on the second reference voltage of 1.8V.

[0103] It should be noted that both the eSPI bus and the LPC bus require a handshake before they can operate. If the handshake fails, they cannot be used, meaning that the baseboard management controller cannot communicate with the server motherboard via the bus.

[0104] Bus handshake is the interaction between two communicating parties by the master control chip transmitting specific handshake signals on the bus.

[0105] Understandably, when the management board CPLD switches to output the second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard so that the bus can operate based on the second reference voltage, the management board CPLD also needs to monitor the bus's operating status information under the second reference voltage. If the operating status information indicates that the bus is working normally, it determines that the bus is the eSPI bus, and the baseboard management controller and the server motherboard are communicating normally, that is, the handshake is successful.

[0106] If the bus's operating status information at the second reference voltage indicates an abnormality in bus operation, it should be logged so that technicians can handle the abnormality accordingly.

[0107] The baseboard management controller communication method provided in this embodiment sets a target logic device in the management board. After the server powers on, the target logic device controls the first power module to output a first power supply to power the flash memory of the baseboard management controller. If the baseboard management controller fails to start normally, the first power module outputs a second power supply to power the flash memory, achieving adaptive switching of the power required by the flash memory. When the baseboard management controller starts normally, the second power module outputs a first bus level by default to provide a first reference voltage for the bus, enabling the bus to operate based on the first reference voltage. If the bus malfunctions, the second power module outputs a second bus level to provide a second reference voltage for the bus, enabling the bus to operate based on the second reference voltage, thus achieving adaptive switching of the required bus level. This allows the same management board to be compatible with different server motherboards, reducing the design complexity and investment cost of the management board.

[0108] This embodiment achieves a design where a single management board is compatible with multiple server motherboards by adding a CPLD monitoring eSPI / LPC signal line design, an eSPI and LPC multiplexing line and power supply design, a power supply line and logic design for BMC Flash adaptive switching, and a CPLD automatic identification of the eSPI bus and LPC bus and a wake-up ME mechanism. By simply adding lines and logic to the management board, this embodiment achieves a design where a single management board is compatible with multiple server motherboards.

[0109] This embodiment provides a baseboard management controller communication method, which can be used to manage target logic devices in the board. Figure 7 This is a flowchart of a baseboard management controller communication method according to an embodiment of the present invention, such as... Figure 7 As shown, the process includes the following steps:

[0110] Step S701: After the server powers on, the first power module outputs a first power supply to power the flash memory of the baseboard management controller. The baseboard management controller boots up by loading firmware from the flash memory. For details, please refer to [link to relevant documentation]. Figure 2 Step S201 of the illustrated embodiment will not be described again here.

[0111] Step S702: If the substrate management controller fails to start normally, control the first power module to output a second power supply to power the flash memory of the substrate management controller. For details, please refer to [link to relevant documentation]. Figure 2 Step S202 of the illustrated embodiment will not be described again here.

[0112] Step S703: When the baseboard management controller is started normally, control the second power module to output a first bus level to provide a first reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the first reference voltage. For details, please refer to [link to details]. Figure 2 Step S203 of the illustrated embodiment will not be described again here.

[0113] Step S704: Monitor the operating status information of the bus under the first reference voltage.

[0114] Specifically, step S704 above includes:

[0115] Step S7041: Monitor the data path of the bus under the first reference voltage.

[0116] The operating status information includes whether there is a continuous data path on the bus under the first reference voltage.

[0117] Because the management board's CPLD can perform protocol conversion, the newly added bus monitoring function can identify whether there is data on the bus, i.e., whether there is a continuous data path. When the bus is operating at the first reference voltage, monitoring the data path of the bus at the first reference voltage is equivalent to monitoring the data path of the bus during the handshake between the server motherboard and the BMC.

[0118] Step S7042: If there is no data transmission interruption in the data path, determine that the bus has a continuous data path under the first reference voltage.

[0119] Step S7043: In the event of a data transmission interruption in the data path, determine that there is no continuous data path on the bus under the first reference voltage.

[0120] Step S7044: When there is a continuous data path on the bus under the first reference voltage, the data transmitted on the bus is parsed to determine whether the data transmitted on the bus meets the bus protocol.

[0121] The operating status information also includes whether the data transmitted on the bus conforms to the bus protocol. The bus protocol under the first reference voltage is the LPC bus protocol.

[0122] Step S7045: If there is a continuous data path on the bus under the first reference voltage and the data transmitted on the bus meets the bus protocol, it is determined that the bus is working normally.

[0123] It should be noted that the bus working properly indicates that the CPU and BMC in the server motherboard have successfully shaken hands and can communicate normally.

[0124] Step S7046: In the absence of a continuous data path on the bus under the first reference voltage, the data transmitted on the bus is parsed to determine whether the data transmitted on the bus meets the bus protocol.

[0125] Step S7047: If there is no continuous data path on the bus under the first reference voltage and the data transmitted on the bus does not meet the bus protocol, determine whether the server motherboard reset signal is in a high state.

[0126] In this case, if there is no continuous data path on the bus under the first reference voltage, and the data transmitted on the bus does not meet the bus protocol, it indicates that the CPU and BMC on the server motherboard have failed to handshake. At this point, it is necessary to determine whether the problem lies with the server motherboard or with the bus itself.

[0127] In other words, if there is no continuous data path and no data is parsed or the data is abnormal, it is determined that the CPU and BMC of the server motherboard have failed to handshake.

[0128] like Figure 6 As shown, the management board CPLD determines whether PLTRST (server motherboard reset signal) is pulled high, that is, whether the server motherboard reset signal is in a high state.

[0129] It's important to note that in a successful handshake, the server motherboard's CPU sends a PLTRST signal to the CPLD. This signal serves as a timing indicator, signifying that the server was functioning correctly before power-on. In this case, the PLTRST signal is high. If the handshake fails, the PLTRST signal will definitely not go high. Therefore, determining whether the server motherboard's reset signal is high is crucial to identifying whether the problem lies with the motherboard itself or the bus.

[0130] Step S7048: If the server motherboard reset signal is high, a server motherboard malfunction is confirmed. The malfunction of the main control chip, i.e., the server motherboard malfunction, can be reported to the BMC.

[0131] Step S7049: If the server motherboard reset signal is in a normal state, determine that the bus is malfunctioning.

[0132] Step S705: If the operating status information indicates a bus malfunction, and it is determined that the baseboard management controller and the server motherboard cannot communicate normally, the second power module is controlled to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the second reference voltage. For details, please refer to [link to relevant documentation]. Figure 2 Step S205 of the illustrated embodiment will not be described again here.

[0133] It should be noted that when the bus operates based on the second reference voltage, the operating status information of the bus under the second reference voltage is monitored. If the operating status information indicates that the bus is working normally, it is determined that the bus is an eSPI bus, and the communication between the baseboard management controller and the server motherboard is normal, that is, the handshake is successful.

[0134] The process of monitoring the bus's operating status information under the second reference voltage is similar to that of monitoring the bus's operating status information under the first reference voltage, and will not be described in detail here.

[0135] The board management controller communication method provided in this embodiment determines whether the bus is working normally or abnormally by continuously monitoring the data path of the bus under a specific voltage and analyzing data transmission interruptions and protocol compliance, thereby accurately identifying and setting the normal operating voltage of the current bus.

[0136] It can also determine whether the problem is with the server motherboard or the bus based on the status of the server motherboard reset signal, thus enabling users to perform corresponding repairs based on different anomalies, greatly improving maintenance efficiency.

[0137] In some optional embodiments, after step S701 and after step S702, the substrate management control communication method further includes:

[0138] Step a1: Listen to the watchdog signal of the board management controller.

[0139] Among them, such as Figure 3 As shown, the watchdog signal (WDT) of the baseboard management controller is connected to the general purpose input / output ports (GPIO) of the management board CPLD. For example... Figure 4 As shown, regarding the issue of BMC adapting to Flash with different power supplies, after the management board CPLD controls the first power module to output the first power supply to power the flash memory of the baseboard management controller, it determines whether the baseboard management controller is starting normally by listening to the WDT of the BMC.

[0140] It should be noted that after the chip starts up normally, the watchdog signal will continuously output a square wave. Therefore, the chip can be determined to be started normally by detecting whether the watchdog signal outputs a square wave.

[0141] Step a2: If the watchdog signal outputs a square wave within a preset time period, it is confirmed that the board management controller has started normally.

[0142] The preset time period is set by the technician. For example, the preset time period can be 2 minutes. If a square wave of the watchdog signal is detected within the preset time period, it is determined that the baseboard management controller has started normally, that is, the baseboard management controller has loaded the firmware normally.

[0143] Step a3: If the watchdog signal does not output a square wave within a preset time period, it is determined that the board management controller has not started normally.

[0144] It is understandable that when the management board CPLD controls the first power module to output the first power to power the flash memory of the baseboard management controller, and the baseboard management controller fails to start normally, the first power module is controlled to output the second power to power the flash memory of the baseboard management controller. At this time, steps a1-a3 also need to be executed to determine whether the baseboard management controller starts normally when the management board CPLD controls the first power module to output the second power to power the flash memory of the baseboard management controller.

[0145] If the baseboard management controller fails to start normally when the first power module of the management board CPLD controls the output of the second power supply to power the flash memory of the baseboard management controller, an error will be logged so that technicians can respond and handle the situation.

[0146] If the baseboard management controller starts normally when the first power module of the management board CPLD controls the output of the second power supply to power the flash memory of the baseboard management controller, then it is determined that the power required for the normal operation of the flash memory of the baseboard management controller is the second power supply, and the steps S703 and subsequent steps are executed.

[0147] The communication method for the baseboard management controller provided in this embodiment can detect startup faults of the baseboard management controller in a timely manner by listening to the watchdog signal of the baseboard management controller and judging whether it outputs a square wave normally within a preset time period, thus ensuring the accuracy of the startup status of the baseboard management controller.

[0148] In some optional embodiments, concurrently with step S702, the substrate management controller communication method further includes:

[0149] Step b1: Pull the reset signal of the substrate management controller low to cause the substrate management controller to reload the firmware in the flash memory.

[0150] like Figure 4As shown, when the baseboard management controller fails to start normally, the first power module is controlled to output the second power supply to power the flash memory of the baseboard management controller. At the same time, the management board CPLD pulls the BMC RST low to reset, that is, pulls the reset signal of the baseboard management controller low, so that the baseboard management controller can reload the firmware in the flash memory when the management board CPLD controls the first power module to output the second power supply to power the flash memory of the baseboard management controller.

[0151] The substrate management controller communication method provided in this embodiment can ensure that the firmware used by the substrate management controller is obtained from the flash memory after the second power supply powers the flash memory of the substrate management controller.

[0152] In some optional implementations, the substrate management controller communication method further includes:

[0153] Step c1: If the working status information indicates that the bus is working normally, determine that the normal working voltage of the bus is the first reference voltage provided by the first bus level, and that the baseboard management controller and the server motherboard are communicating normally.

[0154] The operating status information indicates that the bus is working normally under the first reference voltage, confirming that the bus is an LPC bus, and the baseboard management controller can communicate normally with the CPU of the server motherboard through the LPC bus.

[0155] It is understandable that the operating status information indicates that the bus is working normally under the second reference voltage, confirming that the bus is an eSPI bus, and the baseboard management controller can communicate normally with the PCH of the server motherboard through the eSPI bus.

[0156] The baseboard management controller communication method provided in this embodiment accurately identifies and sets the normal operating voltage of the current bus to the first reference voltage provided by the first bus level, enabling the baseboard management controller to communicate normally with the server motherboard.

[0157] In some optional implementations, the substrate management controller communication method further includes:

[0158] Step d1: In the event of a server motherboard malfunction, the control board management controller records an error log so that the user can handle the server motherboard malfunction based on the error log.

[0159] In the event of a server motherboard malfunction, the management board CPLD notifies the BMC to record an error log, enabling the user to handle the server motherboard malfunction based on the error log, for example, by replacing the server motherboard.

[0160] The baseboard management controller communication method provided in this embodiment records error logs for server motherboard anomalies, which helps technicians quickly locate the cause of the problem and speeds up the repair process.

[0161] In some optional embodiments, concurrently with step S705, the substrate management controller communication method further includes:

[0162] Step e1: Pull down the power-on signal of the server motherboard so that the bus between the baseboard management controller and the server motherboard operates based on the second reference voltage provided by the second bus level.

[0163] Among them, such as Figure 6 As shown, while controlling the second power module to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the second reference voltage, the management board CPLD communicates with the server motherboard CPLD, causing the ME CPLD to pull the PWBTN signal low for a preset duration to perform an ME reset. That is, controlling the server motherboard CPLD to pull the server motherboard's power-on signal low for a preset duration, so that the bus between the baseboard management controller and the server motherboard operates based on the second reference voltage provided by the second bus level.

[0164] The preset duration is set by a technician; for example, the preset duration can be 6 seconds.

[0165] The baseboard management controller communication method provided in this embodiment provides a second reference voltage for the bus between the baseboard management controller and the server motherboard by controlling the second power module to output a second bus level, while simultaneously lowering the power-on signal of the server motherboard. This avoids circuit damage or data corruption during voltage adjustment, enabling the bus between the baseboard management controller and the server motherboard to smoothly transition between different reference voltages and increasing operational safety.

[0166] In some alternative implementations, the monitoring bus data path at a first reference voltage includes:

[0167] The time threshold is determined based on the bus transmission rate.

[0168] Among them, determining the time threshold based on the bus transmission rate includes:

[0169] If the bus transmission rate is lower than the preset transmission rate, a time threshold is determined as the first time threshold; if the bus transmission rate is higher than the preset transmission rate, a time threshold is determined as the second time threshold.

[0170] Understandably, with the first reference voltage, the bus defaults to the LPC bus. With the second reference voltage, the bus defaults to the eSPI bus.

[0171] It should be noted that the first time threshold is greater than the second time threshold. In other words, the higher the transmission rate, the shorter the corresponding time threshold. The preset transmission rate and time thresholds are set by technical personnel.

[0172] If the data path of the bus under the first reference voltage has data transmission within any time threshold, it is determined that there is no data transmission interruption in the data path.

[0173] In other words, if the time threshold is T milliseconds, then if there is data transmission in the data path within each T millisecond, it is determined that there is no data transmission interruption in the data path.

[0174] If no data is transmitted within any time threshold in the data path of the bus under the first reference voltage, it is determined that there is a data transmission interruption in the data path.

[0175] In other words, if there is no data transmission on the data path within any T milliseconds, it is determined that there is a data transmission interruption on the data path.

[0176] The baseboard management controller communication method provided in this embodiment uses different time thresholds based on different bus transmission rates to determine whether there is a data transmission interruption in the data path, thereby improving the accuracy of the judgment on data transmission interruption.

[0177] In related technologies, the management board requirements of different server motherboards can only be met by designing management boards with different eSPI / LPC buses and corresponding power solutions. Similarly, BMC FLASH with different power supply levels also requires different power supply designs and boards. With various combinations of requirements, a large amount of design work and maintenance costs will be generated. Developing management boards with the same functions for different platforms will also lead to problems such as duplication of manpower and waste.

[0178] This embodiment uses eSPI and LPC multiplexed circuitry and power supply, merging the circuitry onto a single management board. The management board is designed with a CPLD monitoring eSPI / LPC signal line, an automatic CPLD identification of the eSPI & LPC buses, and a CPLD wake-up system mechanism, enabling automatic identification of the bus requirements of the main control chips on different server motherboards. Using BMC FLASH adaptive switching power supply lines and logic, the CPLD can automatically identify the BMC startup status, switch power supplies, and perform reset and reload functions on the same board. This shared-board design for different server motherboards saves on manpower and R&D investment while also facilitating subsequent debugging.

[0179] Furthermore, the management board design in this embodiment increases server configuration diversity, offers intelligent identification, is convenient and fast, has wide applicability, saves R&D costs, and increases operability and maintainability. It can also be used in other management board applications and for other product requirements.

[0180] To make the communication method of the baseboard management controller in this embodiment clearer, an Intel X86 platform MB (using eSPI signals to communicate with the BMC) paired with a 1V8 FLASH level management board is used as an example for description.

[0181] AC power-on initially uses a 3V3 level power supply for the FLASH. The management board's CPLD listens to the BMC WDT signal for 2 minutes and finds that the WDT signal fails to output a square wave, determining that the current 3V3 level power supply does not meet the FLASH requirements. The CPLD actively controls the PMIC1 output to switch to a 1V8 level to power the BMC FLASH, and simultaneously performs a reset operation on the BMC, causing it to reload the FLASH firmware. When the CPLD recognizes the WDT signal as a square wave, it indicates that the BMC startup is complete and the logic ends.

[0182] The system defaults to a 3V3 power supply bus. The management board's CPLD monitors the bus and detects unsuccessful handshake signals and abnormal bus data parsing. It then determines that the PLTRST signal is not high, indicating the current input is an eSPI signal, and switches the PMIC2 power supply level to 1V8. Simultaneously, the management board's CPLD communicates with the motherboard's CPLD to reset the motherboard system, causing the controller to re-initiate the handshake. Once the CPLD recognizes a successful handshake and the eSPI bus parsing meets the protocol specifications, the pre-boot preparations are complete, and the logic ends.

[0183] This embodiment also provides a baseboard management controller communication device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0184] This embodiment provides a baseboard management controller communication device, such as... Figure 8 As shown, it includes:

[0185] The first control module 801 is used to control the first power module to output the first power supply to power the flash memory of the baseboard management controller after the server is powered on, wherein the baseboard management controller starts by loading the firmware in the flash memory.

[0186] The second control module 802 is used to control the first power module to output a second power supply to power the flash memory of the baseboard management controller when the baseboard management controller fails to start normally.

[0187] The third control module 803 is used to control the second power module to output a first bus level to provide a first reference voltage for the bus between the baseboard management controller and the server motherboard when the baseboard management controller is started normally, so that the bus operates based on the first reference voltage.

[0188] The monitoring module 804 is used to monitor the operating status information of the bus under the first reference voltage.

[0189] The first determining module 805 is used to determine that the baseboard management controller and the server motherboard cannot communicate normally when the working status information indicates that the bus is malfunctioning. It then controls the second power module to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus can operate based on the second reference voltage.

[0190] In some alternative implementations, the substrate management controller communication device further includes:

[0191] The monitoring module is used to monitor the watchdog signal of the baseboard management controller.

[0192] The second determination module is used to determine that the baseboard management controller is started normally when the watchdog signal outputs a square wave within a preset time period.

[0193] The third determination module is used to determine that the board management controller has not started normally if the watchdog signal does not output a square wave within a preset time period.

[0194] In some alternative implementations, the substrate management controller communication device further includes:

[0195] The first signal pull-down module is used to pull down the reset signal of the substrate management controller so that the substrate management controller can reload the firmware in the flash memory.

[0196] In some alternative implementations, the substrate management controller communication device further includes:

[0197] The fourth determination module is used to determine, under the condition that the working status information indicates that the bus is working normally, the normal working voltage of the bus is the first reference voltage provided by the first bus level, and the baseboard management controller and the server motherboard are communicating normally.

[0198] In some alternative implementations, the monitoring module 804 includes:

[0199] The first monitoring unit is used to monitor the data path of the bus under the first reference voltage.

[0200] The first determining unit is used to determine that the bus has a continuous data path under the first reference voltage when there is no data transmission interruption in the data path.

[0201] The second determining unit is used to determine that there is no continuous data path on the bus under the first reference voltage when there is a data transmission interruption in the data path.

[0202] The first parsing unit is used to parse the data transmitted on the bus when there is a continuous data path on the bus under the first reference voltage, so as to determine whether the data transmitted on the bus meets the bus protocol.

[0203] The third determining unit is used to determine that the bus is working normally when there is a continuous data path on the bus under the first reference voltage and the data transmitted on the bus meets the bus protocol.

[0204] The second parsing unit is used to parse the data transmitted on the bus when there is no continuous data path on the bus under the first reference voltage, so as to determine whether the data transmitted on the bus meets the bus protocol.

[0205] The judgment unit is used to determine whether the server motherboard reset signal is in a high state when there is no continuous data path on the bus under the first reference voltage and the data transmitted on the bus does not meet the bus protocol.

[0206] The fourth determination unit is used to determine if the server motherboard is malfunctioning when the server motherboard reset signal is in a high state.

[0207] The fifth determining unit is used to determine if the bus is malfunctioning when the server motherboard reset signal is in a normal state.

[0208] In some alternative implementations, the substrate management controller communication device further includes:

[0209] The logging module is used to control the baseboard management controller to record error logs in the event of a server motherboard malfunction, so that users can handle the server motherboard malfunction based on the error logs.

[0210] In some alternative implementations, the substrate management controller communication device further includes:

[0211] The second signal pull-down module is used to pull down the power-on signal of the server motherboard so that the bus between the baseboard management controller and the server motherboard operates based on the second reference voltage provided by the second bus level.

[0212] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0213] In this embodiment, the substrate management controller communication device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0214] This invention also provides a computer device having the above-described features. Figure 8 The shown is a communication device for the baseboard management controller.

[0215] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 9 As shown, the computer device includes one or more processors 901, memory 902, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take the 901 processor as an example.

[0216] Processor 901 may be a central processing unit, a network processor, or a combination thereof. Processor 901 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0217] The memory 902 stores instructions executable by at least one processor 901 to cause at least one processor 901 to perform the method shown in the above embodiments.

[0218] The memory 902 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 902 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 902 may optionally include memory remotely located relative to the processor 901, and these remote memories can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0219] The memory 902 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 902 may also include a combination of the above types of memory.

[0220] The computer device also includes a communication interface 903 for communicating with other devices or communication networks.

[0221] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0222] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0223] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A communication method for a baseboard management controller, characterized in that, The method includes: After the server is powered on, the first power module is controlled to output the first power supply to power the flash memory of the baseboard management controller, wherein the baseboard management controller is started by loading the firmware in the flash memory; If the baseboard management controller fails to start normally, the first power module is controlled to output a second power supply to power the flash memory of the baseboard management controller. When the baseboard management controller is started normally, the second power module is controlled to output a first bus level to provide a first reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the first reference voltage; Monitor the operating status information of the bus under the first reference voltage; When the working status information indicates that the bus is malfunctioning, it is determined that the baseboard management controller and the server motherboard cannot communicate normally. The second power module is then controlled to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus operates based on the second reference voltage. The monitoring of the bus's operating status information under the first reference voltage includes: Monitor the data path of the bus under the first reference voltage; If there is no data transmission interruption in the data path, it is determined that the bus has a continuous data path under the first reference voltage; In the event of a data transmission interruption in the data path, it is determined that the bus has no continuous data path under the first reference voltage; When the bus has a continuous data path under the first reference voltage, the data transmitted on the bus is parsed to determine whether the data transmitted on the bus meets the bus protocol. If the bus has a continuous data path under the first reference voltage and the data transmitted by the bus meets the bus protocol, it is determined that the bus is working normally. In the case that there is no continuous data path on the bus under the first reference voltage, the data transmitted on the bus is parsed to determine whether the data transmitted on the bus meets the bus protocol; If there is no continuous data path on the bus under the first reference voltage and the data transmitted on the bus does not meet the bus protocol, determine whether the server motherboard reset signal is in a high state. If the server motherboard reset signal is high, it is determined that the server motherboard is malfunctioning. If the server motherboard reset signal is in a normal state, it is determined that the bus is malfunctioning.

2. The method according to claim 1, characterized in that, After controlling the first power module to output a first power supply to power the flash memory of the substrate management controller and after controlling the first power module to output a second power supply to power the flash memory of the substrate management controller, the method further includes: Monitor the watchdog signal of the baseboard management controller; If the watchdog signal outputs a square wave within a preset time period, it is determined that the baseboard management controller has started normally. If the watchdog signal does not output a square wave within a preset time period, it is determined that the baseboard management controller has not started normally.

3. The method according to claim 1, characterized in that, While controlling the first power module to output a second power supply to power the flash memory of the substrate management controller, the method further includes: Pull the reset signal of the substrate management controller low to cause the substrate management controller to reload the firmware in the flash memory.

4. The method according to claim 1, characterized in that, The method further includes: When the operating status information indicates that the bus is working normally, the normal operating voltage of the bus is determined to be the first reference voltage provided by the first bus level, and the baseboard management controller communicates normally with the server motherboard.

5. The method according to claim 1, characterized in that, The method further includes: In the event of a server motherboard malfunction, the baseboard management controller is controlled to record an error log, enabling the user to handle the server motherboard malfunction based on the error log.

6. The method according to claim 1, characterized in that, While controlling the second power module to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, the method further includes: The power-on signal of the server motherboard is pulled low so that the bus between the baseboard management controller and the server motherboard operates based on a second reference voltage provided by a second bus level.

7. A communication device for a baseboard management controller, characterized in that, The device includes: The first control module is used to control the first power module to output the first power supply to power the flash memory of the baseboard management controller after the server is powered on, wherein the baseboard management controller is started by loading the firmware in the flash memory; The second control module is used to control the first power module to output a second power supply to power the flash memory of the baseboard management controller when the baseboard management controller fails to start normally. The third control module is used to control the second power module to output a first bus level to provide a first reference voltage for the bus between the baseboard management controller and the server motherboard when the baseboard management controller is started normally, so that the bus operates based on the first reference voltage. The monitoring module is used to monitor the operating status information of the bus under the first reference voltage; The first determining module is used to determine that the baseboard management controller and the server motherboard cannot communicate normally when the working status information indicates that the bus is malfunctioning, and to control the second power module to output a second bus level to provide a second reference voltage for the bus between the baseboard management controller and the server motherboard, so that the bus can operate based on the second reference voltage. The monitoring module includes: The first monitoring unit is used to monitor the data path of the bus under the first reference voltage. The first determining unit is used to determine that the bus has a continuous data path under the first reference voltage when there is no data transmission interruption in the data path. The second determining unit is used to determine that there is no continuous data path on the bus under the first reference voltage when there is a data transmission interruption in the data path. The first parsing unit is used to parse the data transmitted on the bus when there is a continuous data path on the bus under the first reference voltage, so as to determine whether the data transmitted on the bus meets the bus protocol. The third determining unit is used to determine that the bus is working normally when there is a continuous data path on the bus under the first reference voltage and the data transmitted on the bus meets the bus protocol. The second parsing unit is used to parse the data transmitted on the bus when there is no continuous data path on the bus under the first reference voltage, so as to determine whether the data transmitted on the bus meets the bus protocol. The judgment unit is used to determine whether the server motherboard reset signal is in a high state when there is no continuous data path on the bus under the first reference voltage and the data transmitted on the bus does not meet the bus protocol. The fourth determining unit is used to determine if the server motherboard is malfunctioning when the server motherboard reset signal is in a high state. The fifth determining unit is used to determine if the bus is malfunctioning when the server motherboard reset signal is in a normal state.

8. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the baseboard management controller communication method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the substrate management controller communication method according to any one of claims 1 to 6.

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