A method for optimizing out-of-order output from cores based on the new generation of Shenwei multi-core processors

Abstract

The present invention relates to a method for optimizing the out-of-order output of slave cores based on a new generation of Shenwei multi-core processors, and belongs to the technical field of electronic information, including: first, selecting one supervisory slave core and 63 computing slave cores from the slave core array, and after the computing slave core calculates the data, the obtained data volume is transmitted to the supervisory slave core through RMA; secondly, the supervisory slave core summarizes the data volume, and transmits the obtained total data volume to the main core through DMA, and the main core constructs a storage array according to the total data volume; at the same time, the supervisory slave core calculates the main memory address according to the data volume, and distributes the obtained main memory address to each computing slave core through RMA broadcast; finally, after the computing slave core obtains the corresponding main memory address, the data stored in the LDM is transmitted to the storage array through DMA. Selecting the method of the present invention for optimization can effectively solve the problem and improve the efficiency of program execution.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic information, and in particular relates to a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor. Background Art

[0002] The computing power of the new generation of Sunway supercomputer is provided by the domestically produced multi-core SW26010pro processor. The architecture of the SW26010pro processor is as follows: Figure 1 As shown in the figure, the processor includes 6 core groups (CG), each of which includes 1 management processing element (MPE, also known as the main core) and 1 computing core cluster (CPE cluster, also known as the slave core array). Each slave core array consists of 64 slave cores (CPE) in an 8×8 mesh format. In the slave core array, each slave core cluster consists of four slave cores, and four adjacent slave cores share a slave core cluster management component and integrate a router. Each core group has its own memory controller (MC), which is connected to 16GB of DDR4 memory with a bandwidth of 51.2GB / s. In the same slave core array, data exchange between slave cores is realized through the remote memory access (RMA) interface. Each slave core has a local data memory (LDM) with a capacity of 256KB. In response to memory access needs, the slave core can access the main memory in a direct discrete manner (i.e., gld / gst); it can also access the main memory in batches through DMA, first moving the data from the main memory to the slave core's quickly accessible local LDM. When the slave core calculates, it only needs to initiate memory access to the LDM.

[0003] The new generation of Sunway supercomputers mainly adopts four heterogeneous parallel methods: master-slave acceleration parallelism, master-slave cooperative parallelism, master-slave asynchronous parallelism, and master-slave dynamic parallelism. Master-slave acceleration parallelism means that in the parallel acceleration of the program, the master core generally focuses on processing the communication, I / O operations and some serial computing tasks of the application, while the computing-intensive tasks are loaded on the slave core for accelerated computing. The slave core is responsible for executing these computing tasks and returning the results to the master core after completion. During the execution of the computing task by the slave core, the master core enters a waiting state until the slave core completes the task; master-slave cooperative parallelism means that the master core and the slave core perform parallel computing as equal individuals, distribute the load according to their respective computing capabilities, and jointly complete the calculation of the core segment; master-slave asynchronous parallelism means that while the slave core is performing accelerated computing, the master core does not wait, but performs other operations such as computing, communication or I / O, thereby improving the computing efficiency of master-slave collaboration; master-slave dynamic parallelism means that the master core is responsible for task allocation, and the slave core is responsible for task computing and writing back the computing results. This parallel method is more suitable for programs where the computing time of the slave core computing task is not fixed or for some tasks in parallel.

[0004] The method of using the Shenwei multi-core processor to optimize a single core group is mainly to start the program through the main core and migrate the hot code segments that can be optimized in parallel in the application to the slave core to achieve the effect of parallel acceleration. When the hot code is running in the slave core, after the slave core completes the calculation task, it needs to transfer the calculation results stored in the LDM to the main memory through discrete memory access (i.e. gld / gst) or DMA. After the main core obtains the data transmitted by the slave core, it continues to execute the subsequent code.

[0005] However, the above method has two problems. First, since the amount of data output by each slave core is unknown before the calculation is completed, and each slave core can only determine its own data amount after the calculation is completed, it is impossible to know the data amount of other slave cores and the output main memory address, resulting in the slave core data cannot be output in the correct order. Second, if the slave core operates according to the logic of transmitting data to the main core once each computing task is completed, it will cause a problem of large communication overhead. If a general optimization method is adopted, for example, 64 arrays can be created in the main memory according to the maximum output of the slave core, the slave core stores the calculation results in the array of the local LDM, and then each slave core outputs to the corresponding main memory array through DMA, and finally the main core creates an array to summarize and store the 64 arrays in order. However, adopting this general optimization method will take up a lot of storage space, resulting in a waste of storage resources, and thus greatly reducing the efficiency of the program. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor.

[0007] The present invention specifically solves the problem that the slave core cannot ensure that data is output in the correct order, successfully reduces the number of communications between the master core and the slave core, improves the utilization rate of storage resources, and applies the method to the slave core acceleration solution.

[0008] Terminology explanation:

[0009] 1. LDM: Local Data Memory (LDM). Each slave core of the Shenwei multi-core processor has a high-speed local data storage space LDM, and the total capacity of LDM is 256KB.

[0010] 2. DMA: Direct Memory Access, initiated by a single slave core, is an operation for batch data transfer between the main memory and the slave core local memory LDM.

[0011] 3. RMA: Remote Memory Access (RMA). In the same slave core array, each slave core can initiate access to other slave cores' LDM through RMA, thereby realizing data transmission between slave cores.

[0012] 4. RMA broadcast: In the same slave core array, each slave core can initiate simultaneous access to a single or multiple slave core LDMs through RMA broadcast, thereby realizing data transmission between slave cores.

[0013] The technical solution of the present invention is:

[0014] A method for optimizing out-of-order output of a slave core based on a new generation of Shenwei multi-core processors, comprising:

[0015] First, one supervisory slave core and 63 computing slave cores are selected from the core array. After the computing slave core calculates the data, the obtained data volume is transmitted to the supervisory slave core through RMA.

[0016] Secondly, the supervisory slave core summarizes the data volume and transfers the total data volume to the master core through DMA. The master core builds a storage array based on the total data volume. At the same time, the supervisory slave core calculates the main memory address based on the data volume and distributes the obtained main memory address to each computing slave core through RMA broadcast.

[0017] Finally, after the calculation slave core obtains the corresponding main memory address, the data stored in the LDM is transferred to the storage array through DMA.

[0018] Preferably according to the present invention, any one of the 16 slave cores No. 18, No. 19, No. 20, No. 21, No. 26, No. 27, No. 28, No. 29, No. 34, No. 35, No. 36, No. 37, No. 42, No. 43, No. 44 and No. 45 is selected as the supervisory slave core.

[0019] Preferably, according to the present invention, after the computing slave core completes the computing task, the obtained data volume is stored in the local LDM, and the data volume is transmitted to the supervision slave core through the RMA.

[0020] Preferably, according to the present invention, the supervisory slave core aggregates the data volume from the 63 computing slave cores, and calculates the data transmission address, i.e., the main memory address, of each computing slave core; the calculation formula is as follows:

[0021] a=b+c;

[0022] a refers to the data transmission address, b refers to the data transmission address of the previous calculation slave core, and c refers to the data volume of the previous calculation slave core.

[0023] Preferably, according to the present invention, the master core constructs a storage array of appropriate capacity according to the total amount of data; the appropriate capacity refers to the capacity of all data that need to be transmitted from the computing slave cores.

[0024] Preferably, according to the present invention, the calculation slave core transfers the amount of data stored in the local LDM to the main memory array, ie, the storage array, through DMA according to the data transmission address.

[0025] Preferably, according to the present invention, the out-of-order optimization method is implemented from the core output through the automation interface STOI;

[0026] The automation interface STOI is divided into a master core part and a slave core part;

[0027] In the slave core part, first, by setting the interface parameters, the slave core is supervised to calculate the total data volume and the data transmission address of the slave core; then, the slave core is supervised to transfer the total data volume to the master core through DMA, and at the same time, the main memory address is transferred to the calculation slave core through RMA;

[0028] In the main core part, the total amount of data from the supervisory slave core is obtained by setting interface parameters, and a storage array is constructed according to the total amount of data to store and calculate the data transmitted by the slave core.

[0029] A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the steps of a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor.

[0030] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor.

[0031] The beneficial effects of the present invention are:

[0032] When optimizing programs on Sunway multi-core processors, when the amount of data output by each slave core cannot be determined in advance, it is usually impossible to simply derive the corresponding output address, which in turn causes the slave core to be unable to output data to the main memory in the correct order. If a general optimization method is used, it will not only cause serious communication overhead problems, but also because the main core blindly applies for the array, it cannot make full use of the array space, resulting in a large amount of storage resources being wasted. For programs that have the above problems, the method of the present invention is selected for optimization, which can effectively solve the problem and improve program execution efficiency. At the same time, the present invention also designs an automation interface STOI (Sunway Thread Output Interface) to facilitate programmers to directly call and use it. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the SW26010pro architecture;

[0034] Figure 2 It is a flowchart of a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor of the present invention;

[0035] Figure 3 This is a schematic diagram of the communication delay between slave core 0 and other slave cores;

[0036] Figure 4 Schematic diagram of regions selected from the nucleus for optimal regulation;

[0037] Figure 5 To solve the out-of-order schematic diagram from the nucleus; DETAILED DESCRIPTION

[0038] The present invention will be further defined below in conjunction with the accompanying drawings and embodiments, but is not limited thereto.

[0039] Example 1

[0040] A method for optimizing out-of-order output of a slave core based on a new generation of Shenwei multi-core processors, comprising:

[0041] First, according to the characteristics of the hardware architecture of the slave core array, one supervisory slave core and 63 computing slave cores are selected from the slave core array. After the computing slave core calculates the data, the obtained data volume is transmitted to the supervisory slave core through RMA.

[0042] Secondly, the supervisory slave core summarizes the data volume and transfers the total data volume to the master core through DMA. The master core builds a storage array based on the total data volume. At the same time, the supervisory slave core calculates the main memory address based on the data volume and distributes the obtained main memory address to each computing slave core through RMA broadcast.

[0043] Finally, after the calculation slave core obtains the corresponding main memory address, the data stored in the LDM is transferred to the storage array through DMA.

[0044] The innovative method of the present invention solves the problem of out-of-order output of slave cores, improves the utilization rate of storage resources of the master core, and reduces the communication overhead between the master and slave cores, thereby greatly improving the execution efficiency of the program. The specific process is as follows: Figure 2 shown.

[0045] Example 2

[0046] The difference between the method for optimizing out-of-order output of a core based on a new generation of Shenwei multi-core processor described in Example 1 is that:

[0047] When selecting a supervisory slave core, the first thing to consider is the communication delay caused by data transmission between the supervisory slave core and the computing slave core, and between the supervisory slave core and the master core.

[0048] According to the characteristics of the hardware architecture of the new generation of Shenwei multi-core processors, the distance between slave core clusters affects the communication delay between slave cores. Selecting different slave cores as supervisory slave cores will produce different communication delays when exchanging data with computing slave cores through RMA. If a slave core is randomly selected as a supervisory slave core, it may cause serious communication overhead. In response to this situation, by performing communication tests on different programs, the communication delay results all show a positive correlation with the distance between slave core clusters. Take the RMA communication test between slave core 0 and other slave cores as an example. Figure 3 As shown, the RMA communication delay between slave core No. 0 and slave cores No. 1, 8, and 9 is 47 beats. When the distance between slave core clusters increases by 1, the communication delay increases by 6 beats.

[0049] Figure 3 and Figure 4 In the example, C0 to C7 represent the column number of the slave core array in the hardware architecture, and C0 represents the slave core array (e.g. Figure 4 0, 8, 16, 24, 32, 40, 48, 56 belong to the first column of the slave array, and C7 is the eighth column of the slave array. R0 to R7 represent the row number of the slave array in the hardware architecture. R0 represents the row in the slave array (as shown in Figure 4 As shown in FIG. 1 , the eight slave cores No. 0, No. 1, No. 2, No. 3, No. 4, No. 5, No. 6, and No. 7 belong to the first row of the slave core array, and R7 is the eighth row of the slave core array.

[0050] If slave core No. 0 is selected as the supervisory slave core and the other slave cores are selected as computing slave cores, the communication delay between the supervisory slave core and the computing slave core will reach 4113 beats, which is not the best choice.

[0051] In order to select the best regulatory core, after continuous testing, we choose Figure 4 In the dashed area shown in the figure, any of the 16 slave cores No. 18, No. 19, No. 20, No. 21, No. 26, No. 27, No. 28, No. 29, No. 34, No. 35, No. 36, No. 37, No. 42, No. 43, No. 44, and No. 45 is used as a supervisory slave core. When communicating with other slave cores, the communication delay between the supervisory slave core and the computing slave core will be reduced to 3729 beats, which is 384 beats less than the communication delay of No. 0 slave core as the supervisory slave core. Therefore, if the Figure 4 Any slave core in the dashed area shown as a supervisory slave core meets the standard of low communication delay, reduces the cost of communication overhead between slave cores, and thus improves the efficiency of the program.

[0052] This communication test method and results are not only applicable to this program, but also have general applicability and can be extended to other similar programs or tasks.

[0053] After the supervisory slave core is selected, there are three problems: first, how to use the supervisory slave core to solve the problem of disordered output of the slave core. Second, the main core and the slave core frequently exchange data through memory access, which causes a large communication overhead. Third, the main core blindly applies for the storage array, resulting in a waste of storage resources. Therefore, the present invention proposes an innovative solution, which aggregates the data volume and allocates addresses through the supervisory slave core to construct a storage array and transmit the data to the main memory array in normal order, thereby solving the problem of disordered data output from the slave core and improving the utilization of storage resources.

[0054] After the computing slave core completes the computing task, it stores the obtained data in the local LDM and transmits the data to the supervisory slave core through RMA.

[0055] The supervisory slave core aggregates the data volume from the 63 computing slave cores and calculates the data transmission address, i.e., the main memory address, for each computing slave core; the calculation formula is as follows:

[0056] a=b+c;

[0057] a refers to the data transmission address, b refers to the data transmission address of the previous calculation slave core, and c refers to the data volume of the previous calculation slave core.

[0058] Specifically, the supervisory core obtains the address of the data transmission of the previous computing core according to the amount of data corresponding to each computing core, combined with the address of the data transmission of the previous computing core. For example, the No. 0 core is the first computing core, and its data transmission address is the pointer of the main memory array (storage array), that is, the transmission address of the No. 0 core = the pointer of the main memory array (storage array), and the No. 1 core is the computing core, and the transmission address of the No. 1 core = the transmission address of the No. 0 core + the data amount of the No. 0 core.

[0059] The main core constructs a storage array of appropriate capacity based on the total amount of data; the appropriate capacity refers to the capacity of the data that needs to be transmitted from all the computing cores.

[0060] The calculation slave core transfers the amount of data stored in the local LDM to the main memory array, i.e., the storage array, through DMA according to the data transfer address. The schematic diagram for solving the out-of-order output of the slave core is as follows Figure 5 shown.

[0061] The out-of-order optimization method is implemented from the core output through the automation interface STOI;

[0062] The automation interface STOI is divided into a master core part and a slave core part;

[0063] In the slave core part, first, by setting the interface parameters, the supervisory slave core calculates the total data volume and the data transmission address of the slave core; since the automation interface void STOI_Slave is oriented to the entire slave core array, this interface is used to implement the different tasks of the supervisory slave core and the calculation slave core. The total data volume is the sum of the data volume of each calculation slave core. Then, the supervisory slave core transfers the total data volume to the master core through DMA, and at the same time, transfers the main memory address to the calculation slave core through RMA;

[0064] In the main core part, the total amount of data from the supervisory slave core is obtained by setting the interface parameters, and a storage array is constructed according to the total amount of data to store the data transmitted by the slave core. In the main core interface, in void STOI_Host(int*all_n) in Table 1, int *all_n is the interface parameter, which is used to receive the total amount of data transmitted from the supervisory slave core. This parameter is set by the programmer, and other programmers can call this interface directly without setting additional parameters.

[0065] The present invention also designs and implements an automation interface STOI (Sunway Thread Output Interface), which is intended to solve the problem of out-of-order output from the core. The implementation of this automation interface STOI reduces the difficulty of programming based on the Sunway supercomputer, and programmers can directly call this interface to solve the problem. The description of the automation interface STOI is shown in Table 1:

[0066] Table 1 Description of automation interface STOI;

[0067] STOI interface Function void STOI_Init(void *func,void*arg) Initialize STOI. void STOI_Host(int *all_n) The programmer calls this interface in the master core to receive the total amount of data from the supervisory slave core, and the master core builds a storage array based on the total amount of data. void STOI_Slave(int *n,int *m,int per_n,int *all_n,double *s_out,athread_rply_t rma_rply) The programmer calls this interface in the slave core, and the computing slave core transfers the data volume to the supervisory slave core. The supervisory slave core calculates the total data volume and the transmission address, and then transfers the total data volume to the master core and broadcasts the transmission address to the corresponding computing slave core. Finally, the computing slave core transfers the data in the local LDM to the main memory array according to the transmission address. void STOI_Finalize() End STOI and release resources.

[0068] Through the implementation of the above method, the present invention has tested the method of this embodiment in a single core group.

[0069] This test takes the nuclear physics nuclear fusion plasma particle orbit Orbit program as an example. Under the condition of inputting the same amount of data, the speedup ratio is tested when the number of iterations of the program is 10, 100, and 1000 respectively.

[0070] The time and speedup ratio of the serial program, the common multi-core optimization program and the patented optimization program are compared. The experimental results show that the method of this embodiment has a significant speedup effect compared with the serial program and the common multi-core optimization program. The specific results and comparisons are shown in the following table.

[0071] Table 2 The running time and speedup ratio of the test program before and after optimization when the number of iterations is 10; Table 2 is as follows:

[0072] Optimization Methods Before optimization (ms) After optimization (ms) Speedup General many-core optimization 500.531 52.583 9.52 This embodiment method optimizes 500.531 13.126 38.13

[0073] Table 3 The running time and speedup ratio of the test program before and after optimization when the number of iterations is 100; Table 3 is as follows:

[0074] Optimization Methods Before optimization (ms) After optimization (ms) Speedup General many-core optimization 5013.118 525.058 9.55 This embodiment method optimizes 5013.118 130.738 38.34

[0075] Table 4 The running time and speedup ratio of the test program before and after optimization when the number of iterations is 1000; Table 4 is as follows:

[0076] Optimization methods Before optimization (ms) After optimization (ms) Speedup General many-core optimization 50130.756 5248.573 9.55 This embodiment method optimizes 50130.756 1305.884 38.39

[0077] The main core calls the STOI interface example as follows:

[0078] / / Call the STOI interface master.c in the main core

[0079] #include "STOI.h"

[0080] int main()

[0081] {

[0082] / / Define the required variables

[0083] / / Initialize the interface

[0084] STOI_Init();

[0085] STOI_Host(int *all_n);

[0086] / / Serial code snippet

[0087] STOI_Finalize();

[0088] return 0;

[0089] }

[0090] An example of calling the STOI interface from the core is as follows:

[0091] / / Call the STOI interface slave.c in the slave core

[0092] #include "STOI.h"

[0093] void func(void *arg)

[0094] {

[0095] / / Define the required variables

[0096] / / Start calculation

[0097] / / The hot part of the program

[0098] / / End of calculation

[0099] STOI_Slave(int *n,int *m,int per_n,int *all_n,double *s_out,athread_rply_t rma_rply);

[0100] return 0;

[0101] }

[0102] Example 3

[0103] A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor as described in Example 1 or 2 are implemented.

[0104] Example 4

[0105] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor as described in Example 1 or 2.

Claims

1. A method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor, characterized in that: include: First, one supervisory slave core and 63 computing slave cores are selected from the core array. After the computing slave core calculates the data, the obtained data volume is transmitted to the supervisory slave core through RMA. Secondly, the supervisory slave core summarizes the data volume and transfers the total data volume to the master core through DMA. The master core builds a storage array based on the total data volume. At the same time, the supervisory slave core calculates the main memory address based on the data volume and distributes the obtained main memory address to each computing slave core through RMA broadcast. Finally, after the calculation slave core obtains the corresponding main memory address, the data stored in the LDM is transferred to the storage array through DMA; Select any one of the 16 slave cores No. 18, No. 19, No. 20, No. 21, No. 26, No. 27, No. 28, No. 29, No. 34, No. 35, No. 36, No. 37, No. 42, No. 43, 44, and No. 45 as the supervisory slave core.

2. According to claim 1, a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processors is characterized in that: After the computing slave core completes the computing task, it stores the obtained data in the local LDM and transmits the data to the supervisory slave core through RMA.

3. According to claim 1, a method for optimizing out-of-order output of a core based on a new generation of Shenwei multi-core processor, characterized in that: The supervisory slave core aggregates the data volume from the 63 computing slave cores and calculates the data transmission address, i.e., the main memory address, for each computing slave core; the calculation formula is as follows: a=b+c; a refers to the data transmission address, b refers to the data transmission address of the previous calculation slave core, and c refers to the data volume of the previous calculation slave core.

4. According to claim 1, a method for optimizing out-of-order output of a core based on a new generation of Shenwei multi-core processor, characterized in that: The main core constructs a storage array of appropriate capacity based on the total amount of data; the appropriate capacity refers to the capacity of the data that needs to be transmitted from all the computing cores.

5. According to claim 1, a method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processors is characterized in that: The calculation slave core transfers the amount of data stored in the local LDM to the main memory array, i.e., the storage array, through DMA according to the data transfer address.

6. A method for optimizing out-of-order output from a core based on a new generation of Shenwei multi-core processor according to any one of claims 1-5, characterized in that: The out-of-order optimization method is implemented from the core output through the automation interface STOI; The automation interface STOI is divided into a master core part and a slave core part; In the slave core part, first, by setting the interface parameters, the slave core is supervised to calculate the total data volume and the data transmission address of the slave core; then, the slave core is supervised to transfer the total data volume to the master core through DMA, and at the same time, the main memory address is transferred to the calculation slave core through RMA; In the main core part, the total amount of data from the supervisory slave core is obtained by setting interface parameters, and a storage array is constructed according to the total amount of data to store and calculate the data transmitted by the slave core.

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