Resource configuration method and device, equipment and storage medium

Abstract

According to the embodiment of the invention, a resource configuration method and device, equipment and a storage medium are provided. The method includes obtaining an indication of a node number of NUMA nodes for a processor slot; based on the number of the nodes, dividing acceleration resources of an accelerator into at least one acceleration resource queue; and causing a plurality of processor cores partitioned to a respective NUMA node to use the at least one acceleration resource queue based on the association by associating the at least one acceleration resource queue to the respective NUMA node contained in the processor slot. Therefore, the availability of the accelerator can be improved.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to the field of computers, and more particularly, to resource configuration methods, apparatuses, devices, and computer-readable storage media. Background Art

[0002] At present, accelerators have been widely used in computing devices. Accelerators can realize a variety of functions, such as artificial intelligence (AI) reasoning, encryption and decryption computing tasks, etc. Compared with the processor core, accelerators can often handle a specific task efficiently, and also have considerable advantages in power consumption and area. Accelerators in computing devices can be scheduled in the following ways: applications can be run on the processor core of the computing device, and the processor core accelerates various tasks or operations in the application by calling the accelerator. Therefore, it is worth paying attention to how the processor core schedules the acceleration resources provided by the accelerator to improve the processing performance of the computing device. Summary of the invention

[0003] In a first aspect of the present disclosure, a resource configuration method is provided. The method includes: obtaining an indication of the number of non-uniform memory access (NUMA) nodes for a processor socket; dividing the acceleration resources of an accelerator into at least one acceleration resource queue based on the number of nodes; and associating at least one acceleration resource queue with a corresponding NUMA node included in the processor socket, so that multiple processor cores divided into the corresponding NUMA node use the at least one acceleration resource queue based on the association.

[0004] In a second aspect of the present disclosure, a resource configuration device is provided. The device includes: an acquisition module configured to acquire an indication of the number of nodes of a non-uniform memory access NUMA node for a processor socket; a division module configured to divide the acceleration resources of the accelerator into at least one acceleration resource queue based on the number of nodes; and a calling module configured to associate at least one acceleration resource queue with a corresponding NUMA node included in the processor socket, so that multiple processor cores divided into the corresponding NUMA node use the at least one acceleration resource queue based on the association.

[0005] In a third aspect of the present disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory, the at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. When the instructions are executed by the at least one processing unit, the device executes the method of the first aspect.

[0006] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and the computer program can be executed by a processor to implement the method of the first aspect.

[0007] It should be understood that the contents described in this content section are not intended to limit the key features or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0009] Figure 1 A schematic diagram showing an example environment in which embodiments of the present disclosure can be implemented;

[0010] Figure 2 A schematic diagram showing a process of a resource configuration method according to some embodiments of the present disclosure;

[0011] Figure 3 A schematic diagram showing the association relationship between NUMA nodes and acceleration resource queues according to some embodiments of the present disclosure;

[0012] Figure 4 A schematic diagram showing a process of an application calling an acceleration resource according to some embodiments of the present disclosure;

[0013] Figure 5 A block diagram showing a resource configuration apparatus according to some embodiments of the present disclosure; and

[0014] Figure 6 A block diagram of a device capable of implementing various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0015] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0016] It should be noted that the titles of any sections / subsections provided herein are not restrictive. Various embodiments are described throughout this article, and any type of embodiment may be included under any section / subsection. In addition, the embodiments described in any section / subsection may be combined in any manner with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0017] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may be included below. The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may be included below.

[0018] As briefly mentioned above, accelerators have been widely used in computing devices. How the processor core schedules the acceleration resources provided by the accelerator to improve the processing performance of the computing device is worthy of attention. At present, processors generally adopt the non-uniform memory access (NUMA) architecture. Under this architecture, different memory devices and processor cores belong to different NUMA nodes. Each NUMA node contains one or more processor cores, and each NUMA node has its own integrated memory controller (IMC). With the improvement of semiconductor process technology and the widespread application of chiplet technology, more and more NUMA nodes need to be split on a single processor socket. That is, multiple processor cores on a single processor socket are split into multiple different NUMA nodes. In this case, how accelerators are used by processor cores in NUMA nodes is worth discussing.

[0019] When the accelerator accesses memory across NUMA nodes, there is a problem of relatively large access latency due to the interconnection limitations between processor sockets or chips (dies). The socket or chip here is the packaging unit of the processor core. Usually, a socket can include multiple chips, and each chip can package multiple processor cores.

[0020] To avoid this problem, the common practice in current computing devices is to configure the corresponding NUMA node for the accelerator and restrict the processor cores that use the accelerator to be in the same NUMA node as the accelerator. In this solution, the accelerator can only be used by the processor cores in the NUMA node to which it belongs, and cannot be used by the processor cores in other NUMA nodes. Therefore, this solution has the problem of limited accelerator usage.

[0021] For example, if multiple processor cores of a processor socket are divided into four NUMA nodes, NUMA0, NUMA1, NUMA2, and NUMA3, and the corresponding NUMA node configured for the accelerator is NUMA1, then only the processor cores in NUMA1 can use the accelerator, and the processor cores in other NUMA nodes cannot use the accelerator.

[0022] In order to solve the problem of limited accelerator usage, there is currently a solution that uses accelerator software to adjust the NUMA configuration and then allocate the use of accelerators so that processor cores in multiple NUMA nodes can use accelerators. This solution requires the configuration of complex software logic. In addition, the software needs to dynamically check the current NUMA configuration of the computing device and then dynamically allocate the use of accelerators based on the NUMA configuration. This further increases the complexity of software configuration.

[0023] In order to at least partially solve the problems existing in the existing solutions, this solution proposes a resource configuration solution. In this solution, the computing device obtains an indication of the number of nodes of the NUMA node for the processor socket. Based on this number of nodes, the acceleration resources of the accelerator are divided into at least one acceleration resource queue, and then by associating at least one acceleration resource queue to the corresponding NUMA node, multiple processor cores divided into the corresponding NUMA node use at least one acceleration resource queue based on the association. In this way, multiple NUMA nodes can use the corresponding acceleration resource queue. On the one hand, the availability of the accelerator can be improved. On the other hand, in this embodiment, the above-mentioned resource configuration can be completed by firmware, thereby reducing the difficulty of accelerator software development.

[0024] Figure 1A schematic diagram of an example environment 100 in which an embodiment of the present disclosure can be implemented is shown. In the environment 100, one or more applications 120 may be installed in a computing device 110. The application 120 may be, for example, an application for file decompression, an application for graphics processing, etc. The embodiments of the present disclosure do not limit the type and number of applications. The application 120 runs on the processor core of the computing device 110. In the embodiments of the present disclosure, the processor architecture of the computing device 110 may adopt the NUMA architecture mentioned above, that is, the multiple processor cores in the processor socket are divided into multiple NUMA nodes.

[0025] In some cases, the application 120 needs to perform tasks such as AI reasoning, encryption and decryption, and the processor core running the application can use an accelerator to perform these tasks. In the embodiment of the present disclosure, the number of accelerators can be one or more. In addition, the accelerator may include an accelerator that operates on data, such as a vector accelerator, an AI accelerator, and the like. The accelerator may also include an accelerator that executes specific algorithms on dedicated hardware, such as an encryption accelerator, a compression accelerator, a graphics accelerator, and the like. The embodiment of the present disclosure does not limit the type and number of accelerators.

[0026] In some embodiments of the present disclosure, an accelerator may be presented as a platform device including multiple acceleration resources. The multiple acceleration resources in an accelerator may be divided into multiple acceleration resource queues.

[0027] The computing device 110 may also present an interface 140 through which the user 130 can perform interactive operations, such as operating the application 120 and the like.

[0028] In some embodiments of the present disclosure, the user 130 can also configure the number of NUMA nodes based on the interface 140 presented by the computing device 110. The computing device 110 can then divide the acceleration resources of the accelerator based on the number of NUMA nodes to obtain multiple acceleration resource queues, and establish an association relationship between the NUMA nodes and the acceleration resource queues so that the NUMA nodes can use the corresponding acceleration resource queues. The specific implementation is described in detail below.

[0029] In environment 100, computing device 110 may be any type of device with computing capabilities, including computing devices or server devices. The computing device may be any type of mobile terminal, fixed terminal or portable terminal, including mobile phones, desktop computers, laptop computers, notebook computers, netbook computers, tablet computers, media computers, multimedia tablets, personal communication systems (PCS) devices, personal navigation devices, personal digital assistants (PDAs), audio / video players, digital cameras / camcorders, positioning devices, television receivers, radio broadcast receivers, e-book devices, gaming devices, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. The server device may include, for example, a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and the like.

[0030] It should be understood that the structure and functionality of environment 100 are described for exemplary purposes only and does not imply any limitation on the scope of the present disclosure.

[0031] Some example embodiments of the present disclosure will be described below with continued reference to the accompanying drawings.

[0032] Figure 2 1 is a flowchart of a process 200 for resource configuration according to some embodiments of the present disclosure. The process 200 may be implemented at the computing device 110. Figure 1 Process 200 is described.

[0033] At block 210 , computing device 110 obtains an indication of a node number for a NUMA node for a processor socket.

[0034] As mentioned above, the processor may adopt a NUMA architecture. In this architecture, multiple processor cores in a processor socket may be divided into multiple NUMA nodes. A NUMA node may include one or more processor cores.

[0035] In some embodiments, the computing device 110 may present an entry for setting the number of nodes of the NUMA node. The entry may be, for example, a configuration item, a configuration menu, etc. presented by the computing device. The user may indicate through the entry the menu to configure the number of nodes of the NUMA node. Accordingly, the computing device 110 may obtain the number of NUMA nodes indicated by the user through the entry.

[0036] In some embodiments, computing device 110 may obtain an indication of the number of NUMA nodes through an entry provided by the firmware. For example, a preset configuration item may be presented in a boot menu of the firmware, and a user may set the preset configuration item to indicate the number of NUMA nodes.

[0037] As an example, the boot mode of the firmware in the embodiment of the present disclosure may be a unified extensible firmware interface (UEFI) mode. The firmware in this mode may also be referred to as UEFI firmware. It is understandable that UEFI is only an example, and the boot mode of the firmware may also be other modes, such as BIOS mode, etc. The embodiment of the present disclosure does not limit this.

[0038] As an example, in the boot menu of the UEFI firmware, the option of how many NUMA nodes each socket contains (NUMA Per Socket, PS) is defined. The user can manually select how many NUMA nodes each socket has, that is, set the number of NUMA nodes that can be divided for each socket. Furthermore, the configuration of the (NUMA Per Socket) option, that is, the number of NUMA nodes can be saved in the Advanced Configuration and Power Interface (ACPI) table.

[0039] In some embodiments, the computing device 110 may further divide multiple processor cores associated with the processor socket into corresponding NUMA nodes based on the node number.

[0040] For example, in response to the value of the NUMA Per Socket option being set to M, the value of M is a positive integer, and the multiple processor cores in the processor socket are divided into M NUMA nodes. The process of specifically dividing the processor cores based on the number of NUMA nodes can be, for example, an average division method, that is, the number of processor cores included in each NUMA node is equal. The present disclosure does not limit the specific configuration implementation of the NUMA node.

[0041] In the embodiment of the present disclosure, the number of nodes obtained by the computing device 110 is not only used to divide the NUMA nodes, but also can be further used to divide the acceleration resources provided by the accelerator and establish an association relationship between the divided acceleration resource queues and the NUMA nodes. For details, see the description of box 220 and box 230 below.

[0042] In block 220 , the computing device 110 divides the acceleration resources of the accelerator into at least one acceleration resource queue based on the number of nodes.

[0043] The accelerator usually uses queues as interfaces for application program interaction, and each queue has corresponding registers for application program operation. In the embodiments of the present disclosure, firmware can be used to present these queues as independent devices.

[0044] In other words, as mentioned above, an accelerator can be presented as a platform device containing multiple acceleration resources. Multiple acceleration resources in an accelerator can be divided into multiple acceleration resource queues and presented as independent devices. In other words, the accelerator can be further divided into smaller granularities.

[0045] In some embodiments, in response to the processor cores in the processor socket being divided into M NUMA nodes, the acceleration resources provided by an accelerator may be divided into N acceleration resource queues. M and N are both positive integers. The value of N may be equal to M. That is, when the number of NUMA nodes is M, the number of acceleration resource queues may also be M. Of course, in some cases, the number of acceleration resource queues N may not be equal to M, for example, N is greater than M or less than M.

[0046] In some embodiments, the number of acceleration resources in each acceleration resource queue obtained by division may be the same or different. For example, when the number of processor cores in each NUMA node is the same, the number of acceleration resources in each acceleration resource queue may also be the same. For another example, when the number of processor cores in each NUMA node is different, the acceleration resource queues may also be divided according to the number of processor cores in different NUMA nodes. Specifically, the number of acceleration resources in the acceleration resource queue may be proportional to the number of processor cores in the associated corresponding NUMA node. In this way, some acceleration resource queues may have more acceleration resources, and then an association may be established between the acceleration resource queue and a NUMA node with a larger number of processor cores. The acceleration resources in the acceleration resource queue may be used by the processor cores in the NUMA node. The disclosed embodiments do not limit the division strategy of the acceleration resources in the acceleration resource queue.

[0047] In some embodiments, the acceleration resources in the accelerator are identified by different numbers. Figure 3 , acceleration resource queue 0-11 means that the acceleration resource queue contains acceleration resources numbered 0-11. Figure 3 The additional resources included in other acceleration resource queues can be deduced in this way and will not be listed in the embodiments of the present disclosure.

[0048] Next, by presenting the accelerator as an acceleration resource queue, different NUMA configurations can be compatible, as shown in block 230 .

[0049] In block 230 , the computing device 110 associates at least one acceleration resource queue with the corresponding NUMA node included in the processor socket, so that the plurality of processor cores divided into the corresponding NUMA node use the at least one acceleration resource queue based on the association.

[0050] By associating the acceleration resource queue with the NUMA node, different NUMA configurations can be compatible. For example, a single socket can be configured to contain 1 NUMA node, 2 NUMA nodes, or 4 NUMA nodes. In each NUMA configuration, the acceleration resource queue can be associated with the corresponding NUMA node, so that the accelerator in each NUMA configuration can be used by all NUMA nodes.

[0051] In some embodiments, the relationship between the acceleration resource queue and the NUMA node can be a one-to-one correspondence. That is, the number of acceleration resource queues is the same as the number of NUMA nodes. An acceleration resource queue can be associated with a NUMA node and used by the processor core in the NUMA node.

[0052] For example, see Figure 3 When the NPS value is 1, that is, the processor socket contains only one NUMA node NUMA0. The acceleration resources in the accelerator are identified by numbers 0-23. They are also divided into an acceleration resource queue 0-23, which can be used by the processor cores in NUMA0. Figure 3 When the NPS value is 2, the processor socket contains two NUMA nodes NUMA0 and NUMA1. Accordingly, the accelerator is also divided into two acceleration resource queues (acceleration resource queues 0-11 and acceleration resource queues 12-23). ​​And acceleration resource queues 0-11 can be used by the processor core of NUMA0, and acceleration resource queues 12-23 can be used by the processor core of NUMA1. Figure 3 330 in the figure. When the NPS value is 4, the processor socket contains four NUMA nodes NUMA0, NUMA1, NUMA2 and NUMA3. Accordingly, the accelerator is also divided into four acceleration resource queues (acceleration resource queues 0-5, acceleration resource queues 6-11, acceleration resource queues 12-17 and acceleration resource queues 18-23). ​​And acceleration resource queues 0-5 can be used by the processor core of NUMA0, acceleration resource queues 6-11 can be used by the processor core of NUMA1, acceleration resource queues 12-17 can be used by the processor core of NUMA2, and acceleration resource queues 18-23 can be used by the processor core of NUMA3.

[0053] It is understandable that in Figure 3In the example, when there are multiple NUMA nodes, the number of processor cores contained in each NUMA node is the same. Accordingly, the number of acceleration resources allocated to each NUMA node is the same. This is just one example of dividing NUMA nodes and allocating acceleration resource queues. In other examples, the number of processor cores in different NUMA nodes may be different, and the number of acceleration resources in the acceleration resource queues allocated to different NUMA nodes may be different. For example, for a NUMA node containing a large number of processor cores, the acceleration resources contained in the acceleration resource queue allocated to the node may also be large. In addition, the correspondence between the NUMA node identifier and the acceleration resource queue identifier is not limited. In other examples, for example, for the case of NPS=4, the acceleration resource queue allocated to the node NUMA0 may also be an acceleration resource queue composed of acceleration resources 6-11.

[0054] In some embodiments, there is not necessarily a one-to-one relationship between the acceleration resource queue and the NUMA node. For example, for a NUMA node that contains more processor cores, two acceleration resource queues may be allocated to the NUMA node. For another example, for some NUMA nodes that contain fewer processor cores, these NUMA nodes can share the same acceleration resource queue. Of course, these NUMA nodes that share the same acceleration resource queue may also need to meet other conditions, such as the access latency when the accelerator accesses the memory of different NUMA nodes needs to meet certain threshold conditions.

[0055] In some embodiments, the computing device 110 may also generate a description of the established association relationship based on the association of at least one acceleration resource queue with the corresponding NUMA node. The description at least indicates the corresponding identifier of at least one acceleration resource queue associated with the corresponding NUMA node. In this way, if at least one core in a certain NUMA node (also referred to as the first node) is to use an accelerator. Then, the first acceleration resource queue assigned to the first node may be determined based on the description. And the at least one core is accelerated using the acceleration resources in the first acceleration resource queue.

[0056] As an example, the ACPI table mentioned above includes a table describing different system information (The Differentiated System Description Table, DSDT). Then the NUMA node information can be configured in the ACPI table, and then the firmware will link the configuration of the association between the identifier of the acceleration resource queue and the identifier of the NUMA node in the DSDT table. This allows software processes running on different NUMA nodes to use the corresponding acceleration resource queue. For example, when the NPS value is 1 by default, the accelerator is allocated to the current NUMA node for use, and a description of the association between the accelerator and the NUMA node is generated in the DSDT.

[0057] In some cases, the number of NUMA nodes can be adjusted. For example, the user changes the value of NPS according to actual needs. Then, in response to the change in the number of NUMA nodes, the association between at least one acceleration resource queue and the corresponding NUMA node is automatically adjusted, and the description is updated based on the adjusted association relationship. In other words, the association relationship is configured in conjunction with the number of NUMA nodes. If the NUMA node is adjusted, the association between the acceleration resource queue identifier and the NUMA node is automatically adjusted without user configuration.

[0058] Still in combination with the above example, when the value of NPS is changed, the association between the identifiers of the NUMA node and the acceleration resource queue in the DSDT table is updated.

[0059] In some embodiments of the present disclosure, the above linkage configuration can be completed by firmware. The firmware can dynamically adjust the association between the accelerator and the NUMA node according to the NUMA configuration of the processor core, which is highly flexible. In addition, no changes need to be made to the accelerator software. In addition, the operating system / accelerator software is shielded from hardware details and configuration changes, and no changes need to be made to ensure that the accelerator is used by the processor core of the appropriate NUMA node, which helps to improve the utilization rate of the device and the performance of the entire system.

[0060] The following describes the process of using the accelerator by the processor core based on the configured affinity.

[0061] In some embodiments of the present disclosure, during the initialization phase of each hardware device in the computing device, the device hardware configuration information is obtained by loading a driver. Based on the device hardware configuration information, the description mentioned above that can indicate the acceleration resource queue identifier and the NUMA node identifier can be obtained. For example, the association relationship recorded in the DSDT table mentioned above. The description is exposed to the application. In this way, if an application wants to use an accelerator for acceleration, it is necessary to call the accelerator through the processor core running the application, and the association relationship between the NUMA node and the acceleration resource can be obtained according to the exposed description to call the accelerator.

[0062] Figure 4 The process of using an accelerator by a processor core running an application is described, and the process includes a device initialization process 410 and an accelerator calling process 420 .

[0063] refer to Figure 4 , the device initialization process 410 is specifically as follows.

[0064] In box 411, during the device initialization process, the device configuration information is obtained. For example, the device configuration information includes the ACPI table and DSDT table mentioned above. The device configuration information can be obtained through a preset function (such as a probe function). In box 412, the association between the acceleration resource queue and the NUMA node is exposed to the application. For example, the association between the acceleration resource queue identifier and the NUMA node identifier in the ACPI table and the DSDT table is exposed to the application.

[0065] For an application program that needs to use acceleration resources, the accelerator calling process 420 is specifically as follows.

[0066] In box 421, the application requests to call the target acceleration resource queue. The target acceleration resource queue can be an acceleration resource determined by the application according to the current task to be performed, for example, an acceleration resource for AI reasoning, etc. In box 422, the application determines the identifier of the NUMA node to which the current processor core belongs. In box 423, it is determined whether the target NUMA node corresponding to the target acceleration resource queue matches the NUMA node to which the current processor core belongs. In box 424, if they match, the application is allowed to call the target acceleration resource queue. If the identifier of the target NUMA node does not match the NUMA node to which the current processor core belongs, the acceleration resource queue associated with the NUMA node to which the current processor core belongs is called.

[0067] Figure 5A schematic structural block diagram of an apparatus 500 for resource configuration according to some embodiments of the present disclosure is shown. The apparatus 500 may be implemented as or included in a computing device 110. Each module / component in the apparatus 500 may be implemented by hardware, software, firmware, or any combination thereof.

[0068] like Figure 5 As shown, the device 500 includes an acquisition module 510, which is configured to obtain an indication of the number of nodes of the NUMA node for the processor socket; the device 500 also includes a division module 520, which is configured to divide the acceleration resources of the accelerator into at least one acceleration resource queue based on the number of nodes; the device 500 also includes a calling module 530, which is configured to associate at least one acceleration resource queue with the corresponding NUMA node included in the processor socket, so that multiple processor cores divided into the corresponding NUMA node use at least one acceleration resource queue based on the association.

[0069] In some embodiments, the acquisition module 510 is further configured to present an entry for setting the number of nodes; and acquire the instruction through the entry.

[0070] In some embodiments, the partitioning module 520 is further configured to partition the plurality of processor cores associated with the processor socket into corresponding NUMA nodes based on the number of nodes.

[0071] In some embodiments, the apparatus 500 further comprises a generating module configured to generate a description of an association relationship based on an association between at least one acceleration resource queue and a corresponding NUMA node, the description at least indicating a corresponding identifier of at least one acceleration resource queue associated with the corresponding NUMA node.

[0072] In some embodiments, the calling module 530 is also configured to, in response to at least one core within a first node in the corresponding NUMA node being about to use an accelerator, determine a first acceleration resource queue in at least one acceleration resource queue that is allocated to the first node based on the description; and enable the at least one core to accelerate using acceleration resources in the first acceleration resource queue.

[0073] In some embodiments, the generation module is further configured to adjust the association between at least one acceleration resource queue and the corresponding NUMA node in response to a change in the number of nodes; and update the above description based on the adjusted association relationship.

[0074] Figure 6 6 shows a block diagram of an electronic device 600 in which one or more embodiments of the present disclosure may be implemented. It should be understood that Figure 6 The electronic device 600 shown is merely exemplary and should not constitute any limitation on the functionality and scope of the embodiments described herein. Figure 6The electronic device 600 shown can be used to implement Figure 1 An electronic device 110.

[0075] like Figure 6 As shown, the electronic device 600 is in the form of a general electronic device. The components of the electronic device 600 may include, but are not limited to, one or more processors or processing units 610, a memory 620, a storage device 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. The processing unit 610 may be an actual or virtual processor and is capable of performing various processes according to a program stored in the memory 620. In a multi-processor system, multiple processing units execute computer executable instructions in parallel to improve the parallel processing capability of the electronic device 600.

[0076] The electronic device 600 typically includes a plurality of computer storage media. Such media may be any accessible media that is accessible to the electronic device 600, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 620 may be a volatile memory (e.g., registers, caches, random access memory (RAM)), a non-volatile memory (e.g., a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 630 may be a removable or non-removable medium, and may include a machine-readable medium, such as a flash drive, a disk, or any other medium, which may be capable of being used to store information and / or data and may be accessed within the electronic device 600.

[0077] The electronic device 600 may further include additional removable / non-removable, volatile / non-volatile storage media. Figure 6 As shown in , a disk drive for reading or writing from a removable, non-volatile disk (e.g., a "floppy disk") and an optical drive for reading or writing from a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to the bus (not shown) by one or more data media interfaces. The memory 620 may include a computer program product 625 having one or more program modules that are configured to perform various methods or actions of various embodiments of the present disclosure.

[0078] The communication unit 640 implements communication with other electronic devices through a communication medium. Additionally, the functions of the components of the electronic device 600 can be implemented with a single computing cluster or multiple computing machines that can communicate through a communication connection. Therefore, the electronic device 600 can operate in a networked environment using a logical connection with one or more other servers, a network personal computer (PC), or another network node.

[0079] The input device 650 may be one or more input devices, such as a mouse, a keyboard, a tracking ball, etc. The output device 660 may be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 600 may also communicate with one or more external devices (not shown) through the communication unit 640 as needed, such as a storage device, a display device, etc., communicate with one or more devices that allow a user to interact with the electronic device 600, or communicate with any device that allows the electronic device 600 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input / output (I / O) interface (not shown).

[0080] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, wherein the computer-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the method described above.

[0081] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices, equipment, and computer program products implemented according to the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0082] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0083] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0084] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple implementations of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some implementations as replacements, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0085] The above descriptions of various implementations of the present disclosure are exemplary, non-exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The selection of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the various implementations disclosed herein.

Claims

1. A resource allocation method, comprising: Get an indication of the node number of the non-uniform memory access NUMA node for a processor socket; Based on the number of nodes, dividing the acceleration resources of the accelerator into at least one acceleration resource queue; as well as By associating the at least one acceleration resource queue with the corresponding NUMA node included in the processor socket, the plurality of processor cores divided into the corresponding NUMA node use the at least one acceleration resource queue based on the association.

2. The method of claim 1, wherein obtaining an indication comprises: Presenting an entry for setting the number of nodes; as well as The instructions are obtained through the entry.

3. The method according to claim 1 or 2, further comprising: The plurality of processor cores associated with the processor sockets are divided into the corresponding NUMA nodes based on the node number.

4. The method according to any one of claims 1 to 3, further comprising: A description of the association relationship is generated based on the association between the at least one acceleration resource queue and the corresponding NUMA node, the description at least indicating a corresponding identifier of the at least one acceleration resource queue associated with the corresponding NUMA node.

5. The method according to claim 4, further comprising: In response to at least one core in a first node of the corresponding NUMA nodes being about to use the accelerator, determining a first acceleration resource queue of the at least one acceleration resource queue that is allocated to the first node based on the description; as well as The at least one core is accelerated by utilizing the acceleration resources in the first acceleration resource queue.

6. The method according to claim 4, further comprising: In response to a change in the number of nodes, adjusting the association between the at least one acceleration resource queue and the corresponding NUMA node; as well as The description is updated based on the adjusted association relationship.

7. A resource allocation device, comprising: An acquisition module configured to obtain an indication of a node number of a non-uniform memory access NUMA node for a processor socket; A division module is configured to divide the acceleration resources of the accelerator into at least one acceleration resource queue based on the number of nodes; as well as The calling module is configured to associate the at least one acceleration resource queue with the corresponding NUMA node included in the processor socket, so that the multiple processor cores divided into the corresponding NUMA node use the at least one acceleration resource queue based on the association.

8. An electronic device, comprising: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 6 when executed by the at least one processing unit.

9. A computer-readable storage medium having a computer program stored thereon, wherein the computer program can be executed by a processor to implement the method according to any one of claims 1 to 6.

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