Circuit layout processing method, device, and program product

Abstract

The present application provides a method, device, and program product for processing a circuit layout. The processing method includes: determining stacking information, layer geometry information, and layer coordinates based on a three-dimensional circuit layout, wherein the stacking information includes: layer sequence number or layer thickness, the layer geometry information includes: layer boundary information and device geometry information, and the layer coordinates are determined based on the layer sequence number or layer thickness; converting at least one first three-dimensional layout layer into a first two-dimensional layout layer based on the layer geometry information; converting the first two-dimensional layout layer into a second two-dimensional layout layer based on the device geometry information; stretching the second two-dimensional layout layer in a preset direction based on the stacking information and the layer coordinates to generate at least one second three-dimensional layout layer; and merging the geometric structure in the second three-dimensional layout layer. The present application has the technical effect of reducing the complexity of geometric processing of circuit layouts and improving the efficiency of geometric processing in the electronic design process.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of electronic design technology, and more particularly to a method, device, and program product for processing a circuit layout. Background Art

[0002] With the continuous development of electronic technology, the complexity of circuit design is increasing day by day. Researchers often use electronic design automation (EDA) software for design and development to solve complex problems in the process of circuit design and verification. Among them, the use of electromagnetic simulation software based on the finite element method plays a vital role in the development of printed circuit boards (PCBs). In particular, when modeling and analyzing printed circuit boards, the processing efficiency and accuracy of geometric components affect the results of subsequent simulation processing. Therefore, the processing efficiency of geometric bodies in circuit layouts of electronic design deserves attention. Summary of the invention

[0003] The disclosed embodiments provide a method, device, and program product for processing a circuit layout, in order to solve the problem of low efficiency in geometric processing of circuit layouts during simulation modeling. In the first aspect, a method for processing a circuit layout is provided, which is used to process a three-dimensional circuit layout, wherein the three-dimensional circuit layout includes at least one first three-dimensional layout layer, and the processing method includes: determining stacking information, layer geometry information, and layer coordinates based on the three-dimensional circuit layout, wherein the stacking information includes: layer sequence number or layer thickness, the layer geometry information includes: layer boundary information and device geometry information, and the layer coordinates are determined based on the layer sequence number or layer thickness; converting at least one first three-dimensional layout layer into a first two-dimensional layout layer based on the layer geometry information; converting the first two-dimensional layout layer into a second two-dimensional layout layer based on the device geometry information; stretching the second two-dimensional layout layer in a preset direction based on the stacking information and the layer coordinates to generate at least one second three-dimensional layout layer; and merging the geometry structure in the second three-dimensional layout layer.

[0004] The above processing method converts the first three-dimensional layout layer into the first two-dimensional layout layer through the stacking information, layer geometry information and layer coordinates of the three-dimensional circuit layout, and performs geometric processing of the shape, structure and other elements of the devices contained in the two-dimensional structure of the first two-dimensional layout layer to generate a second two-dimensional layout layer, and then converts the second two-dimensional layout layer into a second three-dimensional layout layer. Compared with directly operating the three-dimensional structure, the complexity of calculation and graphics processing is reduced, and the efficiency of geometric processing of the three-dimensional circuit layout is improved.

[0005] Optionally, the first two-dimensional layout layer includes a first boundary polygon and a first device polygon; converting at least one first three-dimensional layout layer into a first two-dimensional layout layer based on the layer geometry information includes: determining the first boundary polygon based on the layer boundary information; determining the first device polygon based on the device bottom surface geometry information in the device geometry information.

[0006] Optionally, a second two-dimensional layout layer is stretched in a preset direction based on the stacking information and the layer coordinates to generate at least one second three-dimensional layout layer, including: copying the first boundary polygon and the first device polygon; moving the copied first boundary polygon and the first device polygon along the preset direction based on the layer coordinates and the layer thickness to form a relative boundary polygon and a relative device polygon; closing the space between the first boundary polygon and the relative boundary polygon, and closing the first device polygon and the relative device polygon.

[0007] Optionally, closing the space between the first boundary polygon and the relative boundary polygon, and closing the first device polygon and the relative device polygon, include: constructing a rectangle based on the corresponding edges between the first boundary polygon and the relative boundary polygon; constructing a rectangle based on the corresponding edges between the first device polygon and the relative device polygon.

[0008] Optionally, the device geometric information includes: device geometric position relationship information, the device geometric position relationship information includes: one or more of an inclusion relationship, an overlap relationship, an intersection relationship, or a mutually independent relationship; based on the device geometric information, converting the first two-dimensional layout layer into a second two-dimensional layout layer includes: when the first device polygon and the second device polygon are in an inclusion relationship, setting the included second device polygon as a through hole of the first device polygon; when the first device polygon and the second device polygon are in an overlap relationship, merging the first device polygon and the second device polygon; when the first device polygon and the second device polygon are in an intersection relationship, merging the first device polygon and the second device polygon to generate a third device polygon.

[0009] Optionally, merging the geometric structure in the second three-dimensional layout layer includes: determining structural information of all three-dimensional graphics in the second three-dimensional layout layer, the structural information including: points, lines and surfaces; and merging repeated structural information.

[0010] Optionally, the method further includes: setting identification information based on structural information of all three-dimensional graphics in the second three-dimensional version layer.

[0011] Optionally, the stacking information further includes: layer attributes, and the layer attributes include: metal layer or dielectric layer.

[0012] In a second aspect, a circuit layout processing device is provided, which is used to process a three-dimensional circuit layout, wherein the three-dimensional circuit layout includes at least one first three-dimensional layout layer, and the processing device includes: a determination unit, which is used to determine stacking information, layer geometry information and layer coordinates based on the three-dimensional circuit layout, wherein the stacking information includes: layer sequence number or layer thickness, the layer geometry information includes: layer boundary information and device geometry information, and the layer coordinates are determined based on the layer sequence number and layer thickness; a conversion unit, which is used to convert at least one first three-dimensional layout layer into a first two-dimensional layout layer based on the layer geometry information; the conversion unit is also used to convert the first two-dimensional layout layer into a second two-dimensional layout layer based on the device geometry information; the conversion unit is also used to stretch the second two-dimensional layout layer in a preset direction based on the stacking information and the layer coordinates to generate at least one second three-dimensional layout layer; and a merging unit, which is used to merge the geometry structure in the second three-dimensional layout layer.

[0013] In a third aspect, a computer program product is provided, comprising instructions, and when the instructions are executed by a processor, the processing method provided in the first aspect above is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following is a brief introduction to the drawings used in describing the embodiments of the present disclosure:

[0015] Figure 1 A schematic flow chart of a circuit layout processing method provided in some embodiments of the present application is shown;

[0016] Figure 2 A schematic diagram of the structure of a first two-dimensional layout layer provided in some embodiments of the present application is shown;

[0017] Figure 3 A schematic diagram of the structure of a second two-dimensional layout layer provided in some embodiments of the present application is shown;

[0018] Figure 4 A schematic flow chart of a method for generating at least one second three-dimensional layout layer provided in some embodiments of the present application is shown;

[0019] Figure 5 A schematic diagram showing the structure of 7 first two-dimensional layout layers provided in some embodiments of the present application is shown;

[0020] Figure 6 A schematic diagram showing the structure of 7 layers of the second two-dimensional layout layer provided in some embodiments of the present application is shown;

[0021] Figure 7 A schematic diagram showing the structure of 7 layers of the second three-dimensional version layer provided in some embodiments of the present application is shown;

[0022] Figure 8A schematic diagram of the structure of a circuit layout processing device provided in some embodiments of the present application is shown. DETAILED DESCRIPTION

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other accompanying drawings and other embodiments can be obtained based on these accompanying drawings without creative work. Adjustments and improvements made without departing from the concept of the present application are all within the scope of protection of the present application.

[0024] In order to simplify the drawings, each drawing schematically shows only the parts related to the embodiments, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, some structures or components are schematically depicted in the drawings, and there may be more or fewer similar structures or components in reality.

[0025] With the continuous development of electronic technology, the complexity of circuit design is increasing day by day. R&D personnel often use electronic design automation software for design and development to solve complex problems in the process of circuit design and verification. Among them, the use of electromagnetic simulation software based on the finite element method plays a vital role in the development of printed circuit boards, especially when modeling and analyzing printed circuit boards, the processing efficiency and accuracy of geometric components affect the results of subsequent simulation processing. In the method of finite element analysis of circuit layout, the geometric processing and meshing of circuit layout are important links in the design and simulation process, especially in the electromagnetic field analysis, thermal analysis, signal integrity or power integrity simulation analysis of devices, substrates or traces in the circuit layout. The complexity of the circuit layout determines the processing efficiency of the geometric processing and meshing process, and the above process needs to be optimized. The geometric processing of the circuit layout (such as the geometric processing of the PCB board) refers to the detailed digital modeling of the physical layout of the PCB design (including copper foil, through holes, pads, wiring, etc.), and the assignment of values ​​to the modeled layout from the aspects of structure and electrical parameters, so as to assist the analysis process. The efficiency and accuracy of geometry processing directly affect the efficiency of meshing and the quality of the initial mesh, which in turn has an important impact on the speed and accuracy of simulation. How to improve the speed and accuracy of geometry processing deserves attention.

[0026] The following is a description with reference to the accompanying drawings.

[0027] Please refer to Figure 1, which shows a schematic flow chart of a circuit layout processing method provided in some embodiments of the present application. The processing method is used to process a three-dimensional circuit layout, the three-dimensional circuit layout includes at least one first three-dimensional layout layer, and the processing method includes at least the following steps:

[0028] S110: Determine stacking information, layer geometry information, and layer coordinates based on the three-dimensional circuit layout, wherein the stacking information includes: layer sequence number or layer thickness, the layer geometry information includes: layer boundary information and device geometry information, and the layer coordinates are determined based on the layer sequence number or layer thickness;

[0029] S120: Convert at least one first three-dimensional layout layer into a first two-dimensional layout layer based on the layer geometry information;

[0030] S130: Converting the first two-dimensional layout layer into a second two-dimensional layout layer based on the device geometry information;

[0031] S140: stretching the second two-dimensional layout layer in a preset direction based on the stacking information and the layer coordinates to generate at least one second three-dimensional layout layer;

[0032] S150: Merging the geometric structure in the second three-dimensional version layer.

[0033] In a three-dimensional simulation based on a circuit layout of an actual design, the circuit layout may include one or more three-dimensional layout layers (hereinafter referred to as the first three-dimensional layout layer), and the first three-dimensional layout layer includes three-dimensional graphics formed by structural modeling based on copper foil, pads, pins, wiring and other metal devices or other space-filling dielectric materials that actually exist in the circuit board, and the above three-dimensional graphics often exist independently. For example, the wiring and pads are separately modeled (for example, a structure that is constructed into an independent three-dimensional graphic through multiple grid structures) and then superimposed together, and the two do not form a complete whole. If it is necessary to further form two independent three-dimensional graphics into an overall three-dimensional graphic, the existing technology often performs more complex graphics combination or graphics construction at the three-dimensional level when performing geometric processing. On the one hand, the three-dimensional structure has a complex geometric structure. On the other hand, because the grid modeling method may be used during modeling, such as the use of tetrahedron, hexahedron and other grid modeling, a three-dimensional graphic may contain a large number of other three-dimensional graphics, which further consumes a large amount of computing resources during geometric processing. The embodiments of the present application do not limit the specific implementation method of the circuit layout, and may include a printed circuit board (PCB), a flexible circuit board (FPC), a rigid-flexible PCB (Rigid-Flex PCB), a three-dimensional stacked PCB (3D PCB), a chip scale package (CSP), etc.

[0034] In the present application, based on the three-dimensional circuit layout, the stacking information of the first three-dimensional layout layer actually existing in the three-dimensional circuit layout can be first determined, such as the number of layers, the layer sequence number of the first three-dimensional layout layer, the layer thickness of each first three-dimensional layout layer, and other information. This information can be used to preliminarily define each first three-dimensional layout layer in the three-dimensional circuit layout, so as to accurately locate each component in the subsequent geometric processing process and improve the processing accuracy. In the first three-dimensional layout layer, in addition to the circuit substrate formed by the filling medium, there are other metal devices arranged on the circuit substrate. The layer geometry information can be determined by these three-dimensional structures. For example, the circuit substrate as the device carrier can form a layer boundary, and the layer boundary information can be determined by the size, thickness and other information of the circuit substrate; and the shape, size and other information of the device can determine the device geometry information. In the entire three-dimensional circuit layout, in order to more easily locate the specific position and relative relationship of each component, a coordinate system can be introduced for determination to improve the geometric processing accuracy. For example, a point at the bottom of the first three-dimensional layout layer at the bottom of the three-dimensional circuit layout is set as the coordinate origin, such as a vertex of a rectangular circuit substrate is used as the coordinate origin, and the position information of each point, line, surface, etc. of each three-dimensional figure in the three-dimensional circuit layout is quantified by the layer number and layer thickness, so as to determine the layer coordinates, so as to assist in accurately locating each structure in the process of converting three-dimensional to two-dimensional and then restoring three-dimensional from two-dimensional. For example, the z coordinate of each layer in three-dimensional space is calculated according to the layer number and layer thickness, 0 is used as the starting point of the z coordinate, and the thickness value is accumulated along the positive direction of the z axis to obtain the z coordinate value of each layer.

[0035] After determining the stacking information, layer geometry information and layer coordinates, the first three-dimensional layout layer can be converted into a first two-dimensional layout layer. In the first two-dimensional layout layer, the boundaries formed by the circuit substrate and the device shape can be uniformly reduced in dimension for processing without specifically distinguishing them, such as using the bottom shape of the circuit substrate or the device as the basis for the dimension reduction graphics, or the side shape, or the projection under a uniform viewing angle at a certain angle, such as the upper projection or the side projection. However, in the first two-dimensional layout layer, there may be overlaps of geometric contents such as points, lines, surfaces or bodies between multiple devices, and these overlapping structures are also the key factors causing the complexity of the three-dimensional level processing when performing geometric processing at the three-dimensional level. Therefore, the first two-dimensional layout layer can be further adjusted based on information such as the positional relationship between devices in the device geometry information, and converted into a second two-dimensional layout layer, and the positional relationship between devices can be further simplified, such as forming interconnected devices into a complete whole, or forming overlapping devices into a new whole. Compared with three-dimensional processing, two-dimensional geometric operations reduce one processing dimension, which can reduce the complexity of geometric processing. Compared with directly processing the positional relationship at the three-dimensional level, it is more convenient, and the complexity of calculation and graphics processing is greatly reduced, which is conducive to improving the efficiency of geometric processing. After completing the geometric processing at the two-dimensional level, each second two-dimensional layout layer is converted into a three-dimensional structure (hereinafter referred to as the second three-dimensional layout layer). Compared with some devices in the first three-dimensional layout layer, the converted second three-dimensional layout layer has completed the geometric processing process such as merging or cutting. Finally, all independent three-dimensional structures are merged to form a complete three-dimensional circuit layout, providing design support for finite element simulation design and other links in the electronic design process. The above process of converting the three-dimensional structure into a two-dimensional structure avoids the direct geometric processing of the three-dimensional structure, reduces the complexity of the geometric processing and the calculation requirements, and can effectively improve the efficiency of the geometric processing in the electronic design process. The stacking information also includes: layer attributes, wherein the layer attributes may include metal layers and dielectric layers. The metal layer can be placed with metal devices such as copper foil, pads, pins, wiring, etc., and other spaces within the layer boundary range are filled with dielectric materials to form a circuit substrate. When there is a through-layer structure such as a through hole, a through hole can be set at the corresponding position in the dielectric material and the through hole structure can be placed in the through hole. The property division of the metal layer and the dielectric layer can facilitate the subsequent geometric processing to simplify the geometric operation of the dielectric layer.

[0036] In some embodiments of the present application, the first two-dimensional layout layer includes a first boundary polygon and a first device polygon; converting at least one first three-dimensional layout layer into the first two-dimensional layout layer based on the layer geometry information includes:

[0037] determining a first boundary polygon based on the layer boundary information;

[0038] A first device polygon is determined based on device bottom surface geometric information in the device geometric information.

[0039] Please refer to Figure 2 , which shows a structural schematic diagram of a first two-dimensional layout layer provided in some embodiments of the present application. In the first two-dimensional layout layer, the circuit substrate in the original three-dimensional circuit layout determines the first rectangular boundary polygon R based on the layer boundary information, such as the bottom surface of the circuit substrate, and determines the device polygon set S based on the device bottom surface geometric information in the device geometric information. In the first two-dimensional layout layer, the circuit substrate of the electrical component (such as a metal device) and the device carrier may be included, wherein the circuit substrate defines the boundary in the layout. Therefore, when the first three-dimensional layout layer is converted into the first two-dimensional layout layer, the overall shape of the circuit substrate can be used as the boundary for dimensionality reduction, and the first boundary polygon is determined based on the layer boundary information such as the boundary size and boundary shape, such as the bottom surface shape and size of the circuit substrate as the basis to form the first boundary polygon. The independent device can determine the first device polygon based on the bottom surface geometric information such as the bottom surface shape and size of the bottom surface of the device. For example, when the bottom surface of the routing is a rectangle, the first device polygon formed based on the rectangle and the length and width of the rectangle as the bottom surface geometric information is a rectangle. The polygon may include a figure with a certain curvature, such as an ellipse, a circle, or an irregular polygon, such as a star or other shapes, or an irregular figure composed of a certain curvature and straight lines. The above figures can be determined based on the bottom shape of the device.

[0040] In some embodiments of the present application, the device geometric information includes: device geometric position relationship information, the device geometric position relationship information includes: one or more of an inclusion relationship, an overlap relationship, an intersection relationship, or a mutual independence relationship; based on the device geometric information, converting the first two-dimensional layout layer into the second two-dimensional layout layer includes:

[0041] When the first device polygon and the second device polygon are in a containment relationship, setting the contained second device polygon as a through hole of the first device polygon;

[0042] When the first device polygon and the second device polygon are in a coincident relationship, merging the first device polygon and the second device polygon;

[0043] When the first device polygon and the second device polygon are in an intersecting relationship, the first device polygon and the second device polygon are merged to generate a third device polygon.

[0044] When the first two-dimensional layer is geometrically processed, due to the positional relationship between the devices, the two-dimensional graphics of these devices can be further processed to form a complete plane graphic. The inclusion relationship can be that the graphic B exists within the boundary range of the graphic A, and the graphic B does not exceed the boundary range of the graphic A; the coincidence relationship can be that the boundary ranges of the graphics A and the graphics B completely overlap; the intersection relationship can be that there are partial ranges of graphics A and B belonging to each other, for example, the graphic A includes the first area and the second area, the first area belongs to both the graphic A and the graphic B, and the second area only belongs to the graphic A; the mutual independence relationship is that there is no overlapping area between the graphics A and the graphics B. The first two-dimensional layer may contain one or all of the above relationships. When processing, for example, when the first device polygon P1 contains the second device polygon P2, the second device polygon P2 is set as the through hole (hole) of the first device polygon P1, and the second device polygon P2 is not processed; when the first device polygon P1 and the second device polygon P2 coincide, they are merged; when the first device polygon P1 and the second device polygon P2 intersect, the first device polygon P1 and the second device polygon P2 are merged to generate a new third device polygon P3, and the rest are not processed. The two-dimensional geometric operations used mainly include: plane addition (merging), plane subtraction (setting holes), plane intersection (judging geometric relationships), etc. Please refer to Figure 3 , which shows a schematic diagram of the structure of a second two-dimensional layout layer provided in some embodiments of the present application. Figure 2 The structural diagram of Figure 3 The device polygons with the above relationship have been subjected to corresponding graphic operations, generating a new device polygon set S1.

[0045] In some embodiments of this application, please refer to Figure 4 , which shows a flow chart of a method for generating at least one second three-dimensional layout layer provided in some embodiments of the present application, comprising at least the following steps:

[0046] S410: Copying the first boundary polygon and the first device polygon;

[0047] S420: moving the copied first boundary polygon and the first device polygon along a preset direction based on the layer coordinates and the layer thickness to form a relative boundary polygon and a relative device polygon;

[0048] S430: closing the space between the first boundary polygon and the opposite boundary polygon, and closing the first device polygon and the opposite device polygon.

[0049] In the aforementioned process of reducing the dimension of the three-dimensional circuit layout to the two-dimensional circuit layout, the dimension reduction size is determined based on the layer coordinates and the layer thickness. Therefore, in the process of converting from the second two-dimensional layout layer to the second three-dimensional layout layer, in order to ensure the accuracy of the conversion, an accurate conversion can be performed based on the layer coordinates and the layer thickness. The first boundary polygon is copied and moved to form a relative boundary polygon, and the first device polygon is copied and moved to form a relative device polygon. However, a closed three-dimensional figure has not yet been formed between the two planes. Therefore, a plane figure can be constructed along the space between the first boundary polygon and the corresponding relative boundary polygon to be closed. For example, in some embodiments of the present application, the space between the first boundary polygon and the relative boundary polygon is closed, and the first device polygon and the relative device polygon are closed, including: constructing a rectangle based on the corresponding edges between the first boundary polygon and the relative boundary polygon; constructing a rectangle based on the corresponding edges between the first device polygon and the relative device polygon.

[0050] In some embodiments of the present application, step S150 of merging the geometric structure in the second three-dimensional version layer includes at least the following steps:

[0051] Determine the structural information of all three-dimensional graphics in the second three-dimensional version layer, the structural information including: points, lines and surfaces;

[0052] Merge duplicate structural information.

[0053] In order to ensure the uniqueness of the points, lines, surfaces and other elements in the three-dimensional graphics in the generated second three-dimensional layout layer, so as to improve the accuracy and efficiency of subsequent simulation processes such as electromagnetic finite element calculations, we can first find the intersection points, lines or surfaces between the planes, such as the first boundary polygon, the relative boundary polygon and the rectangle constructed between the three plane figures. The overlapping geometric elements, taking the rectangle as an example, include: the upper and lower sides of the rectangle and the upper and lower vertices of the rectangle. Therefore, the edges of the rectangle overlapping with the first boundary polygon, the edges of the rectangle overlapping with the relative boundary polygon, and the vertices involved in the two overlapping edges can be merged to achieve the uniqueness of the three-dimensional graphics geometric elements in the second three-dimensional layout layer.

[0054] In some embodiments of the present application, it also includes: setting identification information based on the structural information of all three-dimensional graphics in the second three-dimensional layout layer. For example, after merging the points, lines, and surfaces that appear repeatedly between the three plane graphics of the first boundary polygon, the relative boundary polygon, and the rectangle constructed between the two, the merged points, lines, and surfaces can be numbered, and a mapping relationship between the numbers and the points, lines, and surfaces can be established. Then, the vertices, boundary curves, boundary surfaces, and other elements on the three-dimensional graphics are matched one by one with the numbers, and the points, lines, and surfaces of each three-dimensional graphics in the entire second three-dimensional layout layer are merged.

[0055] Please refer to Figure 5 , which shows a schematic diagram of the structure of the 7-layer first two-dimensional layout layer provided in some embodiments of the present application. The schematic diagram is determined based on the 7-layer three-dimensional circuit layout, and the 7-layer first three-dimensional layout layer is converted into 7-layer first two-dimensional layout layers based on the stacking information, layer geometry information and layer coordinates to form the first three-dimensional layout layers L1-L7. Figure 5 In the circuit board and its components such as wiring, copper foil, pads, pins, etc., all structures are converted into two-dimensional structures. Figure 5 In the first three-dimensional layout layer L7, there is an intersection relationship between the first structure J1 and the second structure J2. Therefore, when the first two-dimensional layout layer is converted into the second two-dimensional layout layer, the first structure J1 and the second structure J2 can be combined to form a third structure J3. Please refer to Figure 6 , which shows a schematic diagram of the structure of 7 second two-dimensional layout layers provided in some embodiments of the present application, after converting the first two-dimensional layout layer into the second two-dimensional layout layer based on the device geometry information, Figure 3 The first structure J1 and the second structure J2 are combined to form Figure 4 The third structure J3 in the figure forms a complete and closed two-dimensional figure. Figure 7 A schematic diagram of the structure of the 7-layer second three-dimensional version layer provided in some embodiments of the present application is shown in FIG. Figure 6 On the basis of the stacking information and the layer coordinates, the seven second two-dimensional layout layers are stretched in the z-axis direction to generate seven second three-dimensional layout layers.

[0056] Based on the same technical concept, this application also provides a circuit layout processing device, please refer to Figure 8 , which shows a schematic diagram of the structure of a circuit layout processing device provided in some embodiments of the present application, which is used to process a three-dimensional circuit layout, the three-dimensional circuit layout includes at least one first three-dimensional layout layer, and the processing device 800 includes: a determination unit 810, used to determine stacking information, layer geometry information and layer coordinates based on the three-dimensional circuit layout, wherein the stacking information includes: layer sequence number or layer thickness, the layer geometry information includes: layer boundary information and device geometry information, and the layer coordinates are determined based on the layer sequence number and the layer thickness; a conversion unit 820, used to convert at least one first three-dimensional layout layer into a first two-dimensional layout layer based on the layer geometry information; the conversion unit 820 is also used to convert the first two-dimensional layout layer into a second two-dimensional layout layer based on the device geometry information; the conversion unit 820 is also used to stretch the second two-dimensional layout layer in a preset direction based on the stacking information and the layer coordinates to generate at least one second three-dimensional layout layer; a merging unit 830, used to merge the geometry structure in the second three-dimensional layout layer.

[0057] The division of the above units is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. In addition, the above units can be implemented in the form of a processor calling software; for example, the signal processing device includes a processor, the processor is coupled to a memory, and instructions are stored in the memory. The processor calls the instructions stored in the memory to implement any of the above signal processing methods or realize the functions of each unit, wherein the processor is, for example, a general-purpose processor, such as a CPU, and the memory is a memory in the signal processing device or a memory outside the signal processing device. Or, the above units can be implemented in the form of hardware circuits, and the functions of some or all units can be realized by designing the hardware circuits. The hardware circuit can be understood as one or more processors; for example, the hardware circuit includes an application-specific integrated circuit (ASIC), and the functions of some or all units above can be realized by designing the logical relationship of the components in the circuit; for another example, the hardware circuit can be implemented by a programmable logic device (PLD), for example, it can include a large number of logic gate circuits, and the logical relationship between the logic gate circuits is configured by a configuration file, so as to realize the functions of some or all units above. All units of the above signal processing device may be implemented entirely in the form of a processor calling a program, or entirely in the form of a hardware circuit, or partially in the form of a processor calling a program and the rest in the form of a hardware circuit.

[0058] Based on the same technical concept, the present application also provides a computer program product, including instructions, when the instructions are executed by a processor, the processing method provided in the first aspect above is executed.

[0059] A processor is a circuit with the ability to process signals. For example, a processor includes a circuit with the ability to read and run instructions, such as a CPU, a microprocessor, a graphics processing unit (GPU) or a digital signal processor (DSP). For another example, a processor can be implemented through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit is fixed or reconfigurable. For example, a processor includes a hardware circuit implemented by an ASIC or PLD, such as a hardware circuit implemented by a field programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document to implement the hardware circuit configuration can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. For another example, a processor includes a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as one or more of a neural network processing unit (NPU), a tensor processing unit (TPU), or a deep learning processing unit (DPU).

[0060] It can be seen that each unit in the above processing device 800 can be one or more processors (or processing circuits) configured to implement the above method, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0061] In addition, all or part of the units in the above signal processing device can be integrated together, or can be implemented independently. In one implementation, these units are integrated together and implemented in the form of a system on a chip (SOC). The SOC may include at least one processor for implementing any of the above signal processing methods or implementing the functions of the above signal processing devices.

[0062] The present disclosure does not limit the type of memory. For example, the memory may include a read-only memory (ROM) or a random access memory (RAM). For example, it may include a non-volatile memory or a volatile memory. For example, it may include an on-chip storage resource or an off-chip storage resource. ROM includes, for example, a mask ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash ROM, etc.; RAM includes, for example, a static random-access memory (SRAM) or a dynamic random-access memory (DRAM), etc. On-chip storage resources refer to storage circuits integrated inside the chip, which are integrated with other circuits of the chip (such as processing circuits) to provide storage space for the chip, such as static random access memory (SRAM) resources on the chip, or space resources of configuration registers on the chip, etc. Off-chip storage resources refer to independent storage circuits or chips, such as off-chip double data rate synchronous dynamic RAM (DDRSDRAM, DDR for short), etc.

[0063] In the present disclosure, the term "plurality" may include two or more than two. The term "or" is used to describe the relationship between associated objects, which represents non-exclusive inclusion. For example, "A or B" may include: "A alone", "B alone", or "A and B", where "A" and "B" may include a single object or multiple objects. For another example, "A, B or C" and "A, B and C" may include: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B and C", where "A", "B" and "C" may include a single object or multiple objects. In addition, " / " in the present disclosure is used to represent the "or" relationship between the previously associated objects.

[0064] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A method for processing a circuit layout, characterized in that: Used for processing a three-dimensional circuit layout, the three-dimensional circuit layout includes at least one first three-dimensional layout layer, and the processing method includes: Determine stacking information, layer geometry information and layer coordinates based on the three-dimensional circuit layout, wherein the stacking information includes: layer sequence number or layer thickness, the layer geometry information includes: layer boundary information and device geometry information, and the layer coordinates are determined based on the layer sequence number or the layer thickness; Converting the at least one first three-dimensional layout layer into a first two-dimensional layout layer based on the layer geometry information, wherein the first two-dimensional layout layer includes a first boundary polygon and a first device polygon, including: determining the first boundary polygon based on the layer boundary information; determining the first device polygon based on the device bottom surface geometry information in the device geometry information; Convert the first two-dimensional layout layer into a second two-dimensional layout layer based on the device geometric information; The second two-dimensional layout layer is stretched in a preset direction based on the stacking information and the layer coordinates to generate at least one second three-dimensional layout layer, including: copying the first boundary polygon and the first device polygon; moving the copied first boundary polygon and the first device polygon along the preset direction based on the layer coordinates and the layer thickness to form a relative boundary polygon and a relative device polygon; closing the space between the first boundary polygon and the relative boundary polygon, and closing the first device polygon and the relative device polygon; Merge the geometry in the second 3D version layer.

2. The processing method according to claim 1, characterized in that: The closing of the space between the first boundary polygon and the relative boundary polygon, and the closing of the first device polygon and the relative device polygon, comprises: constructing a rectangle based on the corresponding sides between the first boundary polygon and the relative boundary polygon; A rectangle is constructed based on corresponding sides between the first device polygon and the opposing device polygon.

3. The processing method according to claim 2, characterized in that: The device geometric information includes: device geometric position relationship information, and the device geometric position relationship information includes: one or more of a containment relationship, a coincidence relationship, an intersection relationship, or a mutual independence relationship; The converting the first two-dimensional layout layer into a second two-dimensional layout layer based on the device geometric information includes: When the first device polygon and the second device polygon are in the inclusion relationship, setting the included second device polygon as a through hole of the first device polygon; When the first device polygon and the second device polygon are in the overlap relationship, merging the first device polygon and the second device polygon; When the first device polygon and the second device polygon are in the intersection relationship, the first device polygon and the second device polygon are merged to generate a third device polygon.

4. The processing method according to claim 3, characterized in that: The merging of the geometric structure in the second three-dimensional version layer comprises: Determine structural information of all three-dimensional graphics in the second three-dimensional layer, wherein the structural information includes: points, lines and surfaces; The repeated structural information is merged.

5. The processing method according to claim 4, characterized in that: Also includes: The identification information is set based on the structural information of all three-dimensional graphics in the second three-dimensional version layer.

6. The processing method according to any one of claims 1 to 5, characterized in that: The stacking information further includes: layer attributes, and the layer attributes include: metal layer or dielectric layer.

7. A circuit layout processing device, characterized in that: Used to process a three-dimensional circuit layout, the three-dimensional circuit layout includes at least one first three-dimensional layout layer, the processing device includes: A determination unit, configured to determine stacking information, layer geometry information and layer coordinates based on the three-dimensional circuit layout, wherein the stacking information includes: layer sequence number or layer thickness, the layer geometry information includes: layer boundary information and device geometry information, and the layer coordinates are determined based on the layer sequence number and the layer thickness; a conversion unit, configured to convert the at least one first three-dimensional layout layer into a first two-dimensional layout layer based on the layer geometry information; The conversion unit is further used to convert the first two-dimensional layout layer into a second two-dimensional layout layer based on the device geometric information; The conversion unit is further used to stretch the second two-dimensional layout layer in a preset direction based on the stacking information and the layer coordinates to generate at least one second three-dimensional layout layer; A merging unit is used to merge the geometric structure in the second three-dimensional version layer.

8. A computer program product comprising instructions, characterized in that When the instruction is executed by the processor, the processing method according to any one of claims 1 to 6 is executed.

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