Hierarchical clock tree modeling method, device, equipment and storage medium

Abstract

The present application discloses a hierarchical clock tree modeling method, device, equipment and storage medium, and relates to the field of netlist files. Obtain a netlist file, start from the top-level module and traverse all instances layer by layer inward, determine all custom modules and set modules to be processed; take the tree node set by the top-level module as the node to be processed, traverse all tree wirings and tree ports under it; traverse all set nodes to be processed in turn, traverse all tree wirings and tree ports, and determine all child nodes layer by layer; create a tree node table, wiring table, and port table based on the determined nodes to be processed, and establish a wiring link table according to the signal path; based on the established table, along the top-level entrance of the clock, perform clock modeling according to the hierarchical structure. Using this design method to sample the clock, the sampling signal retains the hierarchical structure of the original netlist. Inserting a probe during debugging can quickly find the sampling clock and sampling signal, reduce the search time, and improve work efficiency.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of netlist files, and in particular to a hierarchical clock tree modeling method, apparatus, device and storage medium. Background Art

[0002] In recent years, the scale of integrated circuits has become larger and larger. The application of large-scale digital circuits with billions or even tens of billions of gates will become more and more common, and the corresponding auxiliary verification needs will become increasingly common. As the complexity of users' DUTs increases, the time consumption of software simulation increases sharply, and the need for hardware online insertion of probes to sample signals becomes more and more obvious. The probe needs to be inserted into the Net of the sampled signal, and the sampling clock needs to be connected to trigger the output of the sampled signal. Therefore, if users want to sample the signals they are interested in, they also need to find the clock nodes that drive the output of the sampled signal. In order to find these clock nodes, it is necessary to model the clock tree.

[0003] In related technologies, clock tree modeling is based on a flattened structure. The flattened structure does not pay attention to the hierarchical structure, ignores the custom modules, and only pays attention to the FPGA primitives, placing the FPGA primitives on the same layer, usually under the top-level module. This loss of the hierarchical structure will cause three problems: 1. The position of the sampling signal Net (node) will change; 2. The Net in the custom module will be deleted; 3. The Net with the same name in different modules will conflict. These three problems lead to differences in the clock tree structure and the netlist structure. These differences make it very difficult, cumbersome and time-consuming to find the sampling signal and sampling clock.

[0004] The problems caused by the flattening structure change can be solved by retaining the hierarchical clock modeling. In this way, the hierarchical structure and connection relationship of the clock signal in the modeled clock tree will be consistent with that in the netlist, making it quick and convenient to find the sampling signal and sampling clock. Summary of the invention

[0005] The embodiments of the present application provide a hierarchical clock tree modeling method, apparatus, device and storage medium to solve the problem of difficulty in finding sampling signals and sampling clocks caused by clock tree modeling with a flat structure in related technologies.

[0006] On the one hand, the present application provides a hierarchical clock tree modeling method, the method comprising:

[0007] Obtain a netlist file, set the top-level module as the module to be processed, traverse all instances under the module to be processed, determine the custom module according to the traversed instance type, and set the custom module as the module to be processed; traverse all instances under the set module to be processed in turn, determine all custom modules and set the module to be processed layer by layer;

[0008] The tree node TreeNode set by the top-level module is used as the node to be processed, all the tree connections TreeNet and tree ports TreePort under the node to be processed are traversed, the association relationship is marked, and all the child nodes of the current TreeNode to be processed are set as the nodes to be processed; all the set nodes to be processed are traversed in turn, all the TreeNet and TreePort therein are traversed in turn, all the child nodes therein are determined layer by layer, and they are determined as the nodes to be processed;

[0009] Based on the identified nodes to be processed and the association between TreeNet and TreePort, a tree node TreeNode table, a tree wiring TreeNet table, a tree port TreePort table are created, and a wiring link NetChain table is established according to the signal path of the netlist structure;

[0010] Read the established TreeNode table, TreeNet table, TreePort table, and NetChain table, and perform clock modeling according to the hierarchical structure along the top-level entrance of the clock.

[0011] Specifically, determining the custom module according to the traversed instance type includes:

[0012] All instances under the module to be processed are traversed in sequence. When the traversed instance is an FPGA primitive, the traversal is terminated; when the traversed instance is a custom module, the custom module is set as the module to be processed.

[0013] Specifically, constructing the TreeNode table includes:

[0014] The top-level module is set as the root node of the hierarchy, the custom module is the middle node, and the FPGA primitive is the leaf node;

[0015] Each instance is mapped to a TreeNode. Different TreeNodes are labeled with the same or different names. Each TreeNode records the corresponding parent node and child node.

[0016] Each TreeNode records the Pin / Port to which it belongs, which is recorded and stored in the port information memory in the form of a TreePort structure; each TreeNode records the wiring Net to which it belongs, which is recorded and stored in the wiring information memory in the form of a TreeNet structure.

[0017] On the other hand, the present application provides a hierarchical clock tree modeling device, the device comprising:

[0018] The first setting module is used to obtain a netlist file, set the top-level module as a module to be processed, traverse all instances under the module to be processed, determine a custom module according to the traversed instance type, and set the custom module as the module to be processed; traverse all instances under the set module to be processed in turn, determine all custom modules layer by layer, and set the module to be processed;

[0019] The second setting module is used to take the tree node TreeNode set by the top-level module as the node to be processed, traverse all the tree connections TreeNet and tree ports TreePort under the node to be processed, mark the association relationship, and set all the child nodes of the current TreeNode to be processed as the nodes to be processed; traverse all the set nodes to be processed in turn, traverse all the TreeNets and TreePorts therein in turn, determine all the child nodes therein layer by layer, and determine them as the nodes to be processed;

[0020] A table building module is used to create a tree node TreeNode table, a tree wiring TreeNet table, a tree port TreePort table based on the identified nodes to be processed and the association relationship between TreeNet and TreePort, and to establish a wiring link NetChain table according to the signal path of the netlist structure;

[0021] The clock modeling module is used to read the established TreeNode table, TreeNet table, TreePort table, and NetChain table, and perform clock modeling according to the hierarchical structure along the top-level entrance of the clock.

[0022] On the other hand, the present application provides a computer device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the hierarchical clock tree modeling method described in the above aspects.

[0023] On the other hand, the present application provides a computer-readable storage medium, wherein the readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the hierarchical clock tree modeling method described in the above aspects.

[0024] The beneficial effects brought about by the technical solution provided by the embodiment of the present application include at least: the present application traverses the entire netlist structure, starting from the top-level module, traverses layer by layer to identify the custom module type therein, and uses the tree nodes of all detected custom modules as subsequent nodes to be processed, traverses the tree ports and internal child nodes inward, establishes a data table according to the relationship between each node, wiring, port and pin, and uses this as the basis for subsequent clock modeling. This method retains the hierarchical structure and connection relationship of the clock signal, making it easy for users to quickly insert probes into the sampling signals and sampling clocks of interest. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a netlist structure diagram including custom modules and instances exemplified in this application;

[0026] Figure 2 It adopts the conventional flat clock modeling diagram;

[0027] Figure 3 is a flowchart of a hierarchical clock tree modeling method provided in an embodiment of the present application;

[0028] Figure 4 The data structure diagrams of four data tables are shown;

[0029] Figure 5 It is a hierarchical diagram constructed based on the example netlist structure data table structure;

[0030] Figure 6 It is the signal path hierarchy NetChain diagram;

[0031] Figure 7 This is a schematic diagram of a clock tree modeled based on a hierarchical structure;

[0032] Figure 8 A structural block diagram of a hierarchical clock tree modeling device is shown;

[0033] Fig. 9 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0035] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0036] Glossary:

[0037] DUT (Design Under Test): Design under test.

[0038] Cell: A module that implements a specific function.

[0039] TreeNode: A tree node that wraps Cell and adds hierarchical information.

[0040] Net: The connection between cells, which is continuously driven by the output of the connected cell device.

[0041] TreeNet: Tree-like wiring is an extension of Net, adding hierarchical information.

[0042] Pin: Pin refers to the external pin of the functional module.

[0043] Port: Port refers to the top-level port of the entire design.

[0044] TreePort: Tree port is an extension of Pin / Port, adding hierarchical information.

[0045] NetChain: A wiring link is a set of TreeNets that a signal passes through from output to reception.

[0046] BUF: Input and output buffer, used to process the input and output signals of the chip's physical port.

[0047] BUFG: Global clock buffer, the clock signal passes through the global clock buffer before driving the logic.

[0048] PLL: Phase-locked loop, with functions of clock multiplication, division, phase shift and programmable duty cycle.

[0049] In order to explain the specific principles of this application scheme, an example is used. Figure 1 The netlist diagram shown is explained as an analysis object.

[0050] Figure 1 In the netlist to be analyzed, the blue dashed box is the instance of the custom module during design, and clk is the top-level clock input port. p1, p2 to p9 are all pins on the custom module, for example, p1 is the input pin of the custom module instance user_cell_2_inst. Figure 1The net between each pin is a connecting line. From left to right, the clock signal clk is input into BUF and then sent to the clock divider MMCM4_ADV to achieve frequency division. MMCM4_ADV itself also constitutes an instance mmcm4_adv. MMCM4_ADV and IBUF constitute another instance user_cell_1_inst. And so on. When the structure is complex, there are multiple nested examples. After frequency division, it is divided into two signals, which are sent to the register REG after passing through the global clock buffer BUFG, and then output to the value lookup table LUT and other devices. There are quite a few pins with the same name. Because there are a lot of pins in a complex netlist structure, they are numbered according to the number inside the example, and the numbers between instances are repeated. Not only that, the net numbers are also repeated, which leads to recognition problems when inserting probe signals later.

[0051] Figure 2 The conventional flat clock modeling diagram is adopted, and the flat clock modeling process is as follows:

[0052] <1> Start along the top-level clock entry (green circle clk) and get the Net on the Port;

[0053] <2> Start along the Net and search to the right for the connected FPGA primitive instance, and select a Net from the Nets you have gone through as the connected Net. If the newly selected Net has the same name as the selected Net, you must rename the newly selected Net. If the FPGA primitive is a BUF or BUFG type primitive, then the output signal on the right side of the primitive is the same as the clock signal received on the left side. If the FPGA primitive is a PLL clock primitive, then the output signal on the right side of the primitive is a new clock signal, and the right side of the PLL clock primitive starts to be a new clock tree. If the FPGA is a primitive of other types except BUF, BUFG or PLL clock, then the signal output on the right side is not a clock signal, and you can just mark the clock domain information.

[0054] <3> According to the steps <2> Find the output Pin corresponding to the right side of the FPGA primitive found in the figure, get the Net on the PIN, and perform the steps for this newly selected Net <2> .

[0055] from Figure 2 It can be seen that due to the mandatory naming rules in the case of duplicate names, although two clock signals are obtained, the position of the sampling signal Net (node) will change, and the Net of the custom module will be forcibly deleted, and there will be conflicts between the Nets under different modules.

[0056] Figure 3 : is a flowchart of a hierarchical clock tree modeling method provided in an embodiment of the present application, comprising the following steps:

[0057] S1. Obtain a netlist file, set the top-level module as the module to be processed, traverse all instances under the module to be processed, determine a custom module according to the traversed instance type, and set the custom module as the module to be processed; traverse all instances under the set module to be processed in turn, determine all custom modules and set the module to be processed layer by layer;

[0058] This step takes the top-level module as the module to be processed, traverses all instances inward, and determines the custom module, that is, Figure 1 The part marked with a blue frame can be identified by the pin. The custom module is ignored by the conventional flattening structure, so this application first sets it as the module to be processed, and then traverses all the instances under it. These instances can be the most basic logic device part and the multi-device combination part, and analyzes inward layer by layer to identify all inner custom modules, and then set them as modules to be processed. Specifically, in the traversal process, all instances under the module to be processed are traversed in turn. When the traversed instance is an FPGA primitive, the traversal ends. When the traversed instance is a custom module, the custom module is set as a module to be processed.

[0059] S2. The tree node TreeNode set by the top-level module is used as the node to be processed, all the tree connections TreeNet and tree ports TreePort under the node to be processed are traversed, the association relationship is marked, and all the child nodes of the current TreeNode to be processed are set as the nodes to be processed; all the set nodes to be processed are traversed in turn, all the TreeNet and TreePort therein are traversed in turn, all the child nodes therein are determined layer by layer, and they are determined as the nodes to be processed;

[0060] In netlist design, each instance corresponds to a TreeNode. By setting the TreeNode as the node to be processed, all the circuit logic inside it can be traversed, that is, the internal TreeNet and TreePort, as well as the connection relationship between TreeNet and TreePort. All child nodes traversed inward based on the top-level TreeNode are the nodes to be processed to be detected later.

[0061] When probing inward layer by layer, the child nodes found in the previous order are taken as the nodes to be processed, and all the contained TreeNets and TreePorts are continued to be probed inward, and then the connection relationship between the two is continued to be marked, the internal child nodes are determined, and the steps of determining the nodes to be processed are continued until all the hierarchical structures are probed.

[0062] S3, based on the identified nodes to be processed and the association between TreeNet and TreePort, create a tree node TreeNode table, a tree wiring TreeNet table, a tree port TreePort table, and establish a wiring link NetChain table according to the signal path of the netlist structure;

[0063] The TreeNode table is used to record the detected TreeNode information, the TreeNet table is used to record all detected Net wiring information, and the TreePort table is used to record all detected Port port information. After obtaining the aforementioned TreeNode, TreeNet, and TreePort, the TreeNet information of the complete path of each clock signal from input to output can be obtained, so the NetChain table can be established to record all signal input and output link data in the table.

[0064] S4. Read the established TreeNode table, TreeNet table, TreePort table, and NetChain table, and perform clock modeling according to the hierarchical structure along the top-level entrance of the clock.

[0065] The clock modeling process is to determine the relationship between each pin, port and wiring according to the constructed TreeNode table, TreeNet table, TreePort table, and NetChain table data during the detection process, and according to the clock path query table data of the clk signal, which is equivalent to index information. According to the belonging relationship and primitive type determined by the query table, the clock signal relationship and clock domain information output on the right after the left clock signal passes through the clock path are determined. According to this detection and search relationship, the entire netlist structure is exhausted to record the complete clock tree structure.

[0066] To summarize, the present application traverses the entire netlist structure, starting from the top-level module, traverses layer by layer to identify the custom module types, and uses the tree nodes of all detected custom modules as subsequent nodes to be processed, traverses the tree ports and internal sub-nodes inward, and establishes a data table based on the relationship between each node, wiring, port and pin, and uses this as the basis for subsequent clock modeling. This method retains the hierarchical structure and connection relationship of the clock signal, making it easy for users to quickly insert probes into the sampling signals and sampling clocks of interest.

[0067] In a possible implementation, the structure of the TreeNode table may be designed as follows:

[0068] Set the top-level module as the root node of the hierarchy, the custom module as the intermediate node, and the FPGA primitive as the leaf node. Each instance corresponds to a TreeNode. The advantage of this design is that different TreeNodes can be labeled with the same or different names, for example Figure 1 There are TreeNode instances with the same name of clk_out_buf under the TreeNode instances user_cell_4_inst and user_cell_6_inst.

[0069] Each TreeNode instance will record the corresponding parent node and child node. The parent node is m_parent, and the child node is m_children. For example Figure 1 The parent node of user_cell_3_inst is user_cell_4_inst, and the child nodes of user_cell_3_inst are cnt_reg and cnt_reg_lut1.

[0070] For each TreeNode, the Pin / Port to which it belongs is recorded and stored in the port information memory m_ports in the form of a TreePort structure. Figure 1 The user_cell_1_inst node has three TreePorts, namely p2, p3, and p4.

[0071] In addition, the corresponding connection Net is recorded for each TreeNode and stored in the connection information memory m_nets in the form of a TreeNet structure. Figure 1 The node user_cell_1_inst has 5 TreeNets, namely net1, net2, net3, and net12.

[0072] Figure 4 The data structure diagrams of four data tables are shown, each of which records all nodes, ports, pins and wiring data of their respective types. The constructed TreeNet table adopts the following design:

[0073] Each Net corresponds to a TreeNet object, and the TreeNode to which each TreeNet object belongs is recorded, and the TreeNode information is stored in the first attribute information storage m_owner. The advantage of this design is that the TreeNets under different TreeNodes can have the same name. For example, the user_cell_4_inst and user_cell_3_inst instances under the TreeNode can both have a TreeNet named net1.

[0074] The TreeNet table also determines the Pin information and Port information of each Net connection, and records and stores the Pin information in the Pin information storage m_portrefs in the TreePort structure. Figure 1 The Pin connected to TreeNet net1 in user_cell_2_inst under TreeNode is TreePort p2 belonging to user_cell_1_inst. In addition, the Port information is recorded and stored in the Port information storage m_ports in the TreePort structure. For example Figure 1 The Port connected to TreeNet net1 in user_cell_2_inst under TreeNode belongs to TreePort p1 of user_cell_2_inst.

[0075] In addition, the table also determines the NetChain object information to which each TreeNet belongs, that is, the signal link information, and stores the NetChain object information in the second attribute information storage m_nc.

[0076] The TreePort table constructed is designed as follows:

[0077] Each Pin / Port is treated as a TreePort object, the TreeNode to which the current Pin / Port belongs is recorded, and the TreeNode information is stored in the first information storage m_owner. The advantage of this design is that different Pin / Ports under different TreeNodes can have the same name. For example Figure 1 Under the TreeNode, user_cell_4_inst and user_cell_3_inst can both have a TreePort named p9.

[0078] The TreePort table also records the TreeNet information connected to the current Pin / Port and stores it in the second information storage m_net. In addition, the TreeNet information connected outside the Pin / Port is stored in the third information storage m_netOut. Figure 1 The TreeNet connected to TreePort p3 in TreeNode user_cell_1_inst is net3, and the TreeNet connected to the outside of p3 is net4.

[0079] After the above detection and establishment of three data tables, the hierarchical structure of the netlist can be determined. Figure 5It is a hierarchical diagram constructed based on the netlist structure data table structure of the example, which gradually extends downward from the top-level module as the root node to each instance as the intermediate node and ends with FPGA primitives and black boxes as leaf nodes.

[0080] After determining the hierarchical structure, it is necessary to further determine the hierarchical structure of NetChain, including the following steps:

[0081] A. Select the top-level TreeNode as the node to be processed, and traverse all TreeNets under the node to be processed; all TreeNets are divided into external TreeNets and internal TreeNets. The external and internal here are determined relative to the instance module of the current detected level. The internal TreeNet is the internal TreeNet, and the external TreeNet is the external TreeNet.

[0082] B. Find the instance connected to the external TreeNet. When the instance connected to the external TreeNet is an instance of a custom module, determine the internal TreeNet inside the custom module that is connected to the external TreeNet. If there is no internal TreeNet, it means that the innermost basic logic device has been detected, and the current operation ends.

[0083] C. When traversing to the internal TreeNet, continue to search for the TreePort connected to the external TreeNet, and find the internal TreeNet connected to the external TreePort; similarly, if there is no internal TreeNet, it means that the innermost basic logic device is detected, and the current operation ends;

[0084] D. After traversing all TreeNets under the current TreeNode, select all child nodes under the current TreeNode as nodes to be processed, and repeatedly search for external TreeNets and internal TreeNets under the nodes to be processed;

[0085] This step is to determine all possible signal paths at an instance level, and then go into a deeper layer and repeat the previous steps after completing the detection one by one.

[0086] E. The set of all TreeNets that each signal goes through from input to output constitutes a NetChain, and the information of all TreeNets gone through is stored in the wiring information memory m_nets.

[0087] NetChain table structure see Figure 4 Content, combined Figure 1Content explanation: For example, the signal output from mmcme4_adv_inst / CLKOUT1 passes through TreeNet net12 (belonging to user_cell_1_inst), net5 (belonging to user_cell_2_inst), net6 (belonging to the top module), net6 (belonging to user_cell_6_inst), and finally reaches the input terminal I of clk_out_buf. Then the NetChain corresponding to this signal contains four TreeNets: net12, net5, net6, and net6.

[0088] Likewise Figure 1 The netlist diagram is used as a prototype, and the scheme described in this application is used to establish Figure 6 The signal path hierarchy NetChain diagram shown in the figure, based on the above, it can be seen that at the I end of clk input to clkin1_ibuf, net11, net1, net1 form a netchain, and the other parts are similar.

[0089] In some embodiments, according to the established TreeNode table, TreeNet table, TreePort table, and NetChain table, clock modeling is performed along the top-level entrance of the clock according to the hierarchical structure, which may specifically include the following steps:

[0090] 1. Start along the TreePort of the top-level entrance of the clock, obtain the TreeNet information connected to the port from the TreePort table, and obtain the corresponding NetChain according to the NetChain information saved by the TreeNet;

[0091] 2. Traverse all TreeNets in the NetChain table and find the target TreePort responsible for receiving signals connected to the current TreeNet;

[0092] 3. Get the target TreeNode to which the target TreePort belongs. When the target TreeNode is a BUF or BUFG type primitive, determine that the signal output on the right side of the current target TreeNode is the same as the clock signal on the left side; that is, the left and right sides are the same clock signal and there is no change.

[0093] Figure 7 This is a schematic diagram of a clock tree modeled based on a hierarchical structure. When the target TreeNode is a PLL clock primitive, the output target TreePort associated with the right side of the target TreeNode is the new clock signal. That is, the TreePort where the sub-clock starts. This TreePort is the starting point of the sub-clock tree.

[0094] Furthermore, if the target TreeNode is a primitive of other types except BUF, BUFG and PLL clock, the signal on the output target TreePort associated with the right side of the target TreeNode is not a clock signal, and the clock domain information on the right output target TreePort can be directly marked.

[0095] 4. Get the target TreeNet connected to the output target TreePort on the right, and get the corresponding target NetChain object from the target TreeNet;

[0096] 5. Continue to traverse the target TreePort responsible for receiving signals according to the target NetChain object, continue to determine the right output of the target TreeNode, and determine all clock structures.

[0097] Combination Figure 7 From the content, we can see that the input from the leftmost clk input to the mmcme4_adv_inst instance is the clock signal clk, and from the output side of mmcme4_adv_inst it is divided into two sub-clock signals. The two continue to the cnt_reg input ends in the user_cell_4_inst and user_cell_6_inst instances respectively. From the cnt_reg output to the cnt_reg input end in the user_cell_5_inst instance, the clock domains of the two sub-clock signals are formed.

[0098] By comparing the conventional flattened clock modeling diagram and the improved hierarchical clock modeling diagram, we can clearly see the three problems of the conventional flattened clock modeling diagram. Problem 1: The position of the sampling signal Net will change. For example, net3, which originally belonged to user_cell_1_inst, belongs to the top-level module after flattening. Problem 2: The Net in the custom module is deleted. For example, net6, which originally belonged to user_cell_4_inst, was deleted. Problem 3: Nets with the same name conflict in different modules. For example, there is a Net named net1 under the top-level modules, user_cell_3_inst and user_cell_4_inst. When these three net1s are in the same module, the other two must be given the same name, so the net1 under user_cell_3_inst is renamed net1_3, and the net1 under user_cell_4_inst is renamed net1_1. The difference between the clock tree model and the netlist will make it difficult or even impossible to find sampling signals and sampling IPs, especially for complex and large netlists.

[0099] The improved hierarchical clock modeling diagram does not change the hierarchical structure and connection relationship, and solves all three problems caused by the conventional flat clock modeling diagram. In this way, when inserting a probe, you only need to find the sampling clock and sampling signal according to the hierarchical structure and connection relationship in the netlist, which makes the operation more convenient.

[0100] Figure 8 A structural block diagram of a hierarchical clock tree modeling device provided in an embodiment of the present application is shown, and the device includes:

[0101] The first setting module 810 is used to obtain the netlist file, set the top-level module as the module to be processed, traverse all instances under the module to be processed, determine the custom module according to the traversed instance type, and set the custom module as the module to be processed; traverse all instances under the set module to be processed in turn, determine all custom modules layer by layer, and set the module to be processed;

[0102] The second setting module 820 is used to take the tree node TreeNode set by the top-level module as the node to be processed, traverse all the tree connections TreeNet and tree ports TreePort under the node to be processed, mark the association relationship, and set all the child nodes of the current TreeNode to be processed as the nodes to be processed; traverse all the set nodes to be processed in turn, traverse all the TreeNets and TreePorts therein in turn, determine all the child nodes therein layer by layer, and determine them as the nodes to be processed;

[0103] The table building module 830 is used to create a tree node TreeNode table, a tree wiring TreeNet table, a tree port TreePort table based on the identified nodes to be processed and the association relationship between TreeNet and TreePort, and to establish a wiring link NetChain table according to the signal path of the netlist structure;

[0104] The clock modeling module 840 is used to read the established TreeNode table, TreeNet table, TreePort table, and NetChain table, and perform clock modeling according to the hierarchical structure along the top-level entrance of the clock.

[0105] The hierarchical clock tree modeling device provided in the embodiment of the present application can be applied to the hierarchical clock tree modeling method provided in the above embodiment. For relevant details, refer to the above method embodiment. The implementation principle and technical effect are similar and will not be repeated here.

[0106] It should be noted that the hierarchical clock tree modeling device provided in the embodiment of the present application is only illustrated by the division of the above-mentioned functional modules / functional units. In practical applications, the above-mentioned functional distribution can be completed by different functional modules / functional units as needed, that is, the internal structure of the hierarchical clock tree modeling device is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the hierarchical clock tree modeling method provided in the above method embodiment and the implementation method of the hierarchical clock tree modeling device provided in this embodiment belong to the same concept. The specific implementation process of the hierarchical clock tree modeling device provided in this embodiment is detailed in the above method embodiment, which will not be repeated here.

[0107] Fig. 9 The block diagram of the structure of a computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. The processor and the memory may be connected via a bus or other means. The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned chips.

[0108] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0109] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0110] In some embodiments, the computer device may further optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen and a keyboard.

[0111] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0112] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen is a touch screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, which is set on the front panel of the computer device; in other embodiments, the display screen can be at least two, which are respectively set on different surfaces of the computer device or are folded; in other embodiments, the display screen can be a flexible display screen, which is set on the curved surface or folded surface of the computer device. Even the display screen can be set into a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode), etc.

[0113] The power supply is used to power various components in the computer device. The power supply can be AC, DC, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0114] Those skilled in the art will appreciate that the structure shown in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0115] The embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0116] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A hierarchical clock tree modeling method, characterized in that: The method comprises: Obtain the netlist file, set the top-level module as the module to be processed, traverse all instances under the module to be processed, and end the traversal when the traversed instance is an FPGA primitive; when the traversed instance is a custom module, set the custom module as the module to be processed, and set the custom module as the module to be processed; traverse all instances under the set module to be processed in turn, determine all custom modules and set the module to be processed layer by layer; The tree node TreeNode set by the top-level module is used as the node to be processed, all the tree connections TreeNet and tree ports TreePort under the node to be processed are traversed, the association relationship is marked, and all the child nodes of the current TreeNode to be processed are set as the nodes to be processed; all the set nodes to be processed are traversed in turn, all the TreeNet and TreePort therein are traversed in turn, all the child nodes therein are determined layer by layer, and they are determined as the nodes to be processed; Based on the identified nodes to be processed and the association between TreeNet and TreePort, a tree node TreeNode table, a tree wiring TreeNet table, a tree port TreePort table are created, and a wiring link NetChain table is established according to the signal path of the netlist structure; constructing the TreeNode table includes: The top-level module is set as the root node of the hierarchy, the custom module is the middle node, and the FPGA primitive is the leaf node; Each instance is mapped to a TreeNode. Different TreeNodes are labeled with the same or different names. Each TreeNode records the corresponding parent node and child node. For each TreeNode record, the Pin / Port to which it belongs is recorded and stored in the port information memory in the TreePort structure; for each TreeNode record, the wiring Net to which it belongs is recorded and stored in the wiring information memory in the TreeNet structure; the established TreeNode table, TreeNet table, TreePort table, and NetChain table are read, and clock modeling is performed according to the hierarchical structure along the top-level entrance of the clock.

2. The method according to claim 1, characterized in that Constructing the TreeNet table includes: Each Net corresponds to a TreeNet object, and the TreeNode to which each TreeNet object belongs is recorded and stored in the first attribute information storage; wherein the TreeNets under different TreeNodes are labeled with the same name or different names; Determine the Pin information and Port information of each Net connection, record and store the Pin information in the Pin information storage in the TreePort structure, and record and store the Port information in the Port information storage in the TreePort structure; The NetChain object information to which the TreeNet belongs is determined, and the NetChain object information is stored in a second attribute information storage.

3. The method according to claim 2, characterized in that Constructing the TreePort table includes: Treat each Pin / Port as a TreePort object, record the TreeNode to which the current Pin / Port belongs, and store it in the first information storage; Record the TreeNet information connected to the current Pin / Port and store it in the second information storage, and store the TreeNet information connected outside the Pin / Port in the third information storage.

4. The method according to claim 3, characterized in that: The method also includes establishing a hierarchical structure of NetChain, including: Select the top-level TreeNode as the node to be processed, and traverse all TreeNets under the node to be processed; all TreeNets are divided into external TreeNets and internal TreeNets; Find the instance connected to the external TreeNet. When the instance connected to the external TreeNet is an instance of a custom module, determine the internal TreeNet inside the custom module that is connected to the external TreeNet. When traversing to the internal TreeNet, continue to search for the TreePort connected to the external TreeNet, and find the internal TreeNet connected to the external TreePort; After traversing all TreeNets under the current TreeNode, select all child nodes under the current TreeNode as nodes to be processed, and repeatedly search for external TreeNets and internal TreeNets under the nodes to be processed; The set of all TreeNets that each signal goes through from input to output constitutes a NetChain, and the information of all TreeNets gone through is stored in the wiring information memory.

5. The method according to claim 4, characterized in that The clock modeling is performed along the top-level clock entry according to the hierarchical structure, including: Start along the TreePort of the top-level entrance of the clock, obtain the TreeNet information connected to the port from the TreePort table, and obtain the corresponding NetChain according to the NetChain information saved by the TreeNet; Traverse all TreeNets in the NetChain table and find the target TreePort connected to the current TreeNet that is responsible for receiving the signal; Get the target TreeNode to which the target TreePort belongs. When the target TreeNode is a BUF or BUFG type primitive, make sure that the signal output on the right side of the target TreeNode is the same as the clock signal on the left side. When the target TreeNode is a PLL clock primitive, determine that the output target TreePort associated with the right side of the target TreeNode is the new clock signal; When the target TreeNode is a primitive of other types except BUF, BUFG and PLL clock, determine that the signal on the output target TreePort associated with the right side of the target TreeNode is not a clock signal, and directly mark the clock domain information on the output target TreePort on the right side; Get the target TreeNet connected to the output target TreePort on the right, and get the corresponding target NetChain object from the target TreeNet; Continue to traverse the target TreePort responsible for receiving the signal according to the target NetChain object, continue to determine the right output of the target TreeNode, and determine all clock structures.

6. A hierarchical clock tree modeling device, characterized in that: The device comprises: The first setting module is used to obtain a netlist file, set the top-level module as a module to be processed, traverse all instances under the module to be processed, and end the traversal when the traversed instance is an FPGA primitive; when the traversed instance is a custom module, set the custom module as a module to be processed, and set the custom module as a module to be processed; traverse all instances under the set module to be processed in turn, determine all custom modules layer by layer, and set the module to be processed; The second setting module is used to take the tree node TreeNode set by the top-level module as the node to be processed, traverse all the tree connections TreeNet and tree ports TreePort under the node to be processed, mark the association relationship, and set all the child nodes of the current TreeNode to be processed as the nodes to be processed; traverse all the set nodes to be processed in turn, traverse all the TreeNets and TreePorts therein in turn, determine all the child nodes therein layer by layer, and determine them as the nodes to be processed; The table building module is used to create a tree node TreeNode table, a tree wiring TreeNet table, a tree port TreePort table based on the identified nodes to be processed and the association relationship between TreeNet and TreePort, and to establish a wiring link NetChain table according to the signal path of the netlist structure; building the TreeNode table includes: The top-level module is set as the root node of the hierarchy, the custom module is the middle node, and the FPGA primitive is the leaf node; Each instance is mapped to a TreeNode. Different TreeNodes are labeled with the same or different names. Each TreeNode records the corresponding parent node and child node. For each TreeNode, record the Pin / Port to which it belongs, record it in a TreePort structure and store it in the port information memory; for each TreeNode, record the wiring Net to which it belongs, record it in a TreeNet structure and store it in the wiring information memory; The clock modeling module is used to read the established TreeNode table, TreeNet table, TreePort table, and NetChain table, and perform clock modeling according to the hierarchical structure along the top-level entrance of the clock.

7. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the hierarchical clock tree modeling method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the hierarchical clock tree modeling method as described in any one of claims 1 to 5.

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