Pad structure for semiconductor device

Abstract

Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes a first die and a second die face-to-face bonded. The first die includes a first transistor formed in a semiconductor portion on a front side of the first die, and at least one contact structure arranged in an insulating portion outside the semiconductor portion. The second die includes a substrate and a second transistor formed on a front side of the second die. Further, the semiconductor device includes a first pad structure arranged on a back side of the first die, and the first pad structure is conductively coupled with the contact structure. An end of the contact structure protrudes from the insulating portion into the first pad structure. Further, in some embodiments, the semiconductor device includes a connection structure arranged on the back side of the first die and conductively connected with the semiconductor portion.

Description

[0001] This application is a divisional application of patent application 202080002320.4, filed on September 2, 2020, entitled "Pad Structure for Semiconductor Devices". Technical Field

[0002] In summary, this application describes embodiments relating to semiconductor memory devices. Background Technology

[0003] In general, semiconductor devices (e.g., semiconductor chips) communicate with the outside world through various input / output (I / O) pad structures, such as signal pad structures and power / ground (P / G) pad structures. In some examples, a semiconductor chip may include multiple metal layers formed on top of circuitry above a substrate. One or more metal layers are used to form pad structures that are electrically coupled to the circuitry above the substrate. The pad structures may be formed to facilitate the attachment of bonding wires that can electrically couple the pad structures to external components, such as power, ground, other semiconductor chips, metal lines on a printed circuit board (PCB), etc. Summary of the Invention

[0004] This disclosure provides a semiconductor device. The semiconductor device includes a first die and a second die bonded face-to-face. The first die includes a first transistor formed on a front side of the first die in a semiconductor portion, and at least one contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a substrate and a second transistor formed on the front side of the second die. Furthermore, the semiconductor device includes a first pad structure disposed on a back side of the first die, and the first pad structure is electrically coupled to the contact structure. An end of the contact structure protrudes from the insulating portion into the first pad structure. Additionally, in some embodiments, the semiconductor device includes a connection structure disposed on the back side of the first die and electrically connected to the semiconductor portion.

[0005] In this embodiment, the interface between the connection structure and the semiconductor portion is substantially flat on the semiconductor portion. In some examples, the bottom and top surfaces of the connection structure on the semiconductor portion have approximately the same dimensions.

[0006] In some embodiments, the contact structure includes at least a first metallic material that is different from the second metallic material in the first pad structure. In one example, the first metallic material includes tungsten, and the second metallic material includes aluminum.

[0007] In some examples, due to the protrusion of the end of the contact structure, the bottom surface of the first pad structure that contacts the insulating portion has a recessed portion corresponding to the end of the contact structure.

[0008] In some embodiments, the first die includes at least a memory cell array formed in a semiconductor portion, and the second die includes peripheral circuitry for the memory cell array. Contact structures on the first die are electrically coupled to input / output circuitry on the second die via bonding structures.

[0009] In some embodiments, the first die includes input / output circuitry electrically coupled to a contact structure.

[0010] This disclosure provides a method for fabricating a semiconductor device. The method includes face-to-face bonding of a first die and a second die. The first die includes a first substrate, a first transistor formed in a semiconductor portion on the front side of the first die, and a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a second substrate, on the front side of the second substrate, a second transistor formed thereon. Furthermore, the method includes removing the first substrate from a back side of the first die. Removing the first substrate exposes the ends of the contact structures on the back side of the first die. The method then includes forming a first pad structure electrically connected to the contact structures on the back side of the first die. The ends of the contact structures protrude from an insulating portion inside the first pad structure.

[0011] In some embodiments, the method further includes forming a connection structure electrically connected to the semiconductor portion on the back side of the first die. In an embodiment, removing the first substrate exposes the semiconductor portion from the back side of the first die, and the method includes depositing a layer for forming the connection structure. The interface between the layer and the semiconductor portion is substantially planar on the semiconductor portion. In some examples, the method includes patterning the layer to form the connection structure. The bottom and top surfaces of the connection structure on the semiconductor portion have approximately the same dimensions.

[0012] In some embodiments, the method includes depositing a second metallic material, different from the first metallic material, onto a contact structure that includes at least a first metallic material. The first pad structure includes at least the second metallic material. In an example, the first metallic material may be tungsten, and the second metallic material may be aluminum. Attached Figure Description

[0013] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0014] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0015] Figure 2A flowchart outlining the process of forming a semiconductor device is shown.

[0016] Figure 3-6 A cross-sectional view of a semiconductor device during fabrication according to some embodiments is shown. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or feature and another element or feature as shown in the figure. Spatially related terms are intended to include different orientations of the device in use or operation (other than those shown in the figure). The device may face other orientations (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0019] This disclosure provides techniques for forming pad structures for a semiconductor device having two dies (e.g., a first die and a second die) with face-to-face bonding. The pad structure is formed on the back side of one of the two dies (e.g., the first die). The techniques for forming the pad structure eliminate the need to form a through-silicon contact (TSC) from the back side of the first die and simplify the process for forming the pad structure. In some embodiments, circuit elements are formed on the front side of both dies. Additionally, at least one contact structure is formed from the front side of the first die in an insulating portion of the first die, and this contact structure is connected to input / output (I / O) circuitry. One of the pad structures on the back side of the first die, such as the first pad structure, is electrically coupled to the contact structure, and the contact structure includes an end protruding from the insulating portion into the interior of the first pad structure. In some examples, the first die includes a semiconductor portion in which transistors are formed. In some embodiments, a connection structure is formed together with the pad structure and is electrically coupled to the semiconductor portion. In the example, the connection structure is electrically coupled to the semiconductor portion without forming a contact based on a contact hole from the back side of the first die. In some examples, the pad structure and the connection structure can be formed using the same metal layer.

[0020] According to some aspects of this disclosure, the semiconductor device can be a semiconductor memory device, wherein one of the two dies includes an array of memory cells formed on the front side and is referred to as an array die, while the other of the two dies includes peripheral circuitry formed on the front side and is referred to as a peripheral die. In some examples, the peripheral circuitry is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the peripheral die is also referred to as a CMOS die. Pad structures and interconnect structures may be formed on the back side of the array die or on the back side of the peripheral die.

[0021] In some embodiments, pad structures and connection structures are formed on the back side of the array die. The array die includes an array of memory cells formed in a semiconductor portion. Then, in an example, the connection structures conductively coupled to the semiconductor portion can be configured to provide a connection for an array common source (ACS) for the memory cell array.

[0022] According to some aspects of this disclosure, two dies (e.g., an array die and a peripheral die) are formed on two wafers. In some embodiments, a first wafer including the array die and a second wafer including the peripheral die are formed. For example, the first wafer can be fabricated to optimize the density and performance of the memory cell array without being affected by fabrication limitations due to the peripheral circuitry; and the second wafer can be fabricated to optimize the performance of the peripheral circuitry without compromising fabrication limitations due to the memory cell array. In some embodiments, the first and second wafers can be bonded face-to-face using wafer-to-wafer bonding technology, so that the array die on the first wafer is bonded to the peripheral die on the second wafer. The techniques provided in this disclosure can then be used to fabricate pad structures on the back side of one of the two wafers.

[0023] Figure 1 Cross-sectional views of semiconductor devices, such as semiconductor memory device 100, according to some embodiments of the present disclosure are shown. Semiconductor memory device 100 includes two dies bonded face-to-face. Pad structures and interconnect structures are formed on the back side of one of the two dies using the techniques provided in this disclosure.

[0024] Specifically, in Figure 1 In the example, semiconductor memory device 100 includes an array die 102 and a CMOS die 101 bonded face-to-face. Note that in some embodiments, the semiconductor memory device may include multiple array dies and a CMOS die. The multiple array dies and the CMOS die may be stacked and bonded together. The CMOS die is coupled to the multiple array dies respectively, and the respective array dies may be driven in a similar manner.

[0025] Semiconductor device 100 can be any suitable device. In some examples, semiconductor device 100 includes at least a first wafer and a second wafer bonded face-to-face. Array die 102 is disposed on the first wafer along with other array dies, and CMOS die 101 is disposed on the second wafer along with other CMOS dies. The first wafer and the second wafer are bonded together, thereby bonding the array dies on the first wafer to the corresponding CMOS dies on the second wafer. In some examples, semiconductor device 100 is a semiconductor chip in which at least array die 102 and CMOS die 101 are bonded together. In this example, the semiconductor chip is diced from the bonded wafers. In another example, semiconductor device 100 is a semiconductor package comprising one or more semiconductor chips assembled on a package substrate.

[0026] The array die 102 includes one or more semiconductor portions 105 and insulating portions 106 between the semiconductor portions 105. A memory cell array may be formed in the semiconductor portions 105, and the insulating portions may isolate the semiconductor portions 105 and provide space for contact structures 170. The CMOS die 101 includes a substrate 104 and peripheral circuitry formed on the substrate 104. For simplicity, the main surface (of the die or wafer) is referred to as the XY plane, and the direction perpendicular to the main surface is referred to as the Z direction.

[0027] In addition, Figure 1 In the example, the connection structure 121 and the pad structures 122-123 are formed on the back side of one of the two dies (e.g., array die 102). Specifically, in Figure 1 In the example, pad structures 122-123 are above the insulating portion 106, and each pad structure in pad structures 122-123 can be electrically connected to one or more contact structures 170. Figure 1 In some examples, the connection structure 121 is located above the semiconductor portion 105 and is electrically connected to the semiconductor portion 105. In some examples, the semiconductor portion 105 is coupled to an array common source (ACS) for a memory cell array, and the connection structure 121 is disposed on the semiconductor portion 105 of a block of memory cell arrays. In some examples, the connection structure 121 is formed of a relatively low resistivity metal layer, and when the connection structure 121 covers a relatively large portion of the semiconductor portion 105, the connection structure 121 can connect to the ACS of the block of memory cell arrays with very small parasitic resistance. The connection structure 121 may include portions of a pad structure configured for ACS to receive ACS signals from an external source. The pad structures 122-123 and the connection structure 121 are made of a suitable metallic material, such as aluminum, which can facilitate the attachment of bonding wires. In some examples, the pad structures 122-123 include a titanium layer 126 and an aluminum layer 128, and the connection structure 121 includes a titanium silicide layer 127 and an aluminum layer 128.

[0028] Note that, for ease of explanation, some components of the semiconductor memory device 100, such as passivation structures, are not shown, and similar components are not shown either.

[0029] Note that the array die 102 initially includes a substrate and a semiconductor portion 105, and an insulating portion 106 is formed on the substrate. The substrate is removed before the pad structures 122-123 and the interconnect structure 121 are formed.

[0030] Figure 2 A flowchart outlining a process 200 for forming a semiconductor memory device (e.g., semiconductor memory device 100) according to some embodiments of this disclosure is shown, and Figure 3-6 A cross-sectional view of a semiconductor device 100 during a process according to some embodiments is shown. Process 200 begins at S201 and proceeds to S210.

[0031] At S210, the first die and the second die are bonded face-to-face. The first die includes a first substrate and includes a semiconductor portion and an insulating portion disposed on the front side of the first substrate. The insulating portion can insulate the semiconductor portion. The first die also includes a first transistor formed in the semiconductor portion from the front side of the first die. In addition, the first die includes contact structures disposed in the insulating portion outside the semiconductor portion. The insulating portion can also insulate the contact structures from each other and from the semiconductor portion. The second die includes a second substrate, wherein a second transistor is formed on the front side of the second die.

[0032] In some embodiments, the first die is an array die, such as array die 102, and the second die is a CMOS die, such as CMOS die 101. In some examples, the first die may be a CMOS die, and the second die may be an array die.

[0033] Figure 3 A cross-sectional view of a semiconductor memory device 100 is shown after the bonding process of the two dies. The semiconductor memory device 100 includes an array die 102 and a CMOS die 101 bonded face-to-face.

[0034] In some embodiments, array die 102 is processed together with other array dies on a first wafer, and CMOS die 101 is processed together with other CMOS dies on a second wafer. In some examples, the first wafer and the second wafer are processed separately. For example, a memory cell array and I / O contact structure are formed on the first wafer using a process that operates on the front side of the first wafer. Furthermore, a first bonding structure is formed on the front side of the first wafer. Similarly, a peripheral circuit is formed on the second wafer using a process that operates on the front side of the second wafer, and a second bonding structure is formed on the front side of the second wafer.

[0035] In some embodiments, the first wafer and the second wafer can be bonded face-to-face using wafer-to-wafer bonding technology. A first bonding structure on the first wafer is bonded to a corresponding second bonding structure on the second wafer, thereby bonding the array dies on the first wafer to the CMOS dies on the second wafer.

[0036] The array die 102 includes a substrate 103. One or more semiconductor portions 105 and insulating portions 106 are formed on the substrate 103. The insulating portions 106 are formed of an insulating material, such as silicon oxide, which can isolate the semiconductor portions 105. Furthermore, a memory cell array can be formed in the semiconductor portions 105, and contact structures can be formed in the insulating portions 106. The CMOS die 101 includes a substrate 104 and includes peripheral circuitry formed on the substrate 104.

[0037] Substrates 103 and 104 can each be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. Substrates 103 and 104 can each comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. Group IV semiconductors can include Si, Ge, or SiGe. Substrates 103 and 104 can each be a bulk wafer or an epitaxial layer. In some examples, the substrate is formed of multiple layers. For example, as... Figure 3 As shown, the substrate 103 includes multiple layers, such as bulk portion 111, silicon oxide layer 112 and silicon nitride layer 113.

[0038] exist Figure 3 In the example, the memory cell array is formed on the substrate 103 of the array die 102, and the peripheral circuitry is formed on the substrate 104 of the CMOS die 101. The array die 102 and the CMOS die 101 are arranged face to face (the surface on which the circuitry is arranged is called the front side, and the opposite surface is called the back side) and are bonded together.

[0039] In some examples, a semiconductor portion 105 is formed on a substrate 103, and a block of three-dimensional (3D) NAND memory cell strings may be formed within the semiconductor portion 105. The semiconductor portion 105 is electrically coupled to a common source of the array of memory cell strings. In some examples, the memory cell array is formed as an array of vertical memory cell strings in a core region 115. In addition to the core region 115, the array die 102 includes a stepped region 116 and an insulating region 117. The stepped region 116 facilitates connections to, for example, the gates of memory cells in the vertical memory cell strings, the gates of select transistors, etc. The gates of the memory cells in the vertical memory cell strings correspond to word lines of the NAND memory structure. The insulating region 117 is used to form an insulating portion 106.

[0040] exist Figure 3In the example, vertical memory cell string 180 is shown as a representation of a vertical memory cell string array formed in core region 115. The vertical memory cell string 180 is formed in a layer stack 190. The layer stack 190 includes alternately stacked gate layers 195 and insulating layers 194. Gate layers 195 and insulating layers 194 are configured to form vertically stacked transistors. In some examples, the transistor stack includes memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors, etc. In some examples, the transistor stack may include one or more dummy select transistors. Gate layer 195 corresponds to the gate of the transistor. Gate layer 195 is made of a gate stack material, such as a high-k gate insulating layer, a metal gate (MG) electrode, etc. Insulating layer 194 is made of an insulating material, such as silicon nitride, silicon dioxide, etc.

[0041] According to some aspects of this disclosure, vertical memory cell strings are formed by channel structures 181 extending vertically (in the Z direction) into a stack 190 of layers. The channel structures 181 may be arranged separately from each other in the XY plane. In some embodiments, the channel structures 181 are arranged in an array between gate wire-cut structures (not shown). The gate wire-cut structures facilitate the replacement of the sacrificial layer with the gate layer 195 in the final gate process. The array of channel structures 181 can have any suitable array shape, such as a matrix array shape along the X and Y directions, a zigzag array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, etc. In some embodiments, each channel structure has a circular shape in the XY plane and a columnar shape in the XZ and YZ planes. In some embodiments, the number and arrangement of channel structures between gate wire-cut structures are not limited.

[0042] In some embodiments, the channel structure 181 has a columnar shape extending in the Z direction perpendicular to the main surface direction of the substrate 103. In one embodiment, the channel structure 181 is formed of a material that is circular in the XY plane and extends in the Z direction. For example, the channel structure 181 includes functional layers such as a barrier insulating layer 182 (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride) 183, a tunneling insulating layer 184 (e.g., silicon oxide), a semiconductor layer 185, and an insulating layer 186, which have a circular shape in the XY plane and extend in the Z direction. In the example, the barrier insulating layer 182 (e.g., silicon oxide) is formed on the sidewall of the aperture (entry layer stack 190) for the channel structure 181, and then the charge storage layer (e.g., silicon nitride) 183, the tunneling insulating layer 184, the semiconductor layer 185, and the insulating layer 186 are sequentially stacked from the sidewall. Semiconductor layer 185 can be any suitable semiconductor material, such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material can be undoped or may include p-type or n-type dopants. In some examples, the semiconductor material is undoped intrinsic silicon. However, due to defects, in some examples, the intrinsic silicon material may have approximately 10... 10 cm -3 The carrier density is on the order of magnitude. The insulating layer 186 is formed of an insulating material, such as silicon oxide and / or silicon nitride, and / or may be formed as an air gap.

[0043] According to some aspects of this disclosure, the channel structure 181 and the layer stack 190 together form a memory cell string 180. For example, the semiconductor layer 185 corresponds to the channel portion for transistors in the memory cell string 180, and the gate layer 195 corresponds to the gate of the transistors in the memory cell string 180. Typically, the transistor has a gate that controls the channel and a drain and a source on each side of the channel. For simplicity, in Figure 3 In the example, Figure 3 The bottom side of the channel used in a transistor is called the drain, while Figure 3 The upper side of the channel used in a transistor is called the source. Note that the drain and source can be switched under certain drive configurations. Figure 3 In the example, semiconductor layer 185 corresponds to the connection channel of the transistor. For a specific transistor, in Figure 3 In the example, the drain of a particular transistor is connected to the source of the lower transistor below it, and the source of the particular transistor is connected to the drain of the upper transistor above it. Therefore, the transistors in the memory cell string 180 are connected in series. It should be noted that "upper" and "lower" are specifically used for... Figure 3 In this case, the array die 102 is arranged in reverse.

[0044] The storage cell string 180 includes storage cell transistors (or storage cells). Based on carrier trapping in a portion of the charge storage layer 183 corresponding to the floating gate of the storage cell transistor, the storage cell transistor can have different threshold voltages. For example, when a large number of holes are trapped (stored) in the floating gate of the storage cell transistor, the threshold voltage of the storage cell transistor is below a predefined value, and the storage cell transistor is in an unprogrammed state (also called an erased state) corresponding to logic "1". When holes are expelled from the floating gate, the threshold voltage of the storage cell transistor is above a predefined value, and therefore in some examples, the storage cell transistor is in a programmed state corresponding to logic "0".

[0045] The memory cell string 180 includes one or more top select transistors configured to couple / decouple memory cells in the memory cell string 180 to bit lines, and includes one or more bottom select transistors configured to couple / decouple memory cells in the memory cell string 180 to the ACS.

[0046] The top-select transistor is controlled by the top-select gate (TSG). For example, when the TSG voltage (the voltage applied to the TSG) is greater than the threshold voltage of the top-select transistor, the top-select transistor in the memory cell string 180 is turned on, and the memory cells in the memory cell string 180 are coupled to bit lines (e.g., the drain of the memory cell string is coupled to a bit line); and when the TSG voltage (the voltage applied to the TSG of the top-select transistor) is less than the threshold voltage of the top-select transistor, the top-select transistor is turned off, and the memory cells in the memory cell string 180 are decoupled from the bit lines (e.g., the drain of the memory cell string is decoupled from the bit lines).

[0047] Similarly, the bottom select transistor is controlled by the bottom select gate (BSG). For example, when the BSG voltage (the voltage applied to the BSG) is greater than the threshold voltage of the bottom select transistor in the memory cell string 180, the bottom select transistor is turned on, and the memory cells in the memory cell string 180 are coupled to the ACS (e.g., the source of the memory cell string in the memory cell string 180 is coupled to the ACS); and when the BSG voltage (the voltage applied to the BSG) is less than the threshold voltage of the bottom select transistor, the bottom select transistor is turned off, and the memory cells are decoupled from the ACS (e.g., the source of the memory cell string in the memory cell string 180 is decoupled from the ACS).

[0048] like Figure 3 As shown, the upper portion of the semiconductor layer 185 in the channel hole corresponds to the source side of the vertical memory cell string 180, and the upper portion is labeled 185(S). Figure 3In this example, the common source layer 189 is formed to be electrically connected to the source of the vertical memory cell string 180. The common source layer 189 may include one or more layers. In some examples, the common source layer 189 includes a silicon material, such as intrinsic polysilicon, doped polysilicon (e.g., N-type doped silicon, P-type doped silicon, etc.). In some examples, the common source layer 189 may include a metal silicide to improve conductivity. The common source layer 189 is similarly electrically connected to the source of other vertical memory cell strings (not shown) in the semiconductor portion 105, and thus forms an array common source (ACS).

[0049] According to some aspects of this disclosure, in some examples, the semiconductor portion 105 and the common source layer 189 are electrically coupled, so the semiconductor portion 105 can be configured as an array common source for vertical memory cell strings formed in the semiconductor portion 105.

[0050] exist Figure 3 In the example, in channel structure 181, semiconductor layer 185 extends vertically downward from the source side of channel structure 181 and forms a bottom portion corresponding to the drain side of vertical memory cell string 180. The bottom portion of semiconductor layer 185 is labeled 185(D). Note that the drain side and source side are named for ease of description. The functions of the drain side and source side may differ from their names.

[0051] exist Figure 3 In the example, interconnect structures such as via 162, metal line 163, bonding structure 164, etc., can be formed to electrically couple the bottom portion of semiconductor layer 185(D) to bit lines (BL).

[0052] In addition, Figure 3 In the example, the stepped region 116 includes a step that is formed to facilitate word line connection to the gate of a transistor (e.g., a memory cell, a top-select transistor, a bottom-select transistor, etc.). For example, the word line connection structure 150 includes a word line contact plug 151, a through-hole structure 152, and a metal wire 153 electrically coupled together. The word line connection structure 150 can electrically couple WL to the gate terminals of transistors in the memory cell string 180.

[0053] exist Figure 3 In the example, contact structure 170 is formed in insulating region 117. In some embodiments, contact structure 170 and word line connection structure 150 can be formed simultaneously by processing on the front side of array die 102. Therefore, in some examples, contact structure 170 has a structure similar to word line connection structure 150. Specifically, contact structure 170 may include a contact plug 171, a through-hole structure 172, and a metal wire 173 electrically coupled together.

[0054] In some examples, a mask may be used, which includes a pattern for contact plug 171 and word line contact plug 151. The mask is used to form contact holes for contact plug 171 and word line contact plug 151. An etching process may be used to form the contact holes. In an example, the etching of the contact holes for word line contact plug 151 may stop on the gate layer 195, and the etching of the contact holes for contact plug 171 may stop in the oxide layer 112. Furthermore, the contact holes may be filled with a suitable liner (e.g., titanium / titanium nitride) and a metal layer (e.g., tungsten) to form contact plugs, such as contact plug 171 and word line contact plug 151. Further back-end processing (BEOL) steps are used to form various connection structures, such as through-hole structures, metal lines, bonding structures, etc.

[0055] In addition, Figure 3 In the example, bonding structures are formed on the front side of array die 102 and CMOS die 101, respectively. For example, bonding structures 174 and 164 are formed on the front side of array die 102, and bonding structures 131 and 134 are formed on the front side of CMOS die 101.

[0056] exist Figure 3 In one example, array die 102 and CMOS die 101 are arranged face-to-face (circuit side is the front, substrate side is the back) and bonded together. Corresponding bonding structures on array die 102 and CMOS die 101 are aligned and bonded together, forming a bonding interface that electrically couples suitable components on the two dies. For example, bonding structures 164 and 131 are bonded together to couple the drain side of memory cell string 180 to the bit line (BL). In another example, bonding structures 174 and 134 are bonded together to couple contact structure 170 on array die 102 to I / O circuitry on CMOS die 101.

[0057] Returning to reference S220, the first substrate of the first die is removed from the back side of the first die. Removing the first substrate exposes the semiconductor portion and the contact structure 170 on the back side of the first die.

[0058] Figure 4 A cross-sectional view of the semiconductor memory device 100 after the first substrate 103 has been removed from the array die 102 is shown. Figure 4In one example, bulk portion 111, silicon oxide layer 112, and silicon nitride layer 113 are removed from the back side of array die 102. In some examples, after a wafer-to-wafer bonding process, a first wafer with array die is bonded to a second wafer with CMOS die. The first substrate is then thinned from the back side of the first wafer. In this example, a chemical mechanical polishing (CMP) or grinding process is used to remove most of the bulk portion 111 of the first wafer. Alternatively, the remaining bulk portion 111, silicon oxide layer 112, and silicon nitride layer 113 can be removed from the back side of the first wafer using a suitable etching process. Removing the bulk portion 111, silicon oxide layer 112, and silicon nitride layer 113 can expose the end of contact structure 170 protruding from insulating portion 106 (as shown at 175). Removing the bulk portion 111, silicon oxide layer 112, and silicon nitride layer 113 can also expose semiconductor portion 105.

[0059] Return to reference Figure 2 At S230, a pad structure and a connection structure are formed on the back side of the first die. In some embodiments, the pad structure includes a first pad structure electrically connected to the contact structure 170. The connection structure is electrically connected to the semiconductor portion 150.

[0060] In some embodiments, the pad structure and connection structure are primarily formed of aluminum (Al). In some embodiments, an interface layer may be formed between the aluminum and the semiconductor portion 105. In some examples, a metal silicide film may be used as the interface layer. In one example, the metal silicide film may be used to achieve an ohmic contact between the aluminum and the semiconductor portion 105. In another example, the metal silicide film is used to form local interconnects to the semiconductor portion 105. In yet another example, the metal silicide film is used as a diffusion barrier to prevent aluminum from diffusing into the semiconductor portion 105.

[0061] In some examples, titanium is deposited integrally on the back side of a first wafer that is bonded face-to-face with a second wafer, and then heated in a nitrogen environment. Titanium can react with exposed silicon surfaces (e.g., semiconductor portion 105) to form titanium silicide. Portions of titanium (e.g., above insulating portions, above the ends of contact structure 170, etc.) do not react to form silicide.

[0062] Then, a metal film can be formed on the surface of the back side of the first wafer. Figure 5 A cross-sectional view of the semiconductor memory device 100 after metal film deposition is shown. Figure 5In this example, the metal film 120 is deposited on the back side of the first wafer. Due to the protruding ends of the contact structure 170, the metal film 120 may have an uneven surface. In some embodiments, the metal film 120 includes a titanium layer 126 and an aluminum layer 128. In an embodiment, the titanium layer 126 on the semiconductor portion 105 may react with a silicon surface to form titanium silicide 127. For example, the titanium layer 126 is deposited and heated in a nitrogen environment. The aluminum layer 128 is then deposited.

[0063] The metal film 120 can be patterned to form pad structures and connection structures. Figure 6 A cross-sectional view of the semiconductor memory device 100 is shown after the metal film 120 has been patterned into pad structures 122-123 and interconnect structures 121. Figure 6 In the example, pad structures 122-123 are respectively connected to contact structure 170 and disposed above insulating portion 106; connection structure 121 is connected to semiconductor portion 105. In some embodiments, a photolithography process is used to define the pattern of pad structures 122-123 and connection structure 121 into a photoresist layer according to a mask, and then an etching process is used to transfer the pattern into metal film 120 and form pad structures 122-123 and connection structure 121.

[0064] According to aspects of this disclosure, the film of the connection structure 121 is deposited directly on the semiconductor portion 105, thus the interface between the connection structure 121 and the semiconductor portion 105 is substantially flat on the semiconductor portion 105. In a related example, the semiconductor portion 105 may be covered by an insulating layer, in which contact holes are formed, and then a suitable metal layer is deposited (in the holes and on the insulating layer) to form contacts and connections. Compared to the related example, the connection structure 121 is formed without contact holes in the insulating layer, and the interface between the connection structure 121 and the semiconductor portion 105 is relatively flat; when etch profile-related differences are ignored, the bottom and top surfaces of the connection structure 121 on the semiconductor portion 105 are substantially the same.

[0065] According to another aspect of this disclosure, the metal film 120 may have an uneven surface due to the protrusion at the end of the contact structure 170. For example, the bottom surface of the metal film 120 intersecting with the insulating portion 106 may have a recessed portion corresponding to the end of the contact structure 170, and thus the bottom surfaces of the pad structures 122-123 may have a recessed portion corresponding to the end of the contact structure 170.

[0066] The wafer fabrication process can be further processed, such as passivation, testing, and dicing.

[0067] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device comprising: A first die and a second die, the first die including a plurality of semiconductor portions, a first transistor formed on the front side of the semiconductor portions, a common source layer conductively coupled to the semiconductor portions, and a plurality of contact structures, the plurality of contact structures including at least two first contact structures disposed in an insulating portion, the second die including a substrate and a second transistor formed on the front side of the second die, wherein at least two first contact structures are located between adjacent semiconductor portions, and a vertical memory cell string of the first transistor extends from the common source layer without penetrating the semiconductor portions, wherein the vertical memory cell string includes silicon nitride in the semiconductor portions; At least one first pad structure is disposed on the back side of the first die and is electrically coupled to at least two first contact structures, the ends of the first contact structures protruding from the insulating portion into the first pad structure; and A connection structure is disposed on the back side of the first die and is electrically connected to the semiconductor portion, wherein the connection structure is in direct contact with the semiconductor portion.

2. The semiconductor device according to claim 1, wherein, The interface between the connection structure and the semiconductor portion is substantially flat on the semiconductor portion.

3. The semiconductor device according to claim 1, wherein, The first contact structure includes at least a first metal material that is different from the second metal material in the first pad structure.

4. The semiconductor device according to claim 3, wherein, The first metallic material includes tungsten, and the second metallic material includes aluminum.

5. The semiconductor device according to claim 1, wherein, The bottom surface of the first pad structure that intersects with the insulating portion has a recessed portion corresponding to the end of the first contact structure.

6. The semiconductor device according to claim 1, wherein, The first die includes at least one array of memory cells, and the second die includes peripheral circuitry for the array of memory cells.

7. The semiconductor device according to claim 6, wherein, The first contact structure on the first die is electrically coupled to the input / output circuit on the second die via a bonding structure.

8. The semiconductor device according to claim 1, wherein, All the first contact structures connected to the same first pad structure are arranged in a row.

9. The semiconductor device according to claim 1, wherein, The common source layer comprises multiple layers.

10. The semiconductor device according to claim 1, wherein, The first pad structure includes a titanium layer.

11. The semiconductor device according to claim 1, wherein, The first die further includes a stacked structure located on the side of the common source layer away from the semiconductor portion, and the stacked structure includes alternately stacked gate layers and insulating layers.

12. The semiconductor device according to claim 11, wherein, The first die also includes a word line connection structure, which is connected to the gate layer.

13. The semiconductor device according to claim 1, wherein, The insulating portion is located between adjacent semiconductor portions.

14. The semiconductor device according to claim 1, wherein, The connection structure overlaps with the plurality of vertical memory cell strings, and the area of ​​the connection structure is smaller than the area of ​​the semiconductor portion on the side closest to the connection structure.

15. The semiconductor device of claim 1, further comprising a second pad, wherein the plurality of contact structures further comprises a plurality of second contact structures, at least a portion of the ends of the second contact structures protruding from the insulating portion into the second pad structure, and the number of the first contact structures connected to the first pad structure is different from the number of the second contact structures connected to the second pad structure.

16. A semiconductor device comprising: A first die and a second die, the first die including a plurality of semiconductor portions, a first transistor formed on the front side of the semiconductor portions, a common source layer conductively coupled to the semiconductor portions, and a plurality of contact structures, the plurality of contact structures including at least two first contact structures disposed in an insulating portion, the second die including a substrate and a second transistor formed on the front side of the second die, wherein at least two first contact structures are located between adjacent semiconductor portions, and a vertical memory cell string of the first transistor extends from the common source layer without penetrating the semiconductor portions, wherein the vertical memory cell string includes silicon nitride in the semiconductor portions; At least one first pad structure is disposed on the back side of the first die, and at least two first contact structures extend through the insulating portion and extend to the same first pad structure; and A connection structure is disposed on the back side of the first die and is electrically connected to the semiconductor portion, wherein the connection structure is in direct contact with the semiconductor portion.

17. The semiconductor device according to claim 16, wherein, The interface between the connection structure and the semiconductor portion is substantially flat on the semiconductor portion.

18. The semiconductor device according to claim 16, wherein, The first contact structure includes at least a first metal material that is different from the second metal material in the first pad structure.

19. The semiconductor device according to claim 18, wherein, The first metallic material includes tungsten, and the second metallic material includes aluminum.

20. The semiconductor device according to claim 16, wherein, The bottom surface of the first pad structure that intersects with the insulating portion has a recessed portion corresponding to the end of the first contact structure.

21. The semiconductor device according to claim 16, wherein, The first die includes at least one array of memory cells, and the second die includes peripheral circuitry for the array of memory cells.

22. The semiconductor device according to claim 21, wherein, The first contact structure on the first die is electrically coupled to the input / output circuit on the second die via a bonding structure.

23. The semiconductor device according to claim 16, wherein, The insulating portion is located between adjacent semiconductor portions.

24. The semiconductor device according to claim 16, wherein, The connection structure overlaps with the plurality of vertical memory cell strings, and the area of ​​the connection structure is smaller than the area of ​​the semiconductor portion on the side closest to the connection structure.

25. The semiconductor device of claim 16, further comprising a second pad, wherein the plurality of contact structures further comprises a plurality of second contact structures, at least a portion of the ends of the second contact structures protruding from the insulating portion into the second pad structure, and the number of the first contact structures connected to the first pad structure is different from the number of the second contact structures connected to the second pad structure.

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