A Te-based image sensor integrated with a CMOS process and a preparation method thereof

Abstract

The application belongs to the technical field of image sensing, and specifically discloses a Te-based image sensor integrated with a CMOS process and a preparation method thereof, which comprises a sapphire substrate, a Te / Si heterojunction photoelectric sensing layer, a Te thin film side leakage electrode, a Si thin film side source electrode, an isolation layer, a metal gate electrode, a gate dielectric layer, a switching processing layer, a switching processing layer side leakage electrode, a switching processing layer side source electrode, a leakage electrode interconnection pole piece and a light shielding layer; the application uses Te and Si as the photosensitive layer material, the constructed Te / Si heterojunction can have bidirectional light response characteristics in the short wave near infrared band, and has high photoelectric conversion efficiency; the application constructs the on-chip integration of the Te / Si heterojunction and the thin film transistor, realizes the complementary advantages of the photoelectric sensing function and the information processing function, improves the stability and reliability of the system, simplifies the circuit design, and meets the miniaturization and light weight requirements.

Description

Technical Field

[0001] This invention relates to the field of image sensing technology, and in particular to a Te-based image sensor integrated with CMOS technology and its fabrication method. Background Technology

[0002] Image sensors, as a key component in the field of optoelectronics, directly affect the efficiency and accuracy of converting light signals into image signals. In numerous applications, such as military reconnaissance, medical imaging, environmental monitoring, and industrial automation, the performance requirements for image sensors are becoming increasingly stringent. While traditional image sensors have advantages in cost and technological maturity, their large size, heavy weight, and reliance on filters make them increasingly difficult to meet the demands of modern technological development.

[0003] To overcome these limitations, researchers have begun exploring novel materials and structural designs. Te, a two-dimensional semiconductor material with high electron mobility and broad spectral absorption characteristics, has shown great potential in the field of optoelectronic devices. These properties of Te give it a significant advantage in improving the response speed of photoelectric sensors and broadening the spectral response range. However, those skilled in the art also recognize that to achieve higher-performance image sensors, new device structure integration technologies need to be developed. This involves not only the optimized fabrication of Te materials but also compatibility studies with CMOS processes and the innovative design of novel image sensor structures. Through these technological breakthroughs, the photoelectric properties of Te materials and the switching characteristics of thin-film transistors can be fully utilized, combined with CMOS processes, to drive photoelectric sensing technology towards higher efficiency, smaller size, and lower power consumption.

[0004] Therefore, how to achieve miniaturized and lightweight broadband imaging technology has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a Te-based image sensor integrated with CMOS technology and its fabrication method.

[0006] To achieve the above objectives, the present invention is implemented according to the following technical solution:

[0007] One of the objectives of this invention is to provide a Te-based image sensor integrated with CMOS technology, comprising a sapphire substrate;

[0008] The sapphire substrate has a Te / Si heterojunction photosensitive layer composed of a Te thin film and a Si thin film on one side of its upper end surface; a Te thin film side drain electrode connected to one end of the Te thin film is provided on the upper end surface of the sapphire substrate on the Te thin film side surface, and a Si thin film side source electrode connected to one end of the Si thin film is provided on the upper end surface of the sapphire substrate on the Si thin film side surface.

[0009] An isolation layer is provided on the other side of the upper end face of the sapphire substrate, the upper end face of the Te / Si heterojunction photosensitive layer, the outer wall of the Te thin film side drain electrode, and the outer wall of the Si thin film side source electrode;

[0010] A metal gate electrode is provided on the other side of the upper end face of the isolation layer; a gate dielectric layer is provided on the upper end face of the isolation layer and the outer wall of the metal gate electrode; a switching processing layer is provided on the upper end face of the gate dielectric layer; a switch processing layer side drain electrode connected to one end of the switch processing layer is provided on the upper end face of the gate dielectric layer at one end of the switch processing layer, and a switch processing layer side source electrode connected to the other end of the switch processing layer is provided on the upper end face of the gate dielectric layer at the other end of the switch processing layer.

[0011] The ends of the switch processing layer side drain electrode and the Te thin film side drain electrode are connected by a drain electrode interconnect that penetrates the gate dielectric layer and the isolation layer.

[0012] A light-shielding layer is provided on the lower end surface of the sapphire substrate directly below the switching processing layer.

[0013] Furthermore, the thickness of the Si thin film is 10-100 nm, and the thickness of the Te thin film is 10-100 nm.

[0014] Furthermore, the Te thin-film side drain electrode and the Si thin-film side source electrode are made of one or more composite structures of Cr, Ti, Ag, and Au, and the thickness of the Te thin-film side drain electrode and the Si thin-film side source electrode is the same, both being 30-50 nm.

[0015] Furthermore, the material of the isolation layer is SiO2 or SiN. x One or more composite structures of AlN with a thickness of 200-400 nm.

[0016] Furthermore, the metal gate electrode is made of one or more composite structures of Mo, Au, Al, and Cu, and its thickness is 10-30 nm.

[0017] Furthermore, the material of the gate dielectric layer is Al2O3 or SiN. x It is one of the HfO2 dielectric thin film materials, with a thickness of 50-100nm.

[0018] Furthermore, the material of the switching processing layer is one or more composite structures of ZnO, Ga2O3, and IGZO thin film transistor materials, and its thickness is 5-20 nm.

[0019] Furthermore, the materials of the switch processing layer side drain electrode and the switch processing layer side source electrode are one or more composite structures of Cr, Ti, Ag, and Au, and the thickness of the switch processing layer side drain electrode and the switch processing layer side source electrode are the same, both being 30-50 nm.

[0020] Furthermore, the material of the light shielding layer is one or more composite structures selected from metal thin film, optical anti-reflection layer, and dark high absorptivity thin film, with a thickness of 50-200 nm.

[0021] The second objective of this invention is to provide a method for fabricating a Te-based image sensor integrated with CMOS technology, comprising the following steps:

[0022] S1. A Te / Si heterojunction photosensitive layer composed of a Te thin film and a Si thin film is prepared on a sapphire substrate. The Te thin film and the Si thin film are stacked horizontally.

[0023] S2. A Te thin film side drain electrode connected to one end of the Te thin film is prepared on the upper surface of the sapphire substrate on the Te side of the Te / Si heterojunction photosensitive layer, and a Si thin film side source electrode connected to one end of the Si thin film is prepared on the upper surface of the sapphire substrate on the Si side.

[0024] S3. An isolation layer is prepared on the other side of the upper end face of the sapphire substrate, on the upper end face of the Te / Si heterojunction photosensitive layer, on the outer wall of the Te thin film side drain electrode, and on the outer wall of the Si thin film side source electrode.

[0025] S4. Fabricate a metal gate electrode on the other side of the upper end face of the isolation layer;

[0026] S5. A gate dielectric layer is prepared on the upper end surface of the isolation layer and the outer wall of the metal gate electrode;

[0027] S6. A switching processing layer is prepared on the upper end face of the gate dielectric layer;

[0028] S7. A switch processing layer side drain electrode connected to one end of the switch processing layer is prepared on the upper surface of the gate dielectric layer at one end of the switch processing layer, and a switch processing layer side source electrode connected to the other end of the switch processing layer is prepared on the upper surface of the gate dielectric layer at the other end of the switch processing layer; and a drain electrode interconnect electrode sheet penetrating the gate dielectric layer and the isolation layer is prepared to connect the switch processing layer side drain electrode to the end of the Te thin film side drain electrode.

[0029] S8. A light shielding layer is provided on the lower end surface of the sapphire substrate directly below the switching processing layer.

[0030] Compared with existing technologies, the Te-based image sensor integrated with CMOS technology in this invention uses Te and Si as photosensitive layer materials, both of which can be directly obtained through mature fabrication methods. Furthermore, the Te / Si heterojunction constructed in this invention exhibits bidirectional photoresponse characteristics in the short-wave near-infrared band and possesses high photoelectric conversion efficiency. The on-chip integration of the Te / Si heterojunction with thin-film transistors in this invention achieves complementary advantages in photoelectric sensing and information processing functions, improving system stability and reliability, simplifying circuit design, and meeting the demands for miniaturization and lightweight design. This invention has a profound impact on the future development of the image sensing industry, helping to promote the development of photoelectric sensing technology towards higher efficiency, smaller size, and lower power consumption. Attached Figure Description

[0031] Figure 1 A schematic diagram of the structure for forming a Te / Si heterojunction photosensitive layer.

[0032] Figure 2 This is a schematic diagram of the structure forming the drain electrode and source electrode on both sides of the photosensitive layer.

[0033] Figure 3 A schematic diagram of the structure forming the isolation layer.

[0034] Figure 4 This is a schematic diagram of the structure for forming a metal gate electrode.

[0035] Figure 5 This is a schematic diagram of the structure forming the gate dielectric layer.

[0036] Figure 6 This is a schematic diagram of the structure forming the switch processing layer.

[0037] Figure 7 This is a schematic diagram of the structure for forming the drain electrode on the switch processing layer side and the interconnecting electrode between the source electrode and drain electrode on the switch processing layer side.

[0038] Figure 8 A schematic diagram of the structure for forming the light shielding layer of the drain electrode interconnect.

[0039] Figure 9 The transient response curves of the Te / Si heterojunction photosensitive layer under a bias voltage of -1V under 808nm band illumination with different optical powers are shown.

[0040] Figure 10 The transient response curves of the Te / Si heterojunction photosensitive layer under a 1V bias voltage are shown under 808nm band illumination with different optical powers.

[0041] Figure 11The photoelectric performance parameters of a Te-based image sensor integrated with CMOS technology under a bias voltage of -1V under 808nm band illumination with different optical powers are shown.

[0042] Figure 12 The photoelectric performance parameters of a Te-based image sensor integrated with CMOS technology under a 1V bias voltage are shown under 808nm band illumination with different optical powers.

[0043] In the figure, the following labels are used: 100, sapphire substrate; 1011, Te thin film; 1012, Si thin film; 1021, Te thin film side drain electrode; 1022, Si thin film side source electrode; 103, isolation layer; 104, metal gate electrode; 105, gate dielectric layer; 106, switching processing layer; 1023, switching processing layer side drain electrode; 1024, switching processing layer side source electrode; 1025, drain electrode interconnect; 107, light shielding layer. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0045] like Figures 1 to 8 As shown in the figure, this embodiment exemplarily demonstrates a method for fabricating a Te-based image sensor integrated with CMOS technology. The specific steps are as follows:

[0046] Step 1: Please refer to Figure 1 As shown, a Si thin film deposition window is defined on a sapphire substrate 100 using photolithography, and a Si thin film 1012 is deposited using chemical vapor deposition. Then, a Te thin film 1011 and a Si thin film 1012 are bonded together to form a Te / Si heterojunction photosensitive layer. Preferably, the Si thin film 1012 has an n-type doping type and a resistivity of n-type and n-type, respectively. The Si thin film 1012 has a thickness of 10-100 nm, and the Te thin film 1011 is prepared by electron beam deposition with a thickness of 10-100 nm. The Te / Si heterojunction photosensitive layer is constructed using photolithography, and the Te / Si is stacked horizontally.

[0047] Step Two: Please refer to Figure 2As shown, drain and source electrode windows are defined on the Te / Si heterojunction photosensitive layer using photolithography. Metal electrodes with composite structures of Cr, Ti, Ag, and Au are deposited on both sides of the Te thin film 1011 and the Si thin film 1012 using electron beam evaporation or thermal evaporation to form the Te thin film side drain electrode 1021 and the Si thin film side source electrode 1022. Preferably, to obtain better gold-semiconductor contact, the Te thin film side drain electrode 1021 is made of Cr / Au with a thickness of 30-50 nm; the Si thin film side source electrode 1022 is made of Ti / Au with a thickness of 30-50 nm.

[0048] Step 3: Please refer to Figure 3 As shown, SiO2 and SiN are deposited on a sapphire substrate 100 with a Te thin-film drain electrode 1021 and a Si thin-film source electrode 1022 deposited thereon via thermal oxidation, chemical vapor deposition, or plasma-enhanced chemical vapor deposition. x An isolation layer 103 comprising one or more composite structures of AlN. Preferably, the thickness of the isolation layer 103 is 200-400 nm.

[0049] Step 4: Please refer to Figure 4 As shown, a metal gate electrode 104 with a composite structure of one or more of Mo, Au, Al, and Cu is deposited above the isolation layer 103 using an electron beam evaporation process or a thermal evaporation process. Preferably, for cost considerations, the metal gate electrode 104 is made of Cu and has a thickness of 10-30 nm. To achieve regional separation between the subsequent switching processing layer 106 and the photosensitive layer, the metal gate electrode 104 is disposed above the sapphire substrate 100, but not above the Te / Si heterojunction photosensitive layer.

[0050] Step 5: Please refer to Figure 5 As shown, Al2O3 and SiN are deposited on a sapphire substrate 100 with a metal gate electrode 104 deposited using chemical vapor deposition, atomic layer deposition, or low-pressure chemical vapor deposition processes. x A gate dielectric layer 105 is constructed from high-k dielectric thin film materials such as HfO2. Preferably, the gate dielectric layer 105 is made of Al2O3 and has a thickness of 50-100 nm.

[0051] Step Six: Please refer to Figure 6 As shown, a switch processing layer window is defined above the metal gate electrode 104 using photolithography. A switch processing layer 106, consisting of one or more composite structures of thin-film transistor materials such as ZnO, Ga2O3, and IGZO, is deposited using pulsed laser deposition, magnetron sputtering, or electron beam evaporation. Preferably, the thickness of the switch processing layer 106 is 5-20 nm.

[0052] Step Seven: Please refer to Figure 7As shown, the etching windows of the isolation layer and gate dielectric layer above the drain electrode of the photosensitive layer are defined by photolithography. Part of the isolation layer 103 and gate dielectric layer 105 etching windows are removed by ICP dry etching or BOE solution wet etching. The drain electrode and source electrode windows on both sides of the switch processing layer, as well as the interconnection window with the drain electrode of the photosensitive layer, are defined by photolithography. One or more composite structures of Cr, Ti, Ag, and Au are deposited using electron beam evaporation and thermal evaporation processes for the switch processing layer side drain electrode 1023, switch processing layer side source electrode 1024, and drain electrode interconnection electrode 1025. Preferably, the material of the switch processing layer side drain electrode 1023, switch processing layer side source electrode 1024, and drain electrode interconnection electrode 1025 is Au, and its thickness is 30-50 nm.

[0053] Step 8: Please refer to Figure 8 As shown, a light-shielding layer window is defined using a photomask or photolithography process. A light-shielding layer 107, consisting of a metal thin film, an optical anti-reflection layer, or a dark-colored high-absorptivity thin film structure, is fabricated beneath the sapphire substrate 100 using a dry transfer technique, resulting in a Te-based image sensor integrated with CMOS technology. Preferably, to achieve optimal light shielding, the light-shielding layer 107 is disposed on the lower surface of the sapphire substrate 100 directly below the switching processing layer 106, and its thickness is 50-200 nm.

[0054] The Te / Si heterojunction photosensitive layer prepared in step one was subjected to current (I)-time (T) tests at different optical power densities and wavelengths of 808 nm. The test results are as follows: Figure 9 and Figure 10 As shown, by Figure 9 and Figure 10 It can be seen that the current value of the Te / Si heterojunction of the present invention continuously increases under negative bias and light illumination, while the current continuously decreases under positive bias and light illumination, exhibiting bidirectional photoresponse characteristics.

[0055] The Te-based image sensor, which was then finally fabricated and integrated with the CMOS process, was then tested. The specific testing process is as follows:

[0056] An 808nm wavelength laser beam was aligned with the bottom back of the Te / Si heterojunction photosensitive layer of the sensor. By varying the laser power density and applying different bias voltages, the photoelectric performance of the device was tested. The test results are as follows: Figure 11 and Figure 12 As shown, the maximum responsivity and detectivity of the device at -1V are 13915 A / W and 2.55 × 10⁻⁶, respectively. 13 Jones Figure 11 The maximum responsivity and detectivity of the device at 1V are 364A / W and 2.28×10⁻⁶, respectively. 12 Jones Figure 12 The above test results demonstrate that this image sensor possesses excellent sensing characteristics.

[0057] The technical solutions of the present invention are not limited to the specific embodiments described above. Any technical modifications made in accordance with the technical solutions of the present invention fall within the protection scope of the present invention.

Claims

1. A Te-based image sensor integrated with CMOS technology, comprising a sapphire substrate; characterized in that: The sapphire substrate has a Te / Si heterojunction photosensitive layer composed of a Te thin film and a Si thin film on one side of its upper end surface; a Te thin film side drain electrode connected to one end of the Te thin film is provided on the upper end surface of the sapphire substrate on the Te thin film side surface, and a Si thin film side source electrode connected to one end of the Si thin film is provided on the upper end surface of the sapphire substrate on the Si thin film side surface. An isolation layer is provided on the other side of the upper end face of the sapphire substrate, the upper end face of the Te / Si heterojunction photosensitive layer, the outer wall of the Te thin film side drain electrode, and the outer wall of the Si thin film side source electrode; A metal gate electrode is provided on the other side of the upper end face of the isolation layer; a gate dielectric layer is provided on the upper end face of the isolation layer and the outer wall of the metal gate electrode; a switching processing layer is provided on the upper end face of the gate dielectric layer; a switch processing layer side drain electrode connected to one end of the switch processing layer is provided on the upper end face of the gate dielectric layer at one end of the switch processing layer, and a switch processing layer side source electrode connected to the other end of the switch processing layer is provided on the upper end face of the gate dielectric layer at the other end of the switch processing layer. The ends of the switch processing layer side drain electrode and the Te thin film side drain electrode are connected by a drain electrode interconnect that penetrates the gate dielectric layer and the isolation layer. A light-shielding layer is provided on the lower end surface of the sapphire substrate directly below the switching processing layer.

2. The Te-based image sensor integrated with CMOS technology according to claim 1, characterized in that: The thickness of the Si thin film is 10-100 nm, and the thickness of the Te thin film is 10-100 nm.

3. The Te-based image sensor integrated with CMOS technology according to claim 1, characterized in that: The Te thin-film side drain electrode and the Si thin-film side source electrode are made of one or more of the following composite structures: Cr, Ti, Ag, and Au. The Te thin-film side drain electrode and the Si thin-film side source electrode have the same thickness, which is 30-50 nm.

4. The Te-based image sensor integrated with CMOS technology according to claim 1, characterized in that: The material of the isolation layer is SiO2 or SiN. x One or more composite structures of AlN with a thickness of 200-400 nm.

5. The Te-based image sensor integrated with CMOS technology according to claim 1, characterized in that: The metal gate electrode is made of one or more composite structures of Mo, Au, Al, and Cu, and its thickness is 10-30 nm.

6. The Te-based image sensor integrated with CMOS technology according to claim 1, characterized in that: The gate dielectric layer is made of Al2O3 or SiN. x It is one of the HfO2 dielectric thin film materials, with a thickness of 50-100nm.

7. The Te-based image sensor integrated with CMOS technology according to claim 1, characterized in that: The switching processing layer is made of one or more composite structures of ZnO, Ga2O3, and IGZO thin film transistor materials, with a thickness of 5-20 nm.

8. The Te-based image sensor integrated with CMOS technology according to claim 1, characterized in that: The materials of the switch processing layer side drain electrode and the switch processing layer side source electrode are one or more composite structures of Cr, Ti, Ag, and Au. The thickness of the switch processing layer side drain electrode and the switch processing layer side source electrode is the same, which is 30-50 nm.

9. The Te-based image sensor integrated with CMOS technology according to claim 1, characterized in that: The material of the light shielding layer is one or more composite structures of metal thin film, optical anti-reflection layer, and dark high absorptivity thin film, with a thickness of 50-200nm.

10. A method for fabricating a Te-based image sensor integrated with CMOS technology as described in any one of claims 1-9, characterized in that, Includes the following steps: S1. A Te / Si heterojunction photosensitive layer composed of a Te thin film and a Si thin film is prepared on a sapphire substrate 100. The Te thin film and the Si thin film are stacked horizontally. S2. A Te thin film side drain electrode connected to one end of the Te thin film is prepared on the upper surface of the sapphire substrate on the Te side of the Te / Si heterojunction photosensitive layer, and a Si thin film side source electrode connected to one end of the Si thin film is prepared on the upper surface of the sapphire substrate on the Si side. S3. An isolation layer is prepared on the other side of the upper end face of the sapphire substrate, on the upper end face of the Te / Si heterojunction photosensitive layer, on the outer wall of the Te thin film side drain electrode, and on the outer wall of the Si thin film side source electrode. S4. Fabricate a metal gate electrode on the other side of the upper end face of the isolation layer; S5. A gate dielectric layer is prepared on the upper end surface of the isolation layer and the outer wall of the metal gate electrode; S6. A switching processing layer is prepared on the upper end face of the gate dielectric layer; S7. A switch processing layer side drain electrode connected to one end of the switch processing layer is prepared on the upper surface of the gate dielectric layer at one end of the switch processing layer, and a switch processing layer side source electrode connected to the other end of the switch processing layer is prepared on the upper surface of the gate dielectric layer at the other end of the switch processing layer; and a drain electrode interconnect electrode sheet penetrating the gate dielectric layer and the isolation layer is prepared to connect the switch processing layer side drain electrode to the end of the Te thin film side drain electrode. S8. A light shielding layer is provided on the lower end surface of the sapphire substrate directly below the switching processing layer.

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